source /opt/Xilinx/Vivado/2016.4/settings64.

sh

vivado

source /opt/Xilinx/Vivado/2017.2/settings64.sh

source /opt/Xilinx/SDK/2016.4/settings64.sh

ibrary IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity password is
 Port (

clk_out: in std_logic;

reset: in std_logic;

b_reg: in std_logic_vector(10 downto 0);

led: out std_logic_vector(3 downto 0);

-- ps2c1: in std_logic;

-- alerta: in std_logic;

-- mode: in std_logic;

mode3: in std_logic

-- salida: out std_logic_vector(10 downto 0)

);

end password;

architecture Behavioral of password is

type state is (st0, st1, st2, st3, st4, st5, st6, st7, st8, st9, st10,st11);

-- type state1 is (st41, st51, st61, st71, st81, st91, st101, st111);

-- signal pr_state1, nx_state1 : state1;

signal pr_state, nx_state : state;

signal tec: STD_LOGIC_VECTOR(7 downto 0);

 signal output : std_logic_vector(10 downto 0);

signal d0,d1,d2: STD_LOGIC_VECTOR(7 downto 0);

begin

tec <= b_reg(8 downto 1); -- data bits

-- SYNC_PROC: process (clk_out,reset)

-- begin

-- if (reset = '1') then

-- pr_state <= st0;

-- -- pr_state1 <= st41;

-- --output<= "00000000";

-- elsif (clk_out'event and clk_out='1') then

-- pr_state<= nx_state;

-- -- pr_state1 <= nx_state1;

-- --output<= "00000001";

-- -- else

-- -- output<= "00000000";

-- -- assign other outputs to internal signals

-- end if;

-- end process;

-----------------------------------------------------------------------

process (clk_out,reset)
 begin

if(reset = '1') then

pr_state <= st0;

elsif (clk_out'event and clk_out='1') then

pr_state <= nx_state;

end if;

end process;

-------------------------------------------------------------------

process(pr_state,clk_out)

begin

case pr_state is

when st0 =>

--led<="0000";

if (tec = "00010110") then

nx_state<=st1;

else

nx_state<= st0;

end if;

when st1 =>

if (tec = "00010110") then

nx_state<= st1;

elsif (tec = "00011110") then

nx_state<=st2;
 else

nx_state<= st0;

end if;

when st2 =>

if (tec = "00010110") then

nx_state<= st1;

elsif (tec = "00011110") then

nx_state<= st2;

elsif (tec = "00100110") then

nx_state<= st3;

else

nx_state<= st0;

end if;

when st3=>

led<="0001";

nx_state<= st3;

end case;

end process;

--end Behavioral;

--OUTPUT_DECODE: process (pr_state)

-- begin

-- --insert statements to decode internal output signals

-- --below is simple example

-- -- led<="0000";

-- if pr_state =st3 then

-- led<="0001";

-- --seguro<='1';

-- elsif pr_state =st7 then

-- led<="0010";

-- elsif pr_state =st11 then

-- led<="0100";

-- --seguro<='1';

-- else

-- led<="0000";

-- --seguro<='0';

-- end if;

-- end process;

-----------------------------------------------------------------------------------

-------------------------------------------------------------------------------------

-- process (pr_state, clk_out)

-- begin

-- case pr_state is

-- when st0 =>

-- --Led<="0000";

-- if (mode3 = '0') then

-- nx_state<=st4;

-- elsif(tec="00010110") then

-- nx_state<=st1;

-- else

-- nx_state<=st0;

-- end if;

-- when st1 =>

-- if (tec = "00010110") then

-- nx_state<= st1;

-- elsif (tec="00011110")then

-- nx_state<=st2;

-- else

-- nx_state<=st0;

-- end if;

-- when st2 =>

-- if (tec = "00010110") then

-- nx_state<= st1;

-- elsif (tec ="00011110") then

-- nx_state<= st2;

-- elsif(tec="00100110") then
-- nx_state<=st3;

-- else

-- nx_state<=st0;

-- end if;

-- when st3 =>

-- nx_state<=st3;

-- led<="0001";

-----------------------------------------------------------------------

-------------------------------------------------------------------------

-- process(pr_state1,clk_out)

-- begin

-- case pr_state1 is

-- when st41=>

-- led<="0000";

-- if(mode3 = '0') then

-- nx_state1<=st41;

-- else
-- d0<=tec;

-- nx_state1<=st51;

-- end if;

-- when st51=>

-- if(tec="01011010")then

-- nx_state1<=st41;

-- elsif(tec=d0)then

-- nx_state1<=st51;

-- else

-- d1<=tec;

-- nx_state1<=st61;

-- end if;

-- when st61=>

-- if(tec="01011010")then

-- nx_state1<=st41;

-- elsif(tec=d0)then

-- nx_state1<=st51;

-- elsif(tec=d1) then

-- nx_state1<=st61;

-- else

-- d2<=tec;
-- nx_state1<=st71;

-- end if;

-- when st71=>

-- if(tec="01011010")then

-- nx_state1<=st81;

-- led<="0010";

-- else

-- nx_state1<=st41;

-- -- led<="0010";

-- end if;

-- -- led<="0010";

------------------------------------------------------------

-- when st81=>

-- if(tec="01011010")then

-- nx_state1<=st41;

-- elsif(tec=d0)then

-- nx_state1<=st91;

-- else

-- nx_state1<=st81;

-- end if;
-- when st91=>

-- if(tec="01011010") then

-- nx_state1<=st41;

-- elsif(tec=d0) then

-- nx_state1<=st91;

-- elsif(tec=d1) then

-- nx_state1<=st101;

-- else

-- nx_state1<=st81;

-- end if;

-- when st101=>

-- if(tec="01011010")then

-- nx_state1<=st41;

-- elsif(tec=d0)then

-- nx_state1<=st91;

-- elsif(tec=d1)then

-- nx_state1<=st101;

-- elsif(tec=d2)then

-- --led<="111";

-- nx_state1<=st111;

-- else
-- nx_state1<=st81;

-- end if;

-- when st111 =>

-- led<="0100";

-- nx_state1<=st111;

-- end case;

4 st0

5 1

6 2

7 3

8 4

9 5

10 6

11 7