STA575

100+100W STEREO POWER AMPLIFIER

MONOCHIP BRIDGE STEREO AMPLIFIER

ON BASH ARCHITECTURE
80+80W OUTPUT POWER @ RL = 4/8 ,
THD = 0.5%
100+100W OUTPUT POWER @ RL = 4/8 ,
( s )

THD = 10%
HIGH DYNAMIC PREAMPLIFIER INPUT
c t FLEXIWATT27

STAGES
d u TRANSISTOR POWER PROTECTION
EXTERNAL PROGRAMMABLE FEEDBACK
TYPE COMPRESSORS r o s ) ABSOLUTE OUTPUT CURRENT LIMIT
AC COUPLED INPUT TO CLASS AB BRIDGE
e P c t ( INTEGRATED THERMAL PROTECTION

OUTPUT AMPLIFIER
PRECISION RECTIFIERS TO DRIVE THE
l e t d u POWER SUPPLY OVER VOLTAGE
PROTECTION
DIGITAL CONVERTER
s o r o FLEXIWATT POWER PACKAGE WITH 27 PIN
ON-OFF SEQUENCE/ TIMER WITH MUTE
AND STANDBY
O b e P BASH LICENCE REQUIRED

PROPORTIONAL OVER POWER OUTPUT

- l e t DESCRIPTION
CURRENT TO LIMIT THE DIGITAL

( s ) o The STA575 is a fully integrated power module de-

CONVERTER

c t
ABSOLUTE POWER BRIDGE OUTPUT
b s signed to implement a BASH amplifier when used
in conjunction with STABP01 digital processor.

BLOCK DIAGRAM
d u - O
r o s )
+VS GND -VS OUT_ PRE1 TRK_1 PWR_INP1

e P c t ( ABSOLUTE CD+1

t
+

u
VALUE +2 OUT1+

e
- BLOCK

o l o dIN_PRE1 G -1 OUT1-

r
COMPRESSOR

b s P ATT_REL1
V/l
OUTPUT BRIDGE CD-1

CD+

O t e S1
PEAK/2

e
DETECTOR
SOA

l
PROT.
DETECTOR
VOLTAGE

o
Ict PROTECTION

b s TRK_OUT
THRESH

O
THERMAL
Ict PROTECTION TURN-
ON/OFF STBY/MUTE
SEQUENCE
PEAK/2
S1
DETECTOR

ATT_REL2
V/l
CD+2
COMPRESSOR +2 OUT2+
IN_PRE2 G
-1 OUT2-
- ABSOLUTE
+ VALUE
BLOCK OUTPUT BRIDGE CD-2

OUT_ PRE2 TRK_2 PWR_INP2 D01AU1263

July 2003 1/20

 STA575

DESCRIPTION (continued)
Notice that normally only one Digital Converter is needed to supply a stereo or multi-channel amplifier system,
therefore most of the functions implemented in the circuit have summing outputs
The signal circuits are biased by fixed negative and positive voltages referred to Ground. Instead the final stag-
es of the output amplifiers are supplied by two external voltages that are following the audio signal . In this way
the headroom for the output transistors is kept at minimum level to obtain a high efficiency power amplifier.
The Compressor circuits, one for each channel, performs a particular transfer behavior to avoid the dynamic
restriction that an adaptive system like this requires. To have a high flexibility the attack / release time and the
threshold levels are externally programmable. The tracking signal for the external digital converter is generated
from the Absolute Value block that rectifies the audio signal present at the compressor output. The outputs of
these blocks are decoupled by a diode to permit an easy sum of this signal for the multichannel application. The
output power bridges have a dedicated input pin to perform an AC decoupling to cancel the compressor output

s )
DC offset. The gain of the stage is equal to 4 (+12dB). A sophisticated circuit performs the output transistor pow-

(
c t
er detector that , with the digital converter, reduces the power supply voltage . Moreover, a maximum current
output limiting and the over temperature sensor have been added to protect the circuit itself. The external volt-

on and turn-off.
d u
age applied to the STBY/MUTE pin forces the two amplifiers in the proper condition to guarantee a silent turn-

r o s )
e P c t (
ABSOLUTE MAXIMUM RATINGS

l e t d u
Symbol

s o Parameter

r o Value Unit

+Vs

O b e P
Positive supply voltage referred to pin 13 (GND) 30 V

-Vs

- l e t
Negative supply voltage referred to pin 13 (GND) -24 V

VCD+

( s )
Positive supply voltage tracking rail referred to pin 13 (GND)
o
22 V

VCD+
t b s
Positive supply voltage operated to Vs+(1)
c
0.3 V

VCD-
u O
Negative supply voltage referred to -Vs (1)
d -
-0.3 V

VCD-
r o )
Negative supply voltage tracking rail referred to pin 13 (GND)
s
-22 V

VAtt_Rel1
e P t (
Pin 3, 25 Negative & Positive maximum voltage referred to GND
c
-0.5 to +20 V

t
VAtt_Rel2

l e
(pin 13)

d u
s o
VPwr_Imp1
VPwr_Imp2
r o
Pin 7, 21, 18, 10 Negative & Positive maximum voltage referred to
GND (pin 13)
-20 to +20 V

O b VTrk_1
VTrk_2
e P
l e t
VIn_pre1 Pin 8, 20 Negative & Positive maximum voltage referred to GND -0.5 to +0.5 V

s o
VIn_pre2 (pin 13)

O b Vthreshold Pin 17 Negative & Positive maximum voltage referred to GND (pin
13)
-7 to +0.5 V

Istb-max Pin 11 maximum input current (Internal voltage clamp at 5V) 500 A

Vstbymute Pin 11 negative maximum voltage referred to GND (pin 13) -0.5 V

Iout Output current 7.7 A

Note 1: VCD- must not be more negative than -Vs and VCD+ must not be more positive than +VS
Note 2: All pins withstand 2KV ESD but not pin 11

2/20
 STA575

THERMAL DATA
Symbol Parameter Value Unit

Tj Max Junction temperature 150 C

Rth j_case Thermal Resistance Junction to case .............................. ..max 1 C/W

OPERATING RANGE
Symbol Parameter Value Unit

+Vs Positive supply voltage +20 to +28 V

-Vs Negative supply voltage

( s ) -10 to -23 V

Vs+ Delta positive supply voltage

c t 5V (Vs+ - VCD+) 10V V

VCD+ Positive supply voltage tracking rail

d u +3 to 20.7 V

VCD- Negative supply voltage tracking rail

r o s ) -20.7 to -3 V

Iin_Max P t (
Current at pin In_Pre1, In_Pre2, related to compressor behaviour
e c
-1 to +1 mA peak

Vtrheshold Voltage at pin Threshold

l e t d u -5 to 0 V

Tamb
s
Ambient Temperature Range
o r o 0 to 70 C

Isb_max b P
Pin 11 maximum input current (Internal voltage clmp at 5V)

O e
200 A

- l e t
( s ) o
PIN CONNECTION
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t 1 27

s o
O b
-VS
CD-1
ATT-REL1
OUT1+
OUT1-
CD+1
PWR_INP1
IN_PRE1
OUT_PRE1
TRK_1
STBY/MUTE
PROTECTION
GND
+VS
CD+
TRK_OUT
THRESHOLD
TRK_2
OUT_PRE2
IN_PRE2
PWR_INP2
CD+2
OUT2-
OUT2+
ATT_REL2
CD-2
-Vs

D01AU1251

Note: Slug connected to pins n. 1 and 27

3/20
 STA575

PIN FUNCTION
N Name Description

1 -Vs Negative Bias Supply

2 CD-1 Channel 1 Time varying tracking rail negative power supply

3 Att_Rel1 Attack release rate for channel 1

4 Out1+ Channel 1 speaker positive output

5 Out1- Channel 1 speaker negative output

6 CD+1 Channel 1 positive power supply

7 Pwr_Inp1 Input to channel 1 power stage

( s )
8 In_pre1
c t
Pre-amp input for channel 1 (virtual ground)

9 Out_pre1 Output channel 1 pre-amp

d u
10 Trk_1
r o
Absolute value block input for channel 1
s )
11 Stby/mute P
Standby/mute input voltage control
e c t (
12 Protection
e t u
Protection signal for STABP01 digital processor
l d
13 Gnd Analog Ground
s o r o
14 +Vs
b
Positive Bias Supply

O e P
15 CD+
- t
Time varying tracking rail positive power supply

l e
16 Trk_out
s ) o
Reference output for STABP01 digital processor

(
17 Threshold
c t b s
Compressor threshold input

18 Trk_2
d u - O
Absolute value block input for channel 2

19
r o
Out_pre2
)
Output channel 2 pre-amp
s
20
e P
In_pre2
c t (
Pre-amp input for channel 2 (virtual ground)

l e
21 t Pwr_Inp2
d u Input to channel 2 power stage

s o 22
r
CD+2
o Channel 2 positive power supply

O b 23

e P
Out2- Channel 2 speaker negative output

l
24
e t Out2+ Channel 2 speaker positive output

s o 25 Att_Rel2 Attack release rate for channel 2

O b 26

27
CD-2

-Vs
Channel 2 Time varying tracking rail negative power supply

Negative Bias Supply

4/20
 STA575

ELECTRICAL CHARACTERISTCS (Test Condition: Vs+ = 28V, Vs- = -23V, V CD+ = 20V, VCD- = -20V, RL =
8, external components at the nominal value f = 1KHz, Tamb = 25C unless otherwise specified
Symbol Parameter Test Condition Min. Typ. Max. Unit

PREAMPLIFIER AND COMPRESSOR

Vout clamp Maximum Voltage at Out_pre pin 9 11 13 Vpeak

Iin Audio input current 0.8 mA

Vcontrol Voltage at Attack_Release pin Attenuation = 0dB 0 V

Attenuation = 6dB 0.35 0.5 0.65 V
Attenuation = 26dB 6 9 12 V

VComp_ Input voltage range for the -5 -1 V

Th compression

( s )
Zth Input impedance of Threshold pin

c t 100 K

Voffset Output Offset at Out_pre pin with:

d u
VCRT= 0V; Attenuation = 0dB
VCRT= 0.5V; Attenuation = 6dB
-15
-250
15
250
mV
mV

r o )
VCRT= 9V; Attenuation = 26dB

s
-1000 450 mV

THD Distortion at Out_pre:

e P t (
VCRT= 0V; Attenuation = 0dB

c
0.01 0.1 %

l e t VCRT= 0.5V; Attenuation = 6dB

u
VCRT= 9V; Attenuation = 26dB
d
0.5
2
%
%

EN Noise at Out_pre pin :

s o r o VCRT= 0V; Attenuation = 0dB 10(2) V
V

O b e P VCRT= 0.5V; Attenuation = 6dB

VCRT= 9V; Attenuation = 26dB
50
60 V

Ict
-
Attack time current at pin
l e t 0.5 1.5 3 mA
Attack_release

( s ) o
t s
1. This value is due to the thermal noise of the external resistors Rr and Ri.

c b
TRACKING PARAMETERS

d u - O
Gtrk

r o
Tracking reference voltage gain

s )
13 14 15 V

Vtrk_out

e P c t (
Tracking ref. output voltage 0 20 V

Itrk_out

l e
Ztrk_in
t Current capability

d u
Input impedance (TRK1/2)
5 6

1
7 mA

s o r o
O b
OUTPUT BRIDGE

Gout
e PHalf Output bridge gain 5.5 6 6.5 dB

Gch
l e t Output bridge differential gain 11 12 13 dB

s o
Gch Output bridges gain mismatch -0.5 0.5 dB

O b Pout Continuous Output Power THD = 0.5%

THD = 10%
75
95
80
100
W
W

THD = 10%; RL= 4; VCD+ = 16V; 90 100 W

VCD- = -16V; VS+ = 22V; VS- = -22V

THD Total harmonic distortion of the Po = 5W 0.01 0.1 %

output bridge
f = 20Hz to 20KHz; Po = 50W 0.2 %

VOff Output bridge D.C. offset -70 70 mV

5/20
 STA575

ELECTRICAL CHARACTERISTCS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

EN Noise at Output bridge pins f = 20Hz to 20KHz; Rg = 50 12 V

Zbr_in Input impedance 100 140 180 K

Rdson Output power Rdson IO = 1A 200 400 m

OLG Open Loop Voltage Gain 100 dB

GB Unity Gain Bandwidth 1.4 MHz

SR Slew Rate 8 V/s

PROTECTION

( s )
Vstby Stby voltage range

c t 0 0.8 V

Vmute Mute voltage range

d u 1.6 2.5 V

Vplay Play voltage range

r o s ) 4 5 V

Th1 First Over temperature threshold

e P c t ( 130 C

Th2 Second Over temperature

threshold
l e t d u 150 C

Unbal. Upper Unbalancing ground

s o r o
Referred to (CD+ - CD-)/2 5 V
Ground threshold

O b e P
Unbal.
Ground
Lower Unbalancing ground
threshold
- l e t Referred to (CD+ - CD-)/2 -5 V

UVth
( s )
Under voltage threshold
o |Vs+| + |Vs-| 18 20 22 V

Pd_reg.
c t b s
Power dissipation threshold for Iprot = 50A; @ Vds = 10V 26 32 39 W

u
system regulation

d - O
Pd_max
r o
threshold
s )
Switch off power dissipation @ Vds = 10V 60 W

Iprot
e P c t (
Protection current slope for Pd > Pdreg 400 A/W

l
Ilct
e t d u
Limiting Current threshold 6.3 7 7.5 A

s o r o
O b I+Vs

e P
Positive supply current Stby (Vstby/mute pin = 0V) 5 7 mA

l e t Mute (Vstby/mute pin = 2.5V)

Play (Vstby/mute pin = 5V no signal)
20
20
35
35
50
50
mA
mA

s o
I-Vs Negative supply current Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V) 20
5
35
7
50
mA
mA

O b ICD+ Positive traking rail supply current

Play (Vstby/mute pin = 5V no signal)

Stby (Vstby/mute pin = 0V)

20

50
35

100
50

200
mA

A
Mute (Vstby/mute pin = 2.5V) 60 110 180 mA
Play (Vstby/mute pin = 5V no signal) 60 110 180 mA

ICD- Negative traking rail supply current Stby (Vstby/mute pin = 0V) 50 100 200 A
Mute (Vstby/mute pin = 2.5V) 60 110 180 mA
Play (Vstby/mute pin = 5V no signal) 60 110 180 mA

6/20
 STA575

FUNCTIONAL DESCRIPTION
The circuit contains all the blocks to build a stereo amplifier. Each single channel is based on the Output Bridge
Power Amplifier, and its protection circuit. Moreover, the compression function and a signal rectifier are added
to complete the circuit.
The operation modes are driven by The Turn-on/off sequence block. In fact the IC can be set in three states by
the Stby/mute pin:
Standby ( Vpin < 0.8V), Mute (1.6V < Vpin < 2.5V), and Play (Vpin > 4V).
In the Standby mode all the circuits involved in the signal path are in off condition, instead
in Mute mode the circuits are biased but the Speakers Outputs are forced to ground potential.
These voltages can be get by the external RC network connected to Stby/Mute pin.
The same block is used to force quickly the I.C. In standby mode or in mute mode when the I.C. dangerous

s )
condition has been detected. The RC network in these cases is used to delay the Normal operation restore.

(
c t
The protection of the I.C. are implemented by the Over Temperature, Unbalance Ground, Output Short circuit,
Under voltage, and output transistor Power sensing as shown in the following table:

d u
Table 1. Protection Implementation
r o s )
Fault Type Condition

e P c t (
Protection strategy Action time Release time
Chip Over
temperature
Tj > 130 C

l e t Mute

d u
Fast Slow Related to
Turn_on sequence
Chip Over
temperature
Tj > 150 C

s o r o
Standby Fast Slow, Related to
Turn_on sequence
Unbalancing
O b
|Vgnd| > ((CD+) -
e P
Standby Fast Slow, Related to
Ground (CD-))/2 + 5V
- l e t Turn_on sequence
Short circuit

( s )
Iout > 7A

o
Standby Fast Slow, related to
Turn_on sequence
Under Voltage
c t b s
|Vs+| + |Vs-|< 20V Standby Fast Slow, related to

d u - O Turn_on sequence
Extra power
dissipation
r o Pd tr. > 32W

s )
Reducing DIGITAL
CONVERTER output
Related to the
DIGITAL
Related to the
DIGITAL

e P
at output transistor

c t ( voltage. CONVERTER CONVERTER

l e t
Maximum power
dissipation
at output transistor
d u
Pd tr. > 60W Standby Fast Slow, related to
Turn_on sequence

s o r o
See the POWER PROTECTION paragraph for the details

O b e P
l e t
Compression

s o
An other important function implemented, to avoid high power dissipation and clipping distortion, is the Com-
pression of the signal input. In fact the preamplifier stage performs a voltage gain equal to 5, fixed by Ri and Rr

O b
external resistor, but in case of high input signal or low power supply voltage, its gain could be reduced of 26dB.
This function is obtained with a feedback type compressor that , in practice, reduces the impedance of the ex-
ternal feedback network. The behavior of compression it's internally fixed but depends from the Audio input volt-
age signal level, and from the Threshold voltage applied to the Threshold pin. The attack and release time are
programmable by the external RC network connected to the Att_Rel pins.
The constraints of the circuit in the typical application are the following:
Vthreshold range = -5 to 0
Vin peak max = 8V
Vout peak max = 10V

7/20
 STA575

Gain without compression (G) =5

Max Attenuation ratio = 26 dB
The following graph gives the representation of the Compressor activation status related to the Vthreshold and
the input voltage. The delimitation line between the two fields, compression or not, is expressed by the formula :
2 ( Vth resho ld + 200 mV )
--------------------------------------------------------------------------
G

Where G is the preamplifier gain without compression.

In the compression region the gain of the preamplifier will be reduced
(G = 2Vthreshold/Vin) to maintain at steady state the output voltage equal 2*|Vthreshold| .
Instead in the other region the compressor will be off (G = 5).

( s )
The delimitation line between the two fields can be related to the output voltage of the preamplifier: in this case
the formula is :
c t
u
V out = 2 ( Vthre sho ld + 200mV )

d
r o s )
Figure 1. Compressor activation field

e P c t (
VIN PEAK
l e t d u
s o r o
O b
8

e P
- 6
l e t
( s ) o COMPRESSION

c t b
4 s G<5

d u - O 2

r o s ) G=5

e P c t ( D01AU1264 1 2 3 4 5
|Vthreshold|

l e t d u
o r o
The relative attenuation introduced by the variable gain cell is the following :
s
O b e P 2 ( V th + 200 mV )
Atten uation = 20 log --- ------------------------------------------

l e t 5 V in_peak

s o
The total gain of the stage will be:
Gdb = 20log5 + Attenuation

O b
The maximum input swing is related to the value of input resistor, to guarantee that the input current remain
under Iin_Max value (1 mA).
V in_peak
R i > ----------------------
I in_max

8/20
 STA575

Figure 2. Compressor attenuation vs. input amplitude

Attenuation(dB)

-6

-12 |Vth
=5|
|Vth
-18 |Vt
( s ) =2.
5|

c t h=
1|
-24

d u
r o s ) |Vinpk|
D01AU1265 1 2 3

e P 4 5

c t ( 6 7 8

ABSOLUTE VALUE BLOCK

l e t d u
The absolute value block rectifies the signal after the compression to extract the control voltage for the external

s o r o
digital converter. The output voltage swing is internally limited, the gain is internally fixed to 14.

O b
rectification (between Out_pre and Trk pins).
e P
The input impedance of the rectifier is very high , to allow the appropriate filtering of the audio signal before the

- l e t
OUTPUT BRIDGE
( s ) o
c t b s
The Output bridge amplifier makes the single-ended to Differential conversion of the Audio signal using two

d u - O
power amplifiers, one in non-inverting configuration with gain equal to 2 and the other in inverting configuration
with unity gain. To guarantee the high input impedance at the input pins, Pwr_Inp1 and Pwr_Inp2, the second

r o )
amplifier stages are driven by the output of the first stages respectively.

s
e P
POWER PROTECTION
c t (
l e t d u
To protect the output transistors of the power bridge a power detector is implemented (fig 3).

o r o
The current flowing in the power bridge and trough the series resistor Rsense is measured reading the voltage
s
drop between CD+1 and CD+. In the same time the voltage drop on the relevant power (Vds) is internally mea-

O b P
sured. These two voltages are converted in current and multiplied: the resulting current , Ipd, is proportional to
e
l e t
the instantaneous dissipated power on the relevant output transistor. The current Ipd is compared with the ref-
erence current Ipda, if bigger (dissipated power > 32W) a current, Iprot, is supplied to the Protection pin. The

s o
aim of the current Iprot is to reduce the reference voltage for the digital converter supplying the power stage of
the chip, and than to reduce the dissipated power. The response time of the system must be less than 200Sec

O b
to have an effective protection. As further protection, when Ipd reaches an higher threshold (when the dissipated
value is higher then 60W) the chip is shut down, forcing low the Stby/Mute pin, and the turn on sequence is
restarted.

9/20
 STA575

Figure 3. Power Protection Block Diagram

RSENSE

CD+1 CD+

ILOAD
V/I OC1
TO TURN-ON/OFF
SEQUENCE
ILIM CURRENT COMP

MULTIPLIER X

( s ) IPD
PDP1
TO TURN-ON/OFF
V/I
c t SEQUENCE

I_PD
d u IPDP CURRENT COMP

r o s ) IPD IPROT

OPA
e P c
OPAt ( TO PROT PAD

l e t d u IPDA

s o r o
OUT1+ CD-
O b OUT1-
e P D01AU1266

- l e t
( s )
In fig. 3 there is the power protection strategy pictures. Under the curve of the 32W power, the chip is in normal
o
c b s
operation, over 60W the chip is forced in Standby. This last status would be reached if the digital converter does
t
not respond quikly enough reducing the stress to less than 60W.

u O
The fig.4 gives the protection current, Iprot, behavior. The current sourced by the pin Prot follows the formula:
d -
r o s ) ( Pd Pd_av _th ) 5 10
4
Iprot ------------------------------------------------------------------

e P c t ( 1.25V

l e t d u
for Pd < Pd_av_th the Iprot = 0
Independently of the output voltage, the chip is also shut down in the folowing conditions:

s o r o
When the currentthrough the sensing resistor, R sense, reaches 7A (Voltage drop (CD+) - (CD+1) = 700mV).

O b P
When the average junction temperature of the chip reaches 150C.
e
l e t
When the ground potential differ from more than 5V from the half of the power supply voltage, ((CD+)-(CD-))/2
When the sum of the supply voltage |Vs+| + |Vs-| <20V

s o
The output bridge is muted when the average junction temperature reaches 130C.

O b

10/20
 STA575

Figure 4. Power protection threshold Figure 5. Protection current behaviour

Ids mA)
(
Ilim = 6A Iprot(mA)
7
6
20
Standby
Bu

4 Pd_M ax =48W
cK

Li 10
mi Iprot slope=0.4mA/W
2 ta
Normal ti Pd_reg = 25W
Operation on

( s )
10 20 30 40 50
c t Vds (V
D01AU1268 10 20 30 40 50 60
Pd(W)

d u
r o s )
Figure 6. Test Circuit for STA575 Stand-alone

e P c t (
l e t d u
o o
C17 C5

r
R7 R11

b s P R3
C7
R9 C1

- O e t e OUT_PRE1 TRK_1 PWR_INP1

s ) o l
INPUT1
R1
8
9 10 7
4
OUT1+

c t ( b s R5
IN_PRE1
ATT_REL1
3 5
5V

d u - O C3 OUT1- R13

r o s ) R16 CD+1
6 R14
CD+

e P c t ( R17
CD+
CD+2
15
11
STBY/
MUTE
MUTE STBY

l
+VS
e t C12

d u
R24
+VS
22
14
C9 R15

s o r o C14 C10
GND
13 OUT2+

O b e P C13 R22 C15 C11

24

-VS

l e t D1
-VS
-VS
27
1
23
OUT2-
C4

s oCD-
CD-1
2
26

O bTRK-OUT

R20
PROT
THRESH
CD-2
TRK-OUT
PROT
16
12
17
25

20
ATT_REL2
IN_PRE2
R6

INPUT2
R19 THRESH 21 18 19 R2
R18 PWR_INP2 TRK_2 OUT_PRE2

C2 R10 R4
C8

R12 R8
C6 C16
D01AU1267

11/20
 STA575

EXTERNAL COMPONENTS (refer to fig. 6)

Name Function Value Formula

Ri Input resistor 10K Rr

R1 = R2 (|G| = 5, Rr = 50K) R i = -------
G

Rr Feedback resistor 50K Rr = G Rr

R3 = R4 (|G| = 5, Ri = 10K
Cac AC Decoupling capacitor 100nF 1
Cac = ---------------------------------
C1 = C2 (fp = 16Hz, 2 fp Rac
Rac =100K )
Cct Capacitor for the attack time 2.2F Ict
Cct = attack -------------------------

)
C3 = C4 (Tattack = 13mSec, Vcontrol

t ( s
Vcontrol = 9V,
Ict = 1.5mA)
R5 = R6 Release constant time Resistor
u c 470K
Rct = ---------

o d (t = 1 Sec. ,
Cct = 2.2 F )
)
Cct

R7 = R8
P r
Resistor for tracking input voltage
( s 10K
filter

t e c t
R9 = R10
filter
l e d u
Resistor for tracking input voltage 56K

R11 = R12
s o r o
Resistor for tracking input voltage 10K
filter

O b e P
C5 = C6
-
voltage filter
l e t
Capacitor for Tracking input 1nF

( s ) o
s
C7 = C8 Dc decoupling capacitor 1F
R13
c t b
Bias Resistor for Stby/Mute 10K

d u function

- O
R14

r o )
Stby/Mute constant time resistor

s
30K
R15

e P c t (
Mute resistor 30K

l e t
C9
R16 = R17
d u
Capacitor for Stby/Mute resistor
Sensing resistor for SOA detector
2.2F
100m

s o r o 5% 4W

O b R18

e P Conversion resistor for threshold

voltage
100K

l e t
C10 = C11 Power supply filter capacitor 100nF

s o R22 = R24 Centering resistor 400 , 1W

O b C12 = C13
R19
Tracking rail power supply filter
Protection
680nF
1K

R20 TRK_out 40K

C14 = C15 Power supply filter capacitor 470 F , 63V
C16 = C17 Feedback capacitor 100pF
D1 Schottky diode SB360
Note: Vcontrol is the voltage at Att_Rel pin.

12/20
 STA575

APPLICATION HINTS (refer to fig. 6)

PREAMPLIFIER AND COMPRESSOR
In the test circuit showed in figure 6, R1/R3 (or R2/R4) ratio fix the gain of the preamplifier.
If the input signal is very low, is possible to increase the gain fixing the product VinG = cost.
In that case is possible to increase G decreasing R1,2 from 10K until 2K without relevant effetcs on the cir-
cuitbehavior and remaining in the operating range Iin_max = Vin_max/R1(2),<1mA.
So it is possible to increase the preamplifier gain until 25.
If no compression is present (equivalnt compressor Gm=0), the effects are:
The output voltage offset increase
The SNR decrease
The following table shows these variations:
( s )
R1,2 VIN MAX G
c t VOFFSET EN

10K 8V
d u
5 15mV 10V

5K 4V
r o 10
s ) 30mV 13V

2K 1.6V
e P 25
c t ( 75mV 20V

l e t d u
R3(4) = 50K and all the other external components are the same
Attenuation = 0 dB
s o r o
b P
If the compression is active the circuit behaviour is the same.

O e
- l e t
Its also possible to eliminate the compressor. In this case the ATT_REL (1,2) pin must be connected to gnd.

STBY-MUTE CIRCUIT
( s ) o
c t b s
In the suggested application circuit (figure 6), the resistor for Standby/Mute function (R13) is connected between

d u - O
the Standby/Mute switches and 5V Supply.
It is possible to connect the resistor to another Supply Voltage level VL, but in that case also the resistor value

r o )
(R13,14) must be changed according to the following formula (fixing VSTBY/MUTE = 2.5V and R15 = 10K):
s
e P c t ( R 13 = ( 4 VL 10 )K

l e t d u
s o r o R 14 = ( 4 VL + 10 )K

O b
HEADROOM
e P
l e t
In the suggested application circuit the supply voltage to obtain 75W (Power Output) on 8 (Rload)
is:

s o
O b V supply = V + I L, MAX R DS on

It is also possible to increase the systems efficiency forcing the headroom to follow the output signal (variable
drop insteadof a constant drop).
In that case:
V sup ply = V + IL ( V ) RDS on

13/20
 STA575

Figure 7. BASH module SAM351 5.1 with 2 x STA575 (see application note AN1656)

+50VDC Signal Power Supply

+/-24V DC / 50
mA

Dynamic Power Supply

(CD+ & CD-)
Buck STA575
Regulator 2 x100Watts

Audio
Inputs
Lines of Controls

STABP01 STA575 6 Ohm Loads

Controller 2 x 100Watts

( s ) Audio

t
Input

u c STA575

d
2 x 100Watts

r o s )
e P c t (
t
+/-24V DC / 50
mA

l e d u Signal Power Supply

s o r o
Power - On-Off sequences:

O b e P
In order to avoid damages to the SAM261 board it is important to follow these sequences:

- e t
At Power-On apply in the first the Auxiliary Power Supply (24V) and after the Main Power Supply
l
( s )
(+50V), in this condition the system is in "Mute state" and it can move in "play state" with the switch present
o
on the pcb.

c t b s
At Power-Off is better to bring the SAM module in "Mute state" and after that to follow this order: switch-

u O
off the Main Supply Voltage (+50V) and subsequently the Auxiliary Power Supply. (24V).
d -
r o s )
System Description & Operating Rules

e P c t (
SAM351 is a BASH 5.1 amplifier ( 6 x 100W) implementation utilizing the STA575 Integrated Circuit.

e t u
Specifically designed for multi-channel implementation in DVD - HTIB systems, Multi-Media systems, AV Re-
l
ceivers.
d
s o r o
SAM351 is dimensioned to provide the maximum Output Power (THD=10 %) on two channels and instanta-

O b e P
neously and 1/3 max Pout on the remaining Outputs, or 1/8 of max Pout continuous; this rule is important to
define the main Power Supply size (+50V).

l e t
s o
Buck Regulator Description
The function of the buck regulator is to convert efficiently an input voltage to a lower voltage by adjusting the

O b
ratio of the switching transistor's on-time to off-time. The resulting waveform is averaged by the output filter to
recover an analog signal.
In the BASH amplifier this output is in effect split in half by centering it on the audio ground to provide CD+ and
CD- rails.
To avoid the need for a high side driver for the transistor switch in the buck regulator the buck circuit recom-
mended has the switch in the return path. Hence the gate drive circuit (part of the STPB01) is referenced to the
negative return of the main supply that provides power for the buck regulator.

14/20
 STA575

Interfacing STA575 to STPB01 (Feedback circuit)

This circuit produces a control signal current that is fed back to the STPB01 digital controller. The network used
in this example compares the track signal (STA575 track out) to a fixed ratio of buck regulator's output (CD+)
using a transistor. This method is effective because the controller's reference is the negative of the main DC
supply, which is not referenced to audio ground.
The tracking signal is generated inside the STA575 (track out) by taking the absolute value of the pre-amp's
output. The outputs of each channel and of each STA575 are then tied together in a diode-oring arrangement.
This means that the highest of any given output is the output that determines the tracking signal.
The absolute value circuit inside the STA575 has gain. This makes it possible to use an RC network and a re-
sistor divider to create a phase shift in the tracking signal at higher frequencies. This is also useful in optimizing
the alignment of the buck regulator's output with the output signal of the bridge amplifier at high frequency
This circuit first converts the buck switch current to a peak voltage. The control current is then converted to a

s )
voltage (using a resistor) and added to the peak voltage. By doing this, the buck is better able to maintain the
(
desired headroom over a wide load range and output level.

c t
Centering Network for CD+ & CD- Rails
d u
r o )
The power rail of a bridge amplifier has no current flowing through the ground node, as the load is not connected
s
P t (
to ground. However there are several different small sources of dynamic and continuos ground currents flowing

e c
from either CD+ or CD- to support the function of various things such as the control signal to the STABP01 con-
troller.

l e t d u
s r o
The centering network prevents these currents from shifting the CD+/- rails away from center i.e. away from a
o
symmetric split of the buck's output about ground. This is critical, even a small centering error requires an in-

O b e P
crease in headroom which results in a significant drop in output losses. In its simplest form the centering network
could be a resistor divider from CD+ to CD- with its center tied to ground.

- e t
As long as the impedance is low enough (for example 200 ohms) this will swamp the smaller offset currents. It
l
) o
is helpful to put this kind of passive network on the board with the STA575 devices to help when testing this

( s
board on its own.

c t b s
d u O
Power Amplifier Heatsink requirements
-
r o )
The heatsink requirements are dependent on several design goals. However there are two common references:
s
e P c t (
Pink noise at 1/8 of full power, all channels loaded. This would approximate a system with all channels repro-
ducing music at full volume with clipping occurring only occasionally. The second would be full power at 1kHz

l e t d u
for 5 minutes after a one hour pre-soak at 1/8 power.
The worse of these two is the full power test. A conservative approach is to assume that the heatsink would
o r o
come to thermal equilibrium after 5 minutes. Thus the Rth of the heatsink can be determined by:
s
O b e P T jmax T amb
R th heatsink = ---------------------------------- R th j R th

l e t Pd ca se c as e to heatsink

s o
For example in the STA575 the Rth jc is 1C / W. R case-to-heatsink with grease is about 0.5C / W. The max-
imum operating junction temperature is 130C, which for margin should be derated to 120C

O b
Buck Regulator Heatsink
The Buck regulator heatsink can be designed in a similar manner and does not change by varying power supply.
In general the efficiency will be in the order of 85%. The thermal impedances from the junction(s) to the heatsink
may be lower and the maximum operating temperature will be higher.
Usually either the sub or the remaining channels are tested at full power. The result is that usually the Buck
heatsink is about the size of the linear heatsink, but this can be strongly affected by the design.

15/20
 STA575
Figure 8. PCBs AND COMPONENTS LAYOUT

4 Pin Harness
50 VDC Power Supply Connections
Input

+/-24 VDC
Input

Mute

Channel 1 and 2

Channel 3 and 4

( s )
c t
u
Channel 5

o d )
r
Channel 6

P t ( s
t e u c
o l e d
9 Pin Harness
Audio Connections

o
b s P r
SAM261 Specification
- O e t e
Parameter

s ) o l Rating Notes

Output Power

c t ( s
100Watts @10% - 6
b
see graphs

THD + N

d u - O
< 0.05% @ 40 Watts
< 0.05% @ 75 Watts
Measured @ 1KHZ

SNR
r o s )
-104 dB (relative to full power)

e P c t ( -113 dB (A-weighted)

l e t
Sensitivity

d u 1 .3VRMS Amplifier

s o
Crosstalk

r o -76dB (relative to10W) 1KHz 8 Ohms,

O b e P
Main Power Supply Inputs 60Volts @ 4 Amps Maximum Voltage is 60V
Minimum Voltage is 50V

l e t
Aux Power Supply Inputs + 24 Volts @ 100mA Vs supply

s o -24 Volts @ 100mA

O b
Input Board 1 .3VRMS Suplied to facilitate testing

16/20
 STA575

Figure 9. THD +N FR Channel Figure 11. Residual Noise vs. Frequency

Audio Precision Audio Precision

10 +0

5
-20

2
-40
1
-60
0.5
dBr
% -80
0.2
-100
0.1

0.05
-120

-140
0.02

0.01
10 20 30 40 50 60 70 80 90 100 110 120 130 140
-160
20 50 100 200 500 1k 2k 5k

( s ) 10k 20k

t
W Hz

Figure 10. THD + N Frequency Figure 12. Frequency Response

u c
o d )
Audio Precision Audio Precision

r s
P t(
10 +40
+38
5 +36
+34

t e u c
e
+32

l d
2
+30
+28

0.5
1

s o
+26
+24

r o
P
+22
%
0.2
Pout = 30W

O b
dBr +20
+18
+16

e
0.1
Pout = 80W

-
+14
+12
+10

le t
0.05

( s ) o
+8
+6

s
+4

t
0.02 Pout = 5W +2

0.01
20 50 100 200 500
Hz

u
1k 2k
c 5k 10k 20k

Ob +0
10 20 50 100 200 500
Hz
1k 2k 5k 10k 20k 40k

o d ) -
P r ( s
e t e u ct
o l o d
b s Pr
O t e
o l e
b s
O

17/20
 STA575

Figure 13. APPICATION BLOCK DIAGRAM

+VS
STA575
-VS 2 CHANNELS

+VS MUTE MUTE

MUTE MUTE CONTROL &
-VS THRESHOLD THRESH-REF THRESH-REF
MUTE REFERENCE OUT1+
IN1
MUTE-BUCK OUT1- J1
RED
OUT2+
IN2
+VS +VS MUTE-BUCK OUT2- J2
TRACK WHITE
-VS -VS J1
PROT CD- TRACK
DC++
CD+ PROT
GATE-DRIVE BUCK CONTROLLER
I-SENSE
PWM-SPLY
CD-

( s )
CD+

c t STA575
PROT

u CD+ 2 CHANNELS
TRACK
PWM-SPLY

o dCD+
CD-

)
CD-
MUTE

r
1800pF I-SENSE

s
OUT3+

(
GATE-DRIVE IN3
DC++
GND
L2
DC++
300W BUCK

e P c t RED
OUT3-

OUT4+
J3

15H
1800pF

l e t d u
-VS J2
IN4
WHITE
OUT4- J4

s o r o +VS -VS
+VS

O b e P CD+ STA575
2 CHANNELS PROT

t
CD-
TRACK

) - l e
MUTE-LIN
-VS

t ( s s o J3
+VS
OUT5+

b
RED IN5

u c O
R77
OUT0-

OUT6+
J5

o d ) - R78
IN6
OUT8- J6

r
J4

s
D02AU1454

e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

18/20
 STA575

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.45 4.50 4.65 0.175 0.177 0.183 OUTLINE AND
B 1.80 1.90 2.00 0.070 0.074 0.079 MECHANICAL DATA
C 1.40 0.055
D 0.75 0.90 1.05 0.029 0.035 0.041
E 0.37 0.39 0.42 0.014 0.015 0.016
F (1) 0.57 0.022
G 0.80 1.00 1.20 0.031 0.040 0.047
G1 25.75 26.00 26.25 1.014 1.023 1.033
H (2) 28.90 29.23 29.30 1.139 1.150 1.153
H1 17.00 0.669
H2 12.80 0.503
H3 0.80 0.031
L (2)
L1
22.07
18.57
22.47
18.97
22.87
19.37
0.869
0.731
0.884
0.747
0.904
0.762

( s )
L2 (2)
L3
15.50
7.70
15.70
7.85
15.90
7.95
0.610
0.303
0.618
0.309
0.626
0.313
c t
L4
L5
5
3.5
0.197
0.138
d u
M
M1
3.70
3.60
4.00
4.00
4.30
4.40
0.145
0.142
0.157
0.157
r o0.169
0.173
s )
N
O
2.20
2 P
0.086
0.079

e c t (
R
R1
1.70
0.5
l e t0.067
0.02
d u
o o
R2 0.3 0.12
R3
R4
V
1.25
0.50
b s
5 (Typ.)
0.049

P
0.019r
V1
V2 O
3 (Typ.)

-
20 (Typ.)
e e
Flexiwatt27
t
(vertical)
V3

s ) 45 (Typ.)

o l
( s
(1): dam-bar protusion not included

c t
(2): molding protusion included

b
d u - O
r o V

s ) C

e PB
c t (
l e t d u H
V

s o r o V3
H1
H2 A

b P
H3
O

O t e
R3

l e R4
L4

V1

s o N
R2
L2

O b R
L L1
V1
L3

V2

R2 D
R1

L5 R1 R1
Pin 1
E
G G1 F
FLEX27ME
M M1

7139011

19/20
 STA575

( s )
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

O b
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

2003 STMicroelectronics - All Rights Reserved
is the registered trademark and patented technology of INDIGO manufacturing inc.

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20/20