L875 GL10FG 6050a2492401-Mb 20110831

8 7 6 5 4 3 2 1
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.
F HSF Property:ROHS or Halogen-Free(5L3?) F
E E
GL10FG D
2011.08..31
C C
B B
A A
DRAWER
DESIGN
EE DATE POWER DATE
INVENTEC
CHECK TITLE MODEL,PROJECT,FUNCTION
RESPONSIBLE Everest Main Board
21-OCT-2002 SIZE= VER: SIZE CODE DOC.NUMBER REV
FILE NAME: C CS 1310xxxxx-0-0 X01
DATE CHANGE NO. REV P/N XXX SHEET 1 of 76
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
TABLE OF CONTENTS
D
PAGE PAGE PAGE
1. COVER PAGE 26. SPEAKER/HP JACK/MIC JACK 51. CPU 5 POWER

2. INDEX 27. AMP 52 .CPU 6 GND
3. BLOCK DIAGRAM 28. CARDREADER 53. PCH 1
4. POWER MAP 29. MINI1 WLAN/DEBUG CARD 54. PCH 2
5. POWER CHARGER 30. MINI2 3G/LTE 55. PCH 3
C 6. POWER +V3LA/+V3A/+5A 31. B-CAS 56. PCH 4 AXG
C
7. POWER +V1.5/+V0.75 32. SATA HDD/ODD CONN

33. USB 2.0 CONN 57. PCH 5 USB
8. POWER +V1.8S 58. PCH 6 MISC
9. POWER VCCIO 34. USB 3.0 CONTROLLER 59. PCH 7 POWER
10. POWER VCCSA 35. USB 3.0 CONN W/ S&C 60. PCH 8 POWER
11. POWER VCORE 36. USB 3.0 CONN 61. PCH 9 GND
37. EDP CONN
12. POWER VGFX 38. LCM CONN 62. VGA 1
13. POWER VCORE_DGPU 39. CRT CONN 63. VGA 2
14. LNB POWER 40. HDMI CONN 64. VGA 3
15. ENABLE PIN 41. HDMI CEC 65. VGA 4
B 16. LOAD SWITCH-1 42. DDR3 DIMM0 66. VGA 5 B
17 LOAD SWITCH-2(FOR OPTIMUS) 67. VRAM 1
18. PCB SCREW 43. DDR3 DIMM1 68. VRAM 2
19. HALL SENSOR 44. DDR3 DIMM0 69. VRAM 3
20. LED 45. DDR3 DIMM1 70. VRAM 4
21. K/B & TP/B CONN 46. FAN & THERMAL SENSOR 71. POWER BUTTON BOARD
22. EC 47. CPU 1 72. EMI
23. LAN 48. CPU 2 73. 3D SENSOR
24. RJ45 & TRANSFORMER 49. CPU 3 DRAM 74. CIR
50. CPU 4 POWER 75. USB3.0 REDRIVER
25. AUDIO CODEC
A A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 2 of 76
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR3@1.5/0.75V
(1333/1600 MHZ)
NVIDIA IVY BRIDGE DDR3 INTERFACE
204-PIN SODIMM0
PEG DC 45W
W/ OPTIMUS DDR3@1.5/0.75V
SOCKET-RPGA989 (1333/1600 MHZ)
N13P-GL/GS 37.5 X 37.5 X 5 mm 204-PIN SODIMM0
29X 29 MM
D DDR3@1.5/0.75V D
DDR3 INTERFACE
(1333/1600 MHZ)
FDI DMI 2.0
204-PIN SODIMM0
DDR3@1.5/0.75V
(1333/1600 MHZ)
204-PIN SODIMM0
EDP INTERNAL MIC IN

AUDIO CODEC EXT MIC IN
HDA
C
HDMI & CEC REA_ALC280Q_GRT_QFN_48P C
HEADPHONE
JUMPER PCH AMP
LCM PANTHER POINT
USB2.0 USB_5: MINICARD WLAN
25 X 25 X 2.3 mm
USB_10:WEBCAM
USB_11: TV2
CRT USB_12:3D
USB_13: TV
SLEEP & CHARGE
B
USB_0: USB3.0 CONN B
PCIE_1:LAN USB3.0
USB_1: USB3.0 CONN
RJ45 PCIE USB_2: USB3.0 CONN
ATHEROS_AR8161/8162 USB_3: USB3.0 CONN
PCIE
PCIE_2:WLAN SATA SATA0: HDDB
PCIE SATA1: HDDA
CARD READER
SATA2: MINICARD/B-CAS
REA_RTS5229
SPI SPI FLASH 2MB SATA5: ODD
A ENE-P2809A EC WINDBOND SPI SPI FLASH 4MB

A
THERMAL SENSOR NPCE885LA0DX
BATTERY CHARGER &

DC/DC & IMVP 7
KEYBOARD TOUCH PAD INVENTEC
LI-ION BATTERY TITLE
6-Cell Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ADAPTOR +VBAT +V5A_+-5% +V5S
FUSE BQ24725RGRR TPS51123 AO6402L

CHARGER
EC_SMB2 POWER BUDGET 12.139 A POWER BUDGET 4.711A INRUSH 0.9A
65W-75W 8A 6036A0003401 CHG_EN F 300K PEAK2.592A 100.82UF_0.842M
90W 10A 6036A0002901 BATT_IN OCP 10.4A R=120K +V0.85S_+-0.5%
120W 12A 6036A0006001 ACPRES PEAK 7.283A AVG 2.363A
D 220UF_25M // 53.92UF_1.529M TSP51461
D
POWER BUDGET 6A
F 340K
BATTERY PACK OCP 6A
PEAK 6A AVG 1.262A
+VCORE_+-0.5% +V3LA_+-5%
+V3A +V3_LAN
+VCORE1_+-0.5% TPS51123 AO6402L AM2321P
TI_TPS61640
POWER BUDGET 9.429 A POWER BUDGET 4.711AINRUSH 0.9A POWER BUDGET 4.711A INRUSH 0.9A
POWER BUDGET 53A F 375K PEAK2.592A
100.82UF_0.842M PEAK2.592A 100.82UF_0.842M
F 280K OCP 10.7A R=130K +V3S +V1.8S
OCP 53A PEAK 5.695A AVG1.048 A
C PEAK 53A AVG 28.822A 220UF_25M //10.6UF_5.924M AO6402L GMT_AT1530F11U C
1880UF_1.1M // 2276UF_0.203M
VDD_CORE POWER BUDGET 4.711A INRUSH 0.9A POWER BUDGET 4.711A INRUSH 0.9A
PEAK2.592A 100.82UF_0.842M PEAK2.592A 100.82UF_0.842M
TPS51217
POWER BUDGET 20.070A V1.5_+-5% +V0.75S
F 340K
OCP 29.1A R=75K
PEAK 20.070A AVG 11.531A TPS51216 TPS51216
560UF_25M // 80UF_0.93M
POWER BUDGET 13.7 A +V1.5S
F 340K
OCP 10.1A R=115K
PEAK 17.107A AVG4.835 A
B
560UF_25M // 1274.8UF_0.214M AON7410 B
+V1.5_CPU
AON7410
+VTT_+-5%
TPS51216
POWER BUDGET 13.7 A
CHANGING POINTS~~ F 340K
A TPS51218 SAME AS 2009 PROJECT OCP 10.1A R=115K A
TPS51217 SAME AS 2010 PROJECT PEAK 17.107A AVG4.835 A
+V1.8S IS NEW IC GMT_AT1530F11U 560UF_25M // 1274.8UF_0.214M
CHARGE IS NEW IC BQ24725
VCC CORE IS NEW IC TPS51640
VTT IS NEW IC TPS51219
V0.85 IS NEW IC TPS 51641
V3_V5 IS NEW IC TPS51123
POWER BUDGET ~~IC SPEC (MAX CURRENT ) INVENTEC
PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION TITLE
AVG CURRENT ~~TEST RESULT(MAX CURRENT) MODEL,PROJECT,FUNCTION
Block Diagram
INRUSH ~~L/S TURN NO DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FUSE6000
65W-75W 8A(6036A0003401)
90W 10A(6036A0002901) TP60001 TP60011 TP6002 PVPACK
1 PVADPTR PVBAT FUSE6050
120W 12A(6036A0006001)
TP30 TP30 TP30 P3V3AL 1 2
L7600
1
CN6000 FUSE6000 NFE31PT222Z1E9L
2
C6050 LITTLEFUSE_R451015_15A_65V
1 1 1 2 1 2 R6053
R6054
1
2 2 R6800 1 2 1 2 1000PF_50V_2
3 3 8A_125V C7602 RSC_0603_DY
4 1M_5%_2 CN6050
220K_5%_2
2
4
C7601 1
10PF_50V_2
1
BATT+
ACES_91202_0047N_TSB_4P 1000PF_50V_2 2 BATT+
R6802
OUT HW_V_ADC 1 2 3
2
ID
R6052
1 1K_5%_2
2 4
33K_5%_2_DY 22E8 22E6 OUT B-I
BATT_IN
1
5
2
1 TP6003
1 TP60041 TP6005 TS
R6050
1 33_5%_2
2 6 G1
D 73C5 73C5 22D3 22D2 BI SMD G
TP30 TP30 TP30 22D2 EC_SMB1_DATA 1 2 7 G2
R6801 22D3 EC_SMB1_CLK
BI SMC G
D
8 G3
2
C6800 R6051 33_5%_2 GND G
RSC_0603_DY 9 G4
0.1UF_16V_2_DY GND G
NEAR EC
2
R6015
1
1 2 D6701 D6702 D6703 SYN_200045GR009G15JZR_9P
PVADPTR EZJZ0V500AA_DY EZJZ0V500AA_DY EZJZ0V500AA_DY
4.7K_5%_3
1
1 R6014 2
RSC_0603_DY PVBAT PVPACK
Q6010 Q6011
R6000 Q6012 C6033
8 D S 1 1 S D 8 1 2 8 D S 1 1 2
7 2 2 7 3 4 7 2
6 3 3 6 0.01_1%_6 6 3 0.1UF_25V_3
RSC_1206_DY CSC0805_DY
5 G 4 4 G 5 5 G 4
1
NMOS_4D3S NMOS_4D3S NMOS_4D3S

C6020
C6014
1
AM4410NC AM4410NC 1 2 TPCA8065_H
C6030 C6031
1 2 1 2 0.1UF_16V_2 TP6006 TP6007 TP6008
1 1 1
1
PAD6000
2
PVADPTR POWERPAD_2_0610 TP30 TP30 TP30
1
2200PF_50V_2 0.1UF_25V_3
2
C C
RSC_1206_DY
R6006
1
1
1 2 3
2
D6000
R6018
2 R6019
RSC_0603_DY D6002
2
1 2
2
DIODES_BAV99 A1 A2
P3V3AL
R6002 C6021 C6022
C
2
R6004 R6005 0.1UF_25V_3
20.5K_1%_2
2
4.3K_5%_2 4.3K_5%_2 BAT54C_30V_0.2A
2
0.1UF_25V_3
2
3
1
5
6
7
8
R6013
1
10K_5%_3 Q6000
R6012
D
AON7410
10_5%_5
NMOS_4D3S
C6001 C6002 C6003 C6004
1
470PF_50V_2 4.7UF_25V_5 4.7UF_25V_5 CSC0805_DY

22E6 OUT
ACPRES
1
5
4
3
2
C6026
2
U6000 1UF_25V_3
G
ACOK
ACDRV
CMSRC
ACP
ACN
1 2
S
TI_BQ24725RGRR_QFN_20P
21
4
3
2
1
TML
VRCHARGER_HG
6 ACDET
VCC 20 L6000 R6001
22E8 22E6 OUT HW_I_ADC 7 IOUT
PHASE 19 VRCHARGER_PH 1 2 1 2
B 8 SDA
18 3 4 B
9 HIDRV C6027 ETQP3W4R7WFN
SCL R6020
1
BTST 17 1 2 1 2
10 ILIM
REGN 16 SHORT_0603 0.01_1%_6
CSC0805_DY
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
BATDRV
C6036
1
3
5
6
7
8
2
LODRV
0.047UF_16V_2
C6037 100PF_50V_2 GND
SRN
C6010
C6011
C6012
C6013
SRP
Q6001
100PF_50V_2 P3V3AL R7600
SBR3U40P1_DY
C
1
D
AON7410
NEAR IC RSC_0603_DY
NMOS_4D3S
1
1
1 2
2
NEAR EC
2
A1 A2 C6023
1
D6700
1 2
12
13
14
15
C6034
11
R6003
CSC0402_DY
2
C6029
1
3.32K_1%_3
CSC0603_DY C6028 D6001 0.1UF_16V_2
1
2
S
1UF_10V_2 BAT54C_30V_0.2A
0.1UF_25V_3
0.1UF_25V_3
C6035
1
CSC0402_DY
2
2
1
C7600
C6024
C6025
2
4
3
2
2
R6007
1
CSC0402_DY
110K_5%_2
2
R6016
1
EC_SMB2_DATA 1 2 VRCHARGER_LG
2
22D3 22D2 BI
66D2 41C3
SHORT_0402
R6017
66E2 41C6 22D3 22D2 EC_SMB2_CLK 1 2
BI
SHORT_0402
R6011
A 1 2 A
1
2
C6032 SHORT_0402
0.1UF_16V_2
R6008 R6010
30K_5%_2 2 1
6.98_1%_2
2
1
1 R6009 2
4.3K_5%_2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
15D7 EN_5V
IN
120K_1%_2
1
R6160
D
D
2
PVBAT
2VREF VRP5V0A_PH 6D3 6D3
15C7 IN EN_3V OUT OUT
1
5V_PG
PAD6110 OUT
1
R6110
130K_1%_2
POWERPAD_2_0610
2
2 VBATP 6C3 15C8
OUT VBATP
15C8 6C6 IN
1
8
7
6
5
5
6
7
8
1
C6123
1
1
Q6100 Q6150
1
25
6
5
4
3
2
0.22UF_6.3V_2
D
C6160 C6161
AON7410
AON7410
C C6111 C
NMOS_4D3S
NMOS_4D3S
C6110
TML
TRIP2
VFB2
TONSEL
VREF
VFB1
TRIP1
4.7UF_25V_5 4.7UF_25V_5
2
4.7UF_25V_5
4.7UF_25V_5
2
2
R6114 7 VO2 VO1 24
S
TP6101
G
1 S 2.2_5%_3 8 23
C6115 VREG3 PGOOD R6155 C6155
1 21 2 9 22
1 2.2_5%_3
12 2
TP30 VBST2 VBST1
2
3
4
4
3
2
1
1
L6100 VRP3V3A_HG10 DRVH2 U6100 DRVH1 VRP5V0A_HG
21 L6150 15D6
15D6 VRP3V3A 1 2 0.1UF_16V_2 VRP3V3A_PH11 VRP5V0A_PH 0.1UF_16V_2
20 1 2 VRP5V0A 15C8
OUT VRP3V3A_LG12
LL2 LL1
VRP5V0A_LG
OUT 15D4
DRVL2 DRVL1 19
ETQP3W3R3WFN ETQP3W3R3WFN
1
1
SKIPSEL
8
7
6
5
5
6
7
8
1
VREG5
Q6101 R6150 TP6100
Q6151
GND
ENC
1
EN0
R7610 R7615
VIN
D
AON7702A
D
AON7702A
R6100 RSC_0603_DY 15C6 OUT VRP3V3A_LDO RSC_0603_DY TP30

15C8
21
TI_TPS51123RGER_QFN_24P
21
1
15.4K_1%_2
13
14
15
16
17
18
1
6.8K_1%_2
2
2
SKIP_3V_5V C7615
+
C6100 15C7 IN C6150
C7610 EN_3V_5V CSC0402_DY
1
+
S
15C7 330UF_6.3V
G
IN
S
CSC0402_DY
1
330UF_6.3V VRP5V0A_VIN VRP5V0A_LDO

2
2
3
4
4
3
2
2
15C7 15D6
1
1
IN OUT R6151
2
R6101 10K_1%_2
1
1UF_25V_3
1
1
B 10K_1%_2 B
2
C6122
C6121 C6120
2
1UF_6.3V_2 R6113
RSC_0402_DY 10UF_6.3V_3
2
2
VO=(( R6150/R6151)+1)*2
VOUT=((R6100/R6101)+1)*2 VRP5V0A_LG
OUT 6B3 15D5 6B3 15D5
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PVBAT
POWERPAD_2_0610
2
P5V0A
PAD6210
2
D
D
1
P0V75S
1
2.2UF_6.3V_3
1
C6216
5
6
7
8
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
1
1
Q6200
FDMS7692
C6210
C6211
C6212
NMOS_4D3S
2
TP6200
2
U6200 1
S
R6215 C6215 TP30
12 V5IN VBST 15 1 2 1 2
4
3
2
1
VRP1V5_HG
14 2.2_5%_3
DRVH 0.1UF_16V_2
L6200
15D1 EN_0V75 17 VRP1V5_PH
13 1 2 VRP1V5 15C2
IN S3 SW OUT
RSC_0603_DY
3 4
POWERPAD1X1M
EN_1V5 16
2
15D1 IN S5 PAN_ETQP4LR36WFC_4P
2
5
6
7
8
C C
R7620
VRP1V5_LG
11
FDMS0306AS
DRVL
PAD6220
Q6201
560UF_2.5V
1
D
2
R6200
DDR3L_SEL
CSC0402_DY
1 2 6 10
IN VREF PGND
+
C6200
1
11
10K_1%_2 20
PGOOD
C7620
1
G
9
2
VDDQSNS
4
3
2
8 2
1
REFIN VLDOIN
2
VTT 3
VTTSNS 1
7
0.01UF_50V_2
GND
0.1UF_16V_2
P0V75M_VREF
1
1
2
43K_1%_2
R6201
C6217
C6218
19 MODE VTTGND 4
18 TRIP VTTREF 5
100K_5%_2
R6203 1
R6202 2
0.22UF_6.3V_2
10UF_6.3V_3
51K_1%_2
21
2
2
1
TML
1
B 1V5_PG B
C6220
C6221
OUT 15C2
TI_TPS51216RUKR_QFN_20P
2
2
VOUT=REFIN=1.8*(R6201/(R6200+R6201))
MODE=100KOHM:TRACKING DISCHARGE
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
P5V0A P3V3S
C TP6970
C
1
10UF_6.3V_3
TP30
1
1
GMT_AT1530F11U_SOP8_8P
10_5%_2
U6970 VOUT=((13K+10K)+1)*0.8
R6970
C6971
TML 9 OCP=4.5AMP
L6970 VRP1V8S
8 7 VRP1V8S_PH 1 2 15A2
VIN LX OUT
2
2
PAN_ELL5PR2R2N
CSC0402_DY
22UF_6.3V_5
13K_1%_2
1
R6973
C6974
C6970
1 VCC FB 4
2
EN_1V8
2
15B1 5 2
IN EN REF
0.1UF_16V_2
0.1UF_16V_2
1
10K_1%_2
PGND
C6972
C6973
R6972
GND
B B
2
2
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
15B7 EN_VCCP PVBAT

IN
POWERPAD_2_0610
2
PAD6310
100K_5%_2
1
2
R6303
1
2
1
15B6 15A8 VCCP_PG
C OUT C
5
6
7
8
R6315 C6315
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
1
1
1 2 1 2
Q6300
FDMC8884
17
16
15
14
13
C6310
C6311
C6312
P3V3A 2.2_5%_3
NMOS_4D3S
0.1UF_16V_2
U6300
R6306
1 2
PWPD
PGOOD
EN
BST
MODE
2
TP6300
G
1
S
10K_5%_2 1 12 VRP1VO_VCCP_PH
VREF SW
R6307 TP30
4
3
2
1
VCCIO_SEL 1 2 2 11 VRP1VO_VCCP_HG
2.2UF_6.3V_3
51A2 IN REFIN DH
1
VSS_SENSE_VCCIO 0_5%_2_DY VRP1V0_VCCP_LG

C6318
50A2 3 10 L6300
IN GSNS DL
VRP1V05S
1 2 15A8
P5V0A
1 2 OUT
RSC_0603_DY
50A2 VCC_SENSE_VCCIO 4 9 3 4
IN VSNS V5 3 4
5
6
7
8
2
COMP
PGND
CYN_PCMB063T_R68MS_4P
TRIP
R7630
GND
2
FDMS0310AS
Q6301
D
2.2UF_6.3V_3
22UF_6.3V_5
560UF_2.5V
1
1
1
TI_TPS51219RTER_QFN_16P
C6316
CSC0402_DY
+
C6300
C6301
11
C6319
5
R6302 2 6
86.6K_1%_2 7
8
2 1
C7630
S
0.01UF_50V_2
2
B B
4
3
2
1
2
1
VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
1
C6522
0.01UF_50V_2
C6520 R6520
1 2 1 2
2
3300PF_50V_2 5.11K_1%_2
1
VCCSA_SENSE 51A2
IN
C6521
P5V0A 0.22UF_6.3V_2 R6521
1 2
RSC_0402_DY
2
TP6500
1
1
2
3
4
5
6
C TP30 C
COMP
MODE
GND
SLEW
VOUT
VREF
TI_TPS51461RGER_QFN_24P
25 TML L6500
24 7 VRPVSA_PH 1 2 VRPVCCSA 15A6
VIN SW 1 2 OUT
23 VIN SW 8 3 3 4 4
22 VIN U6500 SW 9
1
21 PGND SW 10 CYN_PCMB063T_R33MS_4P
C6510 C6511 20 PGND SW 11 C6515
1
0.1UF_16V_2 19 PGND BST 12 1 2
22UF_6.3V_5
V5FILT
C6500 C6501 C6502 C6503
PGOOD
V5DRV
1
VID0
VID1
0.1UF_16V_2
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5_DY
2
EN
R7650
2
RSC_0603_DY
18
17
16
15
14
13
EN_SA
12
IN 15B5
R6524
1 2 VCCSA_VID0 C7650
IN 51A2
CSC0402_DY
SHORT_0402
R6525
2
1 2 VCCSA_VID1 51A2
IN
1UF_6.3V_2
1UF_6.3V_2
1
B SHORT_0402 B
C6523
C6524
2
SA_PG 15A6 22B6

OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R6620 R6622 PVBAT PAD6610

11D7 11D4 11C8 11B7 11A7 11A4 VREF_CPU 1 2 1 2
IN POWERPAD_2_0610
PVBAT_CPU
1
39.2K_1%_2 56K_1%_2 1 2
1 2 OUT
R6624
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
RSC_0402_DY
1
12D5
C6611
C6612
C6613
C6614
C6615
C6616
C6617
C6618
C6619
C6620
C6621
R6621 R6623
C6000
C6610
1 2 1 2
+
68UF_25V
42.2K_1%_2 24K_1%_2
2
P3V3A
IN
C6632
11D6 11D4 11C8 11B7 11A7 11A4 VREF_CPU 1 2
IN
11C3
11C3
IN
1
R6635
1
100PF_50V_2 1 2
C6631 11D5 OUT CPU_CSN1
11D3
11D3
RSC_0402_DY
50A3
50A3
R6618 0.1UF_16V_2_DY
D R6625
100K_5%_NTC
R6636 2
1 2 1 D
2
2
C6623
8.45K_1%_2 RSC_0402_DY R6619
OUT CPU_CSP1 1 2
IN
IN
2 VREF_CPU 11D5
1
1 11A4 11A7 11B7 11C8 11D6
IN 11D7
15.4K_1%_2 0.033UF_16V_2
IN
IN
IN
IN
R6626
CPU_CSN3
CPU_CSP3
2.4K_1%_2 P5V0A PVBAT_CPU 11B3 11D1 12D5 R6605
IN
11 VCCSENSE
12 VSSSENSE
1 2
6 CPU_CSN2
7 CPU_CSP2
4 CPU_CSP1
1 R6617 2 V5DRV_CPU
CPU_CSN1
5
6
7
8
OUT 11C4
1
10_5%_3 162K_1%_2
Q6610
FDMS7692
D
NMOS_4D3S
R6602 R6603 R6604
PVCORE
1 C6629 C6630 1 2 1 2 1 2
10
1
9
2
2.2UF_10V_3 4.7UF_10V_3
R6627 17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
G
39K_1%_2
S
CGFB
CVFB
CCOMP
CCSN3
CCSP3
CCSP2
CCSN2
CCSN1
CCSP1
CF-IMAX
COCP-R
CTHERM
PAN_ETQP4LR36ZFC_4P
3 4
2
4
3
2
P5V0A
1
GND 49 1 2
1
5
6
7
8
L6610
P3V3A 13 48
FDMS0306AS
GOCP-R V5
11D6 11D7 R7661
Q6611
D
11C8 11D4
1
RSC_0603_DY C6600 C6601
11B7
OUT VREF_CPU
1
14 VREF CDH1 47
VREF_CPU 11A4 470UF_2V
IN
21
11A7 R6601 C6622 470UF_2V
+
C 15 46 1 2 1 2 C
+
V3R3 CBST1
1
C7661
C6634 VR_ON 2.2_5%_3 0.1UF_16V_2 CSC0402_DY
G
16 45
S
IN VR_ON CSW1
3
2.2UF_6.3V_3
3
CORE_PG 17 44
OUT CPU_CSN2
4
3
2
2
11A4 U6600 11D5
1
C6633 OUT CPGOOD CDL1
1
R6628 2.2UF_6.3V_3
50B1 11A3 VR_SVID_CLK 18 43 V5DRV_CPU 11D4
IN VCLK V5DRV IN
RSC_0402_DY VR_SVID_ALERT# 19 42
50B1 OUT ALERT# PGND C6625
VR_SVID_DATA
11D6 OUT CPU_CSP2 1 2
20 41
2
R6711 50B1 11A3 BI VDIO TI_TPS51650RSLR_QFN_48P CDL2

0.033UF_16V_2
110K_1%_2 CPU_PROCHOT# 21 40
47D6 22C3 OUT VR_HOT# CSW2 PVBAT_CPU R6610
IN 11D1 11D3 12D5 1 2
R6606 C6624
22 39 1 2 1 2
5
6
7
8
SLEW CBST2
Q6620 162K_1%_2
AXG_PG 2.2_5%_3 0.1UF_16V_2
FDMS7692
D
11A4 23 38 R6607 R6608 R6609
OUT GPGOOD CDH2
PVCORE
NMOS_4D3S
R6616 1 2 1 2 1 2
24 GF_IMAX VBAT 37 1 2
GTHERM
GPWM1
GCOMP
GPWM2
CPWM3
GSKIP#
GCSN1
GCSP1
GCSN2
GCSP2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2

GGFB
GVFB
10K_5%_3
G
1
S
R6629 PAN_ETQP4LR36ZFC_4P
B 20K_1%_2 3 4 B
4
3
2
1
R6712 GFX_VSS_SENSE 1 2 1 2
IN PVBAT
1
25
26
27
28
29
30
32
33
OUT GPWM134
35
OUT CPWM336
31
R6713 0_5%_2 L6620
5
6
7
8
24K_1%_2
GPWM2
51C3 GFX_VCC_SENSE 1 2
IN
2
R7662
FDMS0306AS
R6715 0_5%_2
Q6621
D
RSC_0603_DY
560UF_2.5V
1
1
11D7 P3V3A
21
11D6 C6602
11C8 C6726
C6603
VREF_CPU 470UF_2V
+
1 2 1 2
+
OUT
11A4 IN C7662
11A7
1
R6719
1 0_5%_2_DY
2
11D4 CSC0402_DY
S
100PF_50V_2
R6721 0_5%_2_DY
2
R6714 R6716 1 2
2
R6718
0_5%_2_DY 0_5%_2_DY
4
3
2
12D7
1
12B7
12A7
1 2 R6723 0_5%_2_DY
1 2
4.12K_1%_2
0_5%_2_DY
2
R6725
0_5%_2
0_5%_2
0_5%_2
0_5%_2
22D3 EN_PVCORE R6731

IN
1 2 VREF_CPU 11A7 11B7 11C8 11D4 11D6 11D7
IN
1
RSC_0402_DY
1
R6724
R6720
R6722
R6726
GSKIP# 12B7
R6630 OUT
20K_5%_2
IN GPU_CSN1 2
IN GPU_CSP1 2
IN GPU_CSP2 2
GPU_CSN2 2
A A
2
R6730 P3V3A P1V0S_VCCP

VR_ON 11C7 30K_5%_2
OUT
1
0.1UF_16V_2
R6631
IN
1
54.9_1%_2
130_1%_2
1
2K_5%_2
8.66K_1%_2
R6732
R6632
R6633
C6635
2K_5%_2
R6634
R6728
2
INVENTEC
VREF_CPU 1 2
100K_5%_NTC
11D7 11D6 11D4 11C8 11B7 11A4 IN

1
2
12C5
12A5
12B5
15.4K_1%_2
R6729
2
2
C6727
0.1UF_16V_2_DY
11C7 OUT CORE_PG 11C7
50B1
IN VR_SVID_CLK
TITLE
2
Block Diagram
1
11B7 AXG_PG 50B1 11C7 VR_SVID_DATA

OUT BI DOC.NUMBER REV
12C5
R6638 SIZE
A3
CODE
CS
1310xxxxx-0-0 X01
R6638
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
11D6 CPU_CSN3
OUT
C6628
11D6 CPU_CSP3 1 2
OUT
0.033UF_16V_2
PVBAT_CPU R6615
IN 11B3 11D1 11D3 1 2
5
6
7
8
162K_1%_2
R6611 C6626
Q6630
FDMS7692
D
1 2 1 2 R6612 R6613 R6614
PVCORE
NMOS_4D3S
1 2 1 2 1 2
2.2_5%_3 0.1UF_16V_2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
D P5V0A U6630
G
9 D
S
PAD
PAN_ETQP4LR36ZFC_4P
1 BST DRVH 8 3 4
4
3
2
1
2 SKIP# SW 7 1 2
CPWM3
1
11B5 3 6 L6630
IN PWM VDD
5
6
7
8
4 GND DRVL 5
FDMS0306AS
R7663
Q6631
D
TI_TPS51601DRBR_SON_8P P5V0A RSC_0603_DY
21
1UF_6.3V_2
1
C6627
C7663
S
CSC0402_DY
4
3
2
2
PVBAT
1
2
1
11A6 GPU_CSN1
OUT
1
PAD6710
POWERPAD_2_0610
2
C6722
C GPU_CSP1 1 2 PVBAT_AXG C
2
11A6 OUT OUT 12A5 12C5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
1
1
0.033UF_16V_2
C6710
C6711
C6712
C6713
C6714
C6715
C6716
C6717
PVBAT_AXG R6705
IN 12A5 12C1 1 2
5
6
7
8
162K_1%_2
R6701 C6720
Q6710
FDMS7692
2
1 2 1 2 R6702 R6703 R6704
PVAXG
NMOS_4D3S
1 2 1 2 1 2
2.2_5%_3 0.1UF_16V_2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
U6710
G
9
S
GSKIP# PAD
11A4 IN PAN_ETQP4LR36ZFC_4P
1 BST DRVH 8 3 4
4
3
2
1
2 SKIP# SW 7 1 2
1
11B5 GPWM1 3 6 L6710
IN PWM VDD
5
6
7
8
4 GND DRVL 5
R7671
FDMS0306AS
Q6711
D
P5V0A RSC_0603_DY
TI_TPS51601DRBR_SON_8P
1
21
C6700
1UF_6.3V_2
1
470UF_2V
+
C6721
C7671
B CSC0402_DY B
G
3
2
4
3
2
1
2
11A5 GPU_CSN2
OUT
C6725
11A6 GPU_CSP2 1 2
OUT
0.033UF_16V_2
PVBAT_AXG R6710
IN 12C1 12C5 1 2
5
6
7
8
162K_1%_2
R6706 C6723
Q6720
FDMS7692
1 2 1 2 R6707 R6708 R6709

PVAXG
NMOS_4D3S
1 2 1 2 1 2
2.2_5%_3 0.1UF_16V_2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
A P5V0A U6720
A
G
9
S
PAD
PAN_ETQP4LR36ZFC_4P
1 BST DRVH 8 3 4
4
3
2
1
2 SKIP# SW 7 1 2
1
11B5 GPWM2 3 6 L6720

IN PWM VDD
5
6
7
8
4 GND DRVL 5
R7672
FDMS0306AS
Q6721
D
P5V0A RSC_0603_DY
TI_TPS51601DRBR_SON_8P
1
21
C6701
470UF_2V
INVENTEC
+
+
1UF_6.3V_2
1
C7672 C6702
C6724
CSC0402_DY
G
560UF_2.5V
3
2
TITLE
4
3
2
1
2
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PVBAT
POWERPAD_2_0610
2
PAD6753
2
PVBAT_GPUOUT
1
13C3
1
5
6
7
8
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
D MAX=40A
C6760
C6761
C6762
FDMS7692
D
D
Q6760
NMOS_4D3S
OCP=56A
2
G
S
1 TP6750
4
3
2
1
L6751 TP30
1 2 VRPVCORE_DGPU OUT 15B4
CSC0402_DY RSC_0603_DY
3 4
1
5
6
7
8
ETQP4LR36AFM
FDMS0308AS
R7676
Q6761
D
1 R6769 21 R6754 2 1 R6763 2
1
34.8K_1%_2 62K_1%
1 2
220K_5%_NTC
C6750 C6751 C6752
+
R6768 2
C7676
1
S
422K_1%_2
470UF_2V
470UF_2V
470UF_2V
4
3
2
C6786
3
2 1
DGPU_PG OUT
2
15A4
58C6
C 0.01UF_50V_2 C
EN_DGPU R6772
15B2 IN 1 2
R6779
1 2 0_5%_2
13B8 IN G_CSP2
C6790 R6797
2 1 124K_1%_2 1 2 G_CSN2
13B8 IN
2.2UF_6.3V_3 1 2 0_5%_2 P3V3S
C6792 OUT 13D3
PVBAT_GPU
0_5%_2_DY
330PF_50V_2
R6773 2
C6770
1 21 R6777 2
3900PF_16V_2 6.8K_1%_2 1 R6774 2 GPU_SENSE OUT 13A6
1
5
6
7
8
C6791 0_5%_2_DY
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
2 1
C6763
C6764
C6765
Q6750
FDMS7692
D
NMOS_4D3S
0.22UF_6.3V_2
40
39
38
37
36
35
34
33
32
31
R6756 2
OUT G_CSP2 1
2
13C4
330_5%_2 U6750
C6796
S
TONSEL
PG#
OSRSEL
TRIPSEL
VREF
V5FILT
DROOP
SLEW
EN
PGD
2 1
47PF_50V_2
1
B B
4
3
2
47PF_50V_2 C6799
1
1 PU DRVH2 30 R6762 C6766
2 29 1 2 2 1 L6750
47PF_50V_2 GND VBST2
1 2
3 28
CSC0402_DY RSC_0603_DY
C6797 CSP2 LL2 2.2_5%_2 3 4
1
2 1 4 27
5
6
7
8
CSN2 DRVL2 0.47UF_16V_3
ETQP4LR36AFM
2
5 26 2 1
FDMS0308AS
CSN1 V5IN
R7675
1 R6757
Q6751
G_CSN2
D
13C4 2 6 25 C6771
OUT CSP1 PGND
330_5%_2 7 GFB DRVL1 24 2.2UF_6.3V_3
R6759 R6758 8 23 C6767
13A4 OUT G_CSN1 1 2 VFB LL1
R6761
1 2 9 22 1 2 1
12
THRM VBST1
10 21 R6752
C6794 THAL# DRVH1 2.2_5%_2 1 R6770 21 R6753 2 1 2
330_5%_2 20K_5%_2
C7675
2 1
PCNT
S
IMON
P3V3S 0.47UF_16V_3
47PF_50V_2
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
34.8K_1%_2
SLP
R6755 TML 41 62K_1% 220K_5%_NTC

47PF_50V_2 C6798 1 2
4
3
2
P5V0A
1
CSC0402_DY
47PF_50V_2 RSC_0402_DY
R6771 2
1
1
12
13
14
15
16
17
18
19
20
2
11
C6795 C6776
C6758
2 1 422K_1%_2
2 1 TI_TPS51728RHAR_QFN_40P
2
C6787
R6760
0.022UF_16V_2 2 1
G_CSP1 1 2 1 R6781 2
13A4 OUT
330_5%_2 11.3K_1%_2 0.01UF_50V_2
2
DGPU_VID0 IN 66C2 66C4

R6799
R6782 1 2
PVCORE_DGPU_VSS DGPU_VID1
CSC0402_DY CSC0402_DY
62C2 1 2 66C2 66C4

IN IN G_CSP1
1
13A8 IN
0_5%_2
C6757
0_5%_2 DGPU_VID2 G_CSN1

A IN 66C2 66C4 13B8 IN A
P3V3S
R6783 DGPU_VID3 IN 66C2 66D4
62C2 IN PVCORE_DGPU_SENSE 1 2 R6798
12
1 2 DGPU_VID4 IN 66C2 66D4

0_5%_2
0_5%_2
C6759
DGPU_VID5 IN 66C2 66C4

GPU_SENSE IN 13B1 DGPU_VID6 IN 15A4
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
LNB POWER D
PVBAT P16V0S_LNB
EMI
1
EMI
1
2
PAD6703 C6731
C6730.
2
PAD6702 1 2 CSC0603_DY
CSC0603_DY 1 2
POWERPAD_2_0610
2
POWERPAD_2_0610
2
C C
1
1 3 R6740
VIN VO
22E3 14B6 IN LNB_EN 2 1 LNB_OCP_DET OUT 22E6
2
2
1
10K_5%_2
R6736
U6602 C6729 R6739
C6728
13.3K_1%_2 10UF_25V_6 5.1K_1%_2
3
1UF_25V_3 SHP_PQ200WN3MZPH_5P
Q6708
1
1
D
2
14C4 IN LNB_EN 2 VC VADJ 4 1 G

22E3
S
GND
2
2N7002
R6738
2
R6737
1.5K_1%_1/16W
2.7K_1%_2
5
1
1
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR_P1V5
3V & 5V 73B8
51D3
15B8 R7010
15A6 SLP_S3#_3R 1 2 EN_0V75 7C7
EN_5V 15B4
IN OUT
OUT 6D6 VRP5V0A 47K_5%_2
1
P5V0A 15D6 15C8 6C1 IN 22D6
55B1
0.047UF_16V_2
3
1
Q7000 PAD6150
VRP5V0A 1 C7005
C7000
2
2
15D4 15C8 6C1 IN
D
1 2
16D4 EC_PW_ON# 1 G 0.1UF_16V_2
22C3
IN POWERPAD_2_0610
2
S
2 13
SSM3K7002BFU
2
C7001 D7001
2
0.1UF_16V_2 DIODES_BAV99
P3V3AL R7012
22D3 SLP_S5#_3R 1 2 EN_1V5 7C7
1
55B3
IN OUT
D
1
PAD6100 0_5%_2
6C8 VRP3V3A 1 2 D
IN
1
1
1 2
C7006
POWERPAD_2_0610
2
CSC0402_DY
A1
C7002 C7003
0.1UF_16V_2
2
0.1UF_16V_2
6B3 VRP5V0A_LG 2 13 P3V3S
IN
2
22F6 D7000
15C8 P5VAUXON 3 P5V0AL
16D6
IN C
D7002 P15V0A
2
DIODES_BAV99
1 1
BAT54C_30V_0.2A_DY VRP5V0A_LDO1 2
6B4 IN 1 2 R7013
A2
RSC_0402_DY
PAD6120 C7004 1V5_PG 1V5_PG
EN_3V POWERPAD1X1M 7B3 15C2 7B3 IN OUT
6D6
1
OUT 1UF_25V_3 15C2
2
P3V3_LDO
VRP3V3A_LDO
1 R7000 2
2
15C6 6B6 IN
RSC_0402_DY P1V5
VRP5V0A 1 R7001 2 SKIP_3V_5V VRP3V3A_LDO1 2 PAD6200
15D4 6C1 IN OUT 15C8 6B6 IN 1 2 1 2
15D6 10K_5%_2 1 2
PAD6121 POWERPAD_2_0610
VBATP 1 R7002 2 VRP5V0A_VIN POWERPAD1X1M PAD6201
6C6 6C3 IN OUT 6B5
C 0_5%_3 7C1 VRP1V5 1 2 C
IN 1 2
22F6 R7003 2
15D8 P5VAUXON 1 EN_3V_5V 6B4 POWERPAD_2_0610
16D6
IN OUT
0_5%_2
VCCIO VCCSA DGPU P1V8S

73B8 R7016
15D2 15B8 15A6 SLP_S3#_3R 1 2 EN_DGPU 13C7
55B1 51D3 22D6
IN OUT
73B8 0_5%_2_DY
R7040
51D3 VCCP_PG 1 2 EN_SA
15D2 R7021 15A8 9C6 IN OUT 10B4
SLP_S3#_3R 1 2 EN_VCCP DGPU_PWR_EN R7018
15A6 IN OUT 9D6
1
1 2
15B4 IN
1
22D6
0_5%_2 P3V3S
0.1UF_16V_2
55B1 47K_5%_2 C7040 10K_5%_2

1
C7010
C7020
CSC0402_DY R7050
0.1UF_16V_2 1 2 EN_1V8
OUT 8B6
2
10K_5%_2
2
B B
2
1
PVCORE_DGPU
C7050
0.01UF_50V_2
P3V3S VRPVCORE_DGPU PAD6750
1 2
2
13D1 IN 1 2
1
P3V3S POWERPAD_2_0610
R7041 PAD6751
10K_5%_2 1 1 2
2
2
10K_5%_2
POWERPAD_2_0610
R7022
22B6 15A6 10A5 22B6 15A6 10A5 SA_PG SA_PG PAD6752

IN OUT
1 1 2
2
POWERPAD_2_0610
2
1
15B6
15A8 D7040
9C6 15A8 9C6 VCCP_PG VCCP_PG P1V8S
IN OUT
NC
15B6 73B8
15D2 15B8 15B4 SLP_S3#_3R 3 1 P3V3S
55B1 51D3 22D6
IN
2
PAD6900
DIODE-BAT54-TAP-PHP VRP1V8S 1 2
8C2 IN 1 2
R7017
A 10K_5%_2
A
POWERPAD_2_0610
P1V05S
1
58C6 13C5 DGPU_PG
IN OUT
PAD6300 PVSA
1 1 2
2
DGPU_VID6
1
POWERPAD_2_0610 13A4 IN
PAD6500
10C1 VRPVCCSA 1 2
IN 1 2
R7019
9B1 IN VRP1V05S 1
PAD6301
1 2
2 POWERPAD_2_0610 2.2K_5%_2
INVENTEC
2
POWERPAD_2_0610
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P15V0A P3V3AL 1 TP7103

P3V3AL P3V3A
TP30
Q7102 PAD7100
1
1 D S 4 1 1 2
2
1
2
R7105 5 POWERPAD_2_0610
R7104 100K_5%_2 6 3
G
PVBAT P3V3_LDO NMOS_4D1S
100K_5%_2_DY
1
AO6402AL
3
R7106
1
Q7101 200_5%_2
1
4
R7491
D
U7490 EC_PW_ON#
510K_1%_2 22C3 15D8 1 G C7100
IN
2
VDD
D
2
2200PF_50V_2
S
SSM3K7002BFU
D
2
D7490
1
NC
2
2
OUT THRM_SHUTDWN# 3 1 5 3 P5VAUXON
3
46A8 SENSE RESET# OUT 15C8 15D8 22F6
46B1 R7100
Q7103
1
10K_5%_2
D
DIODE-BAT54-TAP-PHP 1
R7492 G
GND
GND
S
120K_1%_2 TI_TPS3801_01_SC70_5P
SSM3K7002BFU
2
2
1
2
P3V3AL
Q7121
1 D S 4
2
5
6 G 3
NMOS_4D1S
P15V0A AO6402AL_DY P3V3S
C PAD7101 C
POWERPAD_2_0610
Q7105 TP7100
1 D S 4 2 1 1
1
470K_5%_2
2 1
2
TP30
R7107
1
22UF_6.3V_5
200_5%_2
1
5
R7109
C7103
6 G 3
NMOS_4D1S
AO6402AL
2
R7108
680PF_50V_2
1 2
32
1
2
C7102
3
2200PF_50V_2
P5V0A 0_5%_2 Q7106

1
Q7104
D
16B8
SLP_S3_3R
C7101
Q7122 16A4 1 G
IN
D
55A2
16A4 SLP_S3_3R 1 G 1 4 16B4
IN D S
55A2
S
16B4 2
2
S
5 SSM3K7002BFU
SSM3K7002BFU 6 3
2
2
G
NMOS_4D1S
2
AO6402AL_DY P5V0S
PAD7102
POWERPAD_2_0610
Q7107 2 1 TP7101
B 1 D S 4 2 1
1 B
1
2
200_5%_2
TP30
R7111
5
22UF_6.3V_5
1
6 G 3
C7105
NMOS_4D1S
AO6402AL
R7110
23
1 2
CSC0402_DY
Q7108
1
D
16B8
C7104
0_5%_2 SLP_S3_3R 1
16A4 IN G
16B4
55A2
S
SSM3K7002BFU
2
2
P1V5 P1V5S
PAD7103
POWERPAD_2_0610
Q7109 TP7102
8 D S 1 1 1 2
2 1
200_5%_2
1
7 2
TP30
R7113
6 3
22UF_6.3V_5
1
5 G 4
A A
C7107
NMOS_4D3S
23
AON7410 P0V75S
Q7112 Q7110
8 1
D
D S
200_5%_2
7 2 SLP_S3_3R 1
2
16B8 16B4 IN G
R7114
6 3 55A2
S
5 G 4
NMOS_4D3S
SSM3K7002BFU
AON7410
2
R7112
23
INVENTEC
1 2
Q7111
CSC0402_DY
1
D
0_5%_2
C7106
1 G
TITLE
S
SSM3K7002BFU Block Diagram
2
2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V5 P1V5S_DGPU
Q7113 TP7110
8 D S 1 1
7 2
TP30
6 3
5 G 4
NMOS_4D3S
AON7410
Q7114
D 8 D S 1
7 2 D
6 3
5 G 4
NMOS_4D3S
AON7410 NVIDIA OPTIMUS
1
R7116
17B7 17B1 17A7 IN DGPU_PWR_EN_15R 1 2 R7115
DURING RESET AFTER RESET
1
220K_5%_2 200_5%_2
C7108
2
680PF_50V_2
DGPU_PWR_EN# HIGH HIGH 0 : DGPU POWER SWITCH TURNED ON
2
1 : POWER SWITCH TURNED OFF
3
Q7115
0 : DGPU POWER IS NOT STABLE
D
IN DGPU_PWR_EN_3R 1 G SSM3K7002BFU DGPU_PG
1 : DGPU POWER IS STABLE
S
0 : KEEP DGPU IN RESET
2
C DGPU_HOLD_RST# LOW LOW C
1 : RESET IS RELEASED
P1V05S P1V05S_DGPU
Q7116 TP7111
8 D S 1 1
7 2
TP30
6 3
5 G 4
NMOS_4D3S
AON7410
1
P15V0A
R7117 R7118
17D7 17B1 17A7 IN DGPU_PWR_EN_15R 1 2
200_5%_2 P3V3_LDO
1
1
220K_5%_2
2
R7121
C7109 100K_5%_2
10K_5%_2
680PF_50V_2 DGPU_PWR_EN_15R OUT 17A7 17B7 17D7
32
R7033
P3V3S
3
2
B B
Q7117 Q7120
D
D
1
3 2
58C7 57B6 17B5 17A7 IN DGPU_PWR_EN# 1 G SSM3K7002BFU DGPU_PWR_EN_3R 1 G SSM3K7002BFU
R7122
Q7018
S
S
100K_5%_2
SSM3K7002BFU
R7035
D
DGPU_PWR_EN
1 2 1
2
2
G
32
S
0_5%_2
Q7123
CSC0402_DY
D
DGPU_PWR_EN#
2
58C7 57B6 17B7 17A7 1 G SSM3K7002BFU
IN
C7022
S
P3V3S P3V3S_DGPU 2
2
Q7118 TP7112
1 D S 4 1
2
TP30
5
6 G 3
NMOS_4D1S
AO6402AL
1
A R7120 R7119 A
17D7 17B7 17B1 IN DGPU_PWR_EN_15R 1 2
200_5%_2
1
220K_5%_2
2
C7110
680PF_50V_2
3
2
Q7119
INVENTEC
D
58C7 57B6 17B7 17B5 IN DGPU_PWR_EN# 1 G SSM3K7002BFU

S
TITLE
2
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 0~49(PCB SCREW)
D
D
1 FIX1 1 FIX5
FIX_MASK FIX_MASK
1 FIX2 1 FIX6
FIX_MASK FIX_MASK
1 FIX3 1 FIX7
FIX_MASK FIX_MASK
1 FIX4 1 FIX8
FIX_MASK FIX_MASK
C C
PCB CPU GPU WLAN

1 S1 1 S10 1 S14 1 S16
SCREW300_900_1P SCREW120_0_600_1P
SCREW330_600_1P SCREW330_600_1P
1 S2 1 S11 1 S15
SCREW300_900_1P
SCREW330_600_1P SCREW330_600_1P
1 S3 1 S12 3G
SCREW300_900_1P
SCREW330_600_1P
1 S17
S13 SCREW120_0_600_1P
1 S5 1
SCREW300_900_1P
B SCREW330_600_1P B
1 S6
SCREW300_900_1P
MSATA
1 S7
SCREW300_900_1P 1 S19
SCREW120_0_600_1P
1 S8
SCREW300_900_1P
S9
1
SCREW300_900_1P FAN
1 S21
1 S18 SCREW120_0_600_1P
SCREW300_700_600_1P
1 S20
SCREW300_600_700_1P
1 S22
SCREW500_700_800_NP_1P
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 50-99(HALL SENSOR)
D
D
C P3V3AL C
1
R50
U50 100K_5%_2
VDD 1
2
3 GND
OUT 2 LID_SW#_3 OUT 22D3
1
1
MAG_MH248BESO_SOT23_3P D50
C50
1000PF_50V_2 VARISTOR_DY
2
2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 100~199(LED)
D SUSPEND LED P3V3A

D
D154
PWR_OLED# TP100 R160
22B6 1 1 2 1 2
IN
TP30
150_5%_2
HT_191UY
POWER ON LED P5V0S
C D159 C
PWR_WLED# TP101 R150
22D6 1 1 2 1 2
IN
TP30
220_5%_2
19_217_T1D_CP1Q2QY_3T
P3V3S
WIFI/WIMAX/3G/LTE LED
D156
TP104 R155
22D6 IN WL_OLED# 1 1 2 1 2
TP30
150_5%_2
HT_191UY
DC IN / BATTERY CHARGE LED

B D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED B
D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER
BLINK:LOW BATTERY
P5V0A
D152
TP102 R152
22B6 IN DCIN_WLED# 1 1 2 1 2
TP30
220_5%_2
19_217_T1D_CP1Q2QY_3T
P3V3AL
D155
A BAT_OLED# TP103 R154 A
22B6 1 1 2 1 2
IN
TP30
150_5%_2
HT_191UY
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 200~249(POWER CONN)

R253
REFERENCE 250~299(KB/TP CONN) 1 2
0_5%_2_DY
CN250
P3V3S
SCAN_OUT<17..0>
22B3 34
OUT SCAN_OUT<16>
34
16 33 33
32 32
17 SCAN_OUT<17> 31 31 G2 G2
30 30 G1 G1
D 29 29
4 SCAN_OUT<4> 28 28
D
2 SCAN_OUT<2> 27 27
13 SCAN_OUT<13> 26 26
15 SCAN_OUT<15> 25 25
1 SCAN_OUT<1> 24 24
0 SCAN_OUT<0> 23 23
11 SCAN_OUT<11> 22 22
9 SCAN_OUT<9> 21 21
5 SCAN_OUT<5> 20 20
P5V0S
6 SCAN_OUT<6> 19 CN200
19
22D3 PWR_SWIN#_3 1
OUT 1
2
10 SCAN_OUT<10> 18 18
2
3 G1
14 SCAN_OUT<14> 17 3 G1
2
SCAN_OUT<8>
17
22B6 IN PWRBTN_LED# 4 4 G2 G2
8 16 16
12 SCAN_OUT<12> 15 15 D200 ACES_50224_0040N_001_4P
SCAN_OUT<7> 14
VARISTOR_DY
7 14
3 SCAN_OUT<3> 13
1
22B3 IN SCAN_IN<7..0> SCAN_IN<7>
13
7 12 12
C
2 SCAN_IN<2>
SCAN_IN<3>
11 11
POWER CONN C
3 10 10
4 SCAN_IN<4> 9 9 P5V0S
0 SCAN_IN<0> 8 8
5 SCAN_IN<5> 7 7
6 SCAN_IN<6> 6 6
1 SCAN_IN<1> 5 CN201
5
22D6 OUT ECO_BTN# 1 1
4 4
2
2
22B6 IN CAPS_LED#_3 R250 1 2 200_5%_2 3 3
2
3 3 G1 G1
SCROLL_LED#_3 D201 22B6 IN ECO_LED# 4 4 G2 G2
22D6 R251 1 2 200_5%_2 2
IN NUM_LED#_3
2
22D6 IN R252 1 2 200_5%_2 1 1 VARISTOR_DY
ACES_50224_0040N_001_4P
1
PTWO_AFF340_A2G1V_P _34P
KEYBOARD CONN
2
D258
VARISTOR_DY
D259
VARISTOR_DY
D260
VARISTOR_DY
3D/ECO CONN
1
B B
P3V3S
2
R254
P5V0S 10K_5%_2
P5V0S Q250 CN251
1
4 S D 1 4 4 G G2
2 58C6 OUT KBLED_ID 3 3 G G1
P3V3S P5V0S 5 2 2
3 6 1
2
G 1
PMOS_4D1S
R255
TPC6111 ACES_50592_0040N_001_4P
CN280 330_5%_2
1 1 R256
IM_DAT_5 2 CN281 1 2
22D3 22D2 BI 2
1
1
1
22D3 22D2 IM_CLK_5 3 G1
BI 3 G
2 2
4 G2 10K_5%_2
4 G
57B2 BI USB_FP_DN 3 3 G G1
5
3
5
57B2 BI USB_FP_DP 4 4 G G2
6 6 Q251
5 5
A A
D
6 6
G 1 KB_LED_OFF# IN 22E6
1
2
ACES_50224_0060N_001_6P
ACES_50224_0060N_001_6P
S
D280
SSM3K7002BFU
PHP_PESD5V2S2UT_SOT23_3P_DY
2
3
FP CONN
INVENTEC
TOUCHPAD CONN TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 300~389(KBC)
P3V3AL P3V3AL_R P3V3S P3V3AL

F CLOSE PIN4 P3V3AL F
R318
10K_5%_2_DY
1 2
10UF_6.3V_3_DY
2
4.7UF_6.3V_3
RC6 0
R347
2.2_5%_3
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
R320
2
CIR_ID
C313
C300
C301
C302
C303
C304
C312
C306
100K_5%_2
FOR ESD PROTECT D300
NEC 1
NC
1
16D6 15D8 15C8 IN P5VAUXON 3 1 VCC_POR# OUT 22B6 CIR_ID
2
22E3 IN
1
DIODE-BAT54-TAP-PHP
R348
100K_5%_2
2
P3V3AL_R P3V3AL_EC
P3V3AL P3V3AL_EC P3V3S P3V3AL_EC P3V3S
115
102
1
19
46
76
88
1 L300 2
4
10UF_6.3V_3_DY
R332 R323 U301
FBM_11_160808_121T
10K_5%_2 4.7K_5%_2 P3V3S
1
AVCC
VDD
VCC2
VCC3
VCC4
VCC5
VCC1
0.1UF_16V_2
C314
C305
2
2
E 104
P3V3AL_EC_VREF VREF LRESET#/GPIOF7 7 BUF_PLT_RST#
IN 29C3 29C7 30C3 36C3 40A1 E
2 CLK_KBPCI 57A7 57A8 62F5
LCLK/GPIOF5
BI
R326 1
HW_I_ADC 97 3 LPC_3S_FRAME#
2
22E8 5B7 IN BI 29C3 53C3
10K_5%_2
GPIO90/AD0 LFRAME#/GPIOF6
10K_5%_2
14C2 IN LNB_OCP_DET 98 GPIO91/AD1 LAD3/GPIOF4 1 LPC_3S_AD<3>
BI 29C3 53C3
R312
22E8 5D3 BATT_IN 99 128 LPC_3S_AD<2> 29C3 53C3
IN TMPTU2_SXP 100
GPIO92/AD2 LAD2/GPIOF3
127 LPC_3S_AD<1>
BI
30B8 OUT GPIO93/AD3 LAD1/GPIOF2
BI 29C3 53C3
38A6 EC_BKLTEN 108 126 LPC_3S_AD<0> 29C3 53C3
OUT LCM_BKLTEN
GPIO05/AD4 LAD0/GPIOF1
BI
AGND_KBC 96 125 PCI_3S_SERIRQ
2
38A5 IN GPIO04/AD5 SERIRQ/GPIOF0
BI 29B7 53C2
5B8 IN ACPRES 95 GPIO03/AD6 GPIO11/CLKRUN# 8 CIR_ID OUT 22F3
30B2 IN TMPTU1_SXP 94 GPIO07/AD7 GPIO65/SMI# 9 LNB_EN OUT 14B6 14C4
22E6 5B7 HW_I_ADC 29 RUNSCI0#_3 57C7 58D6
IN EC_JD# 101
ECSCI#/GPIO54
124 EC_SMM_PWR OUT
26D5 IN GPIO94/DA0 GPIO10/LPCPD#
OUT 25D8
22E6 5D3 OUT BATT_IN 21A2 OUT KB_LED_OFF# 105 GPIO95/DA1 GPIO85/GA20 121 EC_3S_A20GATE
OUT 58C2
73B8 55B1 51D3 15D2 15B8 15B4 15A6 SLP_S3#_3R 106 122 KBRST# 58C2
IN HDMI_HPD_EC
GPIO96/DA2 KBRST#/GPIO86
P3V3AL OUT
1
41B1 40A1 107

OUT
0.1UF_16V_2
0.1UF_16V_2
GPIO97/DA3
2 R300 1
C317
C315
10K_5%_2
IN LNB_CON 79 GPIO02 GPIO52/PSDAT3/RDY# 27 PWR_SWIN#_3
OUT 21C3
21B7 SCROLL_LED#_3 114 25 TP30 TP306 1 RSMRST# 22D1 55B7 55C2 P5V0S
P3V3AL
OUT ECO_BTN# 6
GPIO16 GPIO50/PSCLK3/TDO
11 EN_PVCORE
OUT
2
21C3 IN GPIO24 GPIO27/PSDAT2

OUT 11A8
21B7 OUT NUM_LED#_3 109 GPIO30/F_WP# GPIO26/PSCLK2 10 USB_OC#_2 IN 36A6 36C3 36C6 IM_DAT_5
66C3 55A6 55A5 ACPRESENT 14 71 IM_DAT_5 21A8 22D2
22D3 21A8 BI R308 2 1 47K_5%_2
EC_PWRSW#
IN GPIO34/CIRRXL GPIO35/PSDAT1
BI 22D3 21A8 BI IM_CLK_5 R311 2 1 47K_5%_2
55B8 IN TP307 1 15 GPIO36 GPIO37/PSCLK1 72 IM_CLK_5
BI 21A8 22D2
R346 55A8 LOW_BAT#_3 TP30 80
2 1 OUT WL_OLED# 26
GPIO41/F_WP# P3V3AL
20B4 OUT GPIO51/N2TCK
100K_5%_2 34C4 USB_OC#_1 123 70 EC_SMB1_CLK 5D3 22D2 73C5
OUT EC_MUTE# 73
GPIO67/N2TMS GPIO17/SCL1/N2TCK
69 EC_SMB1_DATA
BI 73C5 22D3 5D3 BI EC_SMB1_CLK R322 2 1 3.3K_5%_2
27B6 25B6 OUT GPIO70 GPIO22/SDA1/N2TMS
BI 5D3 22D2 73C5 EC_SMB1_DATA 2 1
73C5 22D3 5D3 3.3K_5%_2
D 23D7 OUT WOL_AUX_ON# 74 GPIO71 GPIO73/SCL2 67 EC_SMB2_CLK
BI 5A7 22D2 41C6 66E2 BI EC_SMB2_CLK
R321
2 1 D
66E2 41C6 22D3 5A7 1.8K_5%_2
73A2 OUT HDP_ACT 75 GPIO72 GPIO74/SDA2 68 EC_SMB2_DATA
BI 5A7 22D2 41C3 66D2 BI EC_SMB2_DATA
R317
EC_SMB1 EC_SMB2 EC_SMB3 119 AOAC_ON# 22D2 29C2
66D2 41C3 22D3 5A7 BI R316 2 1 1.8K_5%_2
GPIO23/SCL3A
120 WLON# BI 29C2 22D3 BI AOAC_ON# 2
R334 1 10K_5%_2
GPIO31/SDA3A
BI 22D2 29B2 WLON#
1.BATTERY 1.CHARGE 33D4 33A5 USB30_PWR_EN 117 24 FLASH_OVERRIDE 29B2 22D3 BI 2
R335 1 10K_5%_2
OUT EC_ILIM_SEL 112
GPIO20/TA2/IOX_DIN_DIO GPIO47/SCL4A
28 LID_SW#_3 OUT 53B7 53B8
36C8 36A8 OUT GP(I)O84/IOX_SCLK/XORTR# GPIO53/SDA4A
IN 19C4
2.3D SENSOR 2.GPU THERMAL 36C8 36C1 36A8 EC_CTL2 110 17 IVDET_P3P 30C2
OUT PWR_WLED# 93
GPO82/IOX_LDSH/TEST# GPIO42/SCL3B/TCK
20 TP30 1 SLP_S5#_3R
IN
20C7 OUT GPIO06/IOX_DOUT GPIO43/SDA3B/TMS TP303 IN 15D2 55B3
3.CEC 21 TP30 TP304 1 H_PROCHOT_EC 22B1
GPIO44/SCL4B/TDI
23 TP30 1 SB_USB_2
OUT
GPIO46/SDA4B/CIRRXM/TRST# TP305 OUT 36A8 36C5 36C8
OUT LOGO_LED 91 GPIO81/F_WP# INV_PWM_3_R OUT 37A4
53A6 22C8 EC_SPI_CS0# 90 RSMRST# 22D3 55B7 55C2
OUT EC_SPI_CLK R342 1 33_5%_2
2 EC_SPI_CLK_R 92
F_CS0#
OUT
53A6 22C7 OUT F_SCK
1
82 EC_PW_ON# 15D8 16D4
EC_SPI_SI R341 1 33_5%_2
2 EC_SPI_SI_R 86
GPIO75/SPI_SCK
84 SB_USB_1
OUT
53A6 22C7 OUT F_SDI_F_SDIO1 GPIO77/SPI_DI
OUT 34C3 R333
EC_SPI_SO R340 1 2 EC_SPI_SO_R 87 83 EC_CTL1 R315
53A6 22C8 IN F_SDIO_F_SDIO0 GPIO76/SPI_DO
OUT 36A8 36C1 36C8 10K_5%_2
10K_5%_2
33_5%_2
P3V3AL 44 VCORF
2
P3V3AL
R313 2 10K_5%_2
AGND
GND1
GND2
GND3
GND4
GND5
GND6
1
1
U300 C310
53A6 22D6 EC_SPI_CS0# 1 8 WINB_NPCE885LA0DX_LQFP_128P
IN CS# VCC
1
7 1 R314 2 3.3K_5%_2 1UF_6.3V_2

0.1UF_16V_2
EC_SPI_SO 2
18
45
78
89
116
5
103
22C8 22C6 OUT SO_SIO1 HOLD#
53A6
C309
3 6 EC_SPI_CLK 22C7 22D6

4
WP#_ACC SCLK
5 EC_SPI_SI
IN 53A6 22C6
2
GND SI_SIO0
IN 22C7 PAD319
53A6 2 2 1
1
2
C MXIC_MX25L3206EM2I_12G_SOP_8P POWERPAD1X1M C
P3V3AL P3V3AL
R319
1 10K_5%_2_DY
2
0.1UF_16V_2_DY
U302 AGND_KBC
53A6 EC_SPI_CS1# 1 8
IN CS# VCC
1
EC_SPI_SO 2 17 R325 3.3K_5%_2_DY

2
22C8 22C6 OUT SO_SIO1 HOLD#
53A6
C318
53A6 3 6 EC_SPI_CLK 22C7 22D6

4
WP#_ACC SCLK
5 EC_SPI_SI
IN
GND SI_SIO0
IN 22C6 22C7
53A6
MXIC_MX25L3206EM2I_12G_SOP_8P_DY
2
47D6 11B7 OUT CPU_PROCHOT#
3
U301 Q300
SCAN_OUT<17..0> OUT 21D6
D
73A6 OUT HDP_INT# 31 GPIO56/TA1 KBSOUT0/GPOB0/JENK# 53 SCAN_OUT<0> 0 G 1 H_PROCHOT_EC IN 22D3
FAN_TACH1 IN 22B6 46C8 46C8 22B6 IN FAN_TACH1 63 GPIO14/TB1 KBSOUT1/GPIOB1/TCK 52 SCAN_OUT<1> 1
1
S
SCAN_OUT<2>
1
15A6 10A5 SA_PG 64 51 2

IN GPIO01/TB2 KBSOUT2/GPIOB2/TMS
50 SCAN_OUT<3>
C311 KBSOUT3/GPIOB3/TDI 3 SSM3K7002BFU R324
PWRBTN_LED# 32 49 SCAN_OUT<4> 4 100K_5%_2
2
21C2 OUT GPIO15/A_PWM KBSOUT4/GPOB4/JEN0#
680PF_50V_2 PCH_PWROK 118 48 SCAN_OUT<5> 5
55B7 55A6 OUT GPIO21/B_PWM KBSOUT5/GPIOB5/TDO
20A7 IN BAT_OLED# 62 GPIO13/C_PWM KBSOUT6/GPIOB6/RDY# 47 SCAN_OUT<6> 6
2
DCIN_WLED# 65 43 SCAN_OUT<7> 7
2
20A7 OUT GPIO32/D_PWM KBSOUT7/GPIOB7

21C2 OUT ECO_LED# 22 GPIO45/E_PWM KBSOUT8/GPIOC0 42 SCAN_OUT<8> 8
46C6 FAN1_PWM 81 41 SCAN_OUT<9> 9
OUT GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS#
SCAN_OUT<10>
B 21C7 OUT CAPS_LED#_3 66 GPIO33/H_PWM KBSOUT10_P80_CLK/GPIOC2 40 10 B
20D7 PWR_OLED# 16 39 SCAN_OUT<11> 11
OUT GPIO40/F_PWM KBSOUT11_P80_DAT/GPIOC3
38 SCAN_OUT<12>
KBSOUT12/GPIO64 12
KBSOUT13/GPIO63 37 SCAN_OUT<13> 13
25B6 OUT EC_SMMODE 111 GP(I)O83/SOUT_CR/TRIST# KBSOUT14/GPIO62 36 SCAN_OUT<14> 14
74C5 OUT CIR_OUT 113 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT 35 SCAN_OUT<15> 15
GPIO60/KBSOUT16 34 SCAN_OUT<16> 16
GPIO57/KBSOUT17 33 SCAN_OUT<17> 17
55B3 EC_32KHZ 77
IN LAN_RST# 30
GPIO00/EXTCLK
54 SCAN_IN<0> SCAN_IN<7..0> IN
23B5 0 21C6
OUT GPIO55/CLKOUT/IOX_DIN_DIO KBSIN0/GPIOA0/N2TCK
55 SCAN_IN<1>
KBSIN1/GPIOA1/N2TMS 1
KBSIN2/GPIOA2 56 SCAN_IN<2> 2
22F4 VCC_POR# 85 57 SCAN_IN<3> 3
IN VCC_POR# KBSIN3/GPIOA3
58 SCAN_IN<4>
KBSIN4/GPIOA4 4
R339 KBSIN5/GPIOA5 59 SCAN_IN<5> 5
58C2 47D5 BI H_PECI 1 2EC_PECI13 PECI KBSIN6/GPIOA6 60 SCAN_IN<6> 6
43_5%_2 12 VTT KBSIN7/GPIOA7 61 SCAN_IN<7> 7
P1V05S WINB_NPCE885LA0DX_LQFP_128P
A A
INVENTEC
TITLE
Block Diagram
SIZE CODE DOC.NUMBER REV

C CS 1310xxxxx-0-0 X01
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 400~499(LAN)
D
P3V3A Q400 P3V3A_LAN PAVDDVCO_LAN D
DIODES_DMP2305U_SOT23_3P
10UF_6.3V_3_DY
PAD400
S D 1 2
0.1UF_16V_2
4.7UF_6.3V_3
S D 1 2
1UF_6.3V_2
1
1
CSC0402_DY
0.047UF_16V_2
POWERPAD_2_0610
1UF_10V_2_DY
1
1
C403
C405
G
C400
C401
C402
C404
0.1UF_16V_2
C424
C425
G
2
1
2
2
WOL_AUX_ON# 1 R400 2
22D6 IN
100K_5%_2 R402
0_5%_3
PDVDDL_LAN PAVDDL_LAN
2
1UF_6.3V_2
1
1
0.1UF_16V_2
C427
C426
PVLX_LAN C423
0.1UF_16V_2
2
C FOR LDO MODE C
54A2 54C7
2 R403 1
10K_5%_2 PCIE_LAN_TX_DN IN 54D8
2 R404 1 PCIE_LAN_TX_DP IN 54D8
CLKREQ_LAN# 10K_5%_2_DY CLK_PCIE_LAN_DP IN 54C7
OUT CLK_PCIE_LAN_DN IN 54C7
41
40
39
38
37
36
35
34
33
32
31
P3V3A_LAN
P3V3S U400
LED_0
DVDDL_REG
AVDDL
AVDDL
LX
RX_P
REFCLK_P
GND
RX_N
REFCLK_N
LED_1
2
55B3 1
55A5 LAN_RST#
VDD33
30 PCIE_LAN_RX_C_DP C421 1 2 0.1UF_16V_2 PCIE_LAN_RX_DP OUT 54D8
22B6 R401 2 TX_P
35C6 IN PCIE_WAKE#
PERSTN
29 PCIE_LAN_RX_C_DN C422 1 2 0.1UF_16V_2 PCIE_LAN_RX_DN OUT 54D8
PAVDDL_LAN 30K_5%_2 29C7 3 TX_N
PVLX_LAN PDVDDL_LAN 33C6
OUT WAKEN
28
4 CLKREQN NC
27
L400 R406 5 ISOLATN TESTMODE
PAVDDH_LAN
26
10UF_6.3V_3_DY
1
0.1UF_16V_2_DY
1 2 1 2 6 SMDATA
1000PF_50V_2_DY
1UF_6.3V_2
AVDDL_REG
1
1
25
23A5 PAVDDH_LAN IN LAN_X1 7 XTLO SMCLK
1
LQM21PN2R2MC0D_DY 24
LAN_X2
C412
C413
RSC_0603_DY 23A5 8 PPS

IN XTLI
LED_2
23
C406
C407
9
0.1UF_16V_2
AVDDH_REG
C408
R405 22
1UF_6.3V_2
1
1
1 2 10 RBIAS AVDDH
21
0.1UF_16V_2
1
2.37K_1%_2 TRXN3
AVDD33
C420
B C414 B
AVDDL
AVDDL
TRXN0
TRXN1
TRXN2
2
TRXP0
TRXP1
TRXP2
TRXP3
C415
0.1UF_16V_2
2
2
FOR SW MODE
2
2
LAN_TRD0_DP ATHEROS_AR8161_AL3A_R_QFN_40P
12
13
14
15
16
17
18
19
20
24B7
11
24C7
BI LAN_TRD0_DN
24B7 BI
24C7 LAN_TRD1_DP
BI LAN_TRD1_DN
24B7 BI
24B7 24C7 LAN_TRD2_DP
BI LAN_TRD2_DN P3V3A_LAN
24B7 BI
24B7 LAN_TRD3_DP
BI LAN_TRD3_DN
24B7 BI
1
PAVDDL_LAN
C418 C419
1
1UF_10V_2_DY 0.1UF_16V_2
LAN_X1 23B5
LAN_X2 OUT C416
2
OUT 23B5 C417
X400 0.1UF_16V_2 0.1UF_16V_2
1 2
2
1
1
33PF_50V_2
33PF_50V_2
25MHZ
C409
C410
A C417:8161 STUFF 8162 OPEN A

2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 400~499(LAN)
CN400
24C3 24B2 LAN_TD_DP 1 JACK470
IN LAN_TD_DN
1
LAN_CN_TD_DP1
24C3 24B2 2
IN LAN_RD_DP
2 IN LAN_CN_TD_DN2
TX+
24C3 24B2 3
IN LAN_C_DP
3 IN LAN_CN_RD_DP3
TX-
24C2 24B2 4 G1
IN LAN_C_DN
4 IN LAN_CN_C_DP 4
RX+ G
24C2 24B2 5 G2
IN LAN_RD_DN
5 IN LAN_CN_C_DN 5
P4 G
24C3 24B2 6 G3
IN LAN_D_DP
6 IN LAN_CN_RD_DN6
P5 G
24C2 24B2 7 G4
D IN LAN_D_DN
7 IN LAN_CN_D_DP 7
RX- G
24C2 24B2 8
IN 8 IN LAN_CN_D_DN 8
P7
D
9 G1
9 G IN P8
10 10 G G2
SYN_100073HR008G13CZL_8P
ACES_50224_0100N_001_10P
U471
2 TCT TCT 15
24B7 23B5 LAN_TRD0_DN 3 14 LAN_TD_DN 24B2 24D7
IN LAN_TRD0_DP
TD- TX-
LAN_TD_DP
OUT
24B7 23B5 1 16 24B2 24D7
IN TD+ TX+ OUT
7 RCT RCT 10
C 24B7 23B5 LAN_TRD1_DN 8 9 LAN_RD_DN 24B2 24D7
C
IN LAN_TRD1_DP
RD- RX-
LAN_RD_DP
OUT
24B7 23B5 6 11 24B2 24D7
IN RD+ RX+ OUT
1
1
1
4 12
75_5%_3
75_5%_3
NC NC
0.1UF_16V_2
0.1UF_16V_2
5 13 2 R476 1 LAN_C_DN
NC NC OUT 24B2 24D7
2 R474
2 R475
C478
C479
RSC_0603_DY
BOTH_TS21C_HF_SOP_16P 2 R478 1 LAN_C_DP
OUT 24B2 24D7
RSC_0402_DY
2
2 R477 1 LAN_D_DN
OUT 24B2 24D7
RSC_0603_DY
2 R479 1 LAN_D_DP
OUT 24B2 24D7
RSC_0402_DY
PAVDDL_LAN
U470
1 TCT1 MCT1 24
24C7 23B5 LAN_TRD0_DN 3 22 LAN_TD_DN 24C3 24D7
IN LAN_TRD0_DP
TD1- MX1-
LAN_TD_DP
OUT
24C7 23B5 2 23 24C3 24D7
IN TD1+ MX1+ OUT
4 TCT2 MCT2 21
24C7 23B5 LAN_TRD1_DN 6 19 LAN_RD_DN 24C3 24D7
B IN LAN_TRD1_DP
TD2- MX2-
LAN_RD_DP
OUT B
24C7 23B5 5 20 24C3 24D7
IN TD2+ MX2+ OUT
7 TCT3 MCT3 18
23B5 LAN_TRD2_DN 9 16 LAN_C_DN 24C2 24D7
IN LAN_TRD2_DP
TD3- MX3-
LAN_C_DP
OUT
23B5 8 17 24C2 24D7
IN TD3+ MX3+ OUT
10 TCT4 MCT4 15
23B5 LAN_TRD3_DN 12 13 LAN_D_DN 24C2 24D7
IN LAN_TRD3_DP
TD4- MX4-
LAN_D_DP
OUT
23B5 11 14 24C2 24D7
IN TD4+ MX4+ OUT
BOTH_GST5009_RA_SOP_24P
1
75_5%_3
75_5%_3
75_5%_3
75_5%_3
CSC0402_DY
CSC0402_DY
CSC0402_DY
CSC0402_DY
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1
2 R470
2 R471
2 R472
2 R473
1UF_6.3V_2
C480
C481
C482
C483
C470
C471
C472
C473
C474
2
1
C475
1000PF_2000V_6
CSC0402_DY
A A
1
100PF_50V_2
C476
C477
2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P5V0A_AUDIO_AVDD
REFERENCE 500~549(AUDIO CODEC) R515
P5V0A 1 2
P5V0A_AUDIO_AVDD 0_5%_3
10UF_6.3V_3
Q501
1
DIODES_DMP2305U_SOT23_3P BLM18PG121SN1(6014B0041601_0603)
S D C519 C513
C530
S D
1
0.1UF_16V_2 4.7UF_6.3V_3
2
C525 C527
2
G
P5V0A
1
2
2
C503 CLOSE TO PIN27
1
AGND_AUDIO
D R521 AGND_AUDIO 2.2UF_6.3V_3 AGND_AUDIO
10K_5%_2
D
2
HP_R
1
OUT 26B4
1 R522 2 HP_L
32
C502 OUT 26B4

0_5%_2 2.2UF_6.3V_3 AMP_R
Q500 P3V3A P3V3S_DVDD33 OUT 27B7
Q502 AMP_L
D
EC_SMM_PWR
1 OUT 27B7
4.7UF_6.3V_3
2
22E3 IN G
0.1UF_16V_2
1
1
S S D D
S
1
2.2UF_6.3V_3
0.1UF_16V_2
1
C536
C500
36
35
34
33
32
31
30
29
28
27
26
25
SSM3K7002BFU
C501
C504
G
2
C526 C528
2
U500
2
AVSS2
HP-OUT-L
LINE1-L
CBN
HP-OUT-R
LINE1-R
MIC1-VREFO
VREF
CBP
CPVEE
2
AVDD1
AVSS1
1 R523 2
0_5%_2
37 MONO-OUT NC 24
AGND_AUDIO AGND_AUDIO
38 AVDD2 ANALOG LINE1-VREFO 23 MIC_VREFO OUT 26D1
P5V0A_AUDIO_AVDD P5V0A_PVDD
39 LINE2-L JDREF 22 1 2
C BLM18PG121SN1(6014B0041601_0603) DIGITAL R514 20K_1%_2 C
40 LINE2-R LDO-CAP 21
CLOSE TO PIN 22
1 2 41 PVDD1 MIC1-R 20 MIC_R BI 26D1
10UF_6.3V_3_DY
0.1UF_16V_2_DY
R516 0_5%_3 RESERVE FOR EMI

SPK_OUT_L_P MIC_L C512 AGND_AUDIO
1
26B8 OUT R512 1 2 0_5%_342 SPK-L+ MIC1-L 19

BI 26D1
1
C507 (THERMAL PAD 4X4 VIAS) 1 2

SPK_OUT_L_N
C532
C506
26B8 OUT R511 1 2 0_5%_343 SPK-L- NC 18 10UF_6.3V_3

0.1UF_16V_2
2
CLOSE TO PIN 21
OUT SPK_OUT_R_N R510 1 2 0_5%_344 SPK-R- NC 17
CLOSE TO PIN 41
AGND_AUDIO
2
26C8 OUT SPK_OUT_R_P R509 1 2 0_5%_345 SPK-R+ NC 16
46 PVDD2 AUX_CLK_In 15 12.288MHZ IN

CLOSE TO PIN13
10UF_6.3V_3
EC_SMMODE1 R517
IN 2 47 GPIO2/DMIC-DATA34 Sense B 14 12.288MHZ OSC
1
GPIO1/DMIC-DATA12
100K_5%_2
EC_MUTE# R500 MICS
GPIO0/DMIC-CLK
48 13 1 2
C529
C531 22D6 IN EAPD+PD# Sense A IN 26D6
GPIO3/SPDIFO
27B6 20K_1%_2
SDATA-OUT
0.1UF_16V_2 P3V3S_DVDD3349
EC_SMMODE (PIN47):
SDATA-IN
TML
BIT-CLK
DVDD-IO
R501
PCBEEP
HPS
RESET#
1
EC PULL HIGH PIN47 IN S&M MODE 1 2 26B2
IN
GPIO4
DVDD
SYNC
2
1
39.2K_1%_2
CLOSE TO PIN 46
B C523 B
R520 REA_ALC280Q_GRT_QFN_48P
0.1UF_16V_2
PD# (PIN48): 10K_5%_2 C520
EC OR DRIVER PULL LOW
2
1 2 1 R507 2 PCSPKR_PCH_3 IN 53C8

TO POWER DOWN CODEC INTERNAL AMP
10
12
1
11
C514 47K_1%_2
2 1 AND EXTERANL TWITTER AMP. 0.1UF_16V_2 C521
2 1
1000PF_50V_2
100PF_50V_2
1 R506 2
C515
2 1 4.7K_1%_2
1000PF_50V_2 HDA_3S_RST# IN 53C7
TIED UNDER OR NEAR CODEC HDA_3S_SYNC 53C7
C516 IN
2 1 PAD500 R502
HDA_R_SDIN0 1 2 HDA_3S_SDIN0 IN 53B7
1 1 2
2
1000PF_50V_2 22_5%_2
POWERPAD1X1M HDA_R_BITCLK 1 R503 2 HDA_3S_BITCLK
C517 IN 53C7
2 1 0_5%_2
MIC_IN_CLK 1 R505 HDA_3S_SDOUT IN 53B7
38A3 37A4 2 MIC_IN_CLK_R
1000PF_50V_2 BI
38A3 BI MIC_IN_DATA_R 0_5%_2
AGND_AUDIO P3V3A P3V3S_DVDD33
A AGND_AUDIO 1 R504 2 1 R519 2 A

0_5%_2 0_5%_2_DY
0.1UF_16V_2
0.1UF_16V_2
22PF_50V_2_DY
1UF_6.3V_2
1
1
C509
C510
C522
C518
2
2
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERCE 600~649(JACK/MIC/SPEAKER)
AUDIO JACKS
P3V3A
MIC_VREFO IN 25C1
MICS
3
IN 25B1
1
D601
D R610
100K_5%_2
MICPHONE PHP_PESD5V2S2UT_SOT23_3P
D
12
11
3
2
EC_JD# IN 22E6
Q601 JACK600 R604 R605
6TP607 R606
3
4.7K_5%_2 4.7K_5%_2
D
MIC_SENSE 6
MIC_SENSE
26D6
0_5%_3 C606 2.2UF_6.3V_3
G 1 26D3 Q600 15 26D5 R602
IN 26D5
5 OUT MIC_R
2 1 1 2 1 2
1K_5%_2 1 2
2
BI 25C2
D
2 TP30
S
G 1 MIC_SENSE IN 26D3 26D6 TP30 TP605
SSM3K7002BFU 1 1 1 1 2 1 2 1 2 MIC_L BI 25C2
S
13 1K_5%_2 2.2UF_6.3V_3
2
3 TP30 TP604 C607
7 R607 R603
SSM3K7002BFU 7 TP30 0_5%_3
2
SINGA_2SJ2311_000111_6PTP606
RESERVE FOR EMI
1
C600 C601
AGND_AUDIO AGND_AUDIO CSC0402_DY CSC0402_DY
AGND_AUDIO
2
C RESERVE FOR EMI C
INTERNAL SPEAKERS AGND_AUDIO
NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH
CN601
27B3 IN SPK_AMP_R_P 1 1
27B3 IN SPK_AMP_R_N 2 2
25B6 IN SPK_OUT_R_P 3 3
25C6 IN SPK_OUT_R_N 4 4
27B3 IN SPK_AMP_L_N 5 5
27B3 IN SPK_AMP_L_P 6 6 G G1
25C6 IN SPK_OUT_L_N 7 7 G G2
25C6 IN SPK_OUT_L_P 8 8
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
ACES_50224_0080N_001_8P D600
1
1
1
C609 2
C620
C608
C619
3
C602
C603
C615
C616
C617
C618
C604
C605
B B
2
2
HEADPHONE
2
AGND_AUDIO
JACK601
R601 R609 TP603 6 6
75_5%_2 0_5%_3 25B1 OUT HPS 1 5 5
25D2 IN HP_R 1 2 1 2 TP601 1 TP30
2 2
TP30
RESERVE FOR EMI 25D2 HP_L 1 2 1 2 TP600 1 1
IN TP30
1
1
TP602 3 3
R600 R608 7 7
75_5%_2 0_5%_3 TP30
SINGA_2SJ2311_000111_6P
470PF_50V_2_DY
470PF_50V_2_DY
1
1
C611
C610
AGND_AUDIO
2
A RESERVE FOR EMI A
AGND_AUDIO
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERCE 550~599(AUDIO AMP)
GAIN SETTING
G2 G1 AMP
0 0 11DB
D 0 1 14DB D
P5V0A_AMP
1 0 19DB
1 1 25DB
1
R554 R556
0_5%_2 0_5%_2_DY
27B5 OUT AMP_GAIN2
12
12
27B5 OUT AMP_GAIN1
R555 R557
0_5%_2_DY 0_5%_2
2
AGND_AUDIO
C C
P5V0A_AMP P5V0A_AUDIO_AVDD
1 L550 2
BLM18PG181SN1D
1
C550 C551 C552 C553 C554
0.22UF_6.3V_2 0.22UF_6.3V_2 1UF_16V_3 10UF_6.3V_3 CSC0805_DY
2
U550
13 TML
27D4 IN AMP_GAIN2
12 G2 OUT_LP 1 1
R550 2
0_5%_2 SPK_AMP_L_P
OUT 26B8
27C4 IN AMP_GAIN1
11 G1 OUT_LN 2 1
R551 2
0_5%_2 SPK_AMP_L_N
OUT 26B8
B 25D2 IN AMP_L R561 1 2 4.99K_1%_2 AMP_L_R 1
C556 2
0.015UF_10V_2 AMP_L_C 10 INPUT_L PVDD1 3 B
25D2 IN AMP_R R562 1 2 4.99K_1%_2 AMP_R_R 1
C557 2
0.015UF_10V_2 AMP_R_C 9 INPUT_R PVDD2 4
8 5 1
R552 2
0_5%_2 SPK_AMP_R_N 26C8
BYPASS OUT_RN
SPK_AMP_R_P
OUT
7 6 1
R553 2
0_5%_2 26C8
PD# OUT_RP OUT
REA_ALC105_VE_CG_DFN_12P
1
C558
R563 R564
C559 EC_MUTE# 1 R558 2 P5V0A_AMP
IN
470PF_50V_2 6.49K_1%_2 6.49K_1%_2 470PF_50V_2 1K_5%_2
2
1
R559
20K_5%_2
AMP_BYPASS
2
1
1
AGND_AUDIO
C555 R560
2.2UF_16V_3 22K_5%_2
2
A A
AGND_AUDIO
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERNCE 900~999(CARDREADER)
D
D
C913
R905 0_5%_2 1 2
28C3 BI SD_CMD 1 2 SD_CMD_R P3V3S_CR
C901
SD_D3 R906
1 0_5%_2
2 SD_D3_R 1 2 5PF_50V_2
28C3 BI
SD_D2 R907
1 0_5%_2
2 SD_D2_R
28C1 BI
1
1UF_6.3V_2
C906
SD_CLK_R R903
1 0_5%_2
2 SD_CLK C905
BI 28C3
0.1UF_16V_2
SD_D0_R R904
1 2 SD_D0 10UF_6.3V_3
0_5%_2 BI 28C3
2
P3V3S_CR
18
17
16
15
14
13
C909 C910
200K_5%_2 U900
C 1R909 2 4.7UF_6.3V 0.1UF_16V_2 C
SP6
SP5
SP4
DV33_18
SP3
SP2
0_5%_2 SD_D1 CN900
2
19 12 SD_D1_R R902
1 2
GPIO SP1 BI 28C1 SD_D3 1 G1
SD_WP 20 11 28C7 BI DAT3 GND
28C1 BI SP7 DV12_S
SD_CMD 2 G2
SD_CD# 21 10 28C7 BI CMD GND
28C1 BI SD_CD# CARD_3V3
3 G3
VSS GND
22 MS_INS# 3V3_IN 9
4 VDD WP 10 SD_WP BI 28C7
57A7 47C7 35C6 33C6 PLT_RST# 23 8
IN PERST# RREF
SD_CLK 5 11 SD_CD#
REFCLKN
REFCLKP
CLKREQ_CR# 24 7 28C4 BI CLK CD BI 28C7
54B6 28B7 OUT CLKREQ# AV12 P3V3S_CR SD_D2
1
P3V3S 6 9 28C7
VSS DAT2 BI
HSON
HSOP
25
HSIN
TML HSIP
SD_D1
R900 28C4 SD_D0 7 8 28C4
BI DAT0 DAT1 BI
R901 PLAST_CS1S_201_H_N_11P
1 2 CLKREQ_CR# 6.2K_1%_2
2
3
4
5
6
28C7 54B6
1
IN
2
10K_5%_2 REA_RTS5229_GR_QFN_24P
54D8 PCIE_CR_TX_DP
BI
54D8 PCIE_CR_TX_DN P3V3S
BI
54B6 CLK_PCIE_CR_DP
BI
54B6 CLK_PCIE_CR_DN
BI
54D8 PCIE_CR_RX_DP
1 2PCIE_CR_RX_C_DP
BI
1
1
1
C911 0.1UF_16V_2
C903
B 54D8 BI PCIE_CR_RX_DN
1 2PCIE_CR_RX_C_DN C907 C908 B
C900
C912 0.1UF_16V_2
0.1UF_16V_2
4.7UF_6.3V 0.1UF_16V_2 10UF_6.3V_3
2
2
CLK: CLKOUT 4
PCIE: PCIE 5
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1300~1349(WLAN)
D
D
SUPPORT AOAC:OPEN SUPPORT AOAC:STUFF
P3V3S
P3V3S
1
P3V3A
P1V5S
R1304
Q1300
0_5%_5
1
1 D S 4
2
2
C1302 C1304 5
1
10UF_6.3V_3 0.1UF_16V_2 6 G 3
PMOS_4D1S
C1307
TPC6111_DY
1
CSC0402_DY
C1305 C1301
2
C1306
0.1UF_16V_2 10UF_6.3V_3 CSC0402_DY
2
AOAC_ON# IN 22D2 22D3
CN1300
R1300
C 55B3 55A5 35C6 33C6 23B5 PCIE_WAKE# 1 2 0_5%_2 1 2 C
BI WAKE# 3.3V
3 Reserved GND 4
58B6 29B7 BTIFON# 1 R1301 2 0_5%_2 5 6
BI Reserved 1.5V
54B7 54A2 CLKREQ_WLAN# 7 8 LPC_3S_FRAME# 22E3 53C3
IN CLKREQ# Reserved IN
9 10 LPC_3S_AD<3> 22E3 53C3
GND Reserved IN
54B7 CLK_PCIE_WLAN_DN 11 12 LPC_3S_AD<2> 22E3 53C3
IN REFCLK- Reserved IN
54B7 CLK_PCIE_WLAN_DP 13 14 LPC_3S_AD<1> 22E3 53C3
IN REFCLK+ Reserved IN
15 16 LPC_3S_AD<0> 22E3 53C3
GND Reserved IN
62F5 57A8 40A1 36C3 30C3 29C3 22E3 BUF_PLT_RST# 17 18
IN Reserved GND
57A7 CLK_PCI_DEBUG 19 20
IN Reserved Reserved
21 22 BUF_PLT_RST# 22E3 29C7
GND PERST# IN
3
54D8 PCIE_WLAN_RX_DN 23 24 30C3 36C3
OUT PERN0 +3.3VAUX
40A1 57A8 Q1301
54D8 PCIE_WLAN_RX_DP 25 26
OUT PERP0 GND 62F5
D
27 28
GND 1.5V
G 1 WLON# IN 22D2 22D3
29 30 PCH_3A_ALERT_CLK 54D2
GND SMB_CLK BI 54D3 54D2
54D8 PCIE_WLAN_TX_DN 31 32 PCH_3A_ALERT_DAT
IN BI
S
PETN0 SMB_DATA
54D8 PCIE_WLAN_TX_DP 33 34 54D3
IN PETP0 GND
SSM3K7002BFU
35 36 USB_WLAN_DN 57C2
GND USB_D- BI
2
37 38 USB_WLAN_DP 57B2
Reserved USB_D+ BI
39 Reserved GND 40
41 Reserved LED_WWAN# 42
43 Reserved LED_WLAN# 44
B 0_5%_2
45 Reserved LED_WPAN# 46 B
BTIFON# 1 R1302 2 47 48
58B6 29C7 BI Reserved 1.5V
49 Reserved GND 50
PCI_3S_SERIRQ 1 R1303 2 51 52
53C2 22E3 IN 0_5%_2_DY Reserved 3.3V
G1 G G G2
BELLW_80003_1021_52P
A A
MINI CARD 1(WLAN)

INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1400~1499(3G)
P1V5S
D
D
1
0.1UF_16V_2
0.1UF_16V_2
22UF_6.3V_5
C1410
C1411
C1412
2
2
P3V3S
1
C1402 C1401 C1400
CN1400
1 WAKE# 3.3V 2 0.1UF_16V_2 0.1UF_16V_2
XBCCLK_P3P 3 4 22UF_6.3V_5
31B7 OUT Reserved GND
2
31C1 IN BCCDET_P3N 5 Reserved 1.5V 6
C 54A6 54A3 OUT CLKREQ_MSATA# 7 CLKREQ# Reserved 8 C
9 GND Reserved 10
54A6 IN CLK_MSATA_PCIE_DN 11 REFCLK- Reserved 12
54A6 IN CLK_MSATA_PCIE_DP 13 REFCLK+ Reserved 14
15 GND Reserved 16 BCIO_P5P BI 31A2
31A7 BCRST_P3N 17 18 31C2 IVDET_R_P3P 1 R1404 2IVDET_P3P 22D3
OUT BCPWON_P3P
Reserved GND OUT
1
31D8 19 20 0_5%_2
CLOSE TO CONN SIDE OUT Reserved Reserved
BUF_PLT_RST#
40A1 57A8
21 22 22E3 29C3
SATA_MINICARD_RX_DP C1405 1 0.01UF_50V_2 SATA_MINICARD_C_RX_DP
GND PERST# IN 29C7 36C3
53B3 2 23 24 R1405
BI SATA_MINICARD_RX_DN C1406 1 SATA_MINICARD_C_RX_DN
PERN0 +3.3VAUX
62F5
53B3 2 0.01UF_50V_2 25 26 47K_5%_2
BI PERP0 GND
27 GND 1.5V 28 P3V3S
29 30 USB_TV_DP
2
GND SMB_CLK BI 57B2
53B3 SATA_MINICARD_TX_DN C1407 1 2 0.01UF_50V_2 31 32 USB_TV_DN 57B2
BI PETN0 SMB_DATA BI
SATA_MINICARD_TX_DP C1408 1 2 0.01UF_50V_2
1
53B3 33 34
BI PETP0 GND
USB_TV2_DN
35 36 57B2
54C8 OUT PCIE_MSATA_RX_DN 1 2 GND USB_D-
USB_TV2_DP BI R1406
37 38 57B2
54C8 OUT PCIE_MSATA_RX_DP 1
R1400 2
0_5%_2_DY
Reserved USB_D+ BI 10K_5%_2_DY
39 Reserved GND 40
PCIE_MSATA_TX_DN R1401 0_5%_2_DY 41 42
54C8 IN Reserved LED_WWAN#
PCIE_MSATA_TX_DP 43 44 CPLGP1_P3P OUT
2
54C8 IN Reserved LED_WLAN# 31B4
P3V3S 45 Reserved LED_WPAN# 46 TMPTU1_SXP OUT 22E6
R1407 47 Reserved 1.5V 48
R1403 1 2 49 Reserved GND 50
MSATA_DET
1
58D6 1 2 0_5%_2_DY 51 52
B OUT Reserved 3.3V
B
0_5%_2_DY G1 G G G2
R1402
LOTES_AAA_PCI_093_P06_52P
10K_5%_2_DY
P16V0S_LNB
TMPTU2_SXP
2
22E6 OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2650~2999(RESERVE)
P5V0S P5V0S P5V0S_BCAS

Q2650
S D
D S D
1
D
1
G
R2650 C2651
10K_5%_2 R2652 C2652
CSC0402_DY
G
2.2K_5%_2 4.7UF_6.3V_3
2
1 R2651 2 C2650
1 2
2
33K_5%_2
0.047UF_16V_2
3
BCPWON_P3P 1
C
30C6 IN B
Q2651
E
LTC044EUBFS8TL
2
P5V0S_BCAS P3V3S
1
CN2650
1 VCC GND 5
R2659 1 2 BCCDET_P3N 30C6
BCRST_P5N IN
31A5 2 6 100K_5%_2 R2658 470_5%_2
IN RST VPP
3
31B5 C2653 IN XBCCLK_P5P 3 CLK IO 7 BCIO_P5P BI 30C3 Q2654
2
GND 8 31A2
D
C 0.1UF_16V_2 4 RSVD SWITCH D 1 G C
S
G1 G G G2
G3 G4 SSM3K7002BFU
G G
2
ACES_50785_00942_001_9P
P5V0S_BCAS
5
U2650
1
+
4XBCCLK_P5P 31C4
XBCCLK_P3P
OUT
30C6 2
IN
-
TC7SET08FU P5V0S_BCAS
P5V0S_BCAS
3
B B
1
R2654
10K_5%_2
1
E
2
P5V0S_BCAS
E
1 2 B B Q2653 R2656
C
R2655 10K_5%_2 MMST3906 10K_5%_2
C
CPLGP1_P3P
2
1
C
30B3 IN B
Q2652
5
U2651
E
LTC044EUBFS8TL
1
1
+
1 2 BCIO_P5P OUT 30C3 31C2

4 BCRST_P5N 31C4
OUT 1.5K_5%_2
2
BCRST_P3N
2 R2653 R2657
30C6 IN 10K_5%_2
-
TC7SET08FU
2
3
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1700~1749(HDD)
REFERENCE 1750~1799(ODD)
SATA HDD A SATA HDD B
PLACE CLOSE TO CONNECTOR(<100MILS) PLACE CLOSE TO CONNECTOR(<100MILS)
CN1700 CN1701
1 GND
0.01UF_50V_2 1
53C3 IN SATA_HDDA_TX_DP C1704 1 2 SATA_HDDA_TX_C_DP 2 A+ SATA_HDDB_TX_DP C1708 1 0.01UF_50V_2 SATA_HDDB_TX_C_DP
GND
0.01UF_50V_2 53C3 2 2
53C3 IN SATA_HDDA_TX_DN C1712 1 2 SATA_HDDA_TX_C_DN 3 A- IN SATA_HDDB_TX_DN C1707 1 0.01UF_50V_2 SATA_HDDB_TX_C_DN
A+
53C3 2 3
D 4 GND IN A-
0.01UF_50V_2 4
53C3 OUT SATA_HDDA_RX_DN C1700 1 2 SATA_HDDA_RX_C_DN 5 B- SATA_HDDB_RX_DN C1706 1 0.01UF_50V_2 SATA_HDDB_RX_C_DN
GND
D
0.01UF_50V_2 53C3 2 5
53C3 OUT SATA_HDDA_RX_DP C1701 1 2 SATA_HDDA_RX_C_DP 6 B+ OUT SATA_HDDB_RX_DP C1705 1 0.01UF_50V_2 SATA_HDDB_RX_C_DP
B-
53C3 2 6
7 GND OUT B+
7 GND
8 V3.3
8 V3.3
9 V3.3
9 V3.3
10 V3.3
10 V3.3
P5V0S 11 GND
P5V0S 11 GND
12 GND
12
40MIL 13 GND
40MIL 13
GND
GND
14 V5
14 V5
15
22UF_6.3V_5
22UF_6.3V_5
0.1UF_16V_2
V5
1
15
22UF_6.3V_5
22UF_6.3V_5
0.1UF_16V_2
V5
1
16 V5
C1713
C1703
C1702
16 V5
C1709
C1710
C1711
17 GND
17 GND
18 RESERVED
18 RESERVED
19 GND
19 GND
20 V12
20
2
V12
21 G1
2
V12 G1
21 V12 G1 G1
22 V12 G2 G2
22 V12 G2 G2
SANTA_191001_3_22P
SYN_127043HR022M22SZR_22P
C C
P5V0S
B B
1
P3V3S
C1754
3
R1752
CSC0402_DY
1
1M_5%_2
1
S
G
R1751
PMOS_4D1S
1 2
2
R1750 R1754
10K_5%_2
Q1751
100K_5%_2 0_5%_6_DY
TPC6111
2
Q1750
6
5
2
1
D
58D2 IN SATA_ODD_PWREN 1 G
S
C1758
2 1
SSM3K7002BFU
22UF_6.3V_5
22UF_6.3V_5
0.1UF_16V_2
2
0.047UF_16V_2
1
1
C1757
C1756
C1755
CN1750
P6
2
GND
P5 GND
A 57B6 SATA_ODD_DA# P4 A
57C7
OUT MD
P3 +5V
P2 +5V
SATA_ODD_PRSNT#
SATA ODD
58B6 P1
58D7
OUT DP
S7 GND
53B3 OUT SATA_ODD_RX_DP C1750 1 2 0.01UF_50V_2 SATA_ODD_RX_C_DP S6 B+
53B3 OUT SATA_ODD_RX_DN C1751 1 2 0.01UF_50V_2 SATA_ODD_RX_C_DN S5 B-
S4 GND
53B3 IN SATA_ODD_TX_DN C1753 1 2 0.01UF_50V_2 SATA_ODD_TX_C_DN S3 A-
SATA_ODD_TX_DP SATA_ODD_TX_C_DP
C1752 1
INVENTEC
53B3 2 0.01UF_50V_2 S2 G1
IN A+ G
S1 GND G G2
SUYIN_127382HR013M268ZR_13P
PLACE CLOSE TO CONNECTOR(<100MILS) TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2000~2099(USB) P3V3A P3V3_USB3

Q2403
S D
10UF_6.3V_3
P1V05_USB3
0.047UF_16V_2
CSC0402_DY
0.1UF_16V_2
0.1UF_16V_2
S D
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
1
1
1
C2454
C2400
C2401
C2402
C2403
C2404
C2405
C2470
C2471
C2441
G
R2424
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
10K_5%_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
1
G
C2417
C2421
C2423
C2424
C2425
3 2
2
R2427 2
C2418
C2419
C2420
C2422
1
2
220K_5%_2
Q2402
D
2
2
33A5 22D6 USB30_PWR_EN
1 G
IN
D
S
D
SSM3K7002BFU
2
P3V3_USB3 P1V05_USB3 P3V3_USB30_AVDD
12
22
34
43
21
30
33
39
42
25
6
3
U2400
VDD33
VDD33
VDD33
VDD33
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
AVDD33
AVDD33
54B7 IN CLK_PCIE_USB3_DP 1 PECLKP
54B7 IN CLK_PCIE_USB3_DN 2 PECLKN U3TXDP2 37 USB3_IC_TX2_DP BI 34B7
C2409 0.1UF_16V_2
54D8 OUT PCIE_USB3_RX_DP 1 2 PCIE_USB3_RX_C_DP 4 PETXP U3TXDN2 38 USB3_IC_TX2_DN BI 34B7
54D8 OUT PCIE_USB3_RX_DN 1 2 PCIE_USB3_RX_C_DN 5 PETXN U2DM2 45 USB2_IC_TX2_DN BI 34B4 34C3
C2410 0.1UF_16V_2
P3V3_USB3 54D8 IN PCIE_USB3_TX_DP 7 PERXP U2DP2 44 USB2_IC_TX2_DP BI 34B4 34C3
54D8 IN PCIE_USB3_TX_DN 8 PERXN U3RXDP2 40 USB3_IC_RX2_DP BI 34C3 34C4
U3RXDN2 41 USB3_IC_RX2_DN BI 34C3 34C4

C C
2 R4754 1 CLKREQ_USB3# IN 33B8 54B7
57A7 47C7 35C6 28C7 IN PLT_RST# 47 PERSTB P3V3_USB3
10K_5%_2
55B3 55A5 35C6 29C7 23B5 OUT PCIE_WAKE# 48 PEWAKEB
33B6 IN CLKREQ_IC_USB3# 10 PECREQB OCI2B 17 R2415 1 2 10K_5%_2 P3V3_USB3 P3V3_USB30_AVDD
R4955 OCI1B 19 R2416 1 2 10K_5%_2
1 2 USB3_SMI# IN 33C6 57B6
PPON2 18
10K_5%_2 57B6 33C7 USB3_SMI# 46 20
P3V3_USB3 OUT SMIB PPON1
1 L2400 2
BLM21PG600SN1D_3A
R2406
0.1UF_16V_2
0.1UF_16V_2
0.01UF_50V_2
0.01UF_50V_2
1
1
1 2 11
10UF_6.3V_3
PONRSTB
USB3_IC_TX1_DP
C2406
C2408
C2414
C2415
C2416
10K_5%_2 28 34C7
U3TXDP1 BI
2
33A6 OUT USB3_SCLK 15 SPISCK U3TXDN1 29 USB3_IC_TX1_DN BI 34C7

USB3_CS# 14 36 USB2_IC_TX1_DN
NC
33A8 OUT SPICSB U2DM1 BI 34C3 34C4

3 1 USB3_SI 16
2
33A6 OUT SPISI
33A8 IN USB3_SO 13 SPISO U2DP1 35 USB2_IC_TX1_DP BI 34C3 34C4
USB3_IC_RX1_DP
1
D2400 31 34D3 34D4

U3RXDP1 BI
DIODE-BAT54-TAP-PHP
C2411 U3RXDN1 32 USB3_IC_RX1_DN BI 34D3 34D4
1UF_6.3V_2 USB3_XT1 24 XT1
X2400 USB3_XT2 23 XT2
B 1 2 B
2
R2400
1
1.6K_1%_2
24MHZ 27 IC(L) RREF 26 1 2
C2413 C2412
12PF_50V_2 12PF_50V_2
GND
2
RENESAS_UPD720202K8_BAA_A_QFN_48P
49
R2405
54B7 33C7 OUT CLKREQ_USB3# 1 2 CLKREQ_IC_USB3# IN 33C6
0_5%_2
P1V5 P5V0A
U2403 P1V05_USB3
P3V3_USB3 9 VIN GND 1
P3V3_USB3 33D4 22D6 IN USB30_PWR_EN 8 EN
7 POK FB 2
PAD2400
TRACE WIDTH>20MILS 1
1
R2480 R2481 6 VCNTL VOUT 3 1 2

2
A A
1
10K_5%_2 47K_5%_2
POWERPAD1X1M
1
5 VIN VOUT 4
C2480
1 R2422 2
U2480 0.1UF_16V_2 ANPEC_APL5930KAI_TRG_SOP_8P
1
1
10K_1%_2
2
1 2 C2434
2
C2435
USB3_CS# 1 8 C2438
2
33B6 IN CS# VCC
1
22UF_6.3V_5 1UF_6.3V_2 22UF_6.3V_5
C2433
33B6 OUT USB3_SO 2 SO NC 7 150PF_50V_2
2
R2423
3 WP# SCLK 6 USB3_SCLK IN 33B6 31.6K_1%_2
INVENTEC
2
4 GND SI 5 USB3_SI IN 33B6
TITLE
MAC_MX25L5121EMC_20G_SOP_8P
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2400~2499(USB3.0)
D
D
CN2405
34D4 33B2 BI USB3_IC_RX1_DN1 1
USB3_PCH_RX1_DN USB3_IC_RX1_DN 34D4 33B2 BI USB3_IC_RX1_DP2 2

57C6 BI R2471 1 2 0_5%_2
BI 33B2 34D3 USB3_SSTX1_L_DN3
USB3_PCH_RX1_DP USB3_IC_RX1_DP 34C4 BI 3
57C6 BI R2472 1 2 0_5%_2
BI 33B2 34D3 USB3_SSTX1_L_DP4
34C4 BI 4
USB3_PCH_TX1_DN 34C4 33B2 BI USB2_IC_TX1_DN 5 5

57C6 1
R2469 20_5%_2
BI USB3_PCH_TX1_DP 34C4 33B2 BI USB2_IC_TX1_DP 6 6
57C6 1
R2470 20_5%_2
BI P3V3AL P3V3S 7 7
33B2 USB3_IC_TX1_DN C2491 1 2 0.1UF_16V_2 USB3_SSTX1_L_DN 34D3 P5V0A 33C2 USB3_IC_RX2_DN8
BI USB3_IC_TX1_DP BI BI 8
0.1UF_16V_2 USB3_SSTX1_L_DP 33C2 34C4 USB3_IC_RX2_DP9
1
33B2 BI C2492 1 2
BI 34C3 34C4 BI 9
34B4 BI USB3_SSTX2_L_DN
10 10
57C2 BI USB_P0_DN 1
R2475 20_5%_2 USB2_IC_TX1_DN BI 33B2 34C3 R2478 34B4 BI USB3_SSTX2_L_DP
11 11
57C2 BI USB_P0_DP 1
R2476 20_5%_2 USB2_IC_TX1_DP BI 33B2 34C3 10K_5%_2 BI USB2_IC_TX2_DN12 12
33C2 BI USB2_IC_TX2_DP13 13
34B4 14
2
14
22C3 IN SB_USB_1 15 15
C 22D6 OUT 16 16 G G1 C
USB_OC#_1 17 17 G G2
18 18
19 19
20 20
ACES_50501_02041_001_20P
57C6 BI USB3_PCH_RX2_DN R2483 1 2 0_5%_2 USB3_IC_RX2_DN BI 33C2 34C3
57C6 BI USB3_PCH_RX2_DP R2484 1 2 0_5%_2 USB3_IC_RX2_DP BI 33C2 34C3
57C6 BI USB3_PCH_TX2_DN 1
R2479 20_5%_2
57C6 BI USB3_PCH_TX2_DP 1
R2482 20_5%_2
33C2 BI USB3_IC_TX2_DN C2431 1 2 0.1UF_16V_2 USB3_SSTX2_L_DN BI 34C3

33C2 BI USB3_IC_TX2_DP C2436 1 2 0.1UF_16V_2 USB3_SSTX2_L_DP BI 34C3
57C2 BI USB_P1_DN 1
R2487 20_5%_2 USB2_IC_TX2_DN BI 33C2 34C3
57C2 BI USB_P1_DP 1
R2488 20_5%_2 USB2_IC_TX2_DP BI 33C2 34C3
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
SHEET
8 7 6 USB3.05 4
CHANGE by
3
XXX DATE 21-OCT-2002
2
34 of
1
76
8 7 6 5 4 3 2 1
P1V05_USB3
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
1
1
C2482
C2483
C2484
C2485
C2486
C2487
C2488
C2489
C2490
D
D
2
2
P3V3_USB3 P1V05_USB3 P3V3_USB30_1_AVDD
12
22
34
43
21
30
33
39
42
25
6
3
U2405 P3V3_USB3 P3V3_USB30_1_AVDD
VDD33
VDD33
VDD33
VDD33
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
AVDD33
AVDD33
1 L2401 2
54B7 IN CLK_PCIE_1_USB3_DP 1 PECLKP
CLK_PCIE_1_USB3_DN 2 37 USB3_IC_TX4_DP BLM21PG600SN1D_3A
54B7 IN PECLKN U3TXDP2 BI 36B8
0.1UF_16V_2
0.1UF_16V_2
0.01UF_50V_2
0.01UF_50V_2
1
1
0.1UF_16V_2
10UF_6.3V_3
C2456
OUT PCIE_USB3_RX1_DP PCIE_USB3_RX1_C_DP USB3_IC_TX4_DN
C2472
C2473
C2474
C2475
C2476
54D8 1 2 4 38 36B8
PETXP U3TXDN2 BI
54D8 OUT PCIE_USB3_RX1_DN 1 2 PCIE_USB3_RX1_C_DN 5 PETXN U2DM2 45 USB2_IC_TX4_DN BI 36A8 36B5
C2457 0.1UF_16V_2
54D8 IN PCIE_USB3_TX1_DP 7 PERXP U2DP2 44 USB2_IC_TX4_DP BI 36A8 36B5
C PCIE_USB3_TX1_DN 8 40 USB3_IC_RX4_DP C
2
54D8 IN PERXN U3RXDP2 BI 36B3 36B5
P3V3_USB3
U3RXDN2 41 USB3_IC_RX4_DN BI 36B3 36B5
2 R4755 1 CLKREQ_1_USB3# IN 35A8 54B7

57A7 47C7 33C6 28C7 IN PLT_RST# 47 PERSTB P3V3_USB3
10K_5%_2
55B3 55A5 33C6 29C7 23B5 OUT PCIE_WAKE# 48 PEWAKEB
35A6 IN CLKREQ_1_IC_USB3# 10 PECREQB OCI2B 17 R2462 1 2 10K_5%_2
R4957 OCI1B 19 R2463 1 2 10K_5%_2
1 2 USB3_1_SMI# IN 35C6 57B6
PPON2 18
10K_5%_2 57B6 35C7 OUT USB3_1_SMI# 46 SMIB PPON1 20
P3V3_USB3
R2458
1 2 11 PONRSTB
10K_5%_2 U3TXDP1 28 USB3_IC_TX3_DP BI 36D8
2
35A6 OUT USB3_1_SCLK 15 SPISCK U3TXDN1 29 USB3_IC_TX3_DN BI 36D8

USB3_1_CS# 14 36 USB2_IC_TX3_DN
NC
35A8 OUT SPICSB U2DM1 BI 36D5 36D8

3 1 35A6 OUT USB3_1_SI 16 SPISI
35A8 IN USB3_1_SO 13 SPISO U2DP1 35 USB2_IC_TX3_DP BI 36D5 36D8
USB3_IC_RX3_DP
1
D2401 31 36D3 36D5

U3RXDP1 BI
DIODE-BAT54-TAP-PHP
C2458 U3RXDN1 32 USB3_IC_RX3_DN BI 36D3 36D5
B 1UF_6.3V_2 USB3_3_XT 24 XT1
B
X2401 USB3_4_XT 23 XT2
1 2
2
R2464
1
1.6K_1%_2
24MHZ 27 IC(L) RREF 26 1 2
C2459 C2460
12PF_50V_2 12PF_50V_2
GND
2
RENESAS_UPD720202K8_BAA_A_QFN_48P
49
R2459
54B7 35C7 OUT CLKREQ_1_USB3#1 2 CLKREQ_1_IC_USB3# IN 35C6
0_5%_2
P3V3_USB3
P3V3_USB3
A A
1
R2460 R2461
1
10K_5%_2 47K_5%_2
C2461
U2406 0.1UF_16V_2
2
35B6 IN USB3_1_CS# 1 CS# VCC 8
35B6 OUT USB3_1_SO 2
3
SO NC 7
6 USB3_1_SCLK 35B6
INVENTEC
WP# SCLK IN TITLE
4 GND SI 5 USB3_1_SI IN 35B6 MODEL,PROJECT,FUNCTION
Block Diagram
MAC_MX25L5121EMC_20G_SOP_8P DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CLOSE TO U2405 P5V0A_USB3
57C6 BI USB3_PCH_RX3_DN R2432 1 2 0_5%_2 USB3_IC_RX3_DN BI 35B2 36D3

USB3_PCH_RX3_DP USB3_IC_RX3_DP
1
57C6 BI R2433 1 2 0_5%_2
BI 35B2 36D3
C2427
USB3_PCH_TX3_DN 1 2 C2432
57C6 BI R2430 0_5%_2
USB3_PCH_TX3_DP 1 2 C2426
57C6 BI R2431 0_5%_2
USB_IC_DN 0.1UF_16V_2 1000PF_50V_2
USB3_IC_TX3_DN USB3_SSTX3_DN 36C8 BI 22UF_6.3V_5
35B2 BI C2447 1 2 0.1UF_16V_2
BI 36D3 USB_IC_DP
2
USB3_IC_TX3_DP USB3_SSTX3_DP 36C8 BI
35B2 BI C2448 1 2 0.1UF_16V_2
BI 36D3
L2404 CN2401
CLOSE TO CN2401 USB_P2_R_DN WCM_2012_900T 1 VBUS
36D8 35B2 BI USB2_IC_TX3_DN R2505 1 2 0_5%_2 1
R2447 2 1
0_5%_2 2 USB_P2_L_DN 2 D-
D USB2_IC_TX3_DP USB_P2_L_DP
36D8 35B2 BI R2477 1 2 0_5%_2 1
R2446 2
0_5%_24 3 3 D+
4 D
USB_P2_R_DP 36D5
USB3_IC_RX3_DN
PGND
35B2 5
BI USB3_IC_RX3_DP
SSRX-
36D5 35B2 6 G1
BI SSRX+ G
R2456 2 7 G2
57C2 BI USB_P2_DN 1 0_5%_2 USB3_SSTX3_DN
GND G
36D5 8 G3
USB_P2_DP BI USB3_SSTX3_DP
SSTX- G
57C2 1 2 0_5%_2 P5V0A 36D5 9 G4
BI BI SSTX+ G
R2457
OCTEK_USB_09EREB_9P
36D5 35B2 BI USB2_IC_TX3_DN
1
P5V0A_USB4 P5V0A_USB3
36D5 35B2 BI USB2_IC_TX3_DP
EC_ILIM_SEL
1
36A8 22D6 IN U2401 C2442
0.1UF_16V_2
TI_TPS2540A_QFN_16P R2507
1
4
3
2
0_5%_3_DY
2
DP_OUT
DM_OUT
ILIM_SEL
IN
17
2
PWPD
SB_USB_2
1
36C5 36A8 22D3 5 16
IN EC_CTL1
EN ILIM0
R2494
36C1 36A8 22C3 6 15
IN EC_CTL2
CTL1 ILIM1
P5V0A C2501 BUF_PLT_RST# 0_5%_2 2 EC_CTL1
+
36C1 36A8 22D6 7 14 CURRENT LIMIT 2.5A 30C3 29C7 29C3 22E3 1 22C3 36A8 36C8
IN EC_CTL3
CTL2 GND
USB_OC#_2 62F5 57A8 40A1
IN OUT
1
8 13
DM_IN
36C1 36A8 22D3

DP_IN
IN CTL3 FAULT# OUT U2409 100UF_6.3V

OUT
36A6 36C3
NC
R2435 R2436 1 GND OUT 8
2
C P5V0A 24K_5%_2 210K_1%_2 2 IN OUT 7 C
3 IN OUT 6 P3V3AL P3V3A
9
10
12
R2498 P5V0A_USB3
11
36A8 22D3 IN SB_USB_2 4 EN OC# 5

1 2
2
36C8
1
R2495 10K_5%_2
1
100K_5%_2_DY GMT_G547E1P81U_MSOP_8P 1 2 EC_CTL2 OUT 22D6 36A8 36C8
R2500
C2500
36D4 BI USB_IC_DP 47UF_6.3V_5 10K_5%_2 R2496 10K_5%_2 EC_CTL3
1 2 36A8 36C8
USB_IC_DN OUT
36D4 BI
2
USB_OC#_2
2
OUT 22D3 36A6 36C6
P5V0A_USB4
1
CLOSE TO U2405
C2452
USB3_PCH_RX4_DN USB3_IC_RX4_DN C2453
57C6 BI R2439 1 2 0_5%_2
BI 35C2 36B3
USB3_PCH_RX4_DP USB3_IC_RX4_DP C2451
57C6 BI R2440 1 2 0_5%_2
BI 35C2 36B3
USB_IC_1_DN 0.1UF_16V_2 1000PF_50V_2
36A7 BI 22UF_6.3V_5
USB3_PCH_TX4_DN 1 20_5%_2 USB_IC_1_DP
2
57C6 BI R2437 36A7 BI
57C6 BI USB3_PCH_TX4_DP 1
R2438 20_5%_2
C2443 0.1UF_16V_2 L2403 CN2402
B 35C2 BI USB3_IC_TX4_DN 1 2 USB3_SSTX4_DN BI 36B3 USB_P3_R_DN WCM_2012_900T 1 VBUS B
35C2 BI USB3_IC_TX4_DP 1 2 USB3_SSTX4_DP BI 36B3 36A8 35C2 BI USB2_IC_TX4_DNR2503 1 2 0_5%_2 R2452
1 2
0_5%_2 1 2 USB_P3_L_DN 2 D-
C2444 0.1UF_16V_2 36A8 35C2 BI USB2_IC_TX4_DPR2504 1 2 0_5%_2 R2453
1 2
0_5%_2 4 3 USB_P3_L_DP 3 D+
4 PGND
36B5
CLOSE TO CN2402 USB_P3_R_DP 35C2 BI USB3_IC_RX4_DN 5 SSRX-
36B5 35C2 BI USB3_IC_RX4_DP 6 SSRX+ G G1
7 GND G G2
36B5 BI USB3_SSTX4_DN 8 SSTX- G G3
36B5 BI USB3_SSTX4_DP 9 SSTX+ G G4
OCTEK_USB_09EREB_9P
USB_P3_DN 1 R2489 2
57C2 BI 0_5%_2
57C2 BI USB_P3_DP 1 2 0_5%_2 P5V0A
R2490
36B5 35C2 BI USB2_IC_TX4_DN
1
36B5 35C2 BI USB2_IC_TX4_DP

36C8 22D6 IN EC_ILIM_SEL U2408 C2499
0.1UF_16V_2
TI_TPS2540A_QFN_16P
1
4
3
2
A A
DP_OUT
DM_OUT
ILIM_SEL
IN
PWPD 17
36C8 36C5 22D3 IN SB_USB_2 5 EN ILIM0 16
36C8 36C1 22C3 IN EC_CTL1 6 CTL1 ILIM1 15
36C8 36C1 22D6 IN EC_CTL2 7 CTL2 GND 14
EC_CTL3 USB_OC#_2 OUT
1
8 13
DM_IN
36C8 36C1 22D3

DP_IN
IN CTL3 FAULT#
OUT
36C3 36C6
NC
P5V0A R2492 R2493

24K_5%_2 210K_1%_2
R2497
INVENTEC
9
10
12
P5V0A_USB4
11
1 2
2
100K_5%_2_DY
TITLE
36B4 BI USB_IC_1_DP
36B4 BI USB_IC_1_DN Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
48B7 CPU_EDP_AUX_DP 1
C3300 2
0.1UF_16V_2_DY EDP_AUX_DP 37B4 P3V3S
IN OUT
48B7 CPU_EDP_AUX_DN 1
C3301 2
0.1UF_16V_2_DY EDP_AUX_DN 37B4
IN OUT
48B7 CPU_EDP_TX0_DP 1
C3302 2
0.1UF_16V_2_DY EDP_TX0_DP 37B4
IN OUT
48A7 CPU_EDP_TX0_DN 1
C3303 2
0.1UF_16V_2_DY EDP_TX0_DN 37B4
IN OUT
5
48B7 CPU_EDP_TX1_DP 1
C3304 2
0.1UF_16V_2_DY EDP_TX1_DP 37B4
IN OUT U3300
48A7 CPU_EDP_TX1_DN 1
C3305 2
0.1UF_16V_2_DY EDP_TX1_DN 37B4
IN OUT 1
+
65B2 OUT VGA_EDP_HPD 4 EDP_HPD IN 37B4
EDP_TX2_DP 37B4
OUT 2
EDP_TX2_DN 37B4
OUT
100K_5%_2
D
1
-
EDP_TX3_DP 37B4
OUT TC7SZ08FU D
EDP_TX3_DN 37B4
OUT
R3302
3
2
C3306
65C2 VGA_EDP_AUX_DP 1 2
IN
P1V05S
1
0.1UF_16V_2
R3305 R3306 P3V3S
100K_5%_2 100K_5%_2
1K_5%_2_DY
1
1
R3304
2
R3300
100K_5%_2
C3307
2
CPU_EDP_HPD#
32
VGA_EDP_AUX_DN 1 2 48B7 OUT
65C2 IN
0.1UF_16V_2
1
R3307 Q3300
D
G 1
SSM3K7002BFU_DY
100K_5%_2
C C
S
2
2
65B2 VGA_EDP_TX0_DP 1
C3308 2
0.1UF_16V_2 PVBAT_LCD
IN 38D3 IN P3V3S_LCM
65B2 VGA_EDP_TX0_DN 1
C3309 2
0.1UF_16V_2
IN
65C2 VGA_EDP_TX1_DP 1
C3310 2
0.1UF_16V_2 CN3300
IN G G1
65C2 VGA_EDP_TX1_DN 1
C3311 2
0.1UF_16V_2
IN 1 1
C3312 2
0.1UF_16V_2
IN 37D5 IN EDP_TX3_DN 2 2
C3313 2
0.1UF_16V_2
IN 37D5 IN EDP_TX3_DP 3 3
C3314 2
0.1UF_16V_2
IN 4 4
C3315 2
0.1UF_16V_2
IN 37D5 IN EDP_TX2_DN 5 5
37D5 EDP_TX2_DP 6
IN 6
7 7
37D5 EDP_TX1_DN 8
IN 8
37D5 EDP_TX1_DP 9
IN 9
10 10
37D5 EDP_TX0_DN 11
IN 11
37D5 EDP_TX0_DP 12
B IN 12
B
13 13
37D5 EDP_AUX_DP 14
IN 14
37D5 EDP_AUX_DN 15
IN 15
16 16
17 17
18 18
19 19
20 20
21 21
37D1 OUT EDP_HPD 22 22
23 23
24 24
IN EC_BKLTEN_R 25 25
22D1 IN INV_PWM_3_R 26 26
27 27
28 28
29 29
P3V3S 30 30
31 31
32 32
33 33
34 34
57B2 38A3 IN USB_CAM_DN 35 35
57B2 38A3 IN USB_CAM_DP 36 36
A 37 37
A
38A3 25A5 BI MIC_IN_CLK 38 38
BI MIC_IN_DATA 39 39
40 40
G G2
ACES_50203_04001_001_40P
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P5V0S P3V3S
REFFERENCE 3000~3049(LCM) P3V3S P5V0S
0_5%_3_DY
1
0_5%_3
CN3001
R3008
R3048
1 1
Q3000 USB_3D_DN 2
57B2 BI 2
DIODES_DMP2305U_SOT23_3P PAD3003 USB_3D_DP 3 G1
P3V3S_MOS_LCM P3V3S_LCM 57B2 BI 3 G
2
S D 1 2 37C4 4 G2
S D 1 2 OUT 4 G
5 5
0.01UF_50V_2
POWERPAD_2_0610 6
0.1UF_16V_2
10UF_6.3V_3
6
1
G
1
1
C3000
C3001
ACES_50224_0060N_001_6P
47K_5%_2
C3003
C3002
R3000
2 1
G
680PF_50V_2
2
2
2
D
2
2
R3001 R3004 D
VGA_LCM_VDDEN R3010 1 2 PCH_LCM_VDDEN#
66D2 66C3 1 2 100_5%_2
IN
3
Q3001 470K_5%_2
13
0_5%_2
R3011
D
PCH_LCM_VDDEN1 2 1 Q3002
56D7 IN G
D
0_5%_2_DY 1 G
S
SSM3K7002BFU
S
2
SSM3K7002BFU
2
P3V3S
VGA_LVDS_TXDB0_DP R30351 2 0_5%_2

65E5 BI
VGA_LVDS_TXDB0_DN R30341 2 0_5%_2
0.1UF_16V_2
65E5 BI
1
R30331 0_5%_2 P3V3S
VGA_LVDS_TXCA_DP
C3004
65F5 2
BI
VGA_LVDS_TXCA_DN R30321 2 0_5%_2
65F5 BI
R30311 0_5%_2
1 R3002 2
1 R3005 2
65E5 BI VGA_LVDS_TXDA2_DP 2
2.2K_5%_2
2.2K_5%_2
C 0_5%_2
C
2
VGA_LVDS_TXDA2_DN R30301 2
65E5 BI
VGA_LVDS_TXDA1_DP R30291 2 0_5%_2
65E5 BI CN3000
R30281 0_5%_2 G G1
65E5 BI VGA_LVDS_TXDA1_DN 2
VGA_LVDS_DDCCLK
66D3 BI R30131 2 0_5%_2 1 1
VGA_LVDS_TXDA0_DP R30271 2 0_5%_2 VGA_LVDS_DDCDATA
65F5 BI 66D3 BI R30121 2 0_5%_2 2 2
R30261 0_5%_2 3 3
VGA_LVDS_TXDA0_DN 2
65F5 BI 56D7 PCH_LVDS_DDCCLK R30141 2 0_5%_2_DY 4
BI PCH_LVDS_DDCDATA
4
56C7 BI R30151 2 0_5%_2_DY 5 5
6 6
56C6 PCH_LVDS_TXDA0_DN R30161 2 0_5%_2_DY LVDS_TXDA0_DN 7
BI PCH_LVDS_TXDA0_DP LVDS_TXDA0_DP
7
56C6 BI R30171 2 0_5%_2_DY 8 8
9 9
BI 10
56C6 PCH_LVDS_TXDA1_DP R30191 2 0_5%_2_DY LVDS_TXDA1_DP 11
BI 11
12 12
BI 13
56C6 PCH_LVDS_TXDA2_DP R30211 2 0_5%_2_DY LVDS_TXDA2_DP 14
BI 14
15 15
56C6 PCH_LVDS_TXCA_DN R30221 2 0_5%_2_DY LVDS_TXCL_DN 16
BI 16
56C6 PCH_LVDS_TXCA_DP R30231 2 0_5%_2_DY LVDS_TXCL_DP 17
BI 17
18 18
B 56B6 PCH_LVDS_TXDB0_DN R30241 2 0_5%_2_DY LVDS_TXDB0_DN 19 B
BI 19
56B6 PCH_LVDS_TXDB0_DP R30251 2 0_5%_2_DY LVDS_TXDB0_DP 20
BI 20
21 21
56B6 BI PCH_LVDS_TXDB1_DNR3042 2 1 0_5%_2_DY LVDS_TXDB1_DN 22 22
56B6 BI PCH_LVDS_TXDB1_DPR3043 2 1 0_5%_2_DY LVDS_TXDB1_DP 23 23
24 24
56B6 BI PCH_LVDS_TXDB2_DNR3044 2 1 0_5%_2_DY LVDS_TXDB2_DN 25 25
56B6 BI PCH_LVDS_TXDB2_DPR3045 2 1 0_5%_2_DY LVDS_TXDB2_DP 26 26
27 27
56B6 PCH_LVDS_TXCB_DN R3046 2 1 0_5%_2_DY LVDS_TXCB_DN 28
BI PCH_LVDS_TXCB_DP LVDS_TXCB_DP
28
56B6 BI R3047 2 1 0_5%_2_DY 29 29
30 30
VGA_LVDS_TXDB1_DNR3036 56D7 IN PCH_INV_PWM_3100_5%_2_DY2 1 R3009 INV_PWM_3_R 31 31

65E5 2 1 0_5%_2
BI VGA_LVDS_TXDB1_DPR3037 22E6 IN EC_BKLTEN 100_5%_21 2 R3003 EC_BKLTEN_R 32 32
65E5 2 1 0_5%_2
BI 33
1000PF_50V_2
VGA_INV_PWM_3 100_5%_21 33
100K_5%_2
1
1
CSC0402_DY
66D3 2 R3049
VGA_LVDS_TXDB2_DNR3038 IN 34 34
C3006
65E5 2 1 0_5%_2
BI
C3007
R3006
35 35
65E5 BI VGA_LVDS_TXDB2_DPR3039 2 1 0_5%_2 USB_CAM_DN
57B2 37A4 36
IN USB_CAM_DP
36
57B2 37A4 37
65E5 BI VGA_LVDS_TXCB_DN R3040 2 1 0_5%_2 P3V3S IN 37
38
VGA_LVDS_TXCB_DP R3041 2 1 0_5%_2
38
2
65E5 BI MIC_IN_CLK 39
IN MIC_IN_DATA_R2 R3007 1 MIC_IN_DATA40
39
IN 40
100_5%_2 G G2
1
ACES_50203_04001_001_40P
A C3008 A
0.1UF_16V_2
PVBAT PVBAT_LCD
2
PAD3001
1 1 2
2
VGA_LCM_BKLTEN R3451 0_5%_2
2
66D2 66C3 IN
0.1UF_25V_3
POWERPAD_2_0610
4.7UF_25V_5
PCH_LCM_BKLTEN R344 1 0_5%_2_DY LCM_BKLTEN
1
56D7 2 22E6
IN OUT
C3009
C3010
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 3050~3099(CRT)
P5V0S
2
CRTR 1 R3057 2 CRTR_R L3052 1 2 120NH,5% CRTR_L
56B7 IN OUT 39A7 39C3
0_5%_2_DY D3050
L3051 SBR3U40P1
CRTG 1 R3058 2 CRTG_R 1 2 CRTG_L
56B7 IN 120NH,5% OUT 39A7 39C3
0_5%_2_DY
1
L3050 CRTB_L
56B7 CRTB 1 R3059 2 CRTB_R 1 2 120NH,5% 39A7 39C3
IN OUT P5V0S_CRT1
0_5%_2_DY
D
15PF_50V_2
1
15PF_50V_2
15PF_50V_2
D
2 R3054 1
2
VGA_CRTR R3065 0_5%_2
150_1%_2
150_1%_2
150_1%_2
66F5 1 2
IN
C3052
C3050
C3051
FUSE3050
R3055
R3056
VGA_CRTG R3067
1 0_5%_2
2
66F5 IN SMD1812P110TF
VGA_CRTB R3069
1 0_5%_2
2
2
66F5 IN
1
P5V0S_CRT2
P5V0S_CRTVDD CN3051
39D5 39A7 IN CRTR_L 1 1
39D5 39A7 CRTG_L 2
IN CRTB_L
2
39D5 39A7 3
IN 3
1 TP24 4 4
TP3050 5 5
1
1
6 6
R3050 R3051 7 7
8 8
2.2K_5%_2 9
2.2K_5%_2 9
10 10
2
2
1TP24 11 11
CRT_DDCDATA_OUT 1 R3053 2 CRT_DDCDATA_R_OUT TP3051 12 G1
39A3 BI 12 G
C 39A3 CRT_HSYNC_R_OUT 13 G2 C
100_5%_2 IN CRT_VSYNC_R_OUT
13 G
39A3 14
CRT_DDCCLK_OUT R3052 IN CRT_DDCCLK_R_OUT
14
39A3 1 2 15
BI 15
100_5%_2 SUYIN_070546HR015M251ZR_15P
1
C3053 C3054
0.1UF_16V_2_DY 0.1UF_16V_2_DY
2
CRT_DDCDATA R3076 0_5%_2_DY CRT_DDCDATA_R
56A6 CRT_VSYNC R3070
1 0_5%_2_DY
2 CRT_VSYNC_ROUT 39A4 IN 1 2
OUT 39A4 RESERVE CAP FOR EMI
IN
VGA_CRT_DDCDATA R3077
1 0_5%_2
2
VGA_CRT_VSYNC R3071
1 0_5%_2
2 66F5 IN
66F5 IN
CRT_DDCCLK R3079 0_5%_2_DY CRT_DDCCLK_R

B 56A6 CRT_HSYNC R3073
1 0_5%_2_DY
2 CRT_HSYNC_R 39A4 IN 1 2
OUT 39A4 B
IN OUT
VGA_CRT_DDCCLK R3080
1 0_5%_2
2
VGA_CRT_HSYNC R3074
1 0_5%_2
2 66F5 IN
66F5 IN
P5V0S P3V3S
1
C3056
R3060 R3061
0.22UF_6.3V_2
2.2K_5%_2 2.2K_5%_2
2
P3V3S
U3050
1 16 CRT_VSYNC_OUT 1 R3062 2 30_5%_2 CRT_VSYNC_R_OUT 39C3
VCC-SYNC SYNC_OUT2 OUT
2 15 CRT_VSYNC_R 39B6
VCC-VIDEO SYNC_IN2 IN
A 39D5 39C3 CRTR_L 3 14 CRT_HSYNC_OUT 1 R3063 2 30_5%_2 CRT_HSYNC_R_OUT 39C3 A
IN VIDEO_1 SYNC_OUT1 OUT
1
39D5 39C3 IN CRTG_L 4 VIDEO_2 SYNC_IN1 13 CRT_HSYNC_R

IN 39B6
C3055 39C3 IN CRTB_L 5 VIDEO_3 DCC_OUT2 12 CRT_DDCDATA_OUT
OUT 39C5
P5V0S_CRTVDD 39D5 6 11 CRT_DDCDATA_R 39B4
GND DDC_IN2 IN
0.22UF_6.3V_2 7 10 CRT_DDCCLK_R 39B4
VCC-DCC DDC_IN1 IN
8 9 CRT_DDCCLK_OUT 39C5
BYP DDC_OUT1 OUT
2
TI_TPD7S019_15DBQR_SSOP_16P
C3057
0.22UF_6.3V_2
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 3150~3199(HDMI)
PLACE CLOSE TO CONNECTOR
56B3 PCH_HDMI_TX2_DP C4744 1 20.1UF_16V_2_DY HDMI_TX2_C_DP

BI
65E1 BI VGA_HDMI_TX2_DP C3152 1 2 0.1UF_16V_2
P5V0AL
56B3 PCH_HDMI_TX2_DN C4745 1 20.1UF_16V_2_DY HDMI_TX2_C_DN
BI
1
65E1 BI VGA_HDMI_TX2_DN C3153 1 2 0.1UF_16V_2
2 NC D3150
BI
VGA_HDMI_TX1_DP DIODE-BAT54-TAP-PHP
65E1 BI C3154 1 2 0.1UF_16V_2
D
D
3
56B3 PCH_HDMI_TX1_DN C4747 1 20.1UF_16V_2_DY HDMI_TX1_C_DN
BI
1
VGA_HDMI_TX1_DN R3152
65E1 BI C3155 1 2 0.1UF_16V_2 R3153
2.2K_5%_2
2.2K_5%_2
2
2
BI
65E1 BI VGA_HDMI_TX0_DP C3156 1 2 0.1UF_16V_2
56B3 PCH_HDMI_TX0_DN C4749 1 20.1UF_16V_2_DY HDMI_TX0_C_DN CN3150

BI 1 1
65E1 VGA_HDMI_TX0_DN C3157 1 2 0.1UF_16V_2 2
BI 2
3 3
4 4
56B3 PCH_HDMI_TXC_DP C4750 1 20.1UF_16V_2_DY HDMI_TXC_C_DP 5
BI 5
6 6
65E1 BI VGA_HDMI_TXC_DP C3158 1 2 0.1UF_16V_2 7 7
8 8
9
56B3 PCH_HDMI_TXC_DN C4751 1 20.1UF_16V_2_DY HDMI_TXC_C_DN 9
BI 10 10
65E1 BI VGA_HDMI_TXC_DN C3160 1 2 0.1UF_16V_2 11 11
12 12
C 41D6 HDMI_CEC 13 C
BI TP24 1
13
14 14
P5V0AL HDMI_CN_DDCCLK TP3151 15 P1
41D3 40B5 BI 15 P1
D3155 41C3 40B5 HDMI_CN_DDCDATA 16 P2
BI 16 P2
P3V3S FUSE3150 17 17 P3 P3
40MIL 2 1 P5V0AL_HDMI_VDD1 1 2 P5V0AL_HDMI_VDD2 18 18 P4 P4
19 19
SMD1812P110TF
R3154 SUYIN_100042GB019M173ZR_19P
SBR3U40P1 41C1 OUT HPDET_IC 1 2
1
GM: 2.2K 1K_5%_2
1
2
2.2K_5%_2
2.2K_5%_2
C3150 R3150
PM:10K C3151
R4863
R4864
100PF_50V_2
(60130B1030ZT) P3V3S 470K_5%_2
22PF_50V_2_DY
2
CLOSE TO CONNECTOR
2
Q3151
G
SSM3K17FU P3V3S
R3174 0_5%_2
65E1 BI VGA_HDMI_DDCDATA1 2 HDMI_DDCDATA S S D D HDMI_CN_DDCDATA BI 40C3 41C3
B B
G
1
Q3150
G
R3165
SSM3K17FU
65E1 VGA_HDMI_DDCCLK 1 R3176 20_5%_2 HDMI_DDCCLK S S D D HDMI_CN_DDCCLK 40C3 41D3 100K_5%_2
BI BI
2
Q3152
G
R3175
PCH_HDMI_DDCDATA1 0_5%_2_DY
2
56B2 BI
HDMI_TXC_C_DP 1 R3164 2 SSM3K7002BFU
3 2
IN D S
680_5%_2
PCH_HDMI_DDCCLK R3177
1 0_5%_2_DY
2
56B2 BI HDMI_TXC_C_DN R3163
1 2
IN
680_5%_2
R3162
IN HDMI_TX0_C_DN 1 2
P3V3S
680_5%_2
R3161
5
HDMI_TX0_C_DP 1 2
IN U3150
A 680_5%_2 1 HDMI_HPD_EC A
+
IN 22D6 41B1
PCH_HPDET R3178
1 0_5%_2_DY
2 HPDET 4
56B2 BI
R3160 2 BUF_PLT_RST# IN
HDMI_TX1_C_DN 1 2 22E3 29C3 29C7 30C3
IN 36C3 57A8 62F5
-
680_5%_2 R3179 TC7SZ08FU
VGA_HPDET 1 2
3
65E1 BI
R3159
IN HDMI_TX1_C_DP 1 2
0_5%_2
680_5%_2
IN HDMI_TX2_C_DN 1
R3158
680_5%_2
2 INVENTEC
TITLE
R3157
HDMI_TX2_C_DP 1 2 MODEL,PROJECT,FUNCTION
IN Block Diagram
680_5%_2 DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3AL
P3V3AL
1
D3200
2 R3201 Q3201
G
NC
DIODE-BAT54-TAP-PHP
4.02K_1%_2 SSM3K17FU
G
D
2
3
41B3 BI HDMI_DDCCLK_CEC S S D HDMI_CN_DDCCLK
D
BI 40B5 40C3 D
P3V3AL
1
P3V3AL
R3204
27K_5%_2
1
5
NC
U3203
+
R3214 HDMI_CEC
1
41B6 IN CEC_IN1 24 2
BI 40C3
R3200
G
- Q3200
68_5%_2 4.02K_1%_2
3
SSM3K17FU
G
74LVC1G14GV Q3203
3
2
R3206
D
G 1 1 2 CEC_OUT OUT 41B6 41B3 BI HDMI_DDCDATA_CEC S S D DHDMI_CN_DDCDATA

BI 40B5 40C3
1
P3V3AL
S
22K_5%_2
SSM3K7002BFU
2
0.1UF_16V_2
R3205
1
100K_5%_2 P3V3AL
C3200
P3V3AL
2
C C
1
2
1
1
4.7K_5%_2
4.7K_5%_2
R3209
R3208
R3213
R3210
4.7K_5%_2
4.7K_5%_2
1
5
NC
U3202
2
66E2 U3200
2
2
EC_SMB2_CLK 1 20 EC_SMB2_DATA
+
22D2 5A7 BI P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1 BI 5A7 22D2 R3227
22D3 2 P3_7-CNTR0#-SSO-TXD1 P3_3-TCIN-INT3#-SSI00-CMP1_0 19 22D3 66D2 1 2 4 2 HPDET_IC IN 40C4
3 18 HDMI_DDCDATA_CEC 41C5
CEC_XOUT
RESET# P1_0-KI0#-AN8-CMP0_0 BI
41A8 4 17 HDMI_DDCCLK_CEC 41D5 33_5%_2 -
OUT XOUT-P4_7 P1_1-KI1#-AN9-CMP0_1 BI
5 VSS-AVSS P4_2-VREF 16
CEC_XIN 6 15 PHP_74LVC1G17_SOT753_5P
3
41A6 IN XIN-P4_6 P1_2-KI2#-AN10-CMP0_2
7 VCC-AVCC P1_3-KI3#-AN11-TZOUT 14
8 MODE P1_4-TXD0 13
41D8 IN CEC_IN 9 P4_5-INT0#-RXD1 P1_5-RXD0-CNTR01-INT11# 12
41C6 OUT CEC_OUT 10 P1_7-CNTR00-INT10# P1_6-CLK0-SSI01 11
R3203
1 2
RENESAS_R5F211B4D61SP_LSSOP_20P
P3V3AL 0_5%_2_DY
B B
0.1UF_16V_2
1UF_6.3V_2
1
1
C3202
C3205
HDMI_HPD_EC OUT 22D6 40A1
RSC_0402_DY
1
R3202
2
2
P3V3AL
2
1
1
47K_5%_2
47K_5%_2
R3211
R3212
2
41B6 OUT CEC_XOUT CEC_XIN IN 41B6
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4100~4199(DDR)
49A4 43D8 BI
M_A_A<15..0>
M_A_DQ<63..0>
CHA DIMM0 BUTTOM
CN4100 BI 43D5 49D8
0 M_A_A<0> 98 A0 DQ0 5 M_A_DQ<0> 0
1 M_A_A<1> 97 A1 DQ1 7 M_A_DQ<1> 1
2 M_A_A<2> 96 A2 DQ2 15 M_A_DQ<2> 2
3 M_A_A<3> 95 A3 DQ3 17 M_A_DQ<3> 3
4 M_A_A<4> 92 A4 DQ4 4 M_A_DQ<4> 4
5 M_A_A<5> 91 A5 DQ5 6 M_A_DQ<5> 5
6 M_A_A<6> 90 A6 DQ6 16 M_A_DQ<6> 6
7 M_A_A<7> 86 A7 DQ7 18 M_A_DQ<7> 7
8 M_A_A<8> 89 A8 DQ8 21 M_A_DQ<8> 8
D 9 M_A_A<9> 85 A9 DQ9 23 M_A_DQ<9> 9 P1V5
CN4100
10 M_A_A<10> 107 A10/AP DQ10 33 M_A_DQ<10> 10 D
LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN 75 VDD1 VSS16 44
11 M_A_A<11> 84 A11 DQ11 35 M_A_DQ<11> 11
76 VDD2 VSS17 48
12 M_A_A<12> 83 A12/BC# DQ12 22 M_A_DQ<12> 12
1
81 VDD3 VSS18 49
13 M_A_A<13> 119 A13 DQ13 24 M_A_DQ<13> 13
C4101 C4102 C4103 C4104 C4105 C4106 C4107 82 VDD4 VSS19 54
14 M_A_A<14> 80 A14 DQ14 34 M_A_DQ<14> 14 C4100
+
87 VDD5 VSS20 55
15 M_A_A<15> 78 A15 DQ15 36 M_A_DQ<15> 15
88 VDD6 VSS21 60
DQ16 39 M_A_DQ<16> 16 330UF_2.5V_DY 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 61
49A8 43D8 IN M_A_BS0 109 BA0 DQ17 41 M_A_DQ<17> 17 VDD7 VSS22
94 65
2
99 66
NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S 100 71
M_CS#0 40 M_A_DQ<20> VDD10 VSS25
1
49C5 114 20
IN M_CS#1
S0# DQ20
105 VDD11 VSS26 72
49C5 121 42 M_A_DQ<21> 21 C4110 C4109 C4108
IN M_CLK_DDR0_DP
S1# DQ21
P3V3S 106 VDD12 VSS27 127
49D4 101 50 M_A_DQ<22> 22
IN M_CLK_DDR0_DN
CK0 DQ22
111 VDD13 VSS28 128
49D4 103 52 M_A_DQ<23> 23
IN M_CLK_DDR1_DP
CK0# DQ23
10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 112 VDD14 VSS29 133
49D4 102 57 M_A_DQ<24> 24
IN M_CLK_DDR1_DN
CK1 DQ24
117 VDD15 VSS30 134
104 59 M_A_DQ<25> 25
2
49D4 IN CK1# DQ25
118 138
49D4 IN M_CKE0 73 CKE0 DQ26 67 M_A_DQ<26> 26 VDD16 VSS31
1
123 139
49D4 IN M_CKE1 74 CKE1 DQ27 69 M_A_DQ<27> 27 VDD17 VSS32
124 144
49A8 43C8 IN M_A_CAS# 115 CAS# DQ28 56 M_A_DQ<28> 28 C4114 C4115
VDD18 VSS33
145
49A8 43C8 IN M_A_RAS# 110 RAS# DQ29 58 M_A_DQ<29> 29 VSS34
199 150
49A8 43C8 IN M_A_WE# 113 WE# DQ30 68 M_A_DQ<30> 30 2.2UF_6.3V_3 0.1UF_16V_2
VDDSPD VSS35
151
42A6 OUT SA0_DIM0 197 SA0 DQ31 70 M_A_DQ<31> 31 VSS36
77 155
2
54A8 42A6 OUT SA1_DIM0 201 SA1 DQ32 129M_A_DQ<32> 32 NC1 VSS37
C 45C8 44C8 43C8 PCH_3S_SMCLK 202 131M_A_DQ<33> 33
122 NC2 VSS38 156 C
IN PCH_3S_SMDATA
SCL DQ33
125 NCTEST VSS39 161
45C8 44C8 43C8 200 141M_A_DQ<34> 34
IN SDA DQ34
VSS40 162
54A8 DQ35 143M_A_DQ<35> 35
167
49C5 M_ODT0 116 130M_A_DQ<36> 36 VSS41
IN M_ODT1
ODT0 DQ36
45C3 44C3 43C3 42B5 OUT PM_EXTTS#1_R 198 EVENT# VSS42 168
49C5 120 132M_A_DQ<37> 37 P0V75M_VREF
IN ODT1 DQ37
47A5 45C3 44C3 43C3 OUT DDR3_DRAMRST# 30 RESET# VSS43 172
DQ38 140M_A_DQ<38> 38
VSS44 173
11 DM0 DQ39 142M_A_DQ<39> 39
VSS45 178
28 DM1 DQ40 147M_A_DQ<40> 40 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 1 VREF_DQ VSS46 179
46 DM2 DQ41 149M_A_DQ<41> 41
126 VREF_CA VSS47 184
157M_A_DQ<42>
1
63 DM3 DQ42 42
VSS48 185
136 DM4 DQ43 159M_A_DQ<43> 43
C4150 C4116 VSS49 189 P0V75S
153 DM5 DQ44 146M_A_DQ<44> 44
2 VSS1 VSS50 190
170 DM6 DQ45 148M_A_DQ<45> 45 P0V75M_VREF
2.2UF_6.3V_3 0.1UF_16V_2 3 VSS2 VSS51 195
187 DM7 DQ46 158M_A_DQ<46> 46
8 VSS3 VSS52 196
160M_A_DQ<47> 47
2
DQ47
9
49B5 43B8 IN M_A_DQS0_DP 12 DQS0 DQ48 163M_A_DQ<48> 48 VSS4
13
14
49B5 43B8 M_A_DQS2_DP 47 175M_A_DQ<50> 50 VSS6
IN M_A_DQS3_DP
DQS2 DQ50
19 VSS7
177M_A_DQ<51>
1
49B5 43B8 64 51
IN DQS3 DQ51
20
49B5 43B8 IN M_A_DQS4_DP
M_A_DQS5_DP
137 DQS4 DQ52 164M_A_DQ<52> 52
C4117 C4118 25
VSS8
VSS9 VTT1 203 1.5A
49B5 43B8 154 166M_A_DQ<53> 53
IN M_A_DQS6_DP
DQS5 DQ53
26 VSS10 VTT2 204
49B5 43B8 171 174M_A_DQ<54> 54
IN M_A_DQS7_DP
DQS6 DQ54
2.2UF_6.3V_3 0.1UF_16V_2 31 VSS11
B 49B5 43B8 188 176M_A_DQ<55> 55 P3V3S B
IN M_A_DQS0_DN
DQS7 DQ55
32 VSS12 G1 G1
10 181M_A_DQ<56> 56
2
49B5 43B8 IN DQS0# DQ56
37 G2
49B5 43B8 IN M_A_DQS1_DN 27 DQS1# DQ57 183M_A_DQ<57> 57 VSS13 G2
38
49B5 43B8 IN M_A_DQS2_DN 45 DQS2# DQ58 191M_A_DQ<58> 58 VSS14
1
43
49B5 43B8 IN M_A_DQS3_DN 62 DQS3# DQ59 193M_A_DQ<59> 59 VSS15
49B5 43B8 IN M_A_DQS4_DN 135 DQS4# DQ60 180M_A_DQ<60> 60

M_A_DQS5_DN 152 182M_A_DQ<61> 61 R4104 JAE_MM80_204B1_D9R_R400_DT_204P
49B5 43B8 IN DQS5# DQ61
M_A_DQS6_DN 169 192M_A_DQ<62> 62 10K_5%_2
49B5 43B8 IN DQS6# DQ62
49B5 43B8 IN M_A_DQS7_DN 186 DQS7# DQ63 194M_A_DQ<63> 63
2
PM_EXTTS#1_R
JAE_MM80_204B1_D9R_R400_DT_204P 45C3 44C3 43C3 42C3 IN
PLACE THESE CAPS CLOSE TO VTT1 AND VTT2
1
P3V3S C4119 C4120 C4121 C4122
1
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
NOTE: R4100 R4101
10K_5%_2_DY 10K_5%_2_DY
IF SA0_DIM0=1 , SA1_DIM0=0
A SO-DIMMA SPD ADDRESS IS 0XA2 A
2
SA0_DIM0 IN 42C8
SO-DIMMA TS ADDRESS IS 0X32
SA1_DIM0 IN 42C8
1
SO-DIMMA SPD ADDRESS IS 0XA0 R4102 R4103
10K_5%_2 10K_5%_2
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
49A4 42D8 BI
M_A_A<15..0>
0
1
M_A_A<0>
M_A_A<1>
98
97
CN4200
A0 DQ0 5 M_A_DQ<4>
7 M_A_DQ<5>
4
5
M_A_DQ<63..0>
BI 42D5 49D8
CHA DIMM1 TOP
A1 DQ1
2 M_A_A<2> 96 A2 DQ2 15 M_A_DQ<6> 6
3 M_A_A<3> 95 A3 DQ3 17 M_A_DQ<7> 7
4 M_A_A<4> 92 A4 DQ4 4 M_A_DQ<0> 0
5 M_A_A<5> 91 A5 DQ5 6 M_A_DQ<1> 1
6 M_A_A<6> 90 A6 DQ6 16 M_A_DQ<2> 2
7 M_A_A<7> 86 A7 DQ7 18 M_A_DQ<3> 3
8 M_A_A<8> 89 A8 DQ8 21 M_A_DQ<12> 12 P1V5 CN4200
D 9 M_A_A<9> 85 A9 DQ9 23 M_A_DQ<13> 13
10 M_A_A<10> 107 A10_AP DQ10 33 M_A_DQ<14> 14 D
76 VDD2 VSS17 48
11 M_A_A<11> 84 A11 DQ11 35 M_A_DQ<15> 15
1
81 VDD3 VSS18 49
12 M_A_A<12> 83 A12 DQ12 22 M_A_DQ<8> 8
C4201 C4202 C4203 C4204 C4205 C4206 C4207 82 VDD4 VSS19 54
13 M_A_A<13> 119 A13 DQ13 24 M_A_DQ<9> 9 C4200
+
87 VDD5 VSS20 55
14 M_A_A<14> 80 A14 DQ14 34 M_A_DQ<10> 10
88 VDD6 VSS21 60
15 M_A_A<15> 78 A15 DQ15 36 M_A_DQ<11> 11 330UF_2.5V_DY 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 VDD7 VSS22 61
DQ16 39 M_A_DQ<20> 20
94 65
2
99 66
NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S 100 71
M_A_BS2 53 M_A_DQ<23> VDD10 VSS25
1
49A8 42D8 79 23
IN M_CS#4
BA2 DQ19
105 VDD11 VSS26 72
49C5 114 40 M_A_DQ<16> 16 C4210 C4209 C4208
IN M_CS#5
S0# DQ20
P3V3S 106 VDD12 VSS27 127
49C5 121 42 M_A_DQ<17> 17
IN M_CLK_DDR4_DP
S1# DQ21
111 VDD13 VSS28 128
49D4 101 50 M_A_DQ<18> 18
IN M_CLK_DDR4_DN
CK0 DQ22
49D4 103 52 M_A_DQ<19> 19
IN M_CLK_DDR5_DP
CK0# DQ23
117 VDD15 VSS30 134
102 57 M_A_DQ<28> 28
2
49C4 IN CK1 DQ24
118 138
49C4 IN M_CLK_DDR5_DN 104 CK1# DQ25 59 M_A_DQ<29> 29 VDD16 VSS31
1
123 139
49C4 IN M_CKE4 73 CKE0 DQ26 67 M_A_DQ<30> 30 VDD17 VSS32
124 144
49C4 IN M_CKE5 74 CKE1 DQ27 69 M_A_DQ<31> 31 C4211 C4212
VDD18 VSS33
145
49A8 42C8 IN M_A_CAS# 115 CAS# DQ28 56 M_A_DQ<24> 24 VSS34
199 150
49A8 42C8 IN M_A_RAS# 110 RAS# DQ29 58 M_A_DQ<25> 25 2.2UF_6.3V_3 0.1UF_16V_2
VDDSPD VSS35
151
49A8 42C8 IN M_A_WE# 113 WE# DQ30 68 M_A_DQ<26> 26 VSS36
77 155
2
43A6 OUT SA0_DIM1 197 SA0 DQ31 70 M_A_DQ<27> 27 NC1 VSS37
122 156
43A6 OUT SA1_DIM1 201 SA1 DQ32 129M_A_DQ<36> 36 NC2 VSS38
C 54A8 45C8 44C8 42C8 PCH_3S_SMCLK 202 131M_A_DQ<37> 37
125 NCTEST VSS39 161 C
IN PCH_3S_SMDATA
SCL DQ33
VSS40 162
54A8 45C8 44C8 42C8 200 141M_A_DQ<38> 38
IN SDA DQ34
45C3 44C3 42C3 42B5 OUT PM_EXTTS#1_R 198 EVENT# VSS41 167
143M_A_DQ<39> 39
M_ODT4
DQ35
49C5 116 130M_A_DQ<32> 32 P0V75M_VREF
IN M_ODT5
ODT0 DQ36
VSS43 172
49C5 120 132M_A_DQ<33> 33
IN ODT1 DQ37
VSS44 173
DQ38 140M_A_DQ<34> 34
1 VREF_DQ VSS45 178
11 DM0 DQ39 142M_A_DQ<35> 35 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 126 VREF_CA VSS46 179
28 DM1 DQ40 147M_A_DQ<44> 44
VSS47 184
149M_A_DQ<45>
1
46 DM2 DQ41 45
VSS48 185
63 DM3 DQ42 157M_A_DQ<46> 46
C4213 C4214 2 VSS1 VSS49 189 P0V75S
136 DM4 DQ43 159M_A_DQ<47> 47
3 VSS2 VSS50 190
153 DM5 DQ44 146M_A_DQ<40> 40 P0V75M_VREF
2.2UF_6.3V_3 0.1UF_16V_2 8 VSS3 VSS51 195
170 DM6 DQ45 148M_A_DQ<41> 41
9 VSS4 VSS52 196
187 158M_A_DQ<42> 42
2
DM7 DQ46
13 VSS5
DQ47 160M_A_DQ<43> 43
14
19
20
M_A_DQS2_DP 175M_A_DQ<54> VSS8
1
49B5 42B8 47 54
IN M_A_DQS3_DP
DQS2 DQ50
25 VSS9
49B5 42B8 64 177M_A_DQ<55> 55
IN M_A_DQS4_DP
DQS3 DQ51
C4215 C4216 26 VSS10 VTT1 203
49B5 42B8 137 164M_A_DQ<48> 48
IN M_A_DQS5_DP
DQS4 DQ52
31 VSS11 VTT2 204
49B5 42B8 154 166M_A_DQ<49> 49
IN M_A_DQS6_DP
DQS5 DQ53
2.2UF_6.3V_3 0.1UF_16V_2 32 VSS12
49B5 42B8 171 174M_A_DQ<50> 50
IN M_A_DQS7_DP
DQS6 DQ54
37 VSS13 G1 G1
B 188 176M_A_DQ<51> 51 B
2
49B5 42B8 IN DQS7 DQ55
38 G2
49B5 42B8 IN M_A_DQS0_DN 10 DQS#0 DQ56 181M_A_DQ<60> 60 VSS14 G2
43
49B5 42B8 IN M_A_DQS1_DN 27 DQS#1 DQ57 183M_A_DQ<61> 61 VSS15
49B5 42B8 IN M_A_DQS2_DN 45 DQS#2 DQ58 191M_A_DQ<62> 62

49B5 42B8 IN M_A_DQS3_DN 62 DQS#3 DQ59 193M_A_DQ<63> 63 BELLW_80011_2021_204P
BELLW_80011_2021_204P
1
C4217 C4218 C4219 C4220
P3V3S
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

1
2
NOTE: R4203 R4202
10K_5%_2 10K_5%_2_DY
A SO-DIMMA SPD ADDRESS IS 0XA2 A
2
SA0_DIM1 IN 43C8
SA1_DIM1 IN 43C8
1
SO-DIMMA SPD ADDRESS IS 0XA0 R4201 R4204
SO-DIMMA TS ADDRESS IS 0X30 10K_5%_2_DY 10K_5%_2
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
49A1 45D8 BI
M_B_A<15..0>
M_B_DQ<63..0>
CHB DIMM2 BUTTOM
BI 45D5 49D4
CN4101
0 M_B_A<0> 98 A0 DQ0 5 M_B_DQ<0> 0
1 M_B_A<1> 97 A1 DQ1 7 M_B_DQ<1> 1
2 M_B_A<2> 96 A2 DQ2 15 M_B_DQ<2> 2
3 M_B_A<3> 95 A3 DQ3 17 M_B_DQ<3> 3
4 M_B_A<4> 92 A4 DQ4 4 M_B_DQ<4> 4
5 M_B_A<5> 91 A5 DQ5 6 M_B_DQ<5> 5
6 M_B_A<6> 90 A6 DQ6 16 M_B_DQ<6> 6
D 7 M_B_A<7> 86 A7 DQ7 18 M_B_DQ<7> 7
8 M_B_A<8> 89 A8 DQ8 21 M_B_DQ<8> 8 D
9 M_B_A<9> 85 A9 DQ9 23 M_B_DQ<9> 9 P1V5
10 M_B_A<10> 107 A10_AP DQ10 33 M_B_DQ<10> 10 CN4101
11 M_B_A<11> 84 A11 DQ11 35 M_B_DQ<11> 11
76 VDD2 VSS17 48
12 M_B_A<12> 83 A12 DQ12 22 M_B_DQ<12> 12
1
81 VDD3 VSS18 49
13 M_B_A<13> 119 A13 DQ13 24 M_B_DQ<13> 13
C4124 C4125 C4126 C4127 C4128 C4129 C4130 82 VDD4 VSS19 54
14 M_B_A<14> 80 A14 DQ14 34 M_B_DQ<14> 14
87 VDD5 VSS20 55
15 M_B_A<15> 78 A15 DQ15 36 M_B_DQ<15> 15
88 VDD6 VSS21 60
DQ16 39 M_B_DQ<16> 16 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 61
49A4 45D8 IN M_B_BS0 109 BA0 DQ17 41 M_B_DQ<17> 17 VDD7 VSS22
94 65
2
99 66
49A4 45C8 IN M_B_BS2 79 BA2 DQ19 53 M_B_DQ<19> 19 VDD9 VSS24
100 71
M_CS#2 40 M_B_DQ<20> VDD10 VSS25
1
49C1 114 20
IN M_CS#3
S0# DQ20
105 VDD11 VSS26 72
49C1 121 42 M_B_DQ<21> 21 C4133 C4132 C4131
IN M_CLK_DDR2_DP
S1# DQ21
P3V3S 106 VDD12 VSS27 127
49D1 101 50 M_B_DQ<22> 22
IN M_CLK_DDR2_DN
CK0 DQ22
111 VDD13 VSS28 128
49D1 103 52 M_B_DQ<23> 23
IN M_CLK_DDR3_DP
CK0# DQ23
49D1 102 57 M_B_DQ<24> 24
IN M_CLK_DDR3_DN
CK1 DQ24
117 VDD15 VSS30 134
104 59 M_B_DQ<25> 25
2
49D1 IN CK1# DQ25
118 138
M_CKE2 VDD16 VSS31
49D1 73 67 M_B_DQ<26> 26
IN CKE0 DQ26
1
123 VDD17 VSS32 139
49D1 IN M_CKE3 74 CKE1 DQ27 69 M_B_DQ<27> 27
124 VDD18 VSS33 144
49A4 45C8 IN M_B_CAS# 115 CAS# DQ28 56 M_B_DQ<28> 28 C4138 C4137 145
49A4 45C8 IN M_B_RAS# 110 RAS# DQ29 58 M_B_DQ<29> 29 VSS34
199 150
49A4 45C8 IN M_B_WE# 113 WE# DQ30 68 M_B_DQ<30> 30 2.2UF_6.3V_3 0.1UF_16V_2
VDDSPD VSS35
C 44A7 SA0_DIM2 197 70 M_B_DQ<31> 31 VSS36 151 C
OUT SA0 DQ31
77 155
2
44A6 OUT SA1_DIM2 201 SA1 DQ32 129M_B_DQ<32> 32 NC1 VSS37
122 156
IN PCH_3S_SMCLK 202 SCL DQ33 131M_B_DQ<33> 33 NC2 VSS38
125 161
54A8 45C8 43C8 42C8 PCH_3S_SMDATA 200 141M_B_DQ<34> 34 NCTEST VSS39
IN SDA DQ34
VSS40 162
DQ35 143M_B_DQ<35> 35
M_ODT2 45C3 43C3 42C3 42B5 OUT PM_EXTTS#1_R 198 EVENT# VSS41 167
49C1 116 130M_B_DQ<36> 36 P0V75M_VREF
IN M_ODT3
ODT0 DQ36
49C1 120 132M_B_DQ<37> 37
IN ODT1 DQ37
VSS43 172
DQ38 140M_B_DQ<38> 38
VSS44 173
11 DM0 DQ39 142M_B_DQ<39> 39 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 1 VREF_DQ VSS45 178
28 DM1 DQ40 147M_B_DQ<40> 40
46 DM2 DQ41 149M_B_DQ<41> 41
VSS47 184
157M_B_DQ<42>
1
63 DM3 DQ42 42
VSS48 185
136 DM4 DQ43 159M_B_DQ<43> 43
C4151 C4139 2 VSS1 VSS49 189 P0V75S
153 DM5 DQ44 146M_B_DQ<44> 44
3 VSS2 VSS50 190
170 DM6 DQ45 148M_B_DQ<45> 45 P0V75M_VREF
2.2UF_6.3V_3 0.1UF_16V_2 8 VSS3 VSS51 195
187 DM7 DQ46 158M_B_DQ<46> 46
9 VSS4 VSS52 196
160M_B_DQ<47> 47
2
DQ47
13
49B1 45B8 M_B_DQS0_DP 12 163M_B_DQ<48> 48 VSS5
IN M_B_DQS1_DP
DQS0 DQ48
14 VSS6
49B1 45B8 29 165M_B_DQ<49> 49
IN M_B_DQS2_DP
DQS1 DQ49
19 VSS7
49B1 45B8 47 175M_B_DQ<50> 50
IN M_B_DQS3_DP
DQS2 DQ50
20 VSS8
177M_B_DQ<51>
1
49B1 45B8 64 51
IN DQS3 DQ51
25
49B1 45B8 IN M_B_DQS4_DP
M_B_DQS5_DP
137 DQS4 DQ52 164M_B_DQ<52> 52
C4140 C4141 26
VSS9
VSS10 VTT1 203 1.5A
B 49B1 45B8 154 166M_B_DQ<53> 53 B
IN M_B_DQS6_DP
DQS5 DQ53
31 VSS11 VTT2 204
49B1 45B8 171 174M_B_DQ<54> 54
IN M_B_DQS7_DP
DQS6 DQ54
2.2UF_6.3V_3 0.1UF_16V_2 32 VSS12
49B1 45B8 188 176M_B_DQ<55> 55
IN M_B_DQS0_DN
DQS7 DQ55
37 VSS13 G1 G1
10 181M_B_DQ<56> 56
2
49B1 45B8 IN DQS#0 DQ56
38 G2
49B1 45B8 IN M_B_DQS1_DN 27 DQS#1 DQ57 183M_B_DQ<57> 57 VSS14 G2
43
49B1 45B8 IN M_B_DQS2_DN 45 DQS#2 DQ58 191M_B_DQ<58> 58 VSS15
49B1 45B8 IN M_B_DQS3_DN 62 DQS#3 DQ59 193M_B_DQ<59> 59 JAE_MM80_204B1_H2R_R250_DT_204P

49B1 45B8 IN M_B_DQS4_DN 135 DQS#4 DQ60 180M_B_DQ<60> 60
49B1 45B8 IN M_B_DQS5_DN 152 DQS#5 DQ61 182M_B_DQ<61> 61
49B1 45B8 M_B_DQS6_DN 169 192M_B_DQ<62> 62
IN M_B_DQS7_DN
DQS#6 DQ62
49B1 45B8 186 194M_B_DQ<63> 63
IN DQS#7 DQ63
JAE_MM80_204B1_H2R_R250_DT_204P
1
NOTE: P3V3S C4142 C4143 C4144 C4145
SO-DIMMB SPD ADDRESS IS 0XA4
SO-DIMMB TS ADDRESS IS 0X34
1
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
R4107 R4106
A 10K_5%_2 10K_5%_2
A
2
44C8 IN SA0_DIM2 SA1_DIM2 IN 44C8

1
R4105 R4108
10K_5%_2_DY 10K_5%_2_DY
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
49A1 44D8
M_B_A<15..0> M_B_DQ<63..0>
CHB DIMM3 TOP 44D5 49D4
BI BI
CN4201
0 M_B_A<0> 98 A0 DQ0 5 M_B_DQ<4> 4
1 M_B_A<1> 97 A1 DQ1 7 M_B_DQ<5> 5
2 M_B_A<2> 96 A2 DQ2 15 M_B_DQ<6> 6
3 M_B_A<3> 95 A3 DQ3 17 M_B_DQ<7> 7
4 M_B_A<4> 92 A4 DQ4 4 M_B_DQ<0> 0
5 M_B_A<5> 91 A5 DQ5 6 M_B_DQ<1> 1
6 M_B_A<6> 90 A6 DQ6 16 M_B_DQ<2> 2
7 M_B_A<7> 86 A7 DQ7 18 M_B_DQ<3> 3
D 8 M_B_A<8> 89 21 M_B_DQ<12> 12
A8 DQ8 P1V5 CN4201 D
9 M_B_A<9> 85 A9 DQ9 23 M_B_DQ<13> 13
10 M_B_A<10> 107 A10_AP DQ10 33 M_B_DQ<14> 14
76 VDD2 VSS17 48
11 M_B_A<11> 84 A11 DQ11 35 M_B_DQ<15> 15
1
81 VDD3 VSS18 49
12 M_B_A<12> 83 A12 DQ12 22 M_B_DQ<8> 8
C4221 C4222 C4223 C4224 C4225 C4226 C4227 82 VDD4 VSS19 54
13 M_B_A<13> 119 A13 DQ13 24 M_B_DQ<9> 9
87 VDD5 VSS20 55
14 M_B_A<14> 80 A14 DQ14 34 M_B_DQ<10> 10
88 VDD6 VSS21 60
15 M_B_A<15> 78 A15 DQ15 36 M_B_DQ<11> 11 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 VDD7 VSS22 61
DQ16 39 M_B_DQ<20> 20
94 65
2
99 66
100 71
M_B_BS2 M_B_DQ<23> VDD10 VSS25
1
49A4 44C8 79 53 23
IN M_CS#6
BA2 DQ19
M_B_DQ<16> 105 VDD11 VSS26 72
49C1 114 40 16 C4228 C4229 C4230
IN M_CS#7
S0# DQ20
M_B_DQ<17> P3V3S 106 VDD12 VSS27 127
49C1 121 42 17
IN M_CLK_DDR6_DP
S1# DQ21
M_B_DQ<18> 111 VDD13 VSS28 128
49D1 101 50 18
IN M_CLK_DDR6_DN
CK0 DQ22
M_B_DQ<19> 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 112 VDD14 VSS29 133
49D1 103 52 19
IN M_CLK_DDR7_DP
CK0# DQ23
M_B_DQ<28> 117 VDD15 VSS30 134
102 57 28
2
49C1 IN CK1 DQ24
118 138
49C1 IN M_CLK_DDR7_DN 104 CK1# DQ25 59 M_B_DQ<29> 29 VDD16 VSS31
1
123 139
49D1 IN M_CKE6 73 CKE0 DQ26 67 M_B_DQ<30> 30 VDD17 VSS32
124 144
49C1 IN M_CKE7 74 CKE1 DQ27 69 M_B_DQ<31> 31 C4231 C4232
VDD18 VSS33
145
49A4 44C8 IN M_B_CAS# 115 CAS# DQ28 56 M_B_DQ<24> 24 VSS34
199 150
49A4 44C8 IN M_B_RAS# 110 RAS# DQ29 58 M_B_DQ<25> 25 2.2UF_6.3V_3 0.1UF_16V_2
VDDSPD VSS35
151
49A4 44C8 IN M_B_WE# 113 WE# DQ30 68 M_B_DQ<26> 26 VSS36
77 155
2
C 45A7 OUT SA0_DIM3 197 SA0 DQ31 70 M_B_DQ<27> 27 NC1 VSS37
C
122 156
45A6 OUT SA1_DIM3 201 SA1 DQ32 129 M_B_DQ<36> 36 NC2 VSS38
125 161
IN PCH_3S_SMCLK 202 SCL DQ33 131 M_B_DQ<37> 37 NCTEST VSS39
162
54A8 44C8 43C8 42C8 IN PCH_3S_SMDATA 200 SDA DQ34 141 M_B_DQ<38> 38 PM_EXTTS#1_R
VSS40
44C3 43C3 42C3 42B5 198 167
DQ35 143 M_B_DQ<39> 39 P0V75M_VREF OUT DDR3_DRAMRST#
EVENT# VSS41
47A5 44C3 43C3 42C3 30 168
49C1 IN M_ODT6 116 ODT0 DQ36 130 M_B_DQ<32> 32 OUT RESET# VSS42
172
49C1 IN M_ODT7 120 ODT1 DQ37 132 M_B_DQ<33> 33 VSS43
VSS44 173
DQ38 140 M_B_DQ<34> 34 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 1 VREF_DQ VSS45 178
11 DM0 DQ39 142 M_B_DQ<35> 35
28 DM1 DQ40 147 M_B_DQ<44> 44
VSS47 184
M_B_DQ<45>
1
46 DM2 DQ41 149 45
VSS48 185
63 DM3 DQ42 157 M_B_DQ<46> 46
C4233 C4234 2 VSS1 VSS49 189
136 DM4 DQ43 159 M_B_DQ<47> 47
3 VSS2 VSS50 190
153 DM5 DQ44 146 M_B_DQ<40> 40 P0V75M_VREF
2.2UF_6.3V_3 0.1UF_16V_2 8 VSS3 VSS51 195
170 DM6 DQ45 148 M_B_DQ<41> 41
9 VSS4 VSS52 196
187 158 M_B_DQ<42> 42
2
DM7 DQ46
13 VSS5
DQ47 160 M_B_DQ<43> 43
14
49B1 44B8 IN M_B_DQS0_DP 12 DQS0 DQ48 163 M_B_DQ<52> 52 VSS6
P0V75S
19
49B1 44B8 IN M_B_DQS1_DP
M_B_DQS2_DP
29 DQS1 DQ49 165 M_B_DQ<53>
M_B_DQ<54>
53
20
VSS7
VSS8
1.5A
1
49B1 44B8 47 175 54
IN M_B_DQS3_DP
DQS2 DQ50
M_B_DQ<55> 25 VSS9
49B1 44B8 64 177 55
IN M_B_DQS4_DP
DQS3 DQ51
M_B_DQ<48> C4235 C4236 26 VSS10 VTT1 203
49B1 44B8 137 164 48
IN M_B_DQS5_DP
DQS4 DQ52
M_B_DQ<49> 31 VSS11 VTT2 204
49B1 44B8 154 166 49
B IN M_B_DQS6_DP
DQS5 DQ53
M_B_DQ<50> 2.2UF_6.3V_3 0.1UF_16V_2 32 VSS12 B
49B1 44B8 171 174 50
IN M_B_DQS7_DP
DQS6 DQ54
M_B_DQ<51> 37 VSS13 G1 G1
188 176 51
2
49B1 44B8 IN DQS7 DQ55
38 G2
49B1 44B8 IN M_B_DQS0_DN 10 DQS#0 DQ56 181 M_B_DQ<60> 60 VSS14 G2
43
49B1 44B8 IN M_B_DQS1_DN 27 DQS#1 DQ57 183 M_B_DQ<61> 61 VSS15
49B1 44B8 IN M_B_DQS2_DN 45 DQS#2 DQ58 191 M_B_DQ<62> 62

M_B_DQS3_DN 62 193 M_B_DQ<63> 63 BELLW_80001_2021_204P
49B1 44B8 IN DQS#3 DQ59
BELLW_80001_2021_204P
1
C4237 C4238 C4239 C4240
NOTE: P3V3S
SO-DIMMB SPD ADDRESS IS 0XA4
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
SO-DIMMB TS ADDRESS IS 0X34
1
2
R4205 R4206
A 10K_5%_2_DY 10K_5%_2 A
2
45C8 IN SA0_DIM3 SA1_DIM3 IN 45C8

1
R4207 R4208
10K_5%_2 10K_5%_2_DY
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4300~4349(FAN)
REFERENCE 4411~4449(THERMAL ) P5V0S
PAD4300 P5V0S_FAN
1 1 2
2
POWERPAD_2_0610
22UF_6.3V_5_DY
4.7UF_6.3V_3
0.1UF_16V_2
1
1
C4301
C4302
C4307
D
2
P3V3S D
10K_5%_2
2 R4300
CN4300
1 1
2
22B6
FAN_TACH1 1 TP4300 3
2
G1
IN 3 G
4 4 G G2
TP30
220pF_50V_2
CSC0402_DY
ACES_50228_00471_001_4P
1
1
P3V3S
C4300
C4305
2
1
C C
10K_5%_2
R4306
FAN CN
2
FAN1_PWM 1 TP4301
22B6 IN
TP30
CSC0402_DY
1
C4306
2
B B
55B7 IN PVCORE_PG
THRM_SHUTDWN# OUT 16D8 46A8
P5V0AL
1
0.1UF_16V_2
1
P5V0AL R4414
1
3
26.7K_1%_2
1
C4441
2M_5%_2
R4445 Q4411
R4442
D
2
100K_5%_2 1 G
2
S
C
2
U4441
2
Q4412
1
1 VCC TMSNS1 8 R4413 SSM3K7002BFU
PM_THRMTRIP# 1 2 B
C E
2
58C1 47D5 IN B C4412
100K_1%_NTC
2 71 R4443 2
GND RHYST1 330_5%_2
1
13.3K_1%_2 MMBT4401
R4444
THRM_SHUTDWN# 3 6 CSC0402_DY
E
46B1 16D8 OUT OT1 TMSNS2
2
4 OT2 RHYST2 5
2
ENE_P2809A2_SOT23_8P
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4500~4699(CPU) CN4500
CLOCKS
MISC
P1V8S
A28 CLK_DMI_PCH_DP 54B3
H_SNB_IVB#
BCLK IN
47D8 C26 A27 CLK_DMI_PCH_DN 54B3
OUT PROC_SELECT# BCLK# IN
P1V05S
2
TP4500 1 AN34 SKTOCC#
R4500 R4502 DPLL_REF_CLK A16 R4510 1 2 1K_5%_2
TP24
2.2K_5%_2 2.2K_5%_2_DY DPLL_REF_CLK# A15 R4511 1 2 1K_5%_2
TP4501 1
2
P1V05S
1
AL33
THERMAL
CATERR#
H_SNB_IVB# 1 R4501 2 NV_CLE TP24

47D5 OUT OUT 58B2
D 1K_5%_2
DDR3
PLACE CLOSE TO CPT AND NVRAM CONNECTOR
58C2 22A6 H_PECI AN33 R8 CPU_DRAMRST# 47A5
D
OUT PECI SM_DRAMRST# OUT
MISC
R4503
62_5%_2
CPU_PROCHOT# 1 R4504 2 CPU_PROCHOT#_R AL32 AK1 SM_RCOMP0 R4512 1 2
1 2
22C3 11B7 OUT 140_1%_2
PROCESS STRAP SETTING PROCHOT# SM_RCOMP[0]
SM_RCOMP[1] A5 SM_RCOMP1 R4513 1 2 25.5_1%_2
56_5%_2 A4 SM_RCOMP2
SM_RCOMP[2] R4514 1 2 200_1%_2
C4500
SANDY BRIDGE ONLY STUFF R4502 CSC0402_DY 46A4 PM_THRMTRIP# AN32
58C1
OUT THERMTRIP#
SANDY BRIDGE/IVY BRIDGE STUFF R4500/R4501
PWR MANAGEMENT
PRDY# AP29 TP30 1 TP4502 H_PRDY# OUT
PREQ# AP27 TP30 1 TP4503 H_PREQ# IN 47B2
JTAG & BPM

P1V5S AR26 TP30 1 TP4504 H_TCK 47B2
LOW IN C6/C7
TCK
H_TMS IN
DMI&FDI TERMINATIONVOLTAGE TMS AR27 TP30 1 TP4505 IN 47B2
H_PM_SYNC TP30 1 H_TRST#
1
55A3 AM34 AP30 TP4506 47B2
BI PM_SYNC TRST# IN
NV_CLE SET TOVSS WHEN LOW (DEFAULT) R4505 TDI AR28 TP30 1 TP4507 H_TDI IN 47B2
200_5%_2 TDO AP26
TP30 1 TP4508 H_TDO OUT
C SET TOVCC WHEN HIGH 58C2 IN H_CPUPWRGD AP33 UNCOREPWRGOOD C
2
R4506 DBR# AL35 TP30 1 TP4509 SYS_RESET# OUT 55B8
55B7 IN PM_DRAM_PWRGD 1 2 PM_DRAM_PWRGD_R V8 SM_DRAMPWROK
130_1%_2 AT28
BPM#[0]
BPM#[1] AR29 CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT
R4507 BPM#[2] AR30 - MAX LENGTH = 500 MILS
57A7 35C6 33C6 28C7 IN PLT_RST# 1 2 AR33 RESET# BPM#[3] AT30 - TRACE WIDTH = 15MILS AND
BPM#[4] AP32 - MB TRACE IMPEDANCE < 68 MOHMS
1.5K_5%_2 BPM#[5] AR31 (WORST CASE RESISTANCE)
1
BPM#[6] AT31
BPM#[7] AR32
R4509
R4508
10K_5%_2
750_1%_2 P1V05S
2
FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER 47C1 IN H_TMS R4516 1 2 51_5%_2
47C1 IN H_TDI R4517 1 2 51_5%_2
47C1 IN H_PREQ# R1418 1 2 51_5%_2_DY
B B
H_TCK 1 2 51_5%_2
S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3 47C1 IN
H_TRST#
R4519
47C1 R4520 1 2 51_5%_2
IN
P3V3A P1V5
1
R4602
R4601
1K_5%_2 1K_5%_2
2
R4603 DDR3_DRAMRST#
1 2 42C3 43C3 44C3
DRAMRST_CNTRL OUT 45C3
51D6 OUT
51D8 1K_5%_2
3
Q4600
DRAMRST_CNTRL_PCH R4600
D
54D3 1 2 1 G
IN
S
0_5%_2
A SSM3K7002BFU CPU_DRAMRST# A
IN 47D2
12
1
C4620 R4604
0.047UF_16V_2
4.99K_1%_2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S
REFERENCE 4500~4699(CPU) CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS
SHOULD BE SHORTED AND ROUTED WITH
1
- MAX LENGTH = 500 MILS
R4522
- TYPICAL IMPEDANCE = 43 MOHMS
CN4500 24.9_1%_2
J22 P1V0S_VCCP_PEG_ICOMPI
2
PEG_ICOMPI
J21 PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH
PEG_ICOMPO
55D6 DMI_TX0_DN B27 H22 - MAX LENGTH = 500 MILS
OUT DMI_RX#[0] PEG_RCOMPO
55D6 DMI_TX1_DN B25
OUT DMI_RX#[1]
- TYPICAL IMPEDANCE = 14.5 MOHMS
55D6 DMI_TX2_DN A25
OUT DMI_RX#[2]
PEG_C_RX15_DN
55C6 DMI_TX3_DN B24 K33 62B5
OUT DMI_RX#[3] PEG_RX#[0] IN
DMI
M35 PEG_C_RX14_DN 62B5
PEG_RX#[1]
PEG_C_RX13_DN IN
D 55C6 OUT DMI_TX0_DP B28 DMI_RX[0] PEG_RX#[2] L34
IN 62B5
55C6 OUT DMI_TX1_DP B26 DMI_RX[1] PEG_RX#[3] J35 PEG_C_RX12_DN IN 62C5 D
55C6 OUT DMI_TX2_DP A24 DMI_RX[2] PEG_RX#[4] J32 PEG_C_RX11_DN IN 62C5
55C6 OUT DMI_TX3_DP B23 DMI_RX[3] PEG_RX#[5] H34 PEG_C_RX10_DN IN 62C5
PEG_RX#[6] H31 PEG_C_RX9_DN
PEG_C_RX8_DN IN 62C5 CLOSE TO CPU
PCI EXPRESS* - GRAPHICS

55D6 DMI_RX0_DN G21 G33 62C5
OUT DMI_TX#[0] PEG_RX#[7]
PEG_C_RX7_DN IN
55D6 DMI_RX1_DN E22 G30 62D5
PEG_C_RX6_DN IN PEG_TX0_DN PEG_C_TX0_DN
55D6 DMI_RX2_DN F21 F35 62D5 48B4 C4580 1 20.22UF_6.3V_2 62E5
PEG_C_RX5_DN IN IN OUT
55D6 DMI_RX3_DN D21 E34 62D5
E32 62D5 48B4 C4581 1 20.22UF_6.3V_2 62E5
PEG_RX#[11]
55D6 DMI_RX0_DP G22 D33 62E5
OUT DMI_TX[0] PEG_RX#[12]
55D6 DMI_RX1_DP D22 D31 62E5 48B4 C4582 1 20.22UF_6.3V_2 62E5
55D6 DMI_RX2_DP F20 B33 62E5
55D6 DMI_RX3_DP C21 C32 62E5 48B4 C4583 1 20.22UF_6.3V_2 62D5
OUT DMI_TX[3] PEG_RX#[15] IN IN OUT
PEG_RX[0] J33 PEG_C_RX15_DP IN 62B5 48B4 IN PEG_TX4_DN C4584 1 20.22UF_6.3V_2 PEG_C_TX4_DN OUT 62D5
PEG_RX[1] L35 PEG_C_RX14_DP IN 62B5
Intel(R) FDI
PEG_RX[2] K34 PEG_C_RX13_DP IN 62B5 48B4 IN PEG_TX5_DN C4585 1 20.22UF_6.3V_2 PEG_C_TX5_DN OUT 62D5
55D3 OUT FDI_TX0_DN A21 FDI0_TX#[0] PEG_RX[3] H35 PEG_C_RX12_DP IN 62C5
55D3 OUT FDI_TX1_DN H19 FDI0_TX#[1] PEG_RX[4] H32 PEG_C_RX11_DP IN 62C5 48B4 IN PEG_TX6_DN C4586 1 20.22UF_6.3V_2 PEG_C_TX6_DN OUT 62D5
55D3 OUT FDI_TX2_DN E19 FDI0_TX#[2] PEG_RX[5] G34 PEG_C_RX10_DP IN 62C5
55D3 OUT FDI_TX3_DN F18 FDI0_TX#[3] PEG_RX[6] G31 PEG_C_RX9_DP IN 62C5 48B4 IN PEG_TX7_DN C4587 1 20.22UF_6.3V_2 PEG_C_TX7_DN OUT 62D5
55D3 OUT FDI_TX4_DN B21 FDI1_TX#[0] PEG_RX[7] F33 PEG_C_RX8_DP IN 62D5
55D3 OUT FDI_TX5_DN C20 FDI1_TX#[1] PEG_RX[8] F30 PEG_C_RX7_DP IN 62D5 48B4 IN PEG_TX8_DN C4588 1 20.22UF_6.3V_2 PEG_C_TX8_DN OUT 62C5
C 55D3 FDI_TX6_DN D18 E35 PEG_C_RX6_DP 62D5
C
OUT FDI1_TX#[2] PEG_RX[9]
PEG_C_RX5_DP IN PEG_TX9_DN PEG_C_TX9_DN
55D3 FDI_TX7_DN E17 E33 62D5 48B4 C4589 1 20.22UF_6.3V_2 62C5
OUT FDI1_TX#[3] PEG_RX[10]
PEG_C_RX4_DP IN IN OUT
F32 62D5
PEG_RX[11]
D34 62E5 48B4 C4590 1 2 0.22UF_6.3V_2 62C5
PEG_RX[12]
55D3 FDI_TX0_DP A22 E31 62E5
OUT FDI0_TX[0] PEG_RX[13]
55D3 FDI_TX1_DP G19 C33 62E5 48B4 C4591 1 2 0.22UF_6.3V_2 62C5
OUT FDI0_TX[1] PEG_RX[14]
55D3 FDI_TX2_DP E20 B32 62E5
OUT FDI0_TX[2] PEG_RX[15] IN PEG_TX12_DN PEG_C_TX12_DN
55D3 FDI_TX3_DP G18 48B4 C4592 1 2 0.22UF_6.3V_2 62B5
CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS OUT FDI0_TX[3]
PEG_TX15_DN IN OUT
55C3 FDI_TX4_DP B20 M29 48B3
OUT FDI1_TX[0] PEG_TX#[0]
PEG_TX14_DN OUT PEG_TX13_DN PEG_C_TX13_DN
SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH FDI_TX5_DP C19 M32 48B3 48C4 C4593 1 2 0.22UF_6.3V_2 62B5
PEG_TX13_DN OUT IN OUT
55C3 FDI_TX6_DP D19 M31 48C3
- TYPICAL IMPEDANCE < 25 MOHMS OUT FDI1_TX[2] PEG_TX#[2]
55C3 FDI_TX7_DP F17 L32 48C3 48C4 C4594 1 2 0.22UF_6.3V_2 62B5
L29 48C3
PEG_TX#[4]
55C3 FDI_FSYNC0 J18 K31 48C3 48C4 C4595 1 2 0.22UF_6.3V_2 62B5
IN FDI0_FSYNC PEG_TX#[5]
55C3 FDI_FSYNC1 J17 K28 48C3
IN FDI1_FSYNC PEG_TX#[6]
PEG_TX8_DN OUT PEG_TX0_DP PEG_C_TX0_DP
J30 48C3 48A4 C4596 1 2 0.22UF_6.3V_2 62E5
P1V05S
PEG_TX#[7]
55C3 FDI_INT H20 J28 48C3
IN FDI_INT PEG_TX#[8]
H29 48C3 48A4 C4597 1 2 0.22UF_6.3V_2 62E5
PEG_TX#[9]
1
55C3 FDI_LSYNC0 J19 G27 48C3

IN FDI0_LSYNC PEG_TX#[10]
55C3 FDI_LSYNC1 H17 E29 48C3 48A4 C4598 1 2 0.22UF_6.3V_2 62E5
IN FDI1_LSYNC PEG_TX#[11]
R4521 F27 48C3
PEG_TX#[12]
24.9_1%_2 D28 48D3 48A4 C4599 1 2 0.22UF_6.3V_2 62E5
PEG_TX#[13]
B PEG_TX#[14] F26
OUT 48D3 B
P1V0S_VCCP_EDP_COMPIO A18 E25 PEG_TX0_DN PEG_TX4_DP C4600 1 2 0.22UF_6.3V_2 PEG_C_TX4_DP
2
eDP_COMPIO PEG_TX#[15] OUT 48D3 48A4 IN OUT 62D5

A17 eDP_ICOMPO
37C3 CPU_EDP_HPD# B16 M28 PEG_TX15_DP 48A3 48A4 PEG_TX5_DP C4601 1 2 0.22UF_6.3V_2 PEG_C_TX5_DP 62D5
IN eDP_HDP# PEG_TX[0]
PEG_TX14_DP OUT IN OUT
M33 48A3
PEG_TX[1] OUT
M30 PEG_TX13_DP 48A3 48A4 PEG_TX6_DP C4602 1 2 0.22UF_6.3V_2 PEG_C_TX6_DP 62D5
PEG_TX[2] OUT IN OUT
eDP
37D7 OUT CPU_EDP_AUX_DP C15 eDP_AUX PEG_TX[3] L31 PEG_TX12_DP OUT 48A3
37D7 CPU_EDP_AUX_DN D15 L28 PEG_TX11_DP 48A3 48B4 PEG_TX7_DP C4603 1 2 0.22UF_6.3V_2 PEG_C_TX7_DP 62D5
OUT eDP_AUX# PEG_TX[4]
K30 48A3
PEG_TX[5] OUT
K27 PEG_TX9_DP 48B3 48B4 PEG_TX8_DP C4604 1 2 0.22UF_6.3V_2 PEG_C_TX8_DP 62C5
CPU_EDP_TX0_DP
PEG_TX[6]
37D7 C17 J29 48B3
OUT eDP_TX[0] PEG_TX[7] OUT
37D7 CPU_EDP_TX1_DP F16 J27 PEG_TX7_DP 48B3 48B4 PEG_TX9_DP C4605 1 2 0.22UF_6.3V_2 PEG_C_TX9_DP 62C5
OUT eDP_TX[1] PEG_TX[8]
C16 H28 48B3
eDP_TX[2] PEG_TX[9] OUT
G15 G28 PEG_TX5_DP 48B3 48B4 PEG_TX10_DP C4606 1 2 0.22UF_6.3V_2 PEG_C_TX10_DP 62C5
eDP_TX[3] PEG_TX[10]
E28 48B3
PEG_TX[11] OUT
37D7 CPU_EDP_TX0_DN C18 F28 PEG_TX3_DP 48B3 48B4 PEG_TX11_DP C4607 1 2 0.22UF_6.3V_2 PEG_C_TX11_DP 62C5
OUT CPU_EDP_TX1_DN
eDP_TX#[0] PEG_TX[12]
37D7 E16 D27 48B3
OUT eDP_TX#[1] PEG_TX[13] OUT
D16 E26 PEG_TX1_DP 48B3 48B4 PEG_TX12_DP C4608 1 2 0.22UF_6.3V_2 PEG_C_TX12_DP 62C5
eDP_TX#[2] PEG_TX[14]
F15 D25 48B3
eDP_TX#[3] PEG_TX[15] OUT
48B4 PEG_TX13_DP C4609 1 2 0.22UF_6.3V_2 PEG_C_TX13_DP 62B5
IN OUT
48B4 PEG_TX14_DP C4610 1 2 0.22UF_6.3V_2 PEG_C_TX14_DP 62B5
IN OUT
FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER 48B4 PEG_TX15_DP C4611 1 2 0.22UF_6.3V_2 PEG_C_TX15_DP 62B5
IN OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4500~4699(CPU)
SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR
CN4500
M_B_DQ<63..0> CN4500
M_A_DQ<63..0> 45D5 44D5 BI
43D5 42D5 BI AE2 M_CLK_DDR2_DP
SB_CLK[0] OUT 44C8
M_CLK_DDR0_DP SB_CLK#[0] AD2 M_CLK_DDR2_DN OUT 44C8
AB6 42C8
SA_CLK[0]
M_CLK_DDR0_DN OUT 0 M_B_DQ<0> C9 SB_DQ[0] SB_CKE[0] R9 M_CKE2 OUT 44C8
AA6 42C8
M_A_DQ<0>
SA_CLK#[0]
M_CKE0
OUT 1 M_B_DQ<1> A7 SB_DQ[1]
0 C5 V9 42C8
D M_A_DQ<1>
SA_DQ[0] SA_CKE[0] OUT 2 M_B_DQ<2> D10 SB_DQ[2]
1 D5 SA_DQ[1]
3 M_B_DQ<3> C8 SB_DQ[3] D
2 M_A_DQ<2> D3 SA_DQ[2]
4 M_B_DQ<4> A9 AE1 M_CLK_DDR3_DP 44C8
DDR SYSTEM MEMORY B

3 M_A_DQ<3> D2 SA_DQ[3] M_B_DQ<5> A8
SB_DQ[4] SB_CLK[1]
M_CLK_DDR3_DN OUT
5 AD1 44C8
4 M_A_DQ<4> D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1_DP OUT 42C8 M_B_DQ<6> D9
SB_DQ[5] SB_CLK#[1]
M_CKE3 OUT
6 R10 44C8
DDR SYSTEM MEMORY A

5 M_A_DQ<5> C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR1_DN OUT 42C8 M_B_DQ<7> D8
SB_DQ[6] SB_CKE[1] OUT
M_A_DQ<6> M_CKE1 7 SB_DQ[7]
6 C2 V10 42C8
M_A_DQ<7>
SA_DQ[6] SA_CKE[1] OUT 8 M_B_DQ<8> G4 SB_DQ[8]
7 C3 SA_DQ[7]
9 M_B_DQ<9> F4 SB_DQ[9]
8 M_A_DQ<8> F10
M_A_DQ<9>
SA_DQ[8]
10 M_B_DQ<10> F1 SB_DQ[10] RSVD_TP[11] AB2 M_CLK_DDR6_DP OUT 45C8
9 F8
M_A_DQ<10>
SA_DQ[9]
M_CLK_DDR4_DP 11 M_B_DQ<11> G1 SB_DQ[11] RSVD_TP[12] AA2 M_CLK_DDR6_DN OUT 45C8
10 G10 AB4 43C8
M_A_DQ<11>
SA_DQ[10] RSVD_TP[1]
M_CLK_DDR4_DN OUT 12 M_B_DQ<12> G5 SB_DQ[12] RSVD_TP[13] T9 M_CKE6 OUT 45C8
11 G9 AA4 43C8
M_A_DQ<12>
M_CKE4 OUT 13 M_B_DQ<13> F5 SB_DQ[13]
12 F9 W9 43C8
M_A_DQ<13>
SA_DQ[12] RSVD_TP[3] OUT 14 M_B_DQ<14> F2 SB_DQ[14]
13 F7 SA_DQ[13]
15 M_B_DQ<15> G2 SB_DQ[15]
14 M_A_DQ<14> G8
M_A_DQ<15>
SA_DQ[14]
16 M_B_DQ<16> J7 SB_DQ[16] RSVD_TP[14] AA1 M_CLK_DDR7_DP OUT 45C8
15 G7
M_A_DQ<16>
SA_DQ[15]
M_CLK_DDR5_DP 17 M_B_DQ<17> J8 SB_DQ[17] RSVD_TP[15] AB1 M_CLK_DDR7_DN OUT 45C8
16 K4 AB3 43C8
M_A_DQ<17>
M_CLK_DDR5_DN OUT 18 M_B_DQ<18>K10 SB_DQ[18] RSVD_TP[16] T10 M_CKE7 OUT 45C8
17 K5 AA3 43C8
M_A_DQ<18>
M_CKE5 OUT 19 M_B_DQ<19> K9 SB_DQ[19]
18 K1 W10 43C8
M_A_DQ<19>
SA_DQ[18] RSVD_TP[6] OUT 20 M_B_DQ<20> J9 SB_DQ[20]
19 J1 SA_DQ[19]
21 M_B_DQ<21> J10 SB_DQ[21]
20 M_A_DQ<20> J5
M_A_DQ<21>
SA_DQ[20]
22 M_B_DQ<22> K8 SB_DQ[22] SB_CS#[0] AD3 M_CS#2 OUT 44C8
21 J4
M_A_DQ<22>
SA_DQ[21]
M_CS#0 23 M_B_DQ<23> K7 SB_DQ[23] SB_CS#[1] AE3 M_CS#3 OUT 44C8
22 J2 AK3 42D8
M_A_DQ<23>
SA_DQ[22] SA_CS#[0]
M_CS#1 OUT 24 M_B_DQ<24> M5 SB_DQ[24] RSVD_TP[17] AD6 M_CS#6 OUT 45C8
23 K2 AL3 42C8
M_A_DQ<24>
SA_DQ[23] SA_CS#[1]
M_CS#4 OUT 25 M_B_DQ<25> N4 SB_DQ[25] RSVD_TP[18] AE6 M_CS#7 OUT 45C8
C 24 M8 SA_DQ[24] RSVD_TP[7] AG1
OUT 43D8 26 M_B_DQ<26> N2 C
25 M_A_DQ<25> N10 SA_DQ[25] RSVD_TP[8] AH1 M_CS#5 OUT 43C8 M_B_DQ<27> N1
SB_DQ[26]
M_A_DQ<26> 27 SB_DQ[27]
26 N8 SA_DQ[26]
28 M_B_DQ<28> M4 SB_DQ[28]
27 M_A_DQ<27> N7 SA_DQ[27]
29 M_B_DQ<29> N5 AE4 M_ODT2 44C8
28 M_A_DQ<28> M10 SA_DQ[28] M_B_DQ<30> M2
SB_DQ[29] SB_ODT[0]
M_ODT3 OUT
30 AD4 44C8
29 M_A_DQ<29> M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 OUT 42C8 M_B_DQ<31> M1
SB_DQ[30] SB_ODT[1]
M_ODT6 OUT
31 AD5 45C8
30 M_A_DQ<30> N9 SA_DQ[30] SA_ODT[1] AG3 M_ODT1 OUT 42C8 M_B_DQ<32>AM5
SB_DQ[31] RSVD_TP[19]
M_ODT7 OUT
32 AE5 45C8
31 M_A_DQ<31> M7 SA_DQ[31] RSVD_TP[9] AG2 M_ODT4 OUT 43C8 M_B_DQ<33>AM6
SB_DQ[32] RSVD_TP[20] OUT
33
32 M_A_DQ<32> AG6 SA_DQ[32] RSVD_TP[10] AH2 M_ODT5 OUT 43C8 M_B_DQ<34>AR3
SB_DQ[33]
M_A_DQ<33> 34 SB_DQ[34]
33 AG5 SA_DQ[33]
35 M_B_DQ<35>AP3 SB_DQ[35]
34 M_A_DQ<34> AK6 SA_DQ[34]
36 M_B_DQ<36>AN3 SB_DQ[36]
35 M_A_DQ<35> AK5 SA_DQ[35]
37 M_B_DQ<37>AN2 D7 M_B_DQS0_DN 44B8 45B8
36 M_A_DQ<36> AH5 SA_DQ[36] M_B_DQ<38>AN1
SB_DQ[37] SB_DQS#[0] OUT
38 F3 M_B_DQS1_DN 44B8 45B8
37 M_A_DQ<37> AH6 SA_DQ[37] SA_DQS#[0] C4 M_A_DQS0_DN
OUT 42B8 43B8 M_B_DQ<39>AP2
39 K6 M_B_DQS2_DN 44B8 45B8
38 M_A_DQ<38> AJ5 SA_DQ[38] SA_DQS#[1] G6 M_A_DQS1_DN
40 N3 M_B_DQS3_DN 44B8 45B8
39 M_A_DQ<39> AJ6 SA_DQ[39] SA_DQS#[2] J3 M_A_DQS2_DN
OUT 42B8 43B8 M_B_DQ<41>AN9
41 AN5 M_B_DQS4_DN 44B8 45B8
40 M_A_DQ<40> AJ8 SA_DQ[40] SA_DQS#[3] M6 M_A_DQS3_DN
OUT 42B8 43B8 M_B_DQ<42>AT5
42 AP9 M_B_DQS5_DN 44B8 45B8
41 M_A_DQ<41> AK8 SA_DQ[41] SA_DQS#[4] AL6 M_A_DQS4_DN
43 AK12 M_B_DQS6_DN 44B8 45B8
42 M_A_DQ<42> AJ9 SA_DQ[42] SA_DQS#[5] AM8 M_A_DQS5_DN
44 AP15 M_B_DQS7_DN 44B8 45B8
43 M_A_DQ<43> AK9 SA_DQ[43] SA_DQS#[6] AR12 M_A_DQS6_DN
OUT 42B8 43B8 M_B_DQ<45>AN8
45 SB_DQ[45]
44 M_A_DQ<44> AH8 AM15 M_A_DQS7_DN 42B8 43B8
M_A_DQ<45>
SA_DQ[44] SA_DQS#[7] OUT 46 M_B_DQ<46>AR6 SB_DQ[46]
45 AH9 SA_DQ[45]
47 M_B_DQ<47>AR5 SB_DQ[47]
46 M_A_DQ<46> AL9 SA_DQ[46]
B 48 M_B_DQ<48>AR9 SB_DQ[48] B
47 M_A_DQ<47> AL8 SA_DQ[47]
49 M_B_DQ<49>
AJ11 C7 M_B_DQS0_DP 44B8 45B8
48 M_A_DQ<48> AP11 SA_DQ[48] M_B_DQ<50>AT8
SB_DQ[49] SB_DQS[0] OUT
50 G3 M_B_DQS1_DP 44B8 45B8
49 M_A_DQ<49> AN11 SA_DQ[49] SA_DQS[0] D4 M_A_DQS0_DP
51 J6 M_B_DQS2_DP 44B8 45B8
50 M_A_DQ<50> AL12 SA_DQ[50] SA_DQS[1] F6 M_A_DQS1_DP
OUT 42B8 43B8 M_B_DQ<52>
52 AH11 M3 M_B_DQS3_DP 44B8 45B8
51 M_A_DQ<51> AM12 SA_DQ[51] SA_DQS[2] K3 M_A_DQS2_DP
OUT 42B8 43B8 M_B_DQ<53>AR8
53 AN6 M_B_DQS4_DP 44B8 45B8
52 M_A_DQ<52> AM11 SA_DQ[52] SA_DQS[3] N6 M_A_DQS3_DP
OUT 42B8 43B8 M_B_DQ<54>
54 AJ12 AP8 M_B_DQS5_DP 44B8 45B8
53 M_A_DQ<53> AL11 SA_DQ[53] SA_DQS[4] AL5 M_A_DQS4_DP
OUT 42B8 43B8 M_B_DQ<55>
55 AH12 AK11 M_B_DQS6_DP 44B8 45B8
54 M_A_DQ<54> AP12 SA_DQ[54] SA_DQS[5] AM9 M_A_DQS5_DP
OUT 42B8 43B8 M_B_DQ<56>
56 AT11 AP14 M_B_DQS7_DP 44B8 45B8
55 M_A_DQ<55> AN12 SA_DQ[55] SA_DQS[6] AR11 M_A_DQS6_DP
OUT 42B8 43B8 M_B_DQ<57>
57 AN14 SB_DQ[57]
56 M_A_DQ<56> AJ14 AM14 M_A_DQS7_DP 42B8 43B8
M_A_DQ<57>
SA_DQ[56] SA_DQS[7] OUT 58 M_B_DQ<58>
AR14 SB_DQ[58]
57 AH14 SA_DQ[57]
59 M_B_DQ<59>
AT14
58 M_A_DQ<58> AL15 SA_DQ[58] M_B_DQ<60>
SB_DQ[59] M_B_A<15..0>
60 AT12 44D8
59 M_A_DQ<59> AK15 SA_DQ[59] M_A_A<15..0> OUT M_B_DQ<61>
SB_DQ[60]
M_B_A<0>
OUT 45D8
42D8 43D8 61 AN15 SB_DQ[61] SB_MA[0] AA8 0
60 M_A_DQ<60> AL14 SA_DQ[60]
62 M_B_DQ<62>
AR15 SB_DQ[62] SB_MA[1] T7 M_B_A<1> 1
61 M_A_DQ<61> AK14 SA_DQ[61] SA_MA[0] AD10 M_A_A<0> 0
63 M_B_DQ<63>
AT15 SB_DQ[63] SB_MA[2] R7 M_B_A<2> 2
62 M_A_DQ<62> AJ15 SA_DQ[62] SA_MA[1] W1 M_A_A<1> 1
SB_MA[3] T6 M_B_A<3> 3
63 M_A_DQ<63> AH15 SA_DQ[63] SA_MA[2] W2 M_A_A<2> 2
SB_MA[4] T2 M_B_A<4> 4
SA_MA[3] W7 M_A_A<3> 3
SB_MA[5] T4 M_B_A<5> 5
SA_MA[4] V3 M_A_A<4> 4
SB_MA[6] T3 M_B_A<6> 6
V2 M_A_A<5> 5
SA_MA[5]
M_A_A<6> 45D8 44D8 OUT M_B_BS0 AA9 SB_BS[0] SB_MA[7] R2 M_B_A<7> 7
W3 6
M_A_BS0
SA_MA[6]
M_A_A<7> 45D8 44D8 OUT M_B_BS1 AA7 SB_BS[1] SB_MA[8] T5 M_B_A<8> 8
43D8 42D8 AE10 W6 7
OUT M_A_BS1
SA_BS[0] SA_MA[7]
M_A_A<8> 45C8 44C8 OUT M_B_BS2 R6 SB_BS[2] SB_MA[9] R3 M_B_A<9> 9
43D8 42D8 AF10 V1 8
OUT M_A_BS2
SA_BS[1] SA_MA[8]
M_A_A<9> SB_MA[10] AB7 M_B_A<10> 10
43D8 42D8 V6 W5 9
A OUT SA_BS[2] SA_MA[9]
M_A_A<10> SB_MA[11] R1 M_B_A<11> 11 A
SA_MA[10] AD8 10
SB_MA[12] T1 M_B_A<12> 12
V4 M_A_A<11> 11
SA_MA[11]
M_A_A<12> 45C8 44C8 OUT M_B_CAS# AA10 SB_CAS# SB_MA[13] AB10 M_B_A<13> 13
W4 12
M_A_CAS#
SA_MA[12]
M_A_A<13> 45C8 44C8 OUT M_B_RAS# AB8 SB_RAS# SB_MA[14] R5 M_B_A<14> 14
43C8 42C8 AE8 AF8 13
OUT M_A_RAS#
SA_CAS# SA_MA[13]
M_A_A<14> 45C8 44C8 OUT M_B_WE# AB9 SB_WE# SB_MA[15] R4 M_B_A<15> 15
43C8 42C8 AD9 V5 14
OUT M_A_WE#
SA_RAS# SA_MA[14]
M_A_A<15>
43C8 42C8 AF9 V7 15
OUT SA_WE# SA_MA[15]
FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4500~4699(CPU)
PVCORE CN4500 P1V05S
AG35 VCC1
AG34 VCC2
POWER VCCIO1 AH13
1
AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
1
22UF_6.3V_5
1
22UF_6.3V_5
1
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
AG31 AC10
22UF_6.3V_5
C4510 C4511 C4512 C4513 VCC5 VCCIO4
C4542
C4540
2 C4531
2 C4533
C4534
2 C4535
C4536
2 C4537
AG30 Y10
C4541
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 VCC6 VCCIO5
C4532
AG29 VCC7 VCCIO6 U10
AG28 P10
2
VCC8 VCCIO7
AG27 VCC9 VCCIO8 L10
2
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
D AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11 D
AF32 VCC14 VCCIO13 H14
PEG AND DDR

1
1
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
C4514 C4515 C4516 C4517 AF27 G12
VCC19 VCCIO18
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AF26 F14
VCC20 VCCIO19
AD35 VCC21 VCCIO20 F13
2
2
AD32 VCC24 VCCIO23 E14
AD30 VCC26
AD28 VCC28 VCCIO26 D14
AC35 VCC31 VCCIO29 D11
1
1
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
C4518 C4519 C4520 C4521 AC32 C12
VCC34 VCCIO32
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5
C AC31 VCC35 VCCIO33 C11 C
AC30 VCC36 VCCIO34 B14
2
2
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
P1V05S
1
AA30 VCC46
AA29 PLACE CLOSE TO CPU
CORE SUPPLY
VCC47
C4522 C4523 C4524 C4525 AA28 VCC48
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AA27 VCC49
1
AA26 VCC50
2
Y35 VCC51
Y34 R4528 R4527
VCC52
Y33 130_1%_2 75_5%_2
VCC53
Y32 VCC54
2
Y31 VCC55
Y30 VCC56
Y29 VCC57
B Y28 B
Y27
VCC58
VCC59
SVID SIGNAL TO VR
SVID
Y26 VCC60
V35 VCC61 VIDALERT# AJ29 H_CPU_SVIDALRT# R4529 1 2 43_5%_2 VR_SVID_ALERT# OUT 11C7
V34 VCC62 VIDSCLK AJ30 H_CPU_SVIDCLK R4530 1 2 0_5%_2 VR_SVID_CLK OUT 11A3 11C7
V33 VCC63 VIDSOUT AJ28 H_CPU_SVIDDAT R4531 1 2 0_5%_2 VR_SVID_DATA OUT 11A3 11C7
V32 VCC64
V31 VCC65
V30 VCC66 PVCORE
V29 VCC67
V28 VCC68
1
V27 VCC69
V26 VCC70
U35 R4532
VCC71
U34 100_1%_2
VCC72
U33 VCC73 VCCSENSE
2
U32 OUT 11D6
VCC74 VSSSENSE OUT 11D6
U31 VCC75
1
U30 VCC76
U29 VCC77
U28 R4533
VCC78
U27 100_1%_2
VCC79
U26 VCC80
2
R35 VCC81
A R34 VCC82
A
R33 VCC83
R32 VCC84
R31 P1V05S
SENSE LINES
VCC85
R30 VCC86
R29 VCC87
1
R28 VCC88 VCC_SENSE AJ35
R27 VCC89 VSS_SENSE AJ34
R26 R4534
VCC90
10_1%_2
INVENTEC
P35 VCC91
P34 VCC92
2
P33 VCC93 VCCIO_SENSE B10 VCC_SENSE_VCCIO OUT 9B7
P32 VCC94 VSS_SENSE_VCCIO A10 1 VSS_SENSE_VCCIO OUT 9B7
P31 VCC95 TITLE
P30 VCC96 MODEL,PROJECT,FUNCTION
P29 R4535 Block Diagram
VCC97
P28 10_1%_2
VCC98 DOC.NUMBER REV
P27 VCC99 SIZE CODE 1310xxxxx-0-0 X01
2
P26 A3 CS
VCC100
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT:

ROUTE WITH MIN. TRACE WIDTH OF 10 MILS
P0V75M_VREF P0V75M_VREF P0V75M_VREF_H
P0V75M_VREF
CPUDDR_WR_VREF1 51C3 IN CPUDDR_WR_VREF2 2 3

51C3 2 3 S D 3 2
IN S D D S
Q4502
Q4501
1
AM2302N
G
AM2302N
Q4500
1
AM2302N R4541
1
51D8 47A8 DRAMRST_CNTRL
DRAMRST_CNTRL IN 100K_5%_2
D 51D6 47A8 IN
D
2
R4538
73B8 55B1 22D6 15D2 15B8 0_5%_2
PVAXG 15A6 IN SLP_S3#_3R 1 2
15B4
1
1
CN4500
PVAXG FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER R4539
10_1%_2
C4578
POWER 470PF_50V_2
2
AT24 AK35 GFX_VCC_SENSE
2
VAXG1 VAXG_SENSE OUT 11B8
AT23 AK34 GFX_VSS_SENSE 11B8
VAXG2 VSSAXG_SENSE OUT
SENSE
AT21 VAXG3
LINES
1
1
AT20 VAXG4
AT18 VAXG5
AT17 R4540
VAXG6
C4651 C4545 C4546 C4547 C4548 C4549 C4550 AR24 VAXG7 10_1%_2
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5AR23 VAXG8
VREF
AR21
2
2
VAXG9
AR20 VAXG10
P0V75M_VREF_H
AR18 VAXG11
AR17 VAXG12
C AP24 VAXG13 SM_VREF AL1 C
AP23 VAXG14
AP21 VAXG15
AP20 B4 CPUDDR_WR_VREF1 51D8
VAXG16 SA_DIMM_VREFDQ
CPUDDR_WR_VREF2 IN
AP18 D1 51D6
VAXG17 SB_DIMM_VREFDQ IN
AP17 VAXG18
AN24 VAXG19
AN23 VAXG20 NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE
AN21 VAXG21
AN20 P1V5S
GRAPHICS
VAXG22
AN18 VAXG23
AN17 VAXG24
AM24 VAXG25 VDDQ1 AF7 5A
AM23 AF4
DDR3 -1.5V RAILS

VAXG26 VDDQ2
1
AM21 VAXG27 VDDQ3 AF1
AM20 VAXG28 VDDQ4 AC7
+
AL24 Y7 C4567 C4568 C4569 C4570 C4571 C4572 C4573
VAXG31 VDDQ7
AL23 Y4 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 220UF_2.5V
2
VAXG32 VDDQ8
AL21 VAXG33 VDDQ9 Y1
AL20 VAXG34 VDDQ10 U7
B AL18 VAXG35 VDDQ11 U4 B
AL17 VAXG36 VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
AK20 VAXG40
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
AJ23 VAXG44
AJ21 VAXG45
AJ20 VAXG46
AJ18 VAXG47
AJ17 VAXG48
SA RAIL
AH24 VAXG49
PVSA
AH23 VAXG50
AH21 VAXG51 VCCSA1 M27
1
AH20 VAXG52 VCCSA2 M26
1
AH18 VAXG53 VCCSA3 L26
AH17 VAXG54 VCCSA4 J26
+
J25 C4577
VCCSA5 C4574 C4575 C4576
VCCSA6 J24 PVSA 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 100UF_6.3V
H26
2
VCCSA7
2
VCCSA8 H25
1
A A
R4544
P1V8S
1.8V RAIL
100_5%_2
MISC
L4500
1.2A
2
1 2 P1V8S_VCCPLL B6 VCCPLL1 VCCSA_SENSE H23 VCCSA_SENSE OUT 10C4
A6 VCCPLL2
MPZ1608S221AT
1
A2 VCCPLL3
VCCSA_VID[0] C22 VCCSA_VID0 OUT 10B4

C4562 C4563 C4564
C4565
22UF_6.3V_5
VCCSA_VID[1]
VCCIO_SEL
C24
A19
VCCSA_VID1
VCCIO_SEL OUT
OUT
10B4
9C7 INVENTEC
1
1
10UF_6.3V_3 1UF_6.3V_2 1UF_6.3V_2
2
R4555
R4556 R4547 R4547 TITLE
1K_5%_2 1K_5%_2 MODEL,PROJECT,FUNCTION
10K_5%_2_DY SNB:0 OHM Block Diagram
IVB:10K OHM
2
2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CN4500 CN4500 CN4500

T35 VSS161 VSS234 F22 RSVD28 L7
AT35 VSS1 VSS81 AJ22 T34 VSS162 VSS235 F19 RSVD29 AG7
AT32 VSS2 VSS82 AJ19 T33 VSS163 VSS236 E30
OUT CFG<0> AK28 CFG[0] RSVD30 AE7
OUT CFG<1> AK29 CFG[1] RSVD31 AK2
AT27 VSS4 VSS84 AJ13 T31 VSS165 VSS238 E24 52A6 OUT CFG<2> AL26 CFG[2] RSVD32 W8
OUT CFG<3> AL27 CFG[3]
AT22 VSS6 VSS86 AJ7 T29 VSS167 VSS240 E18 52A6 OUT CFG<4> AK26 CFG[4]
AT19 VSS7 VSS87 AJ4 T28 VSS168 VSS241 E15 52A6 OUT CFG<5> AL29 CFG[5] RSVD33 AT26
AT16 VSS8 VSS88 AJ3 T27 VSS169 VSS242 E13 52A6 OUT CFG<6> AL30 CFG[6] RSVD34 AM33
AT13 VSS9 VSS89 AJ2 T26 VSS170 VSS243 E10 52A6 OUT CFG<7> AM31 CFG[7] RSVD35 AJ27
AT10 VSS10 VSS90 AJ1 P9 VSS171 VSS244 E9
OUT CFG<8> AM32 CFG[8]
AT7 VSS11 VSS91 AH35 P8 VSS172 VSS245 E8
OUT CFG<9> AM30 CFG[9] VCC_DIE_SENSE AH27
OUT CFG<10> AM28 CFG[10] VSS_DIE_SENSE AH26
OUT CFG<11> AM26 CFG[11]
AR25 VSS14 VSS94 AH30 P3 VSS175 VSS248 E5
OUT CFG<12> AN28 CFG[12]
D AR22 AH29 P2 E4 CFG<13> AN31 T8
VSS15 VSS95 VSS176 VSS249 OUT CFG<14>
CFG[13] RSVD37
D
AR19 AH28 N35 E3 AN26 J16
VSS16 VSS96 VSS177 VSS250 OUT CFG<15>
CFG[14] RSVD38
AR16 N34 E2 AM27 H16
VSS17 VSS178 VSS251 OUT CFG<16>
CFG[15] RSVD39
AR13 AH25 N33 E1 AK31 G16
VSS18 VSS98 VSS179 VSS252 OUT CFG[16] RSVD40
RESERVED
AR10 VSS19 VSS99 AH22 N32 VSS180 VSS253 D35
OUT CFG<17> AN29 CFG[17]
AP34 VSS23 VSS103 AH4 N28 VSS184 VSS257 D20 RSVD_NCTF1 AR35
AP31 VSS24 VSS104 AG9 N27 VSS185 VSS258 D17 AJ31 VAXG_VAL_SENSE RSVD_NCTF2 AT34
AP28 VSS25 VSS105 AG8 N26 VSS186 VSS259 C34 AH31 VSSAXG_VAL_SENSE RSVD_NCTF3 AT33
AP25 VSS26 VSS106 AG4 M34 VSS187 VSS260 C31 AJ33 VCC_VAL_SENSE RSVD_NCTF4 AP35
AP22 VSS27 VSS107 AF6 L33 VSS188 VSS261 C28 AH33 VSS_VAL_SENSE RSVD_NCTF5 AR34
AP19 VSS28 VSS108 AF5 L30 VSS189 VSS262 C27
AP16 VSS29 VSS109 AF3 L27 VSS190 VSS263 C25
AP13 VSS30 VSS110 AF2 L9 VSS191 VSS264 C23 AJ26 RSVD5
AP10 VSS31 VSS111 AE35 L8 VSS192 VSS265 C10
AP7
AP4
AP1
VSS32
VSS33
VSS112
VSS113
AE34
AE33
AE32
L6
L5
L4
VSS193
VSS194
VSS VSS266
VSS267
C1
B22
B19
RSVD_NCTF6 B34
A33
VSS34 VSS114 VSS195 VSS268 RSVD_NCTF7
AN30
AN27
AN25
VSS35
VSS36
VSS VSS115
VSS116
AE31
AE30
AE29
L3
L2
L1
VSS196
VSS197
VSS269
VSS270
B17
B15
B13
RSVD_NCTF8
RSVD_NCTF9
A34
B35
C35
VSS37 VSS117 VSS198 VSS271 RSVD_NCTF10
C AN22 VSS38 VSS118 AE28 K35 VSS199 VSS272 B11 C
AN19 VSS39 VSS119 AE27 K32 VSS200 VSS273 B9 F25 RSVD8
AN10 VSS42 VSS122 AD7 J34 VSS203 VSS276 B5 D24 RSVD11 RSVD51 AJ32
AN7 VSS43 VSS123 AC9 J31 VSS204 VSS277 B3 G25 RSVD12 RSVD52 AK32
AN4 VSS44 VSS124 AC8 H33 VSS205 VSS278 B2 G24 RSVD13
AM29 VSS45 VSS125 AC6 H30 VSS206 VSS279 A35 E23 RSVD14
AM25 VSS46 VSS126 AC5 H27 VSS207 VSS280 A32 D23 RSVD15
AM22 VSS47 VSS127 AC3 H24 VSS208 VSS281 A29 C30 RSVD16
AM19 VSS48 VSS128 AC2 H21 VSS209 VSS282 A26 A31 RSVD17
AM16 AB35 H18 A23 B30
AM13
VSS49
VSS50
VSS129
VSS130 AB34 H15
VSS210
VSS211
VSS283
VSS284 A20 B29
RSVD18
RSVD19
REMOVE
AM10 VSS51 VSS131 AB33 H13 VSS212 VSS285 A3 D30 RSVD20 BCLK_ITP AN35 CLK_XDP_CLKGEN_DP
AM7 AB32 H10 B31 AM35
AM4
VSS52
VSS53
VSS132
VSS133 AB31 H9
VSS213
VSS214 A30
RSVD21
RSVD22
BCLK_ITP#
CLK_XDP_CLKGEN_DN
AM3 VSS54 VSS134 AB30 H8 VSS215 C29 RSVD23
AM2 VSS55 VSS135 AB29 H7 VSS216
AM1 VSS56 VSS136 AB28 H6 VSS217
AL34 VSS57 VSS137 AB27 H5 VSS218 J20 RSVD24
AL31 VSS58 VSS138 AB26 H4 VSS219 B18 RSVD25 RSVD_NCTF11 AT2
AL28 VSS59 VSS139 Y9 H3 VSS220 RSVD_NCTF12 AT1
AL25 VSS60 VSS140 Y8 H2 VSS221 RSVD_NCTF13 AR1
B AL22 VSS61 VSS141 Y6 H1 VSS222
B
AL19 VSS62 VSS142 Y5 G35 VSS223 J15 RSVD27
AL16 VSS63 VSS143 Y3 G32 VSS224
AL13 VSS64 VSS144 Y2 G29 VSS225
AL10 VSS65 VSS145 W35 G26 VSS226 KEY B1
AL7 VSS66 VSS146 W34 G23 VSS227
AL4 VSS67 VSS147 W33 G20 VSS228 FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER
AL2 VSS68 VSS148 W32 G17 VSS229
AK33 VSS69 VSS149 W31 G11 VSS230
AK30 VSS70 VSS150 W30 F34 VSS231
AK22 VSS73 VSS153 W27
AK19 VSS74 VSS154 W26 FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER
AK16 VSS75 VSS155 U9
AK13 VSS76 VSS156 U8
AK10 U6
AK7
VSS77
VSS78
VSS157
VSS158 U5 PEG STATIC LANE REVERSAL
AK4 U3
AJ25
VSS79
VSS80
VSS159
VSS160 U2 CFG(2) 1 : (DEFAULT) NORMAL OPERATION
0 : LANE REVERSED
LOW EDP ENABLE
FOX_PZ98927_3641_41F_HURONRIVER_989P_CHIEFRIVER CFG<2> R4550 2
A PEG STATIC LAN REVERSAL IN 1
1 : (DEFAULT) EDP DISABLED A
1K_1%_2
CFG(4) 0 : EDP ENABLED
CFG<4> 1 R4551 2
52D4 IN
LOW EDP ENABLE
1K_1%_2_DY PEG DEFER TRAINING
CFG<5> R4552
52D4 IN 1 2 1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION
1K_1%_2_DY CFG(7) 0 : PEG WAIT FOR BIOS FOR TRAINING
CFG<6> 1 R4553 2
IN PCIE PORT BIFURCATION STRAPS
PCIE PORT BIFURCATION
PEG DEFER TRAINING 52D4 IN CFG<7> 1

1K_1%_2_DY
R4554 2 11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED INVENTEC
1K_1%_2_DY 10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED TITLE
CFG[6:5] 01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED) MODEL,PROJECT,FUNCTION

Block Diagram
STRAP PIN 00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH)
P3V3AL P3V3A
1 R4736 2
0_5%_2_DY
BAT54_30V_0.2A
1
P1V05S
R4737 2
2 D4700 NC 1
RSC_0402_DY
C4703
RTCX2
1
1 2
P3V3_RTC
3
18PF_50V_2
R4703
3
4
1
150_1%_3
1
20K_1%_2 R4738 R4740 R4742
D 1 2 R4708 X4700 PCH_TDI RSC_0402_DY RSC_0402_DY RSC_0402_DY
R4700
2
53A6 OUT D
1
10M_5%_2 32.768KHZ PCH_TMS
53B6 OUT
C4701 PCH_TDO
P3V3_RTC 53A6 OUT
1
R4704
1
2
1
1UF_6.3V_2
2
20K_1%_2
2
1 2 C4704
RTCX1
1
1 2
1.2K_1%_3
2
R4739 R4741 R4743
1
18PF_50V_2 RSC_0402_DY RSC_0402_DY RSC_0402_DY
1UF_6.3V_2
R4710
2
C4702
1UF_6.3V_2
1
1
1M_5%_2
C4700
R4705
2
U4700
2
U4701 A20 C38 LPC_3S_AD<0>
1 P3V3_RTC RTCX1 FWH0/LAD0 BI 22E3 29C3
+
FWH1/LAD1 A38 LPC_3S_AD<1> BI 22E3 29C3
2
2
- LPC_3S_AD<2> P3V3S
1
C20 B37 22E3 29C3

RTCX2 FWH2/LAD2
LPC_3S_AD<3> BI
C37 22E3 29C3
MAXELL_ML1220_T10_2P R4707
FWH3/LAD3 BI
RTC
1
LPC
D20 RTCRST#
330K_5%_3 FWH4/LFRAME# D36 LPC_3S_FRAME# OUT 22E3 29C3
G22 SRTCRST#
E36 R4744
2
R4706 LDRQ0#
K22 K36 10K_5%_2
0_5%_2_DY INTRUDER# LDRQ1#/GPIO23
1 2
2
C17 INTVRMEN SERIRQ V5 PCI_3S_SERIRQ BI 22E3 29B7
C C
INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE STRAPPING
1:ENABLE INTERNAL VRS AM3 SATA_HDDB_RX_DN
SATA0RXN IN 32D5
0:ENABLE EXTERNAL VRS HDA_3S_BITCLK 1 R4709 2 HDA_3S_BITCLK_R N34 AM1 SATA_HDDB_RX_DP
25A2 BI HDA_BCLK SATA0RXP IN 32D5
SATA 6G
33_5%_2 SATA0TXN AP7 SATA_HDDB_TX_DN OUT 32D4
HDA_3S_SYNC
1 R4711 2 HDA_3S_SYNC_R L34 AP5 SATA_HDDB_TX_DP
25A2 BI HDA_SYNC SATA0TXP OUT 32D4
33_5%_2
STRAPPING
25B1 OUT PCSPKR_PCH_3 T10 SPKR SATA1RXN AM10 SATA_HDDA_RX_DN
SATA_HDDA_RX_DP IN 32D8
AM8 32D8
R4712
SATA1RXP IN
PCSPKR_PCH_3(NO REBOOT) 25B2 OUT HDA_3S_RST# 1 2 HDA_3S_RST#_R
K34 HDA_RST# SATA1TXN AP11 SATA_HDDA_TX_DN
SATA_HDDA_TX_DP OUT 32D8
1 : NO REBOOT ENABLED 33_5%_2 AP10 32D8
SATA1TXP OUT
0 : (DEFAULT) NO REBOOT DISABLED
25A2 IN HDA_3S_SDIN0 E34 AD7 SATA_MINICARD_RX_DN IN 30C8
IHDA
HDA_SDIN0 SATA2RXN
SATA2RXP AD5 SATA_MINICARD_RX_DP IN 30C8
G34 HDA_SDIN1 SATA2TXN AH5 SATA_MINICARD_TX_DN OUT 30B8
AH4 SATA_MINICARD_TX_DP OUT 30B8
STRAP C34 HDA_SDIN2
SATA2TXP
FLASH OVERRIDE SATA3RXN AB8

FLASH_OVERRIDE 1 R4715 2 A34 AB10
FLASH DESCRIPTOR SECURITY OVERIDE 22D3 IN HDA_SDIN3 SATA3RXP
53B8 1K_5%_2 SATA3TXN AF3
1:ENABLE AF1
SATA3TXP
0:DISABLE : (DEFAULT INTERNAL PULL-DOWN) P3V3A R4716
OUT HDA_3S_SDOUT 1 2 A36
SATA
25A2 HDA_SDO
B P3V3A 33_5%_2 STRAPPING
SATA4RXN Y7 B
Y5
22D3 FLASH_OVERRIDE 1 R4720 2 SATA4RXP
53B7
OUT C36 HDA_DOCK_EN#/GPIO33 SATA4TXN AD3
1 R343 2
10K_5%_2_DY SATA4TXP AD1
10K_5%_2 EC_SMI N32
IN HDA_DOCK_RST#/GPIO13
SATA_ODD_RX_DN
Y3 32A7
R4718 SATA5RXN
SATA_ODD_RX_DP IN
Y1 32A7
R6 1 2 SATA5RXP
SATA_ODD_TX_DN IN
HDA_3S_SYNC_R 1 2 AB3 32A7
OUT TP4720 PCH_TCK
SATA5TXN
SATA_ODD_TX_DP OUT
1 J3 AB1
JTAG
1K_5%_2 RSC_0402_DY OUT JTAG_TCK SATA5TXP OUT 32A7
TP30
53D3 OUT 1 TP4721 PCH_TMS H7 JTAG_TMS SATAICOMPO Y11 P1V05S
HDA_3S_SYNC_R(PLL ODVR VOLTAGE) TP30 R4747
1 : VCC VRM = 1.6V 53D3 OUT 1 TP4722 PCH_TDI K5 JTAG_TDI SATAICOMPI Y10 P1V05S_SATARCOMPO 1 2
0 : VCC VRM = 1.8V(DEFAULT) TP30 37.4_1%_2
53D3 OUT 1 TP4723 PCH_TDO H1 JTAG_TDO
TP30 SATA3RCOMPO AB12
P1V05S P3V3S
AB13 P1V05S_SATA3RCOMPO 1 R4748 2
SATA3COMPI
49.9_1%_2
1
22D6 22C7 EC_SPI_CLK T3 1 R4749
AH1 2
OUT SPI_CLK SATA3RBIAS
R4751 R4750 R4752
750_1%_2
SPI
22D6 22C8 OUT EC_SPI_CS0# Y14 SPI_CS0# 10K_5%_2 10K_5%_2 10K_5%_2
A EC_SPI_CS1# T1 A
2
22C8 OUT SPI_CS1#
SATALED# P3
22C7 22C6 OUT EC_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14
22C8 22C6 OUT EC_SPI_SO U3 SPI_MISO SATA1GP/GPIO19 P1

STRAPPING
ITL_PANTHERPOINT_FCBGA_989P
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) SMB_ALERT# OUT 54B2
U4700 P3V3A P3V3A

23B1 IN PCIE_LAN_RX_DN BG34 PERN1
PCIE_LAN_RX_DP BJ34 E12 1 R4795 2
23B1 IN C4724 PERP1 SMBALERT#/GPIO11
23C2 OUT PCIE_LAN_TX_DN 1 2 C4725 PCIE_LAN_TX_C_DN AV32 PETN1 10K_5%_2 SML1ALERT# R4796 2
1
SMBUS
PCIE_LAN_TX_DP 1 2 PCIE_LAN_TX_C_DP AU32 H14 PCH_3A_SMCLK 54D3 IN
23C2 OUT PETP1 SMBCLK BI 54A8
10K_5%_2
0.1UF_16V_2
PCIE_WLAN_RX_DN 0.1UF_16V_2 BE34 C9 PCH_3A_SMDATA SML1_CLK 1 R4797 2
29B7 IN PERN2 SMBDATA BI 54A8 54D3 BI
29B7 IN PCIE_WLAN_RX_DP C4726 BF34 PERP2
PCIE_WLAN_TX_DN 1 2 PCIE_WLAN_TX_C_DN BB32 2.2K_5%_2
29B7 OUT C4727 PETN2
29B7 OUT PCIE_WLAN_TX_DP 1 2 PCIE_WLAN_TX_C_DP AY32 PETP2 54D3 BI SML1_DATA 1 R4798 2
0.1UF_16V_2 SML0ALERT#/GPIO60 A12 DRAMRST_CNTRL_PCH OUT 47A8
PCIE_USB3_RX_DN 0.1UF_16V_2 BG36 2.2K_5%_2
33C7 IN PERN3
33C7 IN PCIE_USB3_RX_DP C4793 BJ36 PERP3 SML0CLK C8 PCH_3A_ALERT_CLK OUT 29B3 54D2 54D3 29B3 IN PCH_3A_ALERT_CLK 1 R4799 2
33C7 OUT PCIE_USB3_TX_DN 1 2 C4794 PCIE_USB3_TX_C_DN AV34 PETN3
D 33C7 PCIE_USB3_TX_DP 1 2 PCIE_USB3_TX_C_DP AU34 G12 PCH_3A_ALERT_DAT 29B3 54D2
2.2K_5%_2
OUT PETP3 SML0DATA OUT PCH_3A_ALERT_DAT R4800 D
0.1UF_16V_2 54D3 29B3 1 2
PCIE_USB3_RX1_DN 0.1UF_16V_2 IN
PCI-E*
35C7 BF36
IN PCIE_USB3_RX1_DP
PERN4
2.2K_5%_2
35C7 C4795 BE36
IN PCIE_USB3_TX1_DN PCIE_USB3_TX1_C_DN
PERP4
SML1ALERT#
35C7 1 2 C4796 AY34 C13 54D2
OUT PCIE_USB3_TX1_DP PCIE_USB3_TX1_C_DP
PETN4 SML1ALERT#/PCHHOT#/GPIO74 IN
35C7 1 2 BB34
OUT PETP4
SML1_CLK
0.1UF_16V_2 E14 54D2
0.1UF_16V_2
SML1CLK/GPIO58 OUT
28B7 PCIE_CR_RX_DN BG37
IN PERN5
SML1_DATA
28B7 PCIE_CR_RX_DP BH37 M16 54D2
IN PERP5 SML1DATA/GPIO75 OUT
28B7 PCIE_CR_TX_DN 1C4797 2 PCIE_CR_TX_C_DN AY36
OUT 0.1UF_16V_2
PETN5
28B7 PCIE_CR_TX_DP 1 2 PCIE_CR_TX_C_DP BB36
OUT 0.1UF_16V_2
PETP5
30B8 IN PCIE_MSATA_RX_DN C4798 BJ38 PERN6

30B8 IN PCIE_MSATA_RX_DP C4842 BG38 PERP6
30B8 OUT PCIE_MSATA_TX_DN 1 2 C4843 PCIE_MSATA_TX_C_DN AU36 PETN6 CL_CLK1 M7
30B8 OUT PCIE_MSATA_TX_DP 1 2 PCIE_MSATA_TX_C_DP AV36 PETP6
0.1UF_16V_2_DY
Controller
0.1UF_16V_2_DY
BG40 PERN7 CL_DATA1 T11
Link
BJ40 PERP7
AY40 PETN7 P3V3A
BB40 PETP7 CL_RST1# P10
R4753
1 2
BE38 PERN8
C BC38 PERP8 10K_5%_2 C
AW38 PETN8
AY38
CLOCK TERMINATION FOR FICM PETP8
STUFF FOR INTEGRATED CLK PEG_A_CLKRQ#/GPIO47 M10 CLKREQ_GPU#

OUT 62E4
23C2 OUT CLK_PCIE_LAN_DN Y40 CLKOUT_PCIE0N
R4777 23C2 OUT CLK_PCIE_LAN_DP Y39 CLKOUT_PCIE0P
54B3 IN CLKIN_DMI_PCH_DN 1 2 CLKOUT_PEG_A_N AB37 CLK_PEG_PCH_DN
OUT 62E4
10K_5%_2 23C5 IN CLKREQ_LAN# J2 PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P AB38 CLK_PEG_PCH_DP
OUT 62E4
54A2 XTAL25_OUT OUT 54A3
R4778
1
54B3 IN CLKIN_DMI_PCH_DP 1 2 29C7 OUT CLK_PCIE_WLAN_DN AB49 CLKOUT_PCIE1N CLKOUT_DMI_N AV22 CLK_DMI_PCH_DN
OUT 47D2
10K_5%_2 29C7 OUT CLK_PCIE_WLAN_DP AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLK_DMI_PCH_DP
OUT 47D2
R4801
CLKREQ_WLAN# M1 1M_5%_2
R4779 29C7 IN PCIECLKRQ1#/GPIO18
54B3 IN CLKIN_BUF_DOT96_DN 1 2 54A2 CLKOUT_DP_N AM12
X4701
2
10K_5%_2 AM13
CLK_PCIE_USB3_DN
CLKOUT_DP_P
1 2 XTAL25_IN OUT 54A3
33C7 AA48
OUT CLKOUT_PCIE2N
CLOCKS
R4780 33C7 OUT CLK_PCIE_USB3_DP AA47 CLKOUT_PCIE2P 25MHZ
CLKIN_BUF_DOT96_DP
1
54B3 1 2 BF18 CLKIN_DMI_PCH_DN 54C8
IN CLKIN_DMI_N IN
1
10K_5%_2 33B8 IN CLKREQ_USB3# V10 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P BE18 CLKIN_DMI_PCH_DP
IN 54B8
33C7 C4729
C4728 18PF_50V_2
R4781 R4837
B 54A3 CLKIN_PCH14 1 2 35C7 CLK_PCIE_1_USB3_DN Y37 BJ30 1 2 18PF_50V_2 B
IN OUT CLKOUT_PCIE3N CLKIN_GND1_N
10K_5%_2 CLK_PCIE_1_USB3_DP Y36 BG30
2
35C7 OUT CLKOUT_PCIE3P CLKIN_GND1_P
2
10K_5%_2
R4782 35A8 IN CLKREQ_1_USB3# A8 PCIECLKRQ3#/GPIO25
54B3 IN CLKIN_SATA1_DP 1 2 35C7 CLKIN_DOT_96N G24 CLKIN_BUF_DOT96_DN IN 54B8
10K_5%_2 CLKIN_DOT_96P E24 CLKIN_BUF_DOT96_DP IN 54B8
28B7 CLK_PCIE_CR_DN Y43
BI CLKOUT_PCIE4N
R4783 28B7 CLK_PCIE_CR_DP Y45
CLKIN_SATA1_DN BI CLKOUT_PCIE4P
CLKIN_SATA1_DN
54B3 1 2 AK7 54B8
IN CLKIN_SATA_N
CLKIN_SATA1_DP
IN
28C7 28B7 CLKREQ_CR# L12 AK5 54B8
10K_5%_2 BI PCIECLKRQ4#/GPIO26 CLKIN_SATA_P IN SMB_ALERT# B500
54D3 1 2
IN
CLK_MSATA_PCIE_DNV45 K45 CLKIN_PCH14 PASSWORD_0805
30C6 BI CLKOUT_PCIE5N REFCLK14IN IN 54B8
30C6 BI CLK_MSATA_PCIE_DPV46 CLKOUT_PCIE5P
P3V3S P3V3A
P5V0S 30C6 CLKREQ_MSATA# L14 H45 CLKIN_PCI_FB 57A7
54A3
BI PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK IN
R4775
54C7 54A2 23C5 OUT CLKREQ_LAN# 1 2
1
2.2K_5%_2 P3V3A AB42 V47 XTAL25_IN 54B1 10K_5%_2_DY

CLKOUT_PEG_B_N XTAL25_IN
XTAL25_OUT OUT
R4784 R4785 AB40 V49 54C1
R4787
CLKOUT_PEG_B_P XTAL25_OUT OUT R4776 2
2.2K_5%_2
2.2K_5%_2
R4792
P1V05S
54B7 54A2 29C7 OUT CLKREQ_WLAN# 1
R4786 1 2 E6 PEG_B_CLKRQ#/GPIO56 10K_5%_2_DY
2.2K_5%_2 10K_5%_2_DY R4802
2
XCLK_RCOMP Y47 1 2
A 44C8 V40 90.9_1%_2 P3V3A A
PCH_3S_SMCLK CLKOUT_PCIE6N
2
42C8 BI R4773
43C8 Q4700
V42 CLKOUT_PCIE6P 54C7 54A2 23C5 OUT CLKREQ_LAN# 1 2
45C8 R4793 CLOSE TO PCH
10K_5%_2
S
1 2 T13 PCIECLKRQ6#/GPIO45 P3V3S

1
G
10K_5%_2_DY TP24 R4772
FLEX CLOCKS
V38 K43 1 54B7 54A2 29C7 OUT CLKREQ_WLAN# 1 2

D
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
PCH_3A_SMCLK V37 TP4700
SSM3K7002BFU CLKOUT_PCIE7P TP24 10K_5%_2
54D3 BI F47 1
R4794 CLKOUTFLEX1/GPIO65
TP4701
3
1 2 K12 PCIECLKRQ7#/GPIO46 TP24
INVENTEC
10K_5%_2_DY H47 1
PCH_3A_SMDATA CLKOUTFLEX2/GPIO66
3
54D3 BI AK14 TP4702

CLKOUT_ITPXDP_N
Q4701 AK13 CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 P3V3S
R4771
D
G 1 54A6 30C6 CLKREQ_MSATA#

1 2
OUT TITLE
10K_5%_2
ITL_PANTHERPOINT_FCBGA_989P MODEL,PROJECT,FUNCTION
S
44C8 Block Diagram

42C8 BI PCH_3S_SMDATA
43C8 DOC.NUMBER REV
SSM3K7002BFU
2
45C8 SIZE CODE 1310xxxxx-0-0 X01

A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE

U4700
HIGH-ENABLED(DEFAULT)
48D7 DMI_RX0_DN BC24 BJ14 FDI_TX0_DN 48C7 LOW-DISABLED
IN DMI_RX1_DN BE20
DMI0RXN FDI_RXN0
AY14 FDI_TX1_DN IN
D 48D7 IN DMI1RXN FDI_RXN1 IN 48C7
48D7 DMI_RX2_DN BG18 BE14 FDI_TX2_DN 48C7 D
IN DMI_RX3_DN BG20
DMI2RXN FDI_RXN2
BH13 FDI_TX3_DN IN
48D7 IN DMI3RXN FDI_RXN3 IN 48C7
BC12 FDI_TX4_DN 48C7 P3V3_RTC
DMI_RX0_DP BE24
FDI_RXN4
BJ12 FDI_TX5_DN IN
48D7 IN DMI0RXP FDI_RXN5 IN 48C7
48D7 DMI_RX1_DP BC20 BG10 FDI_TX6_DN 48C7
IN DMI_RX2_DP BJ18
DMI1RXP FDI_RXN6
BG9 FDI_TX7_DN IN
48C7 IN DMI2RXP FDI_RXN7 IN 48C7
DMI_RX3_DP
1
48C7 BJ20
IN DMI3RXP
BG14 FDI_TX0_DP
FDI_RXP0 IN 48C7
DMI_TX0_DN AW24 BB14 FDI_TX1_DP STRAPPING
DMI
48D7 OUT DMI0TXN FDI_RXP1 IN 48C7 R4829
FDI
48D7 DMI_TX1_DN AW20 BF14 FDI_TX2_DP 48C7 330K_5%_2
OUT DMI_TX2_DN BB18
DMI1TXN FDI_RXP2
BG13 FDI_TX3_DP IN
48D7 OUT DMI2TXN FDI_RXP3 IN 48C7
P1V05S DMI_TX3_DN AV18 BE12 FDI_TX4_DP
2
48D7 OUT DMI3TXN FDI_RXP4 IN 48C7
BG12 FDI_TX5_DP 48C7
DMI_TX0_DP AY24
FDI_RXP5
BJ10 FDI_TX6_DP IN
48D7 OUT DMI0TXP FDI_RXP6 IN 48C7
DMI_TX1_DP FDI_TX7_DP
1
48D7 AY20 BH9 48B7

OUT DMI1TXP FDI_RXP7 IN
1
48D7 DMI_TX2_DP AY18
R4812 OUT DMI_TX3_DP AU18
DMI2TXP
48D7 OUT DMI3TXP
AW16 FDI_INT R4830
49.9_1%_2 FDI_INT OUT 48B7
330K_5%_2_DY
BJ24 AV12 FDI_FSYNC0
2
DMI_ZCOMP FDI_FSYNC0 OUT 48B7
2
BG25 BC10 FDI_FSYNC1 48B7
DMI_IRCOMP FDI_FSYNC1 OUT
R4814
C 1 2 BH21 AV14 FDI_LSYNC0 48B7
C
DMI2RBIAS FDI_LSYNC0 OUT
750_1%_2 BB10 FDI_LSYNC1 48B7
P3V3S
FDI_LSYNC1 OUT
P3V3A
1
DSWVRMEN A18
1
R4832
R4815 STRAPPING
R4816
10K_5%_2 SUSACK# 1 2 C12 E22 1 R4831 2 RSMRST# 1K_5%_2_DY
IN SUSACK# DPWROK IN 22D1 22D3 55B7
0_5%_2
0_5%_2_DY
2
P3V3_LDO
2
SYS_RESET# K3 B9 PCIE_WAKE#
System Power Management

47C1 IN SYS_RESET# WAKE# IN 23B5 29C7 33C6 35C6 55A5
1
PVCORE_PG P12 N3 PCI_3S_CLKRUN# R4883
46B4 IN SYS_PWROK CLKRUN#/GPIO32 IN 55A5
10K_5%_2_DY
PCH_PWROK L22 G8
2
55A6 22B6 IN PWROK SUS_STAT#/GPIO61 SLP_S5_3R
OUT
3
L10 N14 EC_32KHZ 22B6 Q4713
APWROK SUSCLK/GPIO62 OUT
B B
D
P3V3A 1 G
47C7 OUT PM_DRAM_PWRGD B13 DRAMPWROK SLP_S5#/GPIO63 D10 SLP_S5#_3R
OUT 15D2 22D3
S
P3V3A
1
55C2 SSM3K7002BFU_DY
RSMRST# C21 H4
2
22D1 IN RSMRST# SLP_S4#
R4820 22D3 U4706
1
+
10K_5%_2_DY SUS_PWR_ACK
K16 F4 SLP_S3#_IC_3R 4 SLP_S3#_3R
2
55A5 OUT SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# OUT 15A6
2
D4706 2 15B4 15B8 15D2 22D6 51D3 73B8
2
NC
-
EC_PWRSW#3 1 E20 G10 TC7SZ08FU R4884
22D6 IN PWRBTN# INT. PU 20K SLP_A#
100K_5%_2
1
ACPRESENT H20 G16 SLP_SUS#
2
BAT54_30V_0.2A 66C3 55A5 22D6 IN ACPRESENT/GPIO31 INT. PD 20K SLP_SUS# OUT

D4707
NC
22D6 LOW_BAT#_3 3 1 E10 AP14 H_PM_SYNC 47C5

IN BATLOW#/GPIO72 INT. PU 20K PMSYNCH BI
P3V3_LDO
BAT54_30V_0.2A 55A5 IN PM_RI# A10 RI# SLP_LAN#/GPIO29 K14
1
P3V3A ITL_PANTHERPOINT_FCBGA_989P
R4834
R4822 P3V3A
A 1 2 10K_5%_2 A
66C3 55A6 22D6 ACPRESENT R4824 1 2 10K_5%_2
8.2K_5%_2 IN SLP_S3_3R
2
OUT 16A4 16B4 16B8
55B7 22B6 PCH_PWROK 55B7 SUS_PWR_ACK R4825 1 2 10K_5%_2
IN IN
3
1
PM_RI# 1 2 Q4714
55A6 IN R4826 10K_5%_2
D
R4823 1 G
35C6 33C6 29C7 23B5 PCIE_WAKE# R4827 1 2 10K_5%_2
10K_5%_2 55B3
IN
S
SSM3K7002BFU
INVENTEC
2
P3V3S
2
TITLE
PCI_3S_CLKRUN# 8.2K_5%_2 Block Diagram
55B3 IN R48281 2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S
1
D R4854 R4855
100K_5%_2
100K_5%_2
D
2
U4700
1
38A7 OUT PCH_LCM_BKLTEN J47 L_BKLTEN SDVO_TVCLKINN AP43

R4856 R4857 38D8 OUT PCH_LCM_VDDEN M45 L_VDD_EN SDVO_TVCLKINP AP45
2.2K_5%_2 2.2K_5%_2
38A6 OUT PCH_INV_PWM_3 P45 L_BKLTCTL SDVO_STALLN AM42
SDVO_STALLP AM40
2
38C6 OUT PCH_LVDS_DDCCLK T40 L_DDC_CLK

38C6 OUT PCH_LVDS_DDCDATA K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
T45 L_CTRL_CLK
P39 L_CTRL_DATA
WHEN 1- LVDS IS DETECTED
R4858
PCH_LVDS_DDCDATA - LVDS DETECT 1 2 AF37 LVD_IBG SDVO_CTRLCLK P38
AF36 LVD_VBG SDVO_CTRLDATA M39
2.37K_1%_2
HIGH-LVDS ENABLED AE48
LVDS
LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
LOW-LVDS DISABLED (DEFAULT) DDPB_AUXP AT47
DDPB_HPD AT40
C 38B8 PCH_LVDS_TXCA_DN AK39 C
OUT PCH_LVDS_TXCA_DP
LVDSA_CLK#
38B8 AK40 AV42
OUT LVDSA_CLK DDPB_0N
DDPB_0P AV40
38C8 PCH_LVDS_TXDA0_DN AN48 AV45
OUT PCH_LVDS_TXDA1_DN
LVDSA_DATA#0 DDPB_1N
38B8 AM47 AV46
OUT PCH_LVDS_TXDA2_DN
LVDSA_DATA#1 DDPB_1P
38B8 AK47 AU48
OUT LVDSA_DATA#2 DDPB_2N
Digital Display Interface

AJ48 LVDSA_DATA#3 DDPB_2P AU47
DDPB_3N AV47
38B8 OUT PCH_LVDS_TXDA0_DP AN47 LVDSA_DATA0 DDPB_3P AV49
38B8 OUT PCH_LVDS_TXDA1_DP AM49 LVDSA_DATA1
38B8 OUT PCH_LVDS_TXDA2_DP AK49 LVDSA_DATA2 PCH_HDMI_DDCCLK
AJ47 P46 40A8
LVDSA_DATA3 DDPC_CTRLCLK
PCH_HDMI_DDCDATA BI
P42 40B8
DDPC_CTRLDATA BI
38B8 OUT PCH_LVDS_TXCB_DN AF40 LVDSB_CLK#
38B8 OUT PCH_LVDS_TXCB_DP AF39 LVDSB_CLK DDPC_AUXN AP47
AP49
PCH_LVDS_TXDB0_DN
DDPC_AUXP PCH_HPDET
38B8 AH45 AT38 40A3
OUT PCH_LVDS_TXDB1_DN
LVDSB_DATA#0 DDPC_HPD IN
38B8 AH47
OUT PCH_LVDS_TXDB2_DN
LVDSB_DATA#1
PCH_HDMI_TX2_DN
38B8 AF49 AY47 40D7
OUT LVDSB_DATA#2 DDPC_0N
PCH_HDMI_TX2_DP OUT
AF45 AY49 40D7
LVDSB_DATA#3 DDPC_0P
PCH_HDMI_TX1_DN OUT
AY43 40D7
PCH_LVDS_TXDB0_DP
DDPC_1N
PCH_HDMI_TX1_DP OUT
B 38B8 OUT AH43 LVDSB_DATA0 DDPC_1P AY45
OUT 40D7 B
38B8 OUT PCH_LVDS_TXDB1_DP AH49 LVDSB_DATA1 DDPC_2N BA47 PCH_HDMI_TX0_DN OUT 40C7
38B8 OUT PCH_LVDS_TXDB2_DP AF47 LVDSB_DATA2 DDPC_2P BA48 PCH_HDMI_TX0_DP OUT 40D7
AF43 LVDSB_DATA3 DDPC_3N BB47 PCH_HDMI_TXC_DN OUT 40C7
DDPC_3P BB49 PCH_HDMI_TXC_DP OUT 40C7
39D8 OUT CRTB N48 CRT_BLUE DDPD_CTRLCLK M43
CRT
39D8 OUT CRTG P49 CRT_GREEN DDPD_CTRLDATA M36
39D8 CRTR T49
OUT CRT_RED
R4859 AT45
DDPD_AUXN
1 2
39B6 OUT CRT_DDCCLK T39 CRT_DDC_CLK DDPD_AUXP AT43
39B6 OUT CRT_DDCDATA M40 CRT_DDC_DATA DDPD_HPD BH41
150_1%_2_DY
R4860 BB43
DDPD_0N
1 2
39B8 OUT CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
39B8 OUT CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
150_1%_2_DY BE44
DDPD_1P
R4861 DDPD_2N BF42
1 2 T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
150_1%_2_DY DDPD_3P BG42
1
A R4862 ITL_PANTHERPOINT_FCBGA_989P A
1K_1%_2
2
CLOSE TO PCH
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) U4700

RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25 TP3
BJ16 TP4 RSVD5 AT10
BG16 TP5 RSVD6 BC8
GPIO51 GPIO19 BOOT BIOS
AH38 TP6
BBS_BIT0 AH37 TP7 RSVD7 AU2

BBS_BIT1 DESTINATION AK43 AT4
TP8 RSVD8
AK45 AT3
0 1 RESERVED(NAND) C18
TP9
TP10
RSVD9
RSVD10 AT1
N30 AY3
1 0 ------ H3
TP11
TP12
RSVD11
RSVD12 AT5
AH12 AV3
1 1 SPI (DEFAULT) TP13 RSVD13
NVRAM
D AM4 TP14 RSVD14 AV1
0 0 LPC
AM5 TP15 RSVD15 BB1 D
RSVD
Y13 TP16 RSVD16 BA3
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8
RSVD21 BD4
P3V3S RSVD22 BF6
B21 TP21 RSVD23 AV5

R4874 1 2 8.2K_5%_2 PCI_3S_INTA# BI 57B6 M20 TP22
AY16 TP23
1 2 PCI_3S_INTB# ROUTE WITH 90 OHMS IMPEDANCE BG46 AV10
R4875 8.2K_5%_2 BI 57B6 TP24 RSVD24
TOTAL LENGTH NO LONGER THAN 11 INCHES
R4876 1 2 8.2K_5%_2 PCI_3S_INTC# BI 57B6 RSVD25 AT8
R4877 1 2 8.2K_5%_2 PCI_3S_INTD# BI 57B6 34D7 BI USB3_PCH_RX1_DN BE28 USB3RN1 RSVD26 AY5
34C7 BI USB3_PCH_RX2_DN BC30 USB3RN2 RSVD27 BA2
R4878 1 2 8.2K_5%_2 RUNSCI0#_3 IN 22E3 58D6 36D8 BI USB3_PCH_RX3_DN BE32 USB3RN3
36B8 BI USB3_PCH_RX4_DN BJ32 USB3RN4 RSVD28 AT12 NOTE:
34D7 BI USB3_PCH_RX1_DP BC28 BF3
34C7 USB3_PCH_RX2_DP BE30
USB3RP1 RSVD29
USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2
PCI_3S_REQ1# BI USB3_PCH_RX3_DP
USB3RP2
R4880 1 2 10K_5%_2 58D6 36D8 BF32
C IN BI USB3RP3
USB_P0_DN C
36B8 BI USB3_PCH_RX4_DP BG32 C24
BI 34C7
R4881 1 2 10K_5%_2 PCI_3S_REQ2# 57B6 34C7 USB3_PCH_TX1_DN AV26
USB3RP4
DEBUG PORT
USBP0N
A24 USB_P0_DP 34C7
P0.P1 RESERVER FOR USB3.0
IN BI USB3_PCH_TX2_DN
USB3TN1 USBP0P
USB_P1_DN BI
34C7 BB26 C25 34B7
PCI_3S_REQ3# BI USB3_PCH_TX3_DN
USB3TN2 USBP1N
USB_P1_DP BI
R4882 1 2 10K_5%_2 58D6 36D8 AU28 B25 34B7
IN BI USB3TN3 USBP1P
USB_P2_DN BI
36B8 USB3_PCH_TX4_DN AY30 C26 36D8
BI USB3_PCH_TX1_DP
USB3TN4 USBP2N
USB_P2_DP BI
34C7 AU26 A26 36D8
BI USB3_PCH_TX2_DP
USB3TP1 USBP2P
USB_P3_DN BI
34B7 AY26 K28 36A8
SATA_ODD_DA# BI USB3_PCH_TX3_DP
USB3TP2 USBP3N BI
R4838 1 2 10K_5%_2 IN 32A5 57B6 36D8 BI AV28 USB3TP3 USBP3P H28 USB_P3_DP BI 36A8
36B8 BI USB3_PCH_TX4_DP AW30 USB3TP4 USBP4N E28
USBP4P D28
USBP5N C28 USB_WLAN_DN BI 29B3
USBP5P A28 USB_WLAN_DP BI 29B3 WLAN
C29 USB_FP_DN BI 21A6
BBS STRAPING
USBP6N
B29 USB_FP_DP 21A6
FP
PCI_3S_INTA#
USBP6P BI
57D7 K40 N28
BI PCI_3S_INTB#
PIRQA# USBP7N
57C7 K38 M28
BBS_BIT1 BI PCI_3S_INTC#
PIRQB# USBP7P
57C7 H38 L30
BI PIRQC# USBP8N
PCI
57C7 BI PCI_3S_INTD# G38 PIRQD# USBP8P K30
USB
STP_A16OVR USBP9N G30
2
58C7 OUT DGPU_HOLD_RST# C46 REQ1#/GPIO50 USBP9P E30

57C7 62F5 PCI_3S_REQ2# C44 C30 USB_CAM_DN
R4885 R4886 OUT DGPU_PWR_EN# E40
REQ2#/GPIO52 USBP10N
A30 USB_CAM_DP BI 38A3
37A4
WEBCAM 37A4 38A3
OUT REQ3#/GPIO54 USBP10P
USB_TV2_DN BI
B 1K_5%_2_DY 1K_5%_2_DY USBP11N L32
BI 30B3
TV2 B
D47 GNT1#/GPIO51 USBP11P K32 USB_TV2_DP BI 30B3
1
E42 G32 USB_3D_DN BI 38D3

F46
GNT2#/GPIO53 USBP12N
E32 USB_3D_DP 38D3
3D
GNT3#/GPIO55 USBP12P
USB_TV_DN BI
C32 30B3
USED AS GPIO ONLY.
INT. PU 20K
USBP13N
USB_TV_DP BI TV
LOW=A16 SWAP OVERRIDE A32 30B3
USB3_SMI#
USBP13P BI
33C7 33C6 G42
STP_A16OVR BI SATA_ODD_DA#
PIRQE#/GPIO2
57C7 32A5 G40 R4835
BI HDP_LOC
PIRQF#/GPIO3
TOP-BLOCK SWAP OVERRIDE 73A1 C42 C33 1 2
IN USB3_1_SMI#
PIRQG#/GPIO4 USBRBIAS#
35C7 35C6 D44
HIGH=DEFAULT BI PIRQH#/GPIO5
P3V3A 22.6_1%_3
USBRBIAS B33
1 R4887 2 P3V3A_PME# K10 CLOSE TO PCH
PME# INT. PU 20K
PLT_RST# 10K_5%_2_DY C6 A14 MACHINE_ID0

47C7 35C6 33C6 28C7 BI PLTRST# OC0#/GPIO59 IN 57A3 57A5
OC1#/GPIO40 K20 MACHINE_ID1 IN 57A3 57A5
OC2#/GPIO41 B17 MACHINE_ID2 IN 57A3 57A5
P3V3A 22E3 OUT CLK_KBPCI R4889 1 2 22_5%_2 CLK_KBPCI_R H49 CLKOUT_PCI0 OC3#/GPIO42 C16 MACHINE_ID3 IN 57A3 57A5
54A3 OUT CLKIN_PCI_FB R4890 1 2 22_5%_2 CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16 MACHINE_ID4
MACHINE_ID5 IN 57A3 57A5
J48 A16 57A3 57A5
TP24 CLKOUT_PCI2 OC5#/GPIO9
MACHINE_ID6 IN
1 K42 D14
5
CLKOUT_PCI3 OC6#/GPIO10 IN 57A3 57A5

TP4717
OUT CLK_PCI_DEBUG R4891 MACHINE_ID1_DB
U4705 29C7 1 2 22_5%_2 H40 C14 57A3 57A5
CLK_PCI_DEBUG_R
CLKOUT_PCI4 OC7#/GPIO14 IN
1
+
30C3 29C7 29C3 22E3 BI BUF_PLT_RST# 4 ITL_PANTHERPOINT_FCBGA_989P

62F5 40A1 36C3 TO BE USED AS GPIO
A 2 A
2
R4888 TC7SZ08FU
3
100K_5%_2 P3V3A
1
MACHINE_ID0 57A5 57A2 OUT MACHINE_ID0 1

R4900 2 10K_5%_2
57A3 57A2 R4892 1 2 10K_5%_2_DY
OUT MACHINE_ID1 57A5 57A2 OUT MACHINE_ID1 1
R4901 2 10K_5%_2
57A3 57A2 R4893 1 2 10K_5%_2_DY
R4902 2 10K_5%_2
57A3 57A2 R4894 1 2 10K_5%_2_DY
R4903 2 10K_5%_2
57A3 57A2 R4895 1 2 10K_5%_2_DY
OUT MACHINE_ID4
INVENTEC
57A5 57A2 1
R4904 2 10K_5%_2
57A3 57A2 OUT MACHINE_ID4 R4896 1 2 10K_5%_2_DY OUT MACHINE_ID5
57A5 57A2 1
R4905 2 10K_5%_2
57A3 57A2 OUT MACHINE_ID5 R4897 1 2 10K_5%_2_DY OUT MACHINE_ID6
57A5 57A2 1
R4906 2 10K_5%_2
57A3 57A2 OUT MACHINE_ID6 R4898 1 2 10K_5%_2_DY OUT MACHINE_ID1_DB
57A5 57A2 1
R4907 2 10K_5%_2
57A3 57A2 OUT MACHINE_ID1_DB R4899 1 2 10K_5%_2_DY OUT TITLE
NOTE:10K_5%(60130B1030ZT) NOTE:10K_5%(60130B1030ZT) Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
R4723 1 210K_5%_2_DY PCH_GPIO06 OUT 58D6

P3V3S
R4908 1 210K_5%_2_DY PCH_GPIO15 OUT 58C6
1 2 10K_5%_2_DY PCH_GPIO12 R4721

R4910 OUT 58C6 1 2
D
33K_5%_2
D
P3V3S U4700 P3V3S
MSATA_DET SATA_ODD_PWREN
30B7 T7 C40 32A8
IN BMBUSY#/GPIO0 TACH4/GPIO68 OUT
R4916 1 2 10K_5%_2_DY PCH_GPIO22
OUT 58C6 58C7 57C7 IN PCI_3S_REQ3# A42 TACH1/GPIO1 TACH5/GPIO69 B41 R4724 1 2 10K_5%_2_DY
R4917 1 2 10K_5%_2_DY PCH_GPIO38

OUT 58B6 58D7 IN PCH_GPIO06 H36 TACH2/GPIO6 TACH6/GPIO70 C41 R4725 1 2 10K_5%_2_DY
R4915 1 2 10K_5%_2_DY PCH_GPIO16

OUT 58C6 57C7 22E3 IN RUNSCI0#_3 E38 TACH3/GPIO7 TACH7/GPIO71 A40 R4726 1 2 10K_5%_2_DY
R4919 1 2 10K_5%_2 SATA_ODD_PRSNT#

OUT 32A5 58B6 57C7 OUT PCI_3S_REQ1# C10 GPIO8 INT. PU 20K
INT. PU 20K
R4722 1 2 10K_5%_2 DGPU_PWR_EN#

OUT 17A7 17B5 17B7 57B6 58D7 OUT PCH_GPIO12 C4 LAN_PHY_PWR_CTRL/GPIO12
R4909 1 2 10K_5%_2 DGPU_HOLD_RST#

OUT 57B6 62F5 58D7 OUT PCH_GPIO15 G2 GPIO15
INT. PD 20K
A20GATE P4 EC_3S_A20GATE
IN 22E2
STRAPPING
AU16 PCH_PECI 1 R4940 2 H_PECI

PECI OUT 22A6 47D5
58D7 OUT PCH_GPIO16 U2 SATA4GP/GPIO16 0_5%_2_DY
CPU/MISC
R4727 1 2 PCH_GPIO22 P5 KBRST#
GPIO
10K_5%_2_DY OUT 58C6 58D7 RCIN# IN 22D2
INT. PU 20K
15A4 13C5 IN DGPU_PG D40 TACH0/GPIO17 PROCPWRGD AY11 H_CPUPWRGD

OUT 47C5
58D7 58C7 OUT PCH_GPIO22 T5 SCLOCK/GPIO22 THRMTRIP# AY10 THRMTRIP#_R

C C
P1V05S P1V05S
21A2 OUT KBLED_ID E8 GPIO24 INIT3_3V# T14
1
R4928 1 2 10K_5%_2_DY E16 GPIO27 INT.PD 20K
1
STRAPPINGDF_TVS AY1
P3V3S 58A7 PLL_ODVR_EN STRAPPING
P8 R4942 R4944
OUT GPIO28 INT. PU 20K
TS_VSS1 AH8 56_5%_2 56_5%_2
R4929 1 2 10K_5%_2_DY K1 STP_PCI#/GPIO34
GFX_CRB_DET(GPIO39) AK11
2
TS_VSS2 R4941 R4943
2
R4930 1 2 10K_5%_2_DY K4 GPIO35 1 2 1 2 PM_THRMTRIP# IN 46A4
INTERNAL GFX :100K PD TS_VSS3 AH10 47D5
0_5%_2_DY
EXTERNAL GFX :10K PU R4932 1 2 10K_5%_2_DY V8 SATA2GP/GPIO36 390_5%_2
INT. PD 20K TS_VSS4 AK10
PCH_GPIO37
STRAPPING
M5 BOTH THESE SHOULD BE CLOSE TO PCH
P3V3S 58B7 OUT SATA3GP/GPIO37
NC_1 P37
58D7 OUT PCH_GPIO38 N2 SLOAD/GPIO38 NV_CLE
R4920 1 2 10K_5%_2_DY PCH_GPIO39
OUT 58B6 OUT 47D6
PCH_GPIO39
STRAPPING FOLLOW EDS1.0
R4926 1 2 100K_5%_2 58B7 OUT M3 SDATAOUT0/GPIO39
TP24 STRAPPING
1 V13 SDATAOUT1/GPIO48 VSS_NCTF_15 BG2
TP4907
58D7 32A5 OUT SATA_ODD_PRSNT# V3 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16 BG48
B B
29C7 29B7 BI BTIFON# D6 GPIO57 VSS_NCTF_17 BH3
FDI_OVRVLTG(GPIO37) VSS_NCTF_18 BH47
LOW- TX,RXTERMINATED TO SAME VOLTAGE A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

(DC COUPLING MODE) DEFAULT A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
P3V3S A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
NCTF
R4934 1 2 1K_5%_2_DY PCH_GPIO37 58B6 A46 BJ46
OUT VSS_NCTF_4 VSS_NCTF_22
R4935 1 2 100K_5%_2
A5 BJ5
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6
B3 VSS_NCTF_7 VSS_NCTF_25 C2
B47 VSS_NCTF_8 VSS_NCTF_26 C48
BD1 VSS_NCTF_9 VSS_NCTF_27 D1

PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28)
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
A HIGH-ENABLED (DEFAULT) A
LOW-DISABLED BE1 VSS_NCTF_11 VSS_NCTF_29 E1
P3V3A BE49 VSS_NCTF_12 VSS_NCTF_30 E49
BF1 VSS_NCTF_13 VSS_NCTF_31 F1

1 R4950 2 PLL_ODVR_EN
IN 58C6 BF49 F49
10K_5%_2
R4936 ITL_PANTHERPOINT_FCBGA_989P
1 2
10K_5%_2_DY INVENTEC
STRAP TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S P3V3S
1.3A U4700 L4700
AA23 U48 15MIL P3V3S_VCCADAC 1 2
VCCCORE[1]
POWER VCCADAC
1
1
1
AC23 VCCCORE[2] FBM_11_160808_121T
P3V3S C4784
CRT
AD21 VCCCORE[3] C4782 C4783
1
AD23 U47
VCC CORE
VCCCORE[4] VSSADAC
C4772 C4773 C4774 C4775
1
AF21 VCCCORE[5] 0.1UF_16V_2
AF23 10UF_6.3V_3 0.01UF_50V_2
VCCCORE[6]
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
D 10UF_6.3V_3 AG21
2
VCCCORE[7] R4717
AG23 VCCCORE[8]
15MIL 0_5%_2_DY D
2
AG24 VCCCORE[9] VCCALVDS AK36
AG26 R4713
2
VCCCORE[10]
1 2
AG27 VCCCORE[11] VSSALVDS AK37 P1V8S
AG29 VCCCORE[12]
AJ23 0_5%_2
LVDS
L4701
AJ26
VCCCORE[13]
VCCCORE[14] VCCTX_LVDS[1] AM37 15MIL P1V8S_VCCTX_LVDS 1 2
1
AJ27 VCCCORE[15]
1
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 BLM11A121S_200MA_DY
0_5%_2
AJ31 C4786 C4787
VCCCORE[17]
L4701 STUFF PN:
R4714
AP36 C4785
P1V05S VCCTX_LVDS[3]
22UF_6.3V_5_DY
0.01UF_50V_2_DY 0.01UF_50V_2_DY 60140EA0319T
AP37
2
20MIL VCCTX_LVDS[4]
2
P1V05S AN19 VCCIO[28]
R4945
P1V05S 1 2 P1V05S_VCCAPLLEXP BJ22 P3V3S
HVCMOS
VCCAPLLEXP
15MIL
0_5%_2_DY V33
3A AN16 VCCIO[15]
VCC3_3[6]
C4788
1 2
AN17 VCCIO[16]
VCC3_3[7] V34
1
1
C 0.1UF_16V_2 C
C4777 C4778 C4779 C4780
C4776
AN21 VCCIO[17]
10UF_6.3V_3 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 P1V5S_VCCAFDI_VRM
AN26 VCCIO[18]
2
VCCVRM[3] AT16 15MIL

AN27 P1V05S
VCCIO
VCCIO[19]
AP21
DMI
VCCIO[20]
VCCDMI[1] AT20 15MIL
AP23 VCCIO[21] P1V05S C4789
1 2
AP24 VCCIO[22]
VCCCLKDMI AB36 15MIL 1UF_6.3V_2
P3V3S AP26 VCCIO[23]
C4790
1 2
AT24 VCCIO[24]
1UF_6.3V_2_DY P1V8S
1
AN33 VCCIO[25]
VCCDFTERM[1] AG16 15MIL
C4781 AN34 VCCIO[26]
B B
1
0.1UF_16V_2 15MIL BH29 VCC3_3[3] VCCDFTERM[2] AG17 C4791
2
P1V5S_VCCAFDI_VRM
NAND / SPI
AJ16 0.1UF_16V_2
VCCDFTERM[3] P3V3A
2
15MIL AP16 VCCVRM[2]
P1V05S VCCDFTERM[4] AJ17
R4946
1 2 P1V05S_VCCAFDIPLL BG6 VccAFDIPLL
P1V05S
FDI
0_5%_2_DY
P1V05S 20MIL AP17 VCCIO[27]
VCCSPI V1 15MIL
1
15MIL AU20 VCCDMI[2]
C4792
ITL_PANTHERPOINT_FCBGA_989P
1UF_6.3V_2
2
A A
P1V5S_VCCAFDI_VRM P1V5S
R4949
1 2
40MIL 0_5%_3
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S P1V05S
P3V3A R4865 2 P1V05S_VCCACLK AD49
U4700
3A REFERENCE 4700~4949(PCH)
1 N26
P3V3S 15MIL VCCACLK
POWER VCCIO[29]
1
0_5%_2_DY
C4803 VCCIO[30] P26
2 1 1 R4866 2 T16 C4829
VCCDSW3_3
0_5%_2 VCCIO[31] P28 1UF_6.3V_2
1
0.1UF_16V_2
C4804
2 1 V12 T27
2
C4801 C4802 DCPSUSBYP VCCIO[32]
P3V3A
2
0.1UF_16V_2 10UF_6.3V_3 0.1UF_16V_2_DY T29
VCCIO[33] P3V3A
20MIL T38 VCC3_3[5]
NC
2
2
P1V05S 10MIL D4708
3 BAT54_30V_0.2A
1
VCCSUS3_3[7] T23
P1V05S 1 R4867 2 P1V05S_VCCAPLLDMI2 BH23 VCCAPLLDMI2
C4830 P5V0A
USB
0_5%_2_DY VCCSUS3_3[8] T24
1 2
20MIL AL29 VCCIO[14]
VCCSUS3_3[9] V23 0.1UF_16V_2
D R4869 1 2 10_5%_5
C4805
1 2 AL24 DCPSUS[3] VCCSUS3_3[10] V24 P3V3A D
P1V05S 1UF_6.3V_2_DY
VCCSUS3_3[6] P24 10MIL
Clock and Miscellaneous

C4833 1 2 0.1UF_16V_2
C4831
1.1A AA19 VCCASW[1]
1 2 P1V05S
AA21 VCCASW[2] VCCIO[34] T26 20MIL 0.1UF_16V_2
2
C4806 C4807 AA24 VCCASW[3] V5REF_SUS M26 V5REF_SUS 10MIL P3V3S
NC
22UF_6.3V_5 22UF_6.3V_5 AA26 D4709 3 1 BAT54_30V_0.2A
VCCASW[4] C4832
DCPSUS[4] AN23 2 1 P3V3A
2
AA27 VCCASW[5]
P5V0S
P1V05S VCCSUS3_3[1] AN24 10MIL 1UF_6.3V_2_DY
AA29 VCCASW[6] R4870 1 2 10_5%_5
AA31 VCCASW[7]
C4834
10MIL
1
1
AC26 VCCASW[8] V5REF P34 V5REF 1 2
C4808 C4809 C4810
AC27 VCCASW[9] P3V3A 1UF_6.3V_2
PCI/GPIO/LPC
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 VCCSUS3_3[2] N20
C AC29 VCCASW[10]
10MIL C
2
2 VCCSUS3_3[3] N22
AC31 VCCASW[11] C4835
VCCSUS3_3[4] P20 1 2
AD29 VCCASW[12]
P1V05S VCCSUS3_3[5] P22 1UF_6.3V_2
AD31 VCCASW[13] P3V3S
L4706
1 2 P1V05S_VCCADPLLA W21 VCCASW[14] VCC3_3[1] AA16 20MIL
1
FBM_11_160808_121T W23 VCCASW[15] VCC3_3[8] W16 C4836 1 2 0.1UF_16V_2 P3V3S

C4812 C4813 C4814
W24 VCCASW[16] VCC3_3[4] T34
22UF_6.3V_5_DY 1UF_6.3V_2 10UF_6.3V_3 C4837 1 2 0.1UF_16V_2
W26 VCCASW[17]
1
2
C4811 W29 VCCASW[18] P3V3S

0.1UF_16V_2 W31 VCCASW[19]
VCC3_3[2] AJ2 20MIL
2
L4707 W33
1 2 P1V05S_VCCADPLLB VCCASW[20]
C4838 1 2 0.1UF_16V_2
VCCIO[5] AF13
1
B FBM_11_160808_121T P1V05S B
P1V5S_VCCAFDI_VRM N16 DCPRTC
C4815 C4816 C4817
VCCIO[12] AH13 20MIL
C4839
22UF_6.3V_5_DY 1UF_6.3V_2 10UF_6.3V_3 15MIL Y49
SATA
VCCVRM[4] VCCIO[13] AH14 1 2
2
1UF_6.3V_2
VCCIO[6] AF14 P1V05S

15MIL BD47 VCCADPLLA L4708
VCCAPLLSATA AK1 P1V05S_VCCAPLLSATA 1 2 P1V5S_VCCAFDI_VRM
15MIL BF47 VCCADPLLB
P1V05S 0603_DY
VCCVRM[1] AF11 10MIL
20MIL AF17 VCCIO[7]
C4818 1UF_6.3V_2 AF33 VCCDIFFCLKN[1]
P1V05S
2 1 15MIL AF34 VCCDIFFCLKN[2] VCCIO[2] AC16
AG34 VCCDIFFCLKN[3]
C4819 1UF_6.3V_2
2 1 VCCIO[3] AC17 20MIL
C4840
15MIL AG33 VCCSSC VCCIO[4] AD17 1 2
C4820 1UF_6.3V_2
1UF_6.3V_2
2 1
C4821 0.1UF_16V_2 V16 DCPSST
2 1
MISC
A T17 T21 A
C4822 DCPSUS[1] VCCASW[22] P1V05S
P1V05S 1 2 V19 DCPSUS[2]
1UF_6.3V_2_DY
VCCASW[23] V21 20MIL
RTC CPU
10MIL BJ8 V_PROC_IO

1
VCCASW[21] T19
P3V3_RTC P3V3A
C4823 C4824 C4825
INVENTEC
HDA
4.7UF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2 A22 VCCRTC VCCSUSHDA P32 10MIL

1
1
2
C4841
C4826 C4827 C4828 ITL_PANTHERPOINT_FCBGA_989P
TITLE
0.1UF_16V_2 1UF_6.3V_2 0.1UF_16V_2 0.1UF_16V_2 MODEL,PROJECT,FUNCTION
Block Diagram
2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) U4700

AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
U4700 AY46 K26
VSS[161] VSS[261]
H5 VSS[0]
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
AA17 VSS[1] VSS[80] AK38
B15 VSS[164] VSS[264] K7
B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
B27 VSS[167] VSS[267] L20
B31 VSS[168] VSS[268] L26
AB11 VSS[6] VSS[85] AL16
B35 VSS[169] VSS[269] L28
B39 VSS[170] VSS[270] L36
B7 VSS[171] VSS[271] L48
F45 VSS[172] VSS[272] M12
BB12 VSS[173] VSS[273] P16
D AB5 VSS[11] VSS[90] AL23
BB16 VSS[174] VSS[274] M18
BB20 VSS[175] VSS[275] M22 D
AC19 VSS[13] VSS[92] AL27
BB22 VSS[176] VSS[276] M24
BB24 VSS[177] VSS[277] M30
BB28 VSS[178] VSS[278] M32
BB30 VSS[179] VSS[279] M34
BB38 VSS[180] VSS[280] M38
AC34 VSS[18] VSS[97] AM11
BB4 VSS[181] VSS[281] M4
AC48 VSS[19] VSS[98] AM14
BB46 VSS[182] VSS[282] M42
AD10 VSS[20] VSS[99] AM36
BC14 VSS[183] VSS[283] M46
AD11 VSS[21] VSS[100] AM39
BC18 VSS[184] VSS[284] M8
AD12 VSS[22] VSS[101] AM43
BC2 VSS[185] VSS[285] N18
AD13 VSS[23] VSS[102] AM45
BC22 VSS[186] VSS[286] P30
AD19 VSS[24] VSS[103] AM46
BC26 VSS[187] VSS[287] N47
AD24 VSS[25] VSS[104] AM7
BC32 VSS[188] VSS[288] P11
AD26 VSS[26] VSS[105] AN2
BC34 VSS[189] VSS[289] P18
AD27 VSS[27] VSS[106] AN29
BC36 VSS[190] VSS[290] T33
AD33 VSS[28] VSS[107] AN3
BC40 VSS[191] VSS[291] P40
AD34 VSS[29] VSS[108] AN31
BC42 VSS[192] VSS[292] P43
AD36 VSS[30] VSS[109] AP12
BC48 VSS[193] VSS[293] P47
AD37 VSS[31] VSS[110] AP19
BD46 VSS[194] VSS[294] P7
AD38 VSS[32] VSS[111] AP28
BD5 VSS[195] VSS[295] R2
AD39 VSS[33] VSS[112] AP30
BE22 VSS[196] VSS[296] R48
AD4 VSS[34] VSS[113] AP32
C AD40 VSS[35] VSS[114] AP38
BE26 VSS[197] VSS[297] T12 C
BE40 VSS[198] VSS[298] T31
BF10 VSS[199] VSS[299] T37
AD43 VSS[37] VSS[116] AP42
BF12 VSS[200] VSS[300] T4
AD45 VSS[38] VSS[117] AP46
BF16 VSS[201] VSS[301] W34
BF20 VSS[202] VSS[302] T46
AD8 VSS[40] VSS[119] AR2
BF22 VSS[203] VSS[303] T47
AE2 VSS[41] VSS[120] AR48
BF24 VSS[204] VSS[304] T8
AE3 VSS[42] VSS[121] AT11
BF26 VSS[205] VSS[305] V11
AF10 VSS[43] VSS[122] AT13
BF28 VSS[206] VSS[306] V17
AF12 VSS[44] VSS[123] AT18
BD3 VSS[207] VSS[307] V26
AD14 VSS[45] VSS[124] AT22
BF30 VSS[208] VSS[308] V27
AD16 VSS[46] VSS[125] AT26
BF38 VSS[209] VSS[309] V29
AF16 VSS[47] VSS[126] AT28
BF40 VSS[210] VSS[310] V31
AF19 VSS[48] VSS[127] AT30
BF8 VSS[211] VSS[311] V36
AF24 VSS[49] VSS[128] AT32
BG17 VSS[212] VSS[312] V39
AF26 VSS[50] VSS[129] AT34
BG21 VSS[213] VSS[313] V43
AF27 VSS[51] VSS[130] AT39
BG33 VSS[214] VSS[314] V7
AF29 VSS[52] VSS[131] AT42
BG44 VSS[215] VSS[315] W17
AF31 VSS[53] VSS[132] AT46
BG8 VSS[216] VSS[316] W19
AF38 VSS[54] VSS[133] AT7
BH11 VSS[217] VSS[317] W2
AF4 VSS[55] VSS[134] AU24
BH15 VSS[218] VSS[318] W27
AF42 VSS[56] VSS[135] AU30
BH17 VSS[219] VSS[319] W48
B AF46 VSS[57] VSS[136] AV16
BH19 VSS[220] VSS[320] Y12 B
AF5 VSS[58] VSS[137] AV20
H10 VSS[221] VSS[321] Y38
BH27 VSS[222] VSS[322] Y4
BH31 VSS[223] VSS[323] Y42
AG19 VSS[61] VSS[140] AV38
BH33 VSS[224] VSS[324] Y46
AG2 VSS[62] VSS[141] AV4
BH35 VSS[225] VSS[325] Y8
AG31 VSS[63] VSS[142] AV43
BH39 VSS[226] VSS[328] BG29
AG48 VSS[64] VSS[143] AV8
BH43 VSS[227] VSS[329] N24
AH11 VSS[65] VSS[144] AW14
BH7 VSS[228] VSS[330] AJ3
AH3 VSS[66] VSS[145] AW18
D3 VSS[229] VSS[331] AD47
D12 VSS[230] VSS[333] B43
AH39 VSS[68] VSS[147] AW22
D16 VSS[231] VSS[334] BE10
AH40 VSS[69] VSS[148] AW26
D18 VSS[232] VSS[335] BG41
AH42 VSS[70] VSS[149] AW28
D22 VSS[233] VSS[337] G14
AH46 VSS[71] VSS[150] AW32
D24 VSS[234] VSS[338] H16
D26 VSS[235] VSS[340] T36
AJ19 VSS[73] VSS[152] AW36
D30 VSS[236] VSS[342] BG22
AJ21 VSS[74] VSS[153] AW40
D32 VSS[237] VSS[343] BG24
AJ24 VSS[75] VSS[154] AW48
D34 VSS[238] VSS[344] C22
AJ33 VSS[76] VSS[155] AV11
D38 VSS[239] VSS[345] AP13
AJ34 VSS[77] VSS[156] AY12
D42 VSS[240] VSS[346] M14
AK12 VSS[78] VSS[157] AY22
D8 VSS[241] VSS[347] AP3
AK3 VSS[79] VSS[158] AY28
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
A ITL_PANTHERPOINT_FCBGA_989P G18 VSS[244] VSS[350] BC16 A
G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
INVENTEC
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257] TITLE
F3 VSS[258] MODEL,PROJECT,FUNCTION
Block Diagram
ITL_PANTHERPOINT_FCBGA_989P DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S_DGPU
5
U5012
BUF_PLT_RST# 1
+
57A8 40A1 36C3 30C3 29C7 29C3 22E3 IN 4
F 58C7 57B6 IN DGPU_HOLD_RST# 2 F
1
-
TC7SZ08FU
1
R5071
3
R5070 100K_5%_2
100K_5%_2
+1.05V POWER RAIL SHOULD HAVE 3500MA CAPABILITY AT LEAST
2
U5000
2
U5000 1/19 PCI_EXPRESS
18/19 NC/VDD33
P3V3S_DGPU P1V05S_DGPU
AJ11 PEX_WAKE*
AC6 NC_1 VDD33_1 J8
1
AG19
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
PEX_IOVDD_1
1
AJ28 K8
4.7UF_6.3V_3
1UF_6.3V_2
NC_2 VDD33_2
DGPU_RST#
1
AJ12 PEX_RST* PEX_IOVDD_2 AG21
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5146
C5145
C5144
C5143
C5014
AJ4 L8
4.7UF_6.3V_3
4.7UF_6.3V_3
NC_3 VDD33_3
C5071
C5010
PEX_IOVDD_3 AG22
C5001
C5005
C5006
C5003
AJ5 M8
NC_4 VDD33_4
CLKREQ_GPU#
C5000
54C3 AK12 AG24
AL11 NC_5 OUT PEX_CLKREQ* PEX_IOVDD_4
AH21
C15 PEX_IOVDD_5
NC_6
CLK_PEG_PCH_DP
CLOSE TO GPU AL13 AH25
2
D19 54C3 IN PEX_REFCLK PEX_IOVDD_6
2
NC_7
CLK_PEG_PCH_DN AK13
2
D20 54C3 IN PEX_REFCLK*
NC_8
D23 C5021
NC_9
48C4 OUT PEG_C_RX0_DP 1 2C5022 PEG_RX0_DP AK14 PEX_TX0
D26 NC_10
48C4 OUT PEG_C_RX0_DN 1 2 PEG_RX0_DN AJ14 PEX_TX0* 3300MA
H31 NC_11
T8 0.22UF_6.3V_2
NC_12
48B1 IN PEG_C_TX0_DP 0.22UF_6.3V_2 AN12 PEX_RX0
V32 NC_13
48D1 IN PEG_C_TX0_DN AM12 PEX_RX0* PEX_IOVDDQ_1 AG13
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
1
1
C5023 PEX_IOVDDQ_2 AG15
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
PEG_C_RX1_DP PEG_RX1_DP AH14
C5099
C5098
C5097
C5008
C5007
C5004
48C4 1 2 C5024 AG16
OUT PEG_C_RX1_DN 1 2 PEG_RX1_DN AG14
PEX_TX1 PEX_IOVDDQ_3
AG18
NVIDIA_N13P_GLP_A1_BGA_908P 48C4 OUT PEX_TX1* PEX_IOVDDQ_4
0.22UF_6.3V_2 PEX_IOVDDQ_5 AG25
E 48B1 PEG_C_TX1_DP 0.22UF_6.3V_2 AN14 AH15 E
IN PEG_C_TX1_DN AM14
PEX_RX1 PEX_IOVDDQ_6
AH18
2
48D1 IN PEX_RX1* PEX_IOVDDQ_7
C5025 PEX_IOVDDQ_8 AH26
48C4 OUT PEG_C_RX2_DP 1 2 C5026 PEG_RX2_DP AK15 PEX_TX2 PEX_IOVDDQ_9 AH27
48D4 OUT PEG_C_RX2_DN 1 2 PEG_RX2_DN AJ15 PEX_TX2* PEX_IOVDDQ_10 AJ27
0.22UF_6.3V_2 PEX_IOVDDQ_11 AK27
48B1 IN PEG_C_TX2_DP 0.22UF_6.3V_2 AP14 PEX_RX2 PEX_IOVDDQ_12 AL27
48D1 IN PEG_C_TX2_DN AP15 PEX_RX2* PEX_IOVDDQ_13 AM28
C5027 PEX_IOVDDQ_14 AN28
48C4 OUT PEG_C_RX3_DP 1 2 C5028 PEG_RX3_DP AL16 PEX_TX3
48D4 OUT PEG_C_RX3_DN 1 2 PEG_RX3_DN AK16 PEX_TX3*
0.22UF_6.3V_2
48C1 IN PEG_C_TX3_DN AM15 PEX_RX3*
C5029
48C4 OUT PEG_C_RX4_DP 1 2 C5030 PEG_RX4_DP AK17 PEX_TX4
48D4 OUT PEG_C_RX4_DN 1 2 PEG_RX4_DN AJ17 PEX_TX4*
0.22UF_6.3V_2
C5031
48C4 OUT PEG_C_RX5_DP 1 2 C5032 PEG_RX5_DP AH17 PEX_TX5 P3V3S_DGPU
48D4 OUT PEG_C_RX5_DN 1 2 PEG_RX5_DN AG17 PEX_TX5* 210MA
0.22UF_6.3V_2 PEX_PLL_HVDD AH12
PEG_C_TX5_DP
1
48B1 0.22UF_6.3V_2 AP17
IN PEG_C_TX5_DN AP18
PEX_RX5
AG12
48C1 IN PEX_RX5* PEX_SVDD_3V3 C5012 C5020
C5033
D 48C4 PEG_C_RX6_DP 1 2 C5034 PEG_RX6_DP AK18 D
OUT PEX_TX6
0.1UF_16V_2 4.7UF_6.3V_3
0.22UF_6.3V_2
2
C5035
48C4 PEG_C_RX7_DP 1 2 C5036 PEG_RX7_DP AL19 PVCORE_DGPU
OUT PEG_C_RX7_DN 1 2 PEG_RX7_DN AK19
PEX_TX7
48D4 OUT PEX_TX7*
1
0.22UF_6.3V_2
PEG_C_TX7_DN AM20 R5008
48C1 IN PEX_RX7*
C5037 100_1%_2_DY
PEG_C_RX8_DN 1 2 PEG_RX8_DN AJ20
2
48D4 OUT PEX_TX8*
0.22UF_6.3V_2 VDD_SENSE L4 PVCORE_DGPU_SENSE OUT 13A8
48B1 IN PEG_C_TX8_DP 0.22UF_6.3V_2 AP20 PEX_RX8
48C1 IN PEG_C_TX8_DN AP21 PEX_RX8*
C5039 GND_SENSE L5 PVCORE_DGPU_VSS OUT 13A8
48C4 OUT PEG_C_RX9_DP 1 2 C5040 PEG_RX9_DP AH20 PEX_TX9
48D4 OUT PEG_C_RX9_DN 1 2 PEG_RX9_DN AG20 PEX_TX9*
1
0.22UF_6.3V_2
48B1 IN PEG_C_TX9_DP 0.22UF_6.3V_2 AN21 PEX_RX9 R5001
100_1%_2_DY
C5041
2
0.22UF_6.3V_2 3V3AUX_NC P8
C 48A1 PEG_C_TX10_DP 0.22UF_6.3V_2 AN23 C
PEX_RX10
48C1 IN PEX_RX10*
C5043
48C4 OUT PEG_C_RX11_DP 1 2 C5044 PEG_RX11_DP AL22 PEX_TX11
48D4 OUT PEG_C_RX11_DN 1 2 PEG_RX11_DN AK22 PEX_TX11*
0.22UF_6.3V_2
48A1 IN PEG_C_TX11_DP 0.22UF_6.3V_2 AP23 PEX_RX11
48C1 IN PEG_C_TX11_DN AP24 PEX_RX11*
1
AJ26 R5005 2
C5045 PEX_TSTCLK_OUT
48C4 OUT PEG_C_RX12_DP 1 2 C5046 PEG_RX12_DP AK23 PEX_TX12 PEX_TSTCLK_OUT* AK26
48D4 OUT PEG_C_RX12_DN 1 2 PEG_RX12_DN AJ23 PEX_TX12* 200_1%_2
0.22UF_6.3V_2
48A1 IN PEG_C_TX12_DP 0.22UF_6.3V_2 AN24 PEX_RX12
C5047 P1V05S_DGPU
48C4 PEG_C_RX13_DP 1 2 C5048 PEG_RX13_DP AH23 150MA
OUT PEG_C_RX13_DN 1 2 PEG_RX13_DN AG23
PEX_TX13
AG26 P1V05S_GPU_PEX_PLLVDD 1 L5000 2
48D4 OUT PEX_TX13* PEX_PLLVDD
1
0.22UF_6.3V_2 BLM18PG181SN1D
48A1 IN PEG_C_TX13_DP 0.22UF_6.3V_2 AN26 PEX_RX13 C5015 C5016 C5017
C5049
PEG_C_RX14_DP 1 2 C5050 PEG_RX14_DP AK24 0.1UF_16V_2 1UF_6.3V_2 4.7UF_6.3V_3
48C4 OUT PEX_TX14
PEG_C_RX14_DN 1 2 PEG_RX14_DN AJ24 1AK11 R5004 2
2
48D4 OUT PEX_TX14* TESTMODE
0.22UF_6.3V_2 10K_5%_2
P1V05S_DGPU 48A1 IN PEG_C_TX14_DP 0.22UF_6.3V_2 AP26 PEX_RX14
48B1 IN PEG_C_TX14_DN AP27 PEX_RX14*
C5051
B L5001 P1V05S_GPU_SP_PLLVDD 48C4 PEG_C_RX15_DP 1 2 C5052 PEG_RX15_DP AL25 B
1 2 OUT PEG_C_RX15_DN PEG_RX15_DN AK25
PEX_TX15
1
48D4 1 2
BLM15AG221SN1D_300MA OUT PEX_TX15*
C5053 C5054 0.22UF_6.3V_2
48A1 PEG_C_TX15_DP 0.22UF_6.3V_2 AN27 1AP29 R5003 2
PEX_RX15 PEX_TERMP
22UF_6.3V_5 48B1 IN PEX_RX15* 2.49K_1%_2
0.1UF_16V_2 U5000
12/19 XTAL_PLL
2
NVIDIA_N13P_GLP_A1_BGA_908P
AD8 PLLVDD 60MA

AE8 SP_PLLVDD 45MA
L5002
1 2 P1V05S_GPU_VID_PLLVDD AD7 VID_PLLVDD 45MA NC
1
1
0.1UF_16V_2
4.7UF_6.3V_3
22UF_6.3V_5
BLM15AG221SN1D_300MA
C5147
0.1UF_16V_2
C5104
C5055
C5056
GF108/GKx GF117
R5006 R5007
2
1 2H1 XTAL_SSIN XTAL_OUTBUFF J4 1 2

10K_5%_2
10K_5%_2
H3 XTAL_IN XTAL_OUT H2
X5000
1 3
1
A A
1
4 2
12PF_50V_2
C5078
27MHZ_12PF
C5079
12PF_50V_2 INVENTEC
2
TITLE
2
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FB_CLAMP
N13P-PES/GL/GLP : NC
N13P-GV;N13M-GS;N13P-GT-GS-LP: PL10K
U5000
U5000 3/19 FBB
2/19 FBA
FBC_D<63..0>
FBA_D<63..0> FBA_D<0> 70F5 70F1 70E5 70E1 69F5 69F1 69E5 69E1 BI 0 FBC_D<0> G9 FBB_D0
68E1 67F6 67F1 67E6 67E1 0 L28 E1
F 68F6 68F1 68E5
BI FBA_D<1> M29
FBA_D0 FB_CLAMP
1 FBC_D<1> E9 FBB_D1 F
1 FBA_D1
FBC_D<2>
2 G8 FBB_D2
I68 2 FBA_D<2> L29 FBA_D2
3 FBC_D<3> F9 FBB_D3
3 FBA_D<3> M28 FBA_D3
4 FBC_D<4> F11 FBB_D4
4 FBA_D<4> N31 FBA_D4 R5029 5 FBC_D<5> G11
5 FBA_D<5> P29 35MA K27 FBB_PLL_AVDD 1 2 P1V05S_GPU_FBA_PLLAVDD 63B1
FBB_D5
FBA_D5 FB_DLL_AVDD IN FBC_D<6>
1
6 F12 FBB_D6
6 FBA_D<6> R29 FBA_D6
C5013 7 FBC_D<7> G12 FBB_D7
7 FBA_D<7> P28 FBA_D7 0_5%_3 8 FBC_D<8> G6 FBB_D8
8 FBA_D<8> J28 FBA_D8
0.1UF_16V_2 9 FBC_D<9> F5 FBB_D9
9 FBA_D<9> H29 FBA_D9
10 FBC_D<10> E6 FBB_D10
10 FBA_D<10> J29 FBA_D10
11 FBC_D<11> F6
2
FBB_D11
11 FBA_D<11> H28 FBA_D11
12 FBC_D<12> F4 FBB_D12
12 FBA_D<12> G29 FBA_D12
13 FBC_D<13> G4 FBB_D13
13 FBA_D<13> E31 FBA_D13
14 FBC_D<14> E2 FBB_D14
14 FBA_D<14> E32 FBA_D14
15 FBC_D<15> F3 FBB_D15
15 FBA_D<15> F30 FBA_D15
16 FBC_D<16> C2 FBB_D16
16 FBA_D<16> C34 FBA_D16
17 FBC_D<17> D4 FBB_D17
17 FBA_D<17> D32 FBA_D17
18 FBC_D<18> D3 FBB_D18
18 FBA_D<18> B33 FBA_D18
19 FBC_D<19> C1 FBB_D19
19 FBA_D<19> C33 FBA_D19
20 FBC_D<20> B3 FBB_D20
20 FBA_D<20> F33 FBA_D20
21 FBC_D<21> C4 FBB_D21
21 FBA_D<21> F32 FBA_D21
22 FBC_D<22> B5 FBB_D22
22 FBA_D<22> H33 FBA_D22
23 FBC_D<23> C5 FBB_D23
23 FBA_D<23> H32 FBA_D23
24 FBC_D<24> A11 FBB_D24
24 FBA_D<24> P34 FBA_D24
25 FBC_D<25> C11 FBB_D25
25 FBA_D<25> P32 FBA_D25
26 FBC_D<26> D11 FBB_D26
26 FBA_D<26> P31 FBA_D26
27 FBC_D<27> B11 FBB_D27
27 FBA_D<27> P33 FBA_D27
28 FBC_D<28> D8 FBB_D28
28 FBA_D<28> L31 FBA_D28
29 FBC_D<29> A8 FBB_D29
29 FBA_D<29> L34 FBA_D29
E 30 FBC_D<30> C8 FBB_D30 E
30 FBA_D<30> L32 FBA_D30
31 FBC_D<31> B8 FBB_D31
31 FBA_D<31> L33 FBA_D31
32 FBC_D<32> F24 FBB_D32
32 FBA_D<32> AG28 FBA_D32 70F4 70F8
33 FBC_D<33> G23 D13 FBC_CMD<0> 0 FBC_CMD<30..0> 63A3 63B3
33 FBA_D<33> AF29 FBA_D33 FBA_CMD0 U30 FBA_CMD<0> 0 FBA_CMD<30..0>
OUT 63A7 63B7 67F3 67F8 68F3 68F8 FBC_D<34> E24
FBB_D33 FBB_CMD0
E14
OUT 69F4 69F8
34 FBB_D34 FBB_CMD1 FBC_CMD<1> 1
34 FBA_D<34> AG29 FBA_D34 FBA_CMD1 T31 FBA_CMD<1> 1
35 FBC_D<35> G24 FBB_D35 FBB_CMD2 F14 FBC_CMD<2> 2
35 FBA_D<35> AF28 FBA_D35 FBA_CMD2 U29 FBA_CMD<2> 2
36 FBC_D<36> D21 FBB_D36 FBB_CMD3 A12 FBC_CMD<3> 3
36 FBA_D<36> AD30 FBA_D36 FBA_CMD3 R34 FBA_CMD<3> 3
37 FBC_D<37> E21 FBB_D37 FBB_CMD4 B12 FBC_CMD<4> 4
37 FBA_D<37> AD29 FBA_D37 FBA_CMD4 R33 FBA_CMD<4> 4
38 FBC_D<38> G21 FBB_D38 FBB_CMD5 C14 FBC_CMD<5> 5
38 FBA_D<38> AC29 FBA_D38 FBA_CMD5 U32 FBA_CMD<5> 5
39 FBC_D<39> F21 FBB_D39 FBB_CMD6 B14 FBC_CMD<6> 6
39 FBA_D<39> AD28 FBA_D39 FBA_CMD6 U33 FBA_CMD<6> 6
40 FBC_D<40> G27 FBB_D40 FBB_CMD7 G15 FBC_CMD<7> 7
40 FBA_D<40> AJ29 FBA_D40 FBA_CMD7 U28 FBA_CMD<7> 7
41 FBC_D<41> D27 FBB_D41 FBB_CMD8 F15 FBC_CMD<8> 8
41 FBA_D<41> AK29 FBA_D41 FBA_CMD8 V28 FBA_CMD<8> 8
42 FBC_D<42> G26 FBB_D42 FBB_CMD9 E15 FBC_CMD<9> 9
42 FBA_D<42> AJ30 FBA_D42 FBA_CMD9 V29 FBA_CMD<9> 9
43 FBC_D<43> E27 FBB_D43 FBB_CMD10 D15 FBC_CMD<10> 10
43 FBA_D<43> AK28 FBA_D43 FBA_CMD10 V30 FBA_CMD<10> 10
44 FBC_D<44> E29 FBB_D44 FBB_CMD11 A14 FBC_CMD<11> 11
44 FBA_D<44> AM29 FBA_D44 FBA_CMD11 U34 FBA_CMD<11> 11
45 FBC_D<45> F29 FBB_D45 FBB_CMD12 D14 FBC_CMD<12> 12
45 FBA_D<45> AM31 FBA_D45 FBA_CMD12 U31 FBA_CMD<12> 12
46 FBC_D<46> E30 FBB_D46 FBB_CMD13 A15 FBC_CMD<13> 13
46 FBA_D<46> AN29 FBA_D46 FBA_CMD13 V34 FBA_CMD<13> 13
47 FBC_D<47> D30 FBB_D47 FBB_CMD14 B15 FBC_CMD<14> 14
47 FBA_D<47> AM30 FBA_D47 FBA_CMD14 V33 FBA_CMD<14> 14
48 FBC_D<48> A32 FBB_D48 FBB_CMD15 C17 FBC_CMD<15> 15
48 FBA_D<48> AN31 FBA_D48 FBA_CMD15 Y32 FBA_CMD<15> 15
49 FBC_D<49> C31 FBB_D49 FBB_CMD16 D18 FBC_CMD<16> 16
49 FBA_D<49> AN32 FBA_D49 FBA_CMD16 AA31 FBA_CMD<16> 16
50 FBC_D<50> C32 FBB_D50 FBB_CMD17 E18 FBC_CMD<17> 17
50 FBA_D<50> AP30 FBA_D50 FBA_CMD17 AA29 FBA_CMD<17> 17
51 FBC_D<51> B32 FBB_D51 FBB_CMD18 F18 FBC_CMD<18> 18
51 FBA_D<51> AP32 FBA_D51 FBA_CMD18 AA28 FBA_CMD<18> 18
52 FBC_D<52> D29 FBB_D52 FBB_CMD19 A20 FBC_CMD<19> 19
52 FBA_D<52> AM33 FBA_D52 FBA_CMD19 AC34 FBA_CMD<19> 19
53 FBC_D<53> A29 FBB_D53 FBB_CMD20 B20 FBC_CMD<20> 20
53 FBA_D<53> AL31 FBA_D53 FBA_CMD20 AC33 FBA_CMD<20> 20
54 FBC_D<54> C29 FBB_D54 FBB_CMD21 C18 FBC_CMD<21> 21
54 FBA_D<54> AK33 FBA_D54 FBA_CMD21 AA32 FBA_CMD<21> 21
55 FBC_D<55> B29 FBB_D55 FBB_CMD22 B18 FBC_CMD<22> 22
55 FBA_D<55> AK32 FBA_D55 FBA_CMD22 AA33 FBA_CMD<22> 22
56 FBC_D<56> B21 FBB_D56 FBB_CMD23 G18 FBC_CMD<23> 23
56 FBA_D<56> AD34 FBA_D56 FBA_CMD23 Y28 FBA_CMD<23> 23
D 57 FBC_D<57> C23 FBB_D57 FBB_CMD24 G17 FBC_CMD<24> 24 D
58 FBC_D<58> A21 FBB_D58 FBB_CMD25 F17 FBC_CMD<25> 25
58 FBA_D<58> AC30 FBA_D58 FBA_CMD25 W31 FBA_CMD<25> 25
60 FBC_D<60> B24 FBB_D60 FBB_CMD27 A18 FBC_CMD<27> 27
60 FBA_D<60> AF31 FBA_D60 FBA_CMD27 AA34 FBA_CMD<27> 27
61 FBA_D<61> AG34 FBA_D61 FBA_CMD28 Y31 FBA_CMD<28> 28
62 FBC_D<62> B26 FBB_D62 FBB_CMD29 A17 FBC_CMD<29> 29
63 FBC_D<63> C26 FBB_D63 FBB_CMD30 B17 FBC_CMD<30> 30
FBB_CMD31 E17
FBA_CMD31 V31
FBA_DQM<7..0>
68C8 68C3 67C8 67C3 BI FBA_DQM<0> 70C7 70C3 69C8 69C3 BI FBC_DQM<7..0> 0 FBC_DQM<0> E11 FBB_DQM0 FBB_CMD_RFU0 C12
0 P30 FBA_DQM0 FBA_CMD_RFU0 R32
1 FBC_DQM<1> E3 FBB_DQM1 FBB_CMD_RFU1 C20
1 FBA_DQM<1> F31 FBA_DQM1 FBA_CMD_RFU1 AC32
2 FBC_DQM<2> A3 FBB_DQM2
2 FBA_DQM<2> F34 FBA_DQM2
3 FBC_DQM<3> C9 FBB_DQM3
3 FBA_DQM<3> M32 FBA_DQM3
4 FBC_DQM<4> F23 FBB_DQM4
4 FBA_DQM<4> AD31 FBA_DQM4
5 FBC_DQM<5> F27 FBB_DQM5
5 FBA_DQM<5> AL29 FBA_DQM5
6 FBC_DQM<6> C30 FBB_DQM6
6 FBA_DQM<6> AM32 FBA_DQM6
7 FBC_DQM<7> A24 FBB_DQM7 FBB_DEBUG0 G14
7 FBA_DQM<7> AF34 FBA_DQM7 FBA_DEBUG0 R28
FBB_DEBUG1 G20
FBA_DEBUG1 AC28
69C8 FBC_DQS0_DP D10

67C3 BI FBA_DQS0_DP M31 FBA_DQS_WP0 BI FBC_DQS1_DP D5
FBB_DQS_WP0
FBA_DQS1_DP G31 69C3 BI FBB_DQS_WP1

67C8 BI FBA_DQS_WP1
FBC_DQS2_DP C3 D12 FBC_CLK0_DP
FBA_DQS2_DP E33 R30 FBA_CLK0_DP 69C3 BI FBB_DQS_WP2 FBB_CLK0 OUT 69C3 69C5 69C8
67C8 BI FBA_DQS_WP2 FBA_CLK0 OUT 67C3 67C5 67C8 FBC_DQS3_DP B9 E12 FBC_CLK0_DN
FBA_DQS3_DP M33 R31 FBA_CLK0_DN 69C8 BI FBB_DQS_WP3 FBB_CLK0* OUT 69C3 69C5 69C8
67C3 BI FBA_DQS_WP3 FBA_CLK0* OUT 67C3 67C5 67C8 FBC_DQS4_DP E23 E20 FBC_CLK1_DP
FBA_DQS4_DP AE31 AB31 FBA_CLK1_DP 70C3 BI FBB_DQS_WP4 FBB_CLK1 OUT 70C3 70C5 70C7
68C8 BI FBA_DQS_WP4 FBA_CLK1 OUT 68C3 68C5 68C8 FBC_DQS5_DP E28 F20 FBC_CLK1_DN
FBA_DQS5_DP AK30 AC31 FBA_CLK1_DN 70C7 BI FBB_DQS_WP5 FBB_CLK1* OUT 70C3 70C5 70C7
68C3 BI FBA_DQS_WP5 FBA_CLK1* OUT 68C3 68C5 68C8 FBC_DQS6_DP B30
FBA_DQS6_DP AN33 70C3 BI FBB_DQS_WP6
68C8 BI FBA_DQS_WP6
FBC_DQS7_DP A23
FBA_DQS7_DP AF33 70C7 BI FBB_DQS_WP7
68C3 BI FBA_DQS_WP7
C C
69B8 FBC_DQS0_DN D9 F8
67C3 BI FBA_DQS0_DN M30 FBA_DQS_RN0 FBA_WCK01 K31 BI FBC_DQS1_DN E4
FBB_DQS_RN0 FBB_WCK01
E8
FBA_DQS1_DN H30 L30 69C3 BI FBB_DQS_RN1 FBB_WCK01*
67C8 BI FBA_DQS_RN1 FBA_WCK01* FBC_DQS2_DN B2 A5
FBA_DQS2_DN E34 H34 69B3 BI FBB_DQS_RN2 FBB_WCK23
67B8 BI FBA_DQS_RN2 FBA_WCK23 FBC_DQS3_DN A9 A6
FBA_DQS3_DN M34 J34 69C8 BI FBB_DQS_RN3 FBB_WCK23*
67C3 BI FBA_DQS_RN3 FBA_WCK23* FBC_DQS4_DN D22 D24
FBA_DQS4_DN AF30 AG30 70B3 BI FBB_DQS_RN4 FBB_WCK45
68B8 BI FBA_DQS_RN4 FBA_WCK45 FBC_DQS5_DN D28 D25
FBA_DQS5_DN AK31 AG31 70B7 BI FBB_DQS_RN5 FBB_WCK45*
68B3 BI FBA_DQS_RN5 FBA_WCK45* FBC_DQS6_DN A30 B27
FBA_DQS6_DN AM34 AJ34 70C3 BI FBB_DQS_RN6 FBB_WCK67
68C8 BI FBA_DQS_RN6 FBA_WCK67 FBC_DQS7_DN B23 C27
FBA_DQS7_DN AF32 AK34 70C7 BI FBB_DQS_RN7 FBB_WCK67*
68C3 BI FBA_DQS_RN7 FBA_WCK67*
FBB_WCKB01 D6
FBA_WCKB01 J30
FBB_WCKB01* D7
FBA_WCKB01* J31
FBB_WCKB23 C6
P1V5S_DGPU FBA_WCKB23 J32
FBB_WCKB23* B6
FBA_WCKB23* J33
FBB_WCKB45 F26
FBA_WCKB45 AH31
E26
2
AJ31 FBB_WCKB45*
FBA_WCKB45* A26
R5027 AJ32 FBB_WCKB67
FBA_WCKB67 A27
FBA_WCKB67* AJ33 P1V05S_DGPU FBB_WCKB67*
FBB_PLL_AVDD R5023
RSC_0402_DY P1V05S_GPU_FBA_PLLAVDD L1 P1V05S_GPU_FBA_PLLAVDD
H26 FB_VREF 66MA FBA_PLL_AVDD U27 1 2 66MA FBB_PLL_AVDD H17 1 2
IN 63F5
1
1
21
BLM18PG181SN1D
0_5%_3
R5028 NVIDIA_N13P_GLP_A1_BGA_908P C5070
NVIDIA_N13P_GLP_A1_BGA_908P C5066 C5068
RSC_0402_DY
0.1UF_16V_2 22UF_6.3V_5 0.1UF_16V_2
2
2
2
1
B B
R5017
R5010 FBC_CMD<2> 1 2
FBA_CMD<2> 1 2 70F8 70F4 69F8 69F4 63E1 IN
68F8 68F3 67F8 67F3 63E5 IN
10K_5%_2
10K_5%_2
R5018
R5011 FBC_CMD<3> 1 2
FBA_CMD<3> 1 2 70F8 70F4 69F8 69F4 63E1 IN
68F8 68F3 67F8 67F3 63E5 IN
10K_5%_2
10K_5%_2
R5019
R5012 FBC_CMD<5> 1 2
FBA_CMD<5> 1 2 70F8 70F4 69F8 69F4 63E1 IN
68F8 68F3 67F8 67F3 63E5 IN
10K_5%_2
10K_5%_2
R5020
R5013 FBC_CMD<18> 1 2
FBA_CMD<18> 1 2 70F8 70F4 69F8 69F4 63E1 IN
68F8 68F3 67F8 67F3 63E5 IN
10K_5%_2
10K_5%_2
R5021
R5014 FBC_CMD<19> 1 2
FBA_CMD<19> 1 2 70F8 70F4 69F8 69F4 63E1 IN
68F8 68F3 67F8 67F3 63E5 IN
10K_5%_2
10K_5%_2
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PVCORE_DGPU U5000
U5000 14/19 NVVDD PVCORE_DGPU
16/19 GND_1/2
A2 GND_001 GND_071 AM25
F AA17 GND_005 GND_072 AN1
AA12 VDD_001 F
AA14 VDD_002
AA18 GND_006 GND_073 AN10
AA16 VDD_003
AA20 AN13
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
4.7UF_6.3V_3
GND_007 GND_074
AA19 VDD_004
1
AA22 GND_008 GND_075 AN16
AA21 VDD_005
C5080
C5081
C5082
C5083
C5084
C5085
C5086
C5087
C5088
C5089
AB12 GND_009 GND_076 AN19
AA23 VDD_006
AB13 VDD_007
AB15 VDD_008
AB17 VDD_009
AB2 AN34
2
GND_013 GND_080
AB18 VDD_010
AB20 VDD_011
A33 GND_002 GND_082 AN7
AB22 VDD_012
AB23 AP2
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
GND_015 GND_083
1
AC12 VDD_013
AB28 GND_016 GND_084 AP33
C5090
C5091
C5092
AC14 VDD_014
AB30 GND_017 GND_085 B1
AC16 VDD_015
AB32 GND_018 GND_086 B10
AC19 VDD_016
AB5 GND_019 GND_087 B22
AC21 VDD_017
AB7 GND_020 GND_088 B25
AC23
2
VDD_018
AC13 GND_021 GND_089 B28
M12 VDD_019
AC15 GND_022 GND_090 B31
M14 VDD_020
AC17 GND_023 GND_091 B34
M16 VDD_021
AC18 B4
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
GND_024 GND_092
1
M19 VDD_022
AA13 GND_003 GND_093 B7
C5093
C5094
C5095
C5096
M21 VDD_023
AC20 GND_025 GND_094 C10
M23 VDD_024
AC22 GND_026 GND_095 C13
N13 VDD_025
AE2 GND_027 GND_096 C19
N15 VDD_026
AE28 GND_028 GND_097 C22
N17
2
VDD_027
AE30 GND_029 GND_098 C25
N18 VDD_028
AE32 GND_030 GND_099 C28
N20 VDD_029
AE33 GND_031 GND_100 C7
E AE5 GND_032 GND_101 D2
N22 VDD_030 E
P12 VDD_031
AE7 GND_033 GND_102 D31
P14 VDD_032
AH10 GND_034 GND_103 D33
P16 VDD_033
AA15 GND_004 GND_104 E10
P19 VDD_034
AH13 GND_035 GND_105 E22
P21 VDD_035
AH16 GND_036 GND_106 E25
P23 VDD_036
AH19 GND_037 GND_107 E5
R13 VDD_037
AH2 GND_038 GND_108 E7
R15 VDD_038
AH22 GND_039 GND_109 F28
R17 VDD_039
AH24 GND_040 GND_110 F7
R18 VDD_040
AH28 GND_041 GND_111 G10
R20 VDD_041
AH29 GND_042 GND_112 G13
R22 VDD_042
AH30 GND_043 GND_113 G16
T12 VDD_043
AH32 GND_044 GND_114 G19
T14 VDD_044
AH33 GND_045 GND_115 G2
T16 VDD_045
AH5 GND_046 GND_116 G22
T19 VDD_046
AH7 GND_047 GND_117 G25
T21 VDD_047
AJ7 GND_048 GND_118 G28
T23 VDD_048
AK10 GND_049 GND_119 G3
U13 VDD_049
AK7 GND_050 GND_120 G30
U15 VDD_050
AL12 GND_051 GND_121 G32
U17 VDD_051
AL14 GND_052 GND_122 G33
U18 VDD_052
AL15 GND_053 GND_123 G5
U20 VDD_053
AL17 GND_054 GND_124 G7
U22 VDD_054
AL18 GND_055 GND_125 K2
V13 VDD_055
AL2 GND_056 GND_126 K28
V15 VDD_056
AL20 GND_057 GND_127 K30
D AL21 GND_058 GND_128 K32
V17 VDD_057 D
V18 VDD_058
AL23 GND_059 GND_129 K33
V20 VDD_059
AL24 GND_060 GND_130 K5
V22 VDD_060
AL26 GND_061 GND_131 K7
W12 VDD_061
AL28 GND_062 GND_132 M13
W14 VDD_062
AL30 GND_063 GND_133 M15
W16 VDD_063
AL32 GND_064 GND_134 M17
W19 VDD_064
AL33 GND_065 GND_135 M18
W21 VDD_065
AL5 GND_066 GND_136 M20
W23 VDD_066
AM13 GND_067 GND_137 M22
Y13 VDD_067
AM16 GND_068 GND_138 N12
Y15 VDD_068
AM19 GND_069 GND_139 N14
Y17 VDD_069
AM22 GND_070 GND_140 N16
Y18 VDD_070
Y20 VDD_071
Y22 VDD_072
P1V5S_DGPU
U5000
15/19 FBVDDQ
U5000
17/19 GND_2/2 AA27 FBVDDQ_01
AA30 FBVDDQ_02 P1V5S_DGPU
N19 GND_141 GND_170 T28 AB27 FBVDDQ_03
C N2 GND_142 GND_171 T32 AB33 FBVDDQ_04 C
N21 GND_143 GND_172 T5 AC27 FBVDDQ_05
U5000
N23 GND_144 GND_173 T7 10/19 XVDD AD27 FBVDDQ_06
N28 GND_145 GND_174 U12 AE27 FBVDDQ_07
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1
1
N30 GND_146 GND_175 U14 CONFIGURABLE AF27 FBVDDQ_08
C5060
C5061
C5062
C5063
C5064
C5065
C5072
C5073
N32 GND_147 GND_176 U16 POWER AG27 FBVDDQ_09
N33 GND_148 GND_177 U19 CHANNELS B13 FBVDDQ_10
N5 GND_149 GND_178 U21 B16 FBVDDQ_11
XVDD_001 U1
N7 GND_150 GND_179 U23 B19 FBVDDQ_12
XVDD_002 U2
P13 V12 E13
2
GND_151 GND_180 FBVDDQ_13
XVDD_003 U3
P15 GND_152 GND_181 V14 E16 FBVDDQ_14
XVDD_004 U4
P17 GND_153 GND_182 V16 E19 FBVDDQ_15
XVDD_005 U5
P18 GND_154 GND_183 V19 H10 FBVDDQ_16
U6
4.7UF_6.3V_3
4.7UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
XVDD_006
1UF_6.3V_2
1UF_6.3V_2
1
1
XVDD_007 U7
C5074
C5075
C5076
C5077
C5100
C5101
C5102
C5103
XVDD_008 U8
R12 GND_157 GND_186 W13 H13 FBVDDQ_19
XVDD_009 V1
V2
2
XVDD_010
XVDD_011 V3
XVDD_012 V4
T13 GND_163 GND_192 W28 H20 FBVDDQ_25
XVDD_013 V5
T15 GND_164 GND_193 Y12 H21 FBVDDQ_26
XVDD_014 V6
XVDD_015 V7
XVDD_016 V8
B T22 GND_169 GND_198 Y23
XVDD_017 W2
H9 FBVDDQ_31 B
L27 FBVDDQ_32
XVDD_018 W3
M27 FBVDDQ_33
XVDD_019 W4
N27 FBVDDQ_34
XVDD_020 W5
P27 FBVDDQ_35
XVDD_021 W7
R27 FBVDDQ_36
XVDD_022 W8
T27 FBVDDQ_37
AG11 GND_F GND_H AH11 T30 FBVDDQ_38
T33 FBVDDQ_39
V27 FBVDDQ_40
W27 FBVDDQ_41
XVDD_023 Y1
W30 FBVDDQ_42
XVDD_024 Y2
W33 FBVDDQ_43
XVDD_025 Y3 P1V5S_DGPU
Y27 FBVDDQ_44
XVDD_026 Y4
XVDD_027 Y5
GND_OPT_1 C16 R5130
XVDD_028 Y6
GND_OPT_2 W32 FB_VDDQ_SENSE F11 2
XVDD_029 Y7
Optional CMD GNDs (2) XVDD_030 Y8
0_5%_2
NC for 4-Lyr cards FB_GND_SENSE F2
P1V5S_DGPU
XVDD_031 AA1
XVDD_032 AA2 R5024
FB_CAL_PD_VDDQ J27 1 2
XVDD_033 AA3
AA4 40.2_1%_2
XVDD_034
XVDD_035 AA5 R5025
FB_CAL_PU_GND H27 1 2
XVDD_036 AA6
AA7 42.2_1%_2
XVDD_037
A XVDD_038 AA8 R5026 2
A
FB_CAL_TERM_GND H25 1
51.1_1%_2
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F F
U5000
6/19 IFPAB
ALL PINS NC FOR GF117
U5000
R5132 IFPA_TXC* AN6 VGA_LVDS_TXCA_DN BI 38C8 7/19 IFPC
1K_1%_2 IFPA_TXC AM6 VGA_LVDS_TXCA_DP BI 38C8
2 1 AJ8 IFPAB_RSET
P1V05S
IFPA_TXD0* AN3 VGA_LVDS_TXDA0_DN BI 38C8 R5131
AP3 VGA_LVDS_TXDA0_DP
IFPA_TXD0 BI 38C8 2 1K_1%_2 1 AF8 IFPC_RSET
L5006 DVI/HDMI DP
1 2 AH8 IFPAB_PLLVDD
P3V3S
4.7UF_6.3V_3
IFPA_TXD1* AM5 VGA_LVDS_TXDA1_DN BI 38C8
1UF_6.3V_2
1
1
0.1UF_16V_2
AN5 VGA_LVDS_TXDA1_DP L5004
FBM_11_160808_181A15T IFPA_TXD1 BI 38C8 VGA_HDMI_DDCDATA
C5119
C5120
C5121
1 2 AF7 I2CW_SDA AG2 40B8
IFPC_PLLVDD IFPC_AUX_I2CW_SDA* BI
4.7UF_6.3V_3
I2CW_SCL AG3 VGA_HDMI_DDCCLK
0.1UF_16V_2
IFPC_AUX_I2CW_SCL BI 40B8
1UF_6.3V_2
1
1
VGA_LVDS_TXDA2_DN FBM_11_160808_181A15T
C5115
C5114
C5113
AK6 38C8
IFPA_TXD2*
AL6 VGA_LVDS_TXDA2_DP BI
IFPA_TXD2 BI 38C8 AG4 VGA_HDMI_TXC_DN
TXC
2
IFPC_L3* BI 40C7
TXC IFPC_L3 AG5 VGA_HDMI_TXC_DP BI 40C7
AH6
2
IFPA_TXD3*
TXD0 IFPC_L2* AH4 VGA_HDMI_TX0_DN BI 40C7
IFPA_TXD3 AJ6 IFPC AH3 VGA_HDMI_TX0_DP
TXD0 IFPC_L2 BI 40D7
VGA_LVDS_TXCB_DN TXD1 IFPC_L1* AJ2 VGA_HDMI_TX1_DN BI 40D7

P3V3S AH9 38A8
E IFPB_TXC*
AJ9 VGA_LVDS_TXCB_DP BI TXD1 IFPC_L1 AJ3 VGA_HDMI_TX1_DP BI 40D7 E
IFPB_TXC BI 38A8
L5007 AJ1 VGA_HDMI_TX2_DN
1 2 AG8 TXD2 IFPC_L0* BI 40D7
IFPA_IOVDD
TXD2 AK1 VGA_HDMI_TX2_DP
4.7UF_6.3V_3
AP5 VGA_LVDS_TXDB0_DN P1V05S IFPC_L0 BI 40D7
0.1UF_16V_2
IFPB_TXD4* BI 38C8
1UF_6.3V_2
1
1
FBM_11_160808_181A15T AG9 IFPB_IOVDD IFPB_TXD4 AP6 VGA_LVDS_TXDB0_DP BI 38C8
C5122
C5123
C5124
L5005
VGA_LVDS_TXDB1_DN 1 2 AF6 IFPC_IOVDD GPIO15 P2 VGA_HPDET IN 40A3
AL7
4.7UF_6.3V_3
IFPB_TXD5* BI 38A8
VGA_LVDS_TXDB1_DP
1UF_6.3V_2
1
1
AM7
0.1UF_16V_2
IFPB_TXD5 BI 38A8
FBM_11_160808_181A15T
2
C5116
C5117
C5118
IFPB_TXD6* AM8 VGA_LVDS_TXDB2_DN BI 38A8

IFPB_TXD6 AN8 VGA_LVDS_TXDB2_DP BI 38A8
2
IFPB_TXD7* AL8
IFPB_TXD7 AK8
R5048
GPIO14 N4 1 2
IFPAB
100K_5%_2_DY
D D
U5000
9/19 IFPEF
U5000
8/19 IFPD
DVI-DL DVI-SL/HDMI DP R5133
2 1K_1%_2 1 AN2 IFPD_RSET
DVI/HDMI DP
P3V3S
C I2CY_SDA I2CY_SDA IFPE_AUX_I2CY_SDA* AB4 C
I2CY_SCL I2CY_SCL AB3 L5008
IFPE_AUX_I2CY_SCL 1 2 AG7 IFPD_PLLVDD I2CX_SDA IFPD_AUX_I2CX_SDA* AK2 VGA_EDP_AUX_DN BI 37C8
AB8
4.7UF_6.3V_3
IFPEF_PLLVDD
I2CX_SCL AK3 VGA_EDP_AUX_DP
0.1UF_16V_2
IFPD_AUX_I2CX_SCL BI 37D8
1UF_6.3V_2
1
1
FBM_11_160808_181A15T
C5125
C5126
C5127
TXC TXC IFPE_L3* AC5
R5033 AD6 AC4
IFPEF_RSET TXC TXC IFPE_L3
TXC AK5 VGA_EDP_TX3_DN
IFPD_L3* BI 37B8
10K_5%_2 TXD0 TXD0 IFPE_L2* AC3 TXC IFPD_L3 AK4 VGA_EDP_TX3_DP BI 37B8
AC2
2
2
TXD0 TXD0 IFPE_L2
TXD0 AL4 VGA_EDP_TX2_DN 37B8
IFPD IFPD_L2*
AL3 VGA_EDP_TX2_DP BI
AC1 TXD0 IFPD_L2 BI 37B8
TXD1 TXD1 IFPE_L1*
IFPE TXD1 TXD1 AD1
IFPE_L1 TXD1 IFPD_L1* AM4 VGA_EDP_TX1_DN BI 37C8
TXD1 IFPD_L1 AM3 VGA_EDP_TX1_DP BI 37C8
TXD2 TXD2 IFPE_L0* AD3
TXD2 TXD2 AD2
IFPE_L0
TXD2 IFPD_L0* AM2 VGA_EDP_TX0_DN BI 37C8
P1V05S TXD2 IFPD_L0 AM1 VGA_EDP_TX0_DP BI 37C8
L5009
HPD_E HPD_E 1 2 AG6 IFPD_IOVDD GPIO17 M6 VGA_EDP_HPD IN 37D4
R1
100K_5%_2_DY
4.7UF_6.3V_3
GPIO18
1UF_6.3V_2
1
1
2
0.1UF_16V_2
C51130
FBM_11_160808_181A15T
R5049
C5128
C5129
2 NVIDIA_N13P_GLP_A1_BGA_908P
2
1
B B
AC7 IFPE_IOVDD
I2CZ_SDA IFPF_AUX_I2CZ_SDA* AF2
1
I2CZ_SCL IFPF_AUX_I2CZ_SCL AF3

AC8 IFPF_IOVDD
R5034
10K_5%_2 TXC IFPF_L3* AF1
TXC IFPF_L3 AG1
2
TXD3 TXD0 IFPF_L2* AD5

TXD3 TXD0 IFPF_L2 AD4
IFPF TXD4 TXD1 IFPF_L1* AF5

TXD4 TXD1 IFPF_L1 AF4
TXD5 TXD2 IFPF_L0* AE4

TXD5 TXD2 IFPF_L0 AE3
HPD_F P3
100K_5%_2_DY
GPIO19
2
R5050
A A
1
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5000
4/19 DACA U5000
P3V3S_DGPU GF108/GKx GF117 GF117 GF108/GKx
13/19 MISC2
L5003 P3V3S_GPU_DACA_VDD
F 1 2 AG10 NC NC R4 VGA_CRT_DDCCLK 39B6 P3V3S_DGPU F
DACA_VDD I2CA_SCL
BI
1
BLM18PG181SN1D NC I2CA_SDA R5 VGA_CRT_DDCDATA BI 39B6 R5065
C5110 AP9
C5111 DACA_VREF TSEN_VREF 10K_5%_2
1UF_6.3V_2
1
ROM_CS* H6 1 2
VGA_CRT_HSYNC
C5130
AP8 NC NC AM9 39B8
4.7UF_6.3V_3 4.7UF_6.3V_3 DACA_RSET DACA_HSYNC
OUT
2
NC DACA_VSYNC AN9 VGA_CRT_VSYNC OUT 39B8 ROM_SI H5 GPU_ROM_SI
OUT 66B4
2
2
C5112 R5066 H7 GPU_ROM_SO
ROM_SO OUT 66B4
0.1UF_16V_2 66B6 IN GPU_STRAP0 J2 STRAP0 ROM_SCLK H4 GPU_ROM_SCLK
OUT 66B4
2
NC AK9 VGA_CRTR GPU_STRAP1 J7
2
124_1%_2 DACA_RED
OUT 39D8 66B6 IN STRAP1
66B6 IN GPU_STRAP2 J6 STRAP2
1
NC DACA_GREEN AL10 VGA_CRTG OUT 39D8 66B6 IN GPU_STRAP3 J5 STRAP3
66B6 IN GPU_STRAP4 J3 STRAP4
NC DACA_BLUE AL9 VGA_CRTB OUT 39D8
2
BUFRST* L2
2
2
R5067
150_1%_2
R5057
R5069
150_1%_2
150_1%_2
2
R5058 2
R5068
1 J1 MULTI_STRAP_REF0_GND CEC L3 10K_5%_2
1
40.2K_1%_2
1
1
1
E E
P3V3S_DGPU
1
R5093 R5094
1
2.2K_5%_2 2.2K_5%_2
Q5002
G
SSM3K7002BFU
2
66D3 IN DGPU_SMB2_CLK 2 S D 3 EC_SMB2_CLK OUT 5A7 22D2 22D3 41C6
1
Q5003
SSM3K7002BFU
G
66D3 IN DGPU_SMB2_DATA 2 S D 3 EC_SMB2_DATA OUT 5A7 22D2 22D3 41C3
U5000
11/19 MISC1
I2CS_SCL T4 DGPU_SMB2_CLK OUT 66E4
I2CS_SDA T3 DGPU_SMB2_DATA OUT 66D4
I2CC_SCL R2 VGA_LVDS_DDCCLK BI 38C6

R3 VGA_LVDS_DDCDATA 38C6 P3V3S_DGPU R5061 2
I2CC_SDA
BI 66C3 38D8 IN VGA_LCM_VDDEN 1
D I2CB_SCL R7 R5091 1 2 2.2K_5%_2
10K_5%_2 D
TP5007 TP30 1 K4 R6 VGA_LCM_BKLTEN R5062 2
THERMDN I2CB_SDA R5092 1 2 2.2K_5%_2 66C3 38A7 IN 1
TP5008
10K_5%_2
TP30 1 K3 THERMDP
TP5000 TP30 1 AM10 JTAG_TCK

TP5001 TP30 1 AP11
TP5002
JTAG_TMS P3V3S_DGPU
TP30 1 AM11 JTAG_TDI
TP5003 TP30 1 AP12 JTAG_TDO
TP5004 TP30 1 AN11 P6 DGPU_VID4
JTAG_TRST* GPIO0
OUT 13A4 66C2
M3 DGPU_VID3
2
GPIO1
OUT 13A4
R5064 GPIO2 L6 66C2 VGA_INV_PWM_3 OUT 38A6
GPIO3 P5 VGA_LCM_VDDEN OUT 38D8 66D2
2 R5161 1
2 R5165 1
2.2K_5%_2
2.2K_5%_2
2.2K_5%_2
GPIO4 P7 VGA_LCM_BKLTEN OUT 38A7 66D2
10K_5%_2 DGPU_VID1
R5163
L7 13A4 66C2
GPIO5
M7 DGPU_VID2 OUT P3V3S_DGPU
1
GPIO6
OUT 13A4 66C2
GPIO7 N8
GPIO8 M1 R5073 1 2 10K_5%_2
2
GPIO9 M2 R5074 1 2 10K_5%_2
L1
GPIO10
DGPU_VID0 66C4 13A4 IN DGPU_VID0
M5 13A4 66C2
GPIO11
N3
OUT 1 R5063 2
GPIO12
DGPU_VID5 66C4 13A4 IN DGPU_VID1
M4 13A4 100K_5%_2
GPIO13
R8
OUT 66C2
GPIO16
66C4 13A4 IN DGPU_VID2
GPIO20 P4
P1
C GPIO21
ACPRESENT 66D4 13A4 IN DGPU_VID3 C
IN 22D6 55A5 55A6
66D4 13A4 IN DGPU_VID4
66C4 13A4 IN DGPU_VID5
2 R5168 1
2 R5170 1
2 R5172 1
2.2K_5%_2
2.2K_5%_2
2.2K_5%_2
P3V3S_DGPU
P3V3S_DGPU
1
1
2
R5079 R5080 R5081 R5044 2 R5059
1
B B
2
45.3K_1%_2 10K_1%_2 4.99K_1%_2 RSC_0402_DY
RSC_0402_DY
GPU_STRAP0
2
66F4 R5085 R5086 R5087

1
IN
GPU_STRAP1 34.8K_1%_2 30K_1%_2 RSC_0402_DY
66F4 IN
GPU_STRAP2 GPU_ROM_SI
1
66F4 IN 66F2 IN
66F4 IN GPU_STRAP3 66F2 IN GPU_ROM_SO
GPU_STRAP4 66F2 IN GPU_ROM_SCLK
66F4 IN
2
R5088 R5089 R5090
1
2
RSC_0402_DY RSC_0402_DY 15K_1%_2

2
R5082 R5083 R5084 R5045 R5060
1
RSC_0402_DY 34.8K_1%_2 RSC_0402_DY RSC_0402_DY 20K_1%_2
2
1
1
1
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
68F3 68F8 68F3 67F8 63E5 63B7 63A7 BI FBA_CMD<0..30>

63E5 FBA_CMD<0..30>
63A7 BI
63B7
67F3 FBA_D<16..23> FBA_D<0..7>
F 68F8 63F8
U5004 BI 63F8 F
BI 9 FBA_CMD<9> N3 A0 DQL0 E3 FBA_D<7> 7
U5003
9 FBA_CMD<9> N3 A0 DQL0 E3 FBA_D<19> 19
FBA_CMD<11> FBA_D<2>
11 P7 A1 DQL1 F7 2
11 FBA_CMD<11> P7 A1 DQL1 F7 FBA_D<21> 21
FBA_CMD<8> FBA_D<4>
8 P3 A2 DQL2 F2 4
8 FBA_CMD<8> P3 A2 DQL2 F2 FBA_D<18> 18
25 N2 A3 DQL3 F8 3
25 FBA_CMD<25> N2 A3 DQL3 F8 FBA_D<20> 20
10 P8 A4 DQL4 H3 6
10 FBA_CMD<10> P8 A4 DQL4 H3 FBA_D<17> 17
24 P2 A5 DQL5 H8 0
24 FBA_CMD<24> P2 A5 DQL5 H8 FBA_D<23> 23
22 R8 A6 DQL6 G2 5
22 FBA_CMD<22> R8 A6 DQL6 G2 FBA_D<16> 16
FBA_CMD<7> FBA_D<1>
7 R2 A7 DQL7 H7 1
7 FBA_CMD<7> R2 A7 DQL7 H7 FBA_D<22> 22
FBA_CMD<21> FBA_D<24..31>
21 T8 63F8
P1V5S_DGPU
A8
BI
21 FBA_CMD<21> T8 A8
FBA_D<8..15> FBA_CMD<6> FBA_D<30>
6 R3 A9 DQU0 D7 30
BI 63F8
1
6 R3 D7 11
A9 DQU0
29 FBA_CMD<29> L7 A10_AP DQU1 C3 FBA_D<25> 25
29 FBA_CMD<29> L7 C3 FBA_D<12> 12 R5101
A10_AP DQU1
23 FBA_CMD<23> R7 A11 DQU2 C8 FBA_D<28> 28
23 FBA_CMD<23> R7 C8 FBA_D<10> 10 1.33K_1%_2
A11 DQU2
28 FBA_CMD<28> N7 A12_BC# DQU3 C2 FBA_D<27> 27
2
FBA_VREFDQ0
28 N7 C2 14 67B8 67B3
A12_BC# DQU3
IN 20 FBA_CMD<20> T3 A13 DQU4 A7 FBA_D<29> 29
1
20 FBA_CMD<20> T3 A13 DQU4 A7 FBA_D<9> 9
E R5102 C5156 4 T7 A14_NC DQU5 A2 26 E
4 FBA_CMD<4> T7 A14_NC DQU5 A2 FBA_D<13> 13 1.33K_1%_2 0.01UF_50V_2 FBA_CMD<14> FBA_D<31>
14 M7 A15 DQU6 B8 31
14 FBA_CMD<14> M7 B8 FBA_D<8> 8
2
A15 DQU6
DQU7 A3 FBA_D<24> 24
DQU7 A3 FBA_D<15> 15
P1V5S_DGPU
P1V5S_DGPU 12 FBA_CMD<12> M2 BA0 VDD_B2 B2
12 FBA_CMD<12> M2 BA0 VDD_B2 B2
FBA_CMD<27>
27 N8 BA1 VDD_D9 D9
27 FBA_CMD<27> N8 BA1 VDD_D9 D9
FBA_CMD<26>
26 M3 BA2 VDD_G7 G7
26 FBA_CMD<26> M3 BA2 VDD_G7 G7 P1V5S_DGPU VDD_K2 K2
VDD_K2 K2
VDD_K8 K8
1
K8
VDD_K8
R5103 2 FBA_CMD<2> K1 ODT VDD_N1 N1
2 FBA_CMD<2> K1 ODT VDD_N1 N1
FBA_CMD<0>
1.33K_1%_2 0 L2 CS# VDD_N9 N9
0 FBA_CMD<0> L2 N9
2
CS# VDD_N9
FBA_VREFCA0 30 FBA_CMD<30> J3 RAS# VDD_R1 R1
67B8 67B3 IN
FBA_CMD<30>
1
30 J3 R1
RAS# VDD_R1
15 FBA_CMD<15> K3 CAS# VDD_R9 R9
15 FBA_CMD<15> K3 R9 R5104 C5157
CAS# VDD_R9
13 FBA_CMD<13> L3 WE#
D 1.33K_1%_2 0.01UF_50V_2 D
VDDQ_A1 A1
2
VDDQ_A1 A1
VDDQ_A8 A8
A8
VDDQ_A8
5 FBA_CMD<5> T2 RESET# VDDQ_C1 C1
VDDQ_C9 C9
C9
VDDQ_C9
3 FBA_CMD<3> K9 CKE VDDQ_D2 D2
3 FBA_CMD<3> K9 CKE VDDQ_D2 D2
VDDQ_E9 E9
E9
VDDQ_E9
FBA_CLK0_DP 67C8 67C5 63C5 IN FBA_CLK0_DP J7 CK VDDQ_F1 F1
67C8 67C3 63C5 IN
FBA_CLK0_DP J7 F1
2
67C5 67C3 63C5 IN CK VDDQ_F1
FBA_CLK0_DN K7 H2
R5105 67C8 67C5 63C5 IN CK# VDDQ_H2
67C5 67C3 63C5 IN FBA_CLK0_DN K7 CK# VDDQ_H2 H2

VDDQ_H9 H9
H9 162_1%_2
VDDQ_H9
FBA_CLK0_DN 63D8 BI FBA_DQM<3> D3 DMU
1
67C8 67C3 63C5 IN
63D8 BI FBA_DQM<1> D3 DMU
VSS_A9 A9
A9
VSS_A9
63C7 BI FBA_DQS3_DP C7 DQSU VSS_B3 B3
63C7 BI FBA_DQS1_DP C7 DQSU VSS_B3 B3

VSS_E1 E1
E1
C VSS_E1
63C7 BI FBA_DQS3_DN B7 DQSU# VSS_G8 G8 C
63C7 BI FBA_DQS1_DN B7 DQSU# VSS_G8 G8
P1V5S_DGPU VSS_J2 J2
J2
VSS_J2
63D8 BI FBA_DQM<0> E7 DML VSS_J8 J8
63D8 BI FBA_DQM<2> E7 DML VSS_J8 J8
VSS_M1 M1
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
M1
VSS_M1
63C7 BI FBA_DQS0_DP F3 DQSL VSS_M9 M9
C5158
C5159
C5160
C5161
C5162
C5163
63C7 BI FBA_DQS2_DP F3 DQSL VSS_M9 M9
VSS_P1 P1
P1
VSS_P1
63C7 BI FBA_DQS0_DN G3 DQSL# VSS_P9 P9
2
2
63C7 BI FBA_DQS2_DN G3 DQSL# VSS_P9 P9
VSS_T1 T1
T1 R5106
VSS_T1
1 2 L8 ZQ VSS_T9 T9
R5100
1 2 L8 ZQ VSS_T9 T9
243_1%_2
243_1%_2 P1V5S_DGPU J1 NC_J1 VSSQ_B1 B1
J1 NC_J1 VSSQ_B1 B1
L1 NC_L1 VSSQ_B9 B9
L1 NC_L1 VSSQ_B9 B9
J9 NC_J9 VSSQ_D1 D1
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
J9 NC_J9 VSSQ_D1 D1
C5150
C5151
C5152
C5153
C5154
C5155
L9 NC_L9 VSSQ_D8 D8
B L9 NC_L9 VSSQ_D8 D8 B
VSSQ_E2 E2
VSSQ_E2 E2
E8
2
2
VSSQ_E8
E8
VSSQ_E8
67E5 67B8 IN FBA_VREFDQ0 H1 VREFDQ VSSQ_F9 F9
67E5 67B3 IN FBA_VREFDQ0 H1 VREFDQ VSSQ_F9 F9

FBA_VREFCA0
67D5 67B8 M8 G1
IN VREFCA VSSQ_G1
67D5 67B3 IN FBA_VREFCA0 M8 VREFCA VSSQ_G1 G1

VSSQ_G9 G9
VSSQ_G9 G9
HYNIX_H5TQ2G63BFR_12C_FBGA_96P
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FBA_CMD<30..0>
F 68F3 67F8 68F8 67F8 67F3 63E5 63B7 63A7 BI FBA_CMD(30..0) F
63B7 63A7 BI
67F3 63E5
FBA_D<32..39> FBA_D(40..47) BI 63F8

U5005 BI 63F8 U5006
FBA_CMD<9> FBA_D<36> 9 FBA_CMD<9> N3 A0 DQL0 E3 FBA_D<47> 47
9 N3 A0 DQL0 E3 36
FBA_CMD<11> FBA_D<32> 11 FBA_CMD<11> P7 A1 DQL1 F7 FBA_D<41> 41

11 P7 A1 DQL1 F7 32
FBA_CMD<8> FBA_D<37> 8 FBA_CMD<8> P3 A2 DQL2 F2 FBA_D<46> 46

8 P3 A2 DQL2 F2 37
FBA_CMD<25> FBA_D<35> 25 FBA_CMD<25> N2 A3 DQL3 F8 FBA_D<42> 42

25 N2 A3 DQL3 F8 35
FBA_CMD<10> FBA_D<38> 10 FBA_CMD<10> P8 A4 DQL4 H3 FBA_D<45> 45

10 P8 A4 DQL4 H3 38
FBA_CMD<24> FBA_D<34> 24 FBA_CMD<24> P2 A5 DQL5 H8 FBA_D<40> 40

24 P2 A5 DQL5 H8 34
FBA_CMD<22> FBA_D<39> 22 FBA_CMD<22> R8 A6 DQL6 G2 FBA_D<44> 44

22 R8 A6 DQL6 G2 39
FBA_CMD<7> FBA_D<33> 7 FBA_CMD<7> R2 A7 DQL7 H7 FBA_D<43> 43

7 R2 A7 DQL7 H7 33
P1V5S_DGPU 21 FBA_CMD<21> T8
21 FBA_CMD<21> T8 A8
A8
FBA_D(56..63)
FBA_D(48..55) BI 63F8
BI 63F8 6 FBA_CMD<6> R3 D7 FBA_D<58> 58
FBA_CMD<6> FBA_D<49> A9 DQU0
1
6 R3 A9 DQU0 D7 49
FBA_CMD<29> FBA_D<52> R5108 29 FBA_CMD<29> L7 A10_AP DQU1 C3 FBA_D<60> 60

29 L7 A10_AP DQU1 C3 52
1.33K_1%_2 23 FBA_CMD<23> R7 C8 FBA_D<56> 56
23 FBA_CMD<23> R7 A11 DQU2 C8 FBA_D<50> 50 A11 DQU2
2
FBA_CMD<28> FBA_D<55> FBA_VREFDQ1 28 FBA_CMD<28> N7 A12_BC# DQU3 C2 FBA_D<61> 61
E 28 N7 A12_BC# DQU3 C2 55 68B8 68B3 IN E
1
FBA_CMD<20> FBA_D<48> 20 FBA_CMD<20> T3 A13 DQU4 A7 FBA_D<57> 57
20 T3 A13 DQU4 A7 48
R5156 C5170
FBA_CMD<4> FBA_D<54> 4 FBA_CMD<4> T7 A14_NC DQU5 A2 FBA_D<62> 62
4 T7 A14_NC DQU5 A2 54 1.33K_1%_2 0.01UF_50V_2
FBA_CMD<14> FBA_D<51> 14 FBA_CMD<14> M7 A15 DQU6 B8 FBA_D<59> 59
14 M7 B8 51
2
A15 DQU6
FBA_D<53> DQU7 A3 FBA_D<63> 63

DQU7 A3 53
P1V5S_DGPU
P1V5S_DGPU
FBA_CMD<12> 12 FBA_CMD<12> M2 BA0 VDD_B2 B2
12 M2 BA0 VDD_B2 B2
FBA_CMD<27> 27 FBA_CMD<27> N8 BA1 VDD_D9 D9

27 N8 BA1 VDD_D9 D9
FBA_CMD<26> 26 FBA_CMD<26> M3 BA2 VDD_G7 G7

26 M3 BA2 VDD_G7 G7 P1V5S_DGPU
VDD_K2 K2
VDD_K2 K2
1
VDD_K8 K8
VDD_K8 K8
R5109
FBA_CMD<18> 18 FBA_CMD<18> K1 ODT VDD_N1 N1
18 K1 ODT VDD_N1 N1 1.33K_1%_2
FBA_CMD<16> 16 FBA_CMD<16> L2 CS# VDD_N9 N9
16 L2 N9
2
CS# VDD_N9
68B8 68B3 IN FBA_VREFCA1 FBA_CMD<30>
30 J3 R1
FBA_CMD<30> RAS# VDD_R1
1
30 J3 RAS# VDD_R1 R1
D R5160 C5171 15 FBA_CMD<15> K3 R9 D
15 FBA_CMD<15> K3 CAS# VDD_R9 R9 CAS# VDD_R9
1.33K_1%_2 0.01UF_50V_2 13 FBA_CMD<13> L3

WE#
2
VDDQ_A1 A1
VDDQ_A1 A1
VDDQ_A8 A8
VDDQ_A8 A8
FBA_CMD<5> T2 C1
5 RESET# VDDQ_C1
VDDQ_C9 C9
VDDQ_C9 C9
FBA_CMD<19> 19 FBA_CMD<19> K9 CKE VDDQ_D2 D2

19 K9 CKE VDDQ_D2 D2
VDDQ_E9 E9
VDDQ_E9 E9
68C8 68C3 63C5 IN FBA_CLK1_DP FBA_CLK1_DP
68C8 68C5 63C5 J7 F1
FBA_CLK1_DP J7 F1 IN CK VDDQ_F1
2
68C5 68C3 63C5 IN CK VDDQ_F1
R5110
FBA_CLK1_DN 68C8 68C5 63C5 IN FBA_CLK1_DN K7 CK# VDDQ_H2 H2
68C5 68C3 63C5 K7 H2
IN CK# VDDQ_H2
VDDQ_H9 H9
VDDQ_H9 H9 162_1%_2
FBA_CLK1_DN
1
68C8 68C3 63C5 IN FBA_DQM<7> D3
FBA_DQM<6> D3 63D8 BI DMU
63D8 BI DMU
VSS_A9 A9
VSS_A9 A9
FBA_DQS6_DP 63C7 BI FBA_DQS7_DP C7 DQSU VSS_B3 B3

C 63C7 BI C7 DQSU VSS_B3 B3 C
VSS_E1 E1
VSS_E1 E1
FBA_DQS6_DN 63C7 BI FBA_DQS7_DN B7 DQSU# VSS_G8 G8

63C7 B7 G8
BI DQSU# VSS_G8
VSS_J2 J2
FBA_DQM<4> 63D8 BI FBA_DQM<5> E7 DML VSS_J8 J8

63D8 E7 J8
BI DML VSS_J8
VSS_M1 M1
VSS_M1 M1 0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
FBA_DQS4_DP 63C7 BI FBA_DQS5_DP F3 DQSL VSS_M9 M9
C5172
C5173
C5174
C5175
C5176
C5177
63C7 F3 M9
BI DQSL VSS_M9
VSS_P1 P1
VSS_P1 P1
FBA_DQS4_DN 63C7 BI FBA_DQS5_DN G3 DQSL# VSS_P9 P9

G3 P9
2
2
63C7 BI DQSL# VSS_P9
VSS_T1 T1
VSS_T1 T1
R5111
R5107 2 1 2 L8 ZQ VSS_T9 T9
1 L8 ZQ VSS_T9 T9
243_1%_2 243_1%_2
P1V5S_DGPU J1 NC_J1 VSSQ_B1 B1
J1 NC_J1 VSSQ_B1 B1
L1 NC_L1 VSSQ_B9 B9
L1 NC_L1 VSSQ_B9 B9
B J9 NC_J9 VSSQ_D1 D1 B
J9 NC_J9 VSSQ_D1 D1
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
L9 NC_L9 VSSQ_D8 D8
C5164
C5165
C5166
C5167
C5168
C5169
L9 NC_L9 VSSQ_D8 D8
VSSQ_E2 E2
VSSQ_E2 E2
VSSQ_E8 E8
E8
2
VSSQ_E8
FBA_VREFDQ1 68E5 68B8 IN FBA_VREFDQ1 H1 VREFDQ VSSQ_F9 F9

68E5 68B3 H1 F9
IN VREFDQ VSSQ_F9
FBA_VREFCA1 68D5 68B8 IN FBA_VREFCA1 M8 VREFCA VSSQ_G1 G1

68D5 68B3 M8 G1
IN VREFCA VSSQ_G1
VSSQ_G9 G9
VSSQ_G9 G9
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F FBC_CMD<30..0> F
63E1 63B3 63A3 BI FBC_CMD<30..0>
70F8 70F4 69F4 70F8 70F4 69F8 63E1 63B3 63A3 BI
U5007 FBC_D<0..7> FBC_D<16..23> BI 63F4
BI 63F4 U5008
9 FBC_CMD<9> N3 A0 DQL0 E3 FBC_D<4> 4
FBC_CMD<9> FBC_D<18>
9 N3 A0 DQL0 E3 18
11 FBC_CMD<11> P7 A1 DQL1 F7 FBC_D<0> 0
11 P7 A1 DQL1 F7 20
8 P3 A2 DQL2 F2 19
25 FBC_CMD<25> N2 A3 DQL3 F8 FBC_D<2> 2
25 N2 A3 DQL3 F8 21
10 FBC_CMD<10> P8 A4 DQL4 H3 FBC_D<7> 7
10 P8 A4 DQL4 H3 17
24 P2 A5 DQL5 H8 22
22 FBC_CMD<22> R8 A6 DQL6 G2 FBC_D<6> 6
22 R8 A6 DQL6 G2 16
7 FBC_CMD<7> R2 A7 DQL7 H7 FBC_D<1> 1 FBC_CMD<7> FBC_D<23>
7 R2 A7 DQL7 H7 23
21 FBC_CMD<21> T8 A8 FBC_D<24..31> BI 63F4 FBC_CMD<21>
21 T8 A8
FBC_CMD<6> FBC_D<28> FBC_D<8..15> BI 63F4

6 R3 D7 28
A9 DQU0
6 FBC_CMD<6> R3 A9 DQU0 D7 FBC_D<9> 9
29 FBC_CMD<29> L7 A10_AP DQU1 C3 FBC_D<25> 25
29 L7 A10_AP DQU1 C3 14
23 FBC_CMD<23> R7 A11 DQU2 C8 FBC_D<30> 30
23 R7 A11 DQU2 C8 8
E 28 FBC_CMD<28> N7 C2 FBC_D<24> 24 E
A12_BC# DQU3
28 FBC_CMD<28> N7 A12_BC# DQU3 C2 FBC_D<15> 15
20 FBC_CMD<20> T3 A7 FBC_D<29> 29 P1V5S_DGPU
A13 DQU4
20 FBC_CMD<20> T3 A13 DQU4 A7 FBC_D<10> 10
4 FBC_CMD<4> T7 A14_NC DQU5 A2 FBC_D<26> 26
1
4 T7 A14_NC DQU5 A2 13
14 FBC_CMD<14> M7 A15 DQU6 B8 FBC_D<31> 31 R5113 FBC_CMD<14> FBC_D<11>
14 M7 A15 DQU6 B8 11
A3 FBC_D<27> 27 1.33K_1%_2
DQU7
DQU7 A3 FBC_D<12> 12
2
P1V5S_DGPU FBC_VREFDQ0
69B8 69B3 IN P1V5S_DGPU
1
12 FBC_CMD<12> M2 BA0 VDD_B2 B2
FBC_CMD<12>
12 M2 BA0 VDD_B2 B2
R5114 C5184
27 FBC_CMD<27> N8 BA1 VDD_D9 D9
FBC_CMD<27>
1.33K_1%_2 0.01UF_50V_2 27 N8 BA1 VDD_D9 D9
26 FBC_CMD<26> M3 BA2 VDD_G7 G7
FBC_CMD<26>
26 M3 G7
2
BA2 VDD_G7
VDD_K2 K2
VDD_K2 K2
VDD_K8 K8
VDD_K8 K8
2 FBC_CMD<2> K1 ODT VDD_N1 N1
FBC_CMD<2>
2 K1 ODT VDD_N1 N1
0 FBC_CMD<0> L2 CS# VDD_N9 N9
FBC_CMD<0>
0 L2 CS# VDD_N9 N9
30 FBC_CMD<30> J3 RAS# VDD_R1 R1
FBC_CMD<30>
D P1V5S_DGPU 30 J3 RAS# VDD_R1 R1 D
15 FBC_CMD<15> K3 CAS# VDD_R9 R9
FBC_CMD<15>
15 K3 CAS# VDD_R9 R9
1
13 FBC_CMD<13> L3 WE#
FBC_CMD<13>
13 L3 WE#
R5115
VDDQ_A1 A1
VDDQ_A1 A1
1.33K_1%_2
VDDQ_A8 A8
A8
2
VDDQ_A8
FBC_CMD<5> 69B8 69B3 IN FBC_VREFCA0

5 T2 C1
RESET# VDDQ_C1
FBC_CMD<5>
1
5 T2 RESET# VDDQ_C1 C1
VDDQ_C9 C9 R5116 C5185
VDDQ_C9 C9
3 FBC_CMD<3> K9 D2 1.33K_1%_2 0.01UF_50V_2
CKE VDDQ_D2
3 FBC_CMD<3> K9 CKE VDDQ_D2 D2
2
VDDQ_E9 E9
VDDQ_E9 E9
69C5 69C3 63C2 IN FBC_CLK0_DP J7 CK VDDQ_F1 F1

FBC_CLK0_DP
69C8 69C5 63C2 J7 F1
IN CK VDDQ_F1
69C5 69C3 63C2 IN FBC_CLK0_DN K7 CK# VDDQ_H2 H2

FBC_CLK0_DN
69C8 69C5 63C2 K7 H2
IN CK# VDDQ_H2
VDDQ_H9 H9
VDDQ_H9 H9
63D4 BI FBC_DQM<3> D3 DMU

FBC_DQM<1>
63D4 D3
BI DMU
VSS_A9 A9
VSS_A9 A9
C FBC_DQS3_DP 69C8 69C3 63C2 IN FBC_CLK0_DP FBC_DQS1_DP C
63C4 C7 B3
BI DQSU VSS_B3
C7 B3
2
63C4 BI DQSU VSS_B3
R5117
VSS_E1 E1
VSS_E1 E1
FBC_DQS3_DN
63C4 B7 G8
BI DQSU# VSS_G8
63C4 BI FBC_DQS1_DN B7 DQSU# VSS_G8 G8
FBC_CLK0_DN 162_1%_2
69C8 69C3 63C2
1
VSS_J2 J2 IN J2
VSS_J2
63D4 BI FBC_DQM<0> E7 DML VSS_J8 J8

FBC_DQM<2>
63D4 E7 J8
BI DML VSS_J8
VSS_M1 M1
P1V5S_DGPU VSS_M1 M1
63C4 BI FBC_DQS0_DP F3 DQSL VSS_M9 M9

FBC_DQS2_DP
63C4 F3 M9
BI DQSL VSS_M9
VSS_P1 P1
VSS_P1 P1
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
FBC_DQS0_DN
1UF_6.3V_2
1UF_6.3V_2
1
1
63C4 G3 P9
BI DQSL# VSS_P9
63C4 BI FBC_DQS2_DN G3 DQSL# VSS_P9 P9
C5186
C5187
C5188
C5189
C5190
C5191
VSS_T1 T1
VSS_T1 T1
R5112
1 2 L8 T9 R5118
ZQ VSS_T9
1 2 L8 ZQ VSS_T9 T9
2
2
243_1%_2 243_1%_2
J1 NC_J1 VSSQ_B1 B1
J1 NC_J1 VSSQ_B1 B1
L1 NC_L1 VSSQ_B9 B9
B P1V5S_DGPU L1 NC_L1 VSSQ_B9 B9 B
J9 NC_J9 VSSQ_D1 D1
J9 NC_J9 VSSQ_D1 D1
L9 NC_L9 VSSQ_D8 D8
L9 NC_L9 VSSQ_D8 D8
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
1
VSSQ_E2 E2
VSSQ_E2 E2
C5178
C5179
C5180
C5181
C5182
C5183
VSSQ_E8 E8
VSSQ_E8 E8
69E5 69B3 IN FBC_VREFDQ0 H1 VREFDQ VSSQ_F9 F9

FBC_VREFDQ0
69E5 69B8 H1 F9
IN VREFDQ VSSQ_F9
2
69D5 69B3 IN FBC_VREFCA0 M8 VREFCA VSSQ_G1 G1

FBC_VREFCA0
69D5 69B8 M8 G1
IN VREFCA VSSQ_G1
VSSQ_G9 G9
VSSQ_G9 G9
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
69F8 69F4 63E1 63B3 63A3 BI FBC_CMD<30..0>

F 70F4 70F8 69F8 69F4 63E1 63B3 63A3 FBC_CMD<30..0> F
BI
FBC_D<40..47> BI 63F4
U5009 FBC_D<32..39> BI 63F4
9 FBC_CMD<9> N3 A0 DQL0 E3 FBC_D<45> 45 U5010
9 FBC_CMD<9> N3 A0 DQL0 E3 FBC_D<37> 37
7 FBC_CMD<7> R2 A7 DQL7 H7 FBC_D<40> 40
7 FBC_CMD<7> R2 A7 DQL7 H7 FBC_D<32> 32
21 FBC_CMD<21> T8 A8
FBC_D<56..63> BI 63F4 21 FBC_CMD<21> T8 A8
6 FBC_CMD<6> R3 A9 DQU0 D7 FBC_D<57> 57 FBC_D<48..55> BI 63F4
6 FBC_CMD<6> R3 A9 DQU0 D7 FBC_D<49> 49
23 FBC_CMD<23> R7 A11 DQU2 C8 FBC_D<59> 59 P1V5S_DGPU
23 FBC_CMD<23> R7 A11 DQU2 C8 FBC_D<50> 50
28 FBC_CMD<28> N7 A12_BC# DQU3 C2 FBC_D<60> 60
1
E 28 FBC_CMD<28> N7 A12_BC# DQU3 C2 FBC_D<52> 52 E
20 FBC_CMD<20> T3 A13 DQU4 A7 FBC_D<56> 56 R5120
20 FBC_CMD<20> T3 A13 DQU4 A7 FBC_D<51> 51
4 FBC_CMD<4> T7 A14_NC DQU5 A2 FBC_D<63> 63 1.33K_1%_2
4 FBC_CMD<4> T7 A14_NC DQU5 A2 FBC_D<54> 54
2
14 FBC_CMD<14> M7 A15 DQU6 B8 FBC_D<58> 58
FBC_VREFDQ1
70B7 70B3 IN 14 FBC_CMD<14> M7 B8 FBC_D<48> 48
A15 DQU6
1
DQU7 A3 FBC_D<62> 62
R5121 C5199 DQU7 A3 FBC_D<55> 55
P1V5S_DGPU 1.33K_1%_2 0.01UF_50V_2
12 FBC_CMD<12> M2 BA0 VDD_B2 B2 P1V5S_DGPU
2
12 FBC_CMD<12> M2 BA0 VDD_B2 B2
VDD_K2 K2
VDD_K2 K2
VDD_K8 K8
VDD_K8 K8
18 FBC_CMD<18> K1 ODT VDD_N1 N1
P1V5S_DGPU 18 FBC_CMD<18> K1 ODT VDD_N1 N1
1
30 FBC_CMD<30> J3 RAS# VDD_R1 R1
R5122 30 FBC_CMD<30> J3 RAS# VDD_R1 R1
D 15 FBC_CMD<15> K3 CAS# VDD_R9 R9 D
1.33K_1%_2 15 FBC_CMD<15> K3 CAS# VDD_R9 R9
13 FBC_CMD<13> L3 WE#
2
FBC_VREFCA1 13 FBC_CMD<13> L3 WE#
A1 70B7 70B3 IN
VDDQ_A1
1
VDDQ_A1 A1
VDDQ_A8 A8 R5123 C5198
VDDQ_A8 A8
5 FBC_CMD<5> T2 RESET# VDDQ_C1 C1 1.33K_1%_2 0.01UF_50V_2
5 FBC_CMD<5> T2 RESET# VDDQ_C1 C1
2
VDDQ_C9 C9
VDDQ_C9 C9
VDDQ_E9 E9
VDDQ_E9 E9
VDDQ_H9 H9
H9
FBC_DQM<7> 70C7 70C3 63C2 IN FBC_CLK1_DP VDDQ_H9
63D4 D3
BI DMU
2
R5124 63D4 BI FBC_DQM<6> D3 DMU
VSS_A9 A9
VSS_A9 A9
63C4 BI FBC_DQS7_DP C7 DQSU VSS_B3 B3
162_1%_2 FBC_DQS6_DP
C FBC_CLK1_DN 63C4 BI C7 DQSU VSS_B3 B3 C
1
E1 70C7 70C3 63C2 IN
VSS_E1
VSS_E1 E1
VSS_J2 J2
VSS_M1 M1
VSS_M1 M1
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
FBC_DQS5_DP
1UF_6.3V_2
1UF_6.3V_2
1
1
63C4 F3 M9
BI DQSL VSS_M9
FBC_DQS4_DP F3
C5200
C5201
C5202
C5203
C5204
C5205
63C4 M9
P1
BI DQSL VSS_M9
VSS_P1
VSS_P1 P1
63C4 BI FBC_DQS5_DN G3 DQSL# VSS_P9 P9
FBC_DQS4_DN G3 P9
2
2
63C4 BI DQSL# VSS_P9
VSS_T1 T1
R5119 VSS_T1 T1
1 2 L8 ZQ VSS_T9 T9 R5125
1 2 L8 ZQ VSS_T9 T9
243_1%_2
243_1%_2
J1 NC_J1 VSSQ_B1 B1
P1V5S_DGPU J1 NC_J1 VSSQ_B1 B1
L1 NC_L1 VSSQ_B9 B9
L1 NC_L1 VSSQ_B9 B9
B J9 NC_J9 VSSQ_D1 D1 B
J9 NC_J9 VSSQ_D1 D1
L9 D8
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
NC_L9 VSSQ_D8
1UF_6.3V_2
1UF_6.3V_2
1
L9 NC_L9 VSSQ_D8 D8
C5192
C5193
C5194
C5195
C5196
C5197
VSSQ_E2 E2
VSSQ_E2 E2
VSSQ_E8 E8
VSSQ_E8 E8
2

VSSQ_G9 G9
VSSQ_G9 G9
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 9000~9999(SMALL BOARD)
D
POWER BUTTON D
SW9000 D9000
4 1 PHP_PESD5V2S2UT_SOT23_3P_DY 1 PAD9000
A B SMDPAD_1P_40X120 PWR_SWIN#_3
1
5 2
1
2
6 C D 3
C9000
MISAKI_NTC017_DA1G_E160T_6P 1000PF_50V_2_DY
2
PAD9001
3
1
SMDPAD_1P_40X120 GND
DGND_PWRSW_DB
P5V0S_PBN
C C
1 PAD9003
SMDPAD_1P_40X120 POWER
D9001
R9001 PWRBTN_LED#_L PAD9002
1 2 2 1 1
SMDPAD_1P_40X120 PWRBTN_LED#
150_5%_2
19_217_T1D_CP1Q2QY_3T
B B
FIX9000 FIX9001 FIX9002

1
FIX_MASK FIX_MASK FIX_MASK
S9000
1
SCREW540_700_NP_1P
1 S9001
SCREW540_700_NP_1P
A A
DGND_PWRSW_DB
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1000~1099(3D SENSOR) P3V3S_HDP
P3V3S_HDP
1
P5V0S C1002 C1003
1
U1001
1 GND Reserved 9
U1000 1UF_6.3V_2 0.1UF_10V_2 2 10
R1000 Vdd Reserved
GMT_G916T1UF_SOT23_5_5P HDP_XOUT 3 11
1 5 16.5K_1%_2 73B1 OUT VOUTX Reserved
2
IN OUT
73B6 OUT HDP_ST# 4 ST Vdd 12
1
73B1 OUT HDP_YOUT 5 VOUTY GND 13
4
12
SET
C1000 6 PD NC 14
3
GND
SHDN#
73B1 OUT HDP_ZOUT 7 VOUTZ NC 15
1
1UF_6.3V_2 8 16
FS NC
R1001
D C1001
10K_1%_2 ST_TSH35TR_LGA_16P
2
0.1UF_10V_2
D
2
2
P3V3S_HDP P3V3S_HDP
SSM3K7002BFU
2
R1011 R1010
1
4.7K_5%_2 4.7K_5%_2
Q1000
G
SSM3K7002BFU
1
22D3 22D2 5D3 BI EC_SMB1_CLK 3 D S 2 HDP_CLK BI 73B6
1
Q1001
C C
G
EC_SMB1_DATA HDP_DATA
22D3 22D2 5D3 3 2 73B2
BI D S
BI
P3V3S_HDP
P3V3S_HDP
P3V3S_HDP
1
C1015
1
2
2
0.1UF_10V_2
C1005 C1006
R1003 R1002 R1004
4.7K_5%_2 4.7K_5%_2 4.7K_5%_2 0.1UF_10V_2 0.1UF_10V_2
2
2
2
1
B P3V3S_HDP B
1
P3V3S_HDP
P3V3S_HDP
1
R1005
1
2
56.2K_1%_2 R1006 U1002

HDP_CLK HDP_DATA
NC
D1000 U1003 0_5%_2_DY 73C2 1 20 73C2

BI HDP_ST#
P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1 BI
2 19
NC
55B1 73D2 IN P3_7-CNTR0#-SSO-TXD1 P3_3-TCIN-INT3#-SSI00-CMP1_0

1 2
SLP_S3#_3R 3 1 2 4 3 18 HDP_YOUT
2
15B8 15B4 15A6 IN RESET# P1_0-KI0#-AN8-CMP0_0 IN 73D2

51D3 22D6 15D2 4 17 HDP_XOUT 73D2
XOUT-P4_7 P1_1-KI1#-AN9-CMP0_1 IN
- 5 VSS-AVSS P4_2-VREF 16
BAT54_30V_0.2A PHP_74LVC1G17_SOT753_5P 6 15 HDP_ZOUT
XIN-P4_6 P1_2-KI2#-AN10-CMP0_2 IN 73D2
C1007 7 14 HDP_LOC
3
VCC-AVCC P1_3-KI3#-AN11-TZOUT OUT 57B6

0.1UF_10V_2 TP1000
1
R1007 8 MODE P1_4-TXD0 13 1
HDP_INT# 1 2 9 12 TP1001
TP30 1
2
22B6 IN P4_5-INT0#-RXD1 P1_5-RXD0-CNTR01-INT11#

10 11 HDP_ACT C1008
P1_7-CNTR00-INT10# P1_6-CLK0-SSI01 TP30 IN 22D6
1
1K_5%_2 RENESAS_R5F211B4D34SP_LSSOP_20P 0.033UF_16V
1
R1008
2
R1009
47K_5%_2 C1009
47K_5%_2
0.033UF_16V
1
2
2
C1010
A 0.033UF_16V A
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 390~399
D
D
CIR
P5V0AL
C C
100_5%_2
R390
1
CIR_OUT D390
22B6 4
OUT OUT
3 VS
2 GND
1
1 GND
C390 VISHAY_TSOP6238_SMD_4P
4.7UF_6.3V_3
2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S_USB3_DB CN2406
P5V0A_USB3_DB
75C8 USB3_CN_RX1_DN1
BI USB3_CN_RX1_DP 2
1
75C8 BI 2
2
75D7 BI USB3_CN_TX1_DN 3 3
USB3_CN_TX1_DP 4
1
R2409 R2411 R2449 75D7 BI 4
RSC_0402_DY RSC_0402_DY RSC_0402_DY 75C3 BI USB2_CN_TX1_DN 5 5 P5V0A_DB
USB2_CN_TX1_DP 6 C2407
+
75C3 BI 6
7 7
CURRENT LIMIT 2.5A 100UF_6.3V
2 1
2 1
2 1
75A8 BI USB3_CN_RX2_DN8 8
USB3_CN_RX2_DP 9
2
75A8 BI 9 U2404
75A7 P3V3S_USB3_DB USB3_CN_TX2_DN10 1 8 DGND_USB3_DB
R2412 R2450 BI USB3_CN_TX2_DP11
10 GND OUT
P3V3S_USB3_DB R2407 75A7 2 7
RSC_0402_DY RSC_0402_DY BI USB2_CN_TX2_DN12
11 IN OUT
RSC_0402_DY 75B3 3 6
BI USB2_CN_TX2_DP13
12
SB_USB_1_DB
IN OUT
75B3 75D4 4 5USB_OC#_1_DB 75D4
BI 13 IN EN OC# OUT
1
14
1
14
R2401 SB_USB_1_DB 15 GMT_G547E1P81U_MSOP_8P
1 2 75D3 IN 15
D P5V0A_DB 75D1 USB_OC#_1_DB 16 G1 C2430
DGND_USB3_DB OUT 16 G
47UF_6.3V_5
10K_5%_2 17 17 G G2 D
18 18
19
2
19
DGND_USB3_DB 20 20
1
6
5
4
3
2
U2411 DGND_USB3_DB
TI_SN65LVPE502RGER_QFN_24P
ACES_50501_02041_001_20P
GND
EN_RXD
VCC
OS1
DE1
EQ1
TML 25
7 24 DGND_USB3_DB
NC NC
75D4 BI USB3_CN_TX1_DN 8 RX- TX1- 23 USB3_DB_TX1_DNC2508
1 0.1UF_16V_2
2 USB3_DB_TX1_C_DN BI 75C3
75D4 BI USB3_CN_TX1_DP 9 RX+ TX1+ 22 USB3_DB_TX1_DP C2507
1 0.1UF_16V_2
2 USB3_DB_TX1_C_DP BI 75C3
10 GND GND 21 P5V0A_USB3_DB
75D4 BI USB3_CN_RX1_DN 1
C2506 0.1UF_16V_2
2 USB3_C_RX1_DN 11 TX2- RX2+ 20 USB3_DB_RX1_DP BI 75C3
75D4 BI USB3_CN_RX1_DP 1
C2505 0.1UF_16V_2
2 USB3_C_RX1_DP 12 TX2+ RX2- 19 USB3_DB_RX1_DN BI 75C3
GND
VCC
OS2
EQ2
DE2
CM
1
P3V3S_USB3_DB P3V3S_USB3_DB
13
2 14
15
16
17
18
C2495 C2496 C2497
DGND_USB3_DB
1
2
22UF_6.3V_5 0.1UF_16V_2 1000PF_50V_2
2
C2504 R2402
R2421 R2426 R2428 L2402
0.1UF_16V_2 10K_5%_2 CN2403
RSC_0402_DY RSC_0402_DY RSC_0402_DY WCM_2012_900T 1 VBUS DGND_USB3_DB
C 75D4 USB2_CN_TX1_DN
1 USB2_DB_TX1_DN
2 2 C
1
BI D-
2
1
75D4 BI USB2_CN_TX1_DP
4 USB2_DB_TX1_DP
3 3 D+
4 PGND
2
DGND_USB3_DB DGND_USB3_DB USB3_DB_RX1_DN 5
75C5 BI SSRX-
75C5 BI USB3_DB_RX1_DP 6 SSRX+ G G1
R2425 R2429 R2434 7 G2
GND G
RSC_0402_DY RSC_0402_DY RSC_0402_DY USB3_DB_TX1_C_DN 8 G3
75D4 BI SSTX- G
75D4 BI USB3_DB_TX1_C_DP 9 SSTX+ G G4
1
OCTEK_USB_09EREB_9P
DGND_USB3_DB
DGND_USB3_DB DGND_USB3_DB
P3V3S_USB3_DB
P5V0A_USB3_DB
2
R2419 R2417
R2413
P3V3S_USB3_DB RSC_0402_DY RSC_0402_DY
1
RSC_0402_DY
B B
C2449
C2450
2 1
2 1
2 1
C2439
2
0.1UF_16V_2 1000PF_50V_2
22UF_6.3V_5
2
R2404 R2420 R2418
R2414
10K_5%_2 RSC_0402_DY RSC_0402_DY
RSC_0402_DY L2405 DGND_USB3_DB
CN2404
WCM_2012_900T 1 VBUS
51
1
DGND_USB3_DB 75D4 BI USB2_CN_TX2_DN 1 2 USB2_DB_TX2_DN
2 D-
1
6
4
3
2
U2412 DGND_USB3_DB 75D4 BI USB2_CN_TX2_DP 4 3 USB2_DB_TX2_DP

3 D+
TI_SN65LVPE502RGER_QFN_24P 4 PGND
GND
EN_RXD
VCC
OS1
DE1
EQ1
75A5 BI USB3_DB_RX2_DN 5 SSRX-

25
TML
75A5 BI USB3_DB_RX2_DP 6 SSRX+ G G1
7 NC NC 24
7 G2
75D4 BI USB3_CN_TX2_DN 8 RX- TX1- 23 USB3_DB_TX2_DNC2512
1 0.1UF_16V_2
2 USB3_DB_TX2_C_DN BI 75A2 USB3_DB_TX2_C_DN
GND G
75A4 8 G3
75D4 BI USB3_CN_TX2_DP 9 RX+ TX1+ 22 USB3_DB_TX2_DP C2513
1 0.1UF_16V_2
2 USB3_DB_TX2_C_DP BI 75A2 BI USB3_DB_TX2_C_DP
SSTX- G
75A4 9 G4
10 GND GND 21 BI SSTX+ G
75D4 BI USB3_CN_RX2_DN 1
C2510 20.1UF_16V_2 USB3_C_RX2_DN 11 TX2- RX2+ 20 USB3_DB_RX2_DP BI 75A2 OCTEK_USB_09EREB_9P
75D4 BI USB3_CN_RX2_DP 1
C2511 20.1UF_16V_2 USB3_C_RX2_DP 12 TX2+ RX2- 19 USB3_DB_RX2_DN BI 75B2
GND
VCC
OS2
EQ2
DE2
CM
DGND_USB3_DB DGND_USB3_DB
13
14
15
16
17
18
A P3V3S_USB3_DB A
P3V3S_USB3_DB DGND_USB3_DB
2
R2443 R2445
1
R2441
RSC_0402_DY RSC_0402_DY
RSC_0402_DY
2
C2509
0.1UF_16V_2
R2403
2 1
2 1
2 1
10K_5%_2
INVENTEC
2
R2444 R2448
R2442
1
RSC_0402_DY RSC_0402_DY
DGND_USB3_DB RSC_0402_DY
DGND_USB3_DB TITLE
1
Block Diagram
DGND_USB3_DB DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
3D/ECO VISION D
SW9001
4 1 1 PAD9005
A B SMDPAD_1P_40X120 ECO_BTN#
1
2
5 2
6 C D 3 C9003
1000PF_50V_2_DY
MISAKI_NTC017_DA1G_E160T_6P
PAD9006
1 GND
2
SMDPAD_1P_40X120
D9003
C C
DGND_PWRSW_DB
P5V0S_PBN
1 PAD9007
SMDPAD_1P_40X120 POWER
D9002
R9002 ECO_LED#_L PAD9008
1 2 2 1 1
SMDPAD_1P_40X120 ECO_LED#
150_5%_2
19_217_T1D_CP1Q2QY_3T
B B
FIX9003 FIX9004 FIX9005

1
1
FIX_MASK FIX_MASK FIX_MASK
S9002
1
SCREW540_700_NP_1P
1 S9003
SCREW540_700_NP_1P
DGND_PWRSW_DB
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1

L875 GL10FG 6050a2492401-Mb 20110831

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8 7 6 5 4 3 2 1

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

F HSF Property:ROHS or Halogen-Free(5L3?) F

PAGE PAGE PAGE

1. COVER PAGE 26. SPEAKER/HP JACK/MIC JACK 51. CPU 5 POWER

7. POWER +V1.5/+V0.75 32. SATA HDD/ODD CONN

EDP INTERNAL MIC IN

A ENE-P2809A EC WINDBOND SPI SPI FLASH 4MB

THERMAL SENSOR NPCE885LA0DX

BATTERY CHARGER &

ADAPTOR +VBAT +V5A_+-5% +V5S

FUSE BQ24725RGRR TPS51123 AO6402L

NMOS_4D3S NMOS_4D3S NMOS_4D3S

PVADPTR POWERPAD_2_0610 TP30 TP30 TP30

4.3K_5%_2 4.3K_5%_2 BAT54C_30V_0.2A

470PF_50V_2 4.7UF_25V_5 4.7UF_25V_5 CSC0805_DY

R6114 7 VO2 VO1 24

R6100 RSC_0603_DY 15C6 OUT VRP3V3A_LDO RSC_0603_DY TP30

330UF_6.3V VRP5V0A_VIN VRP5V0A_LDO

15B7 EN_VCCP PVBAT

VSS_SENSE_VCCIO 0_5%_2_DY VRP1V0_VCCP_LG

SA_PG 15A6 22B6

R6620 R6622 PVBAT PAD6610

R6711 50B1 11A3 BI VDIO TI_TPS51650RSLR_QFN_48P CDL2

17.8K_1%_2 100K_5%_NTC 28.7K_1%_2

R6713 0_5%_2 L6620

22D3 EN_PVCORE R6731

R6730 P3V3A P1V0S_VCCP

11D7 11D6 11D4 11C8 11B7 11A4 IN

11B7 AXG_PG 50B1 11C7 VR_SVID_DATA

1 2 1 2 R6707 R6708 R6709

11B5 GPWM2 3 6 L6720

3900PF_16V_2 6.8K_1%_2 1 R6774 2 GPU_SENSE OUT 13A6

R6755 TML 41 62K_1% 220K_5%_NTC

DGPU_VID0 IN 66C2 66C4

62C2 1 2 66C2 66C4

0_5%_2 DGPU_VID2 G_CSN1

1 2 DGPU_VID4 IN 66C2 66D4

DGPU_VID5 IN 66C2 66C4

14C4 IN LNB_EN 2 VC VADJ 4 1 G

VCCIO VCCSA DGPU P1V8S

55B1 47K_5%_2 C7040 10K_5%_2

22B6 15A6 10A5 22B6 15A6 10A5 SA_PG SA_PG PAD6752

P15V0A P3V3AL 1 TP7103

P5V0A 0_5%_2 Q7106

AON7410 NVIDIA OPTIMUS

58C7 57B6 17B7 17B5 IN DGPU_PWR_EN# 1 G SSM3K7002BFU

REFERENCE 0~49(PCB SCREW)

PCB CPU GPU WLAN

REFERENCE 50-99(HALL SENSOR)

D SUSPEND LED P3V3A

POWER ON LED P5V0S

DC IN / BATTERY CHARGE LED

REFERENCE 200~249(POWER CONN)

P5V0S Q250 CN251

P3V3AL P3V3AL_R P3V3S P3V3AL

22E8 5B7 IN BI 29C3 53C3

41B1 40A1 107

21C3 IN GPIO24 GPIO27/PSDAT2

7 1 R314 2 3.3K_5%_2 1UF_6.3V_2

3 6 EC_SPI_CLK 22C7 22D6

EC_SPI_SO 2 17 R325 3.3K_5%_2_DY

53A6 3 6 EC_SPI_CLK 22C7 22D6