CS6303 Computer Architecture Instruction Set and Addressing Modes

CS6303 COMPUTER ARCHITECTURE DEPARTMENT OF EIE 2017 - 2018
CS6303 COMPUTER ARCHITECTURE
UNIT I OVERVIEW & INSTRUCTIONS

PART A
1. List the eight great ideas invented by computer architects. (May 2015)
i. Design for Moores Law
ii. Use Abstraction to Simplify Design
iii. Make the Common Case Fast
iv. Performance via Parallelism
v. Performance via Pipelining
vi. Performance via Prediction
vii. Hierarchy of Memories
viii. Dependability via Redundancy
2. Distinguish pipelining from parallelism. (May 2015)

Pipelining is a method of increasing system performance and throughput. It takes advantage of the
inherent parallelism in instructions. Instructions are divided into 5 stages: IF, ID, EX, EME, WB.
Parallelism means we are using more hardware for the executing the desired task. In Parallel computing
more than one processors are running in parallel. It increases performance but the area also increases.
3. What is Instruction set architecture (ISA)? (Nov 2015)

The ISA serves as the boundary between the software and hardware. It is the structure of a computer
that a machine language programmer (or a compiler) must understand to write a correct (timing
independent) program for that machine. It also specifies a processors functionality what operations it
supports what storage mechanisms it has & how they are accessed how the programmer/compiler
communicates programs to processor.
4. How CPU execution time for a program is calculated? / Give the formula for CPU execution time
for a program. (Nov 2015 / Nov 2016)
CPU execution time for a program = CPU clock cycles for a program x clock cycle time
CPU clock cycles for a program
CPU execution time for a program =
5. How to represent instruction in a computer system? (May 2016)

The figure shows the simple instruction format having three fields: opcode, operand address1, operand
address2.
Opcode Operand address1 Operand address2
4 bits 6 bits 6 bits
6. Distinguish between auto increment and auto decrement addressing mode. (May 2016)
Auto increment addressing mode: The effective address of the operand is the contents of a register
specified in the instruction. After accessing the operand, the contents of this register are incremented to
address the next location. Ex: MOV R0, (R2)+
Auto decrement addressing mode: The contents of a register specified in the instruction are decremented
and then they are used as an effective address to access a memory location.
Ex: MOV (R0),R1
7. State Amdahls Law.(Nov 2014)

Amdahls Law tells us the improvement expected from specific enhancements. The performance
improvement or speedup due to improvement is calculated as follows
Speedup = Execution time before improvement / Execution time after improvement
1
JERUSALEM COLLEGE OF ENGINEERING
8. Brief about relative addressing mode with an example. (Nov 2014)

In relative addressing mode, the referenced register is program counter (PC). The effective address is
determined by adding the contents of PC to the address field.
EA = PC + Address part of instruction. Its most common use is to specify the target address in branch
instructions.
Ex: JNZ BACK : This instruction causes program execution to go to the branch target location identified
by the name BACK, if the branch condition is satisfied.
9. What is an instruction register? (Nov 2016)

An instruction register (IR) is the part of a CPU's control unit that holds the instruction currently being
executed. The output of IR is available to control circuits which generate the timing signals that control the
various processing elements involved in executing the instruction.
10. List the major components of a computer system? (May 2017)

i. Input unit
ii. Output unit
iii. Control unit
iv. Memory unit
v. Arithmetic and logic unit
11. State the need for indirect addressing mode. Give an example. (May 2017)
The effective address of the operand is the contents of a register. We denote the indirection by the name
of the register or new address given in the instruction. Address of an operand (B) is stored into R1 register.
If we want this operand, we can get it through register R1 (indirection).
Ex: MOV A, (R0)
12. Define addressing modes and its various types.

The different ways in which the location of a operand is specified in an instruction is referred to as
addressing modes. The various types are Immediate Addressing, Register Addressing, Based or
Displacement Addressing, PC-Relative Addressing, Pseudodirect Addressing.
13. What is program counter?

The program counter (PC) keeps track of the execution of a program. It contains the memory address
of the next instruction to be fetched and executed.
14. What is RISC and CISC?

The processors with simple instructions are called as Reduced Instruction Set Computers (RISC). The
processors with more complex instructions are called as Complex Instruction Set Computers (CISC).
15. List out the methods used to improve system performance?

The methods used to improve system performance are
Processor clock
Basic Performance Equation
Pipelining
Clock rate
Instruction set
Compiler
16. Define register mode addressing.
In register mode addressing, the name of the register is used to specify the operand. Eg. add $s3,$s5,$s6.
Advantage: Only a small address field is needed in the instruction and no memory is referenced.
Disadvantage: Address space is very limited.
2
17. Define Based or Displacement mode addressing.

In based or displacement mode addressing, the operand is in a memory location whose address is the sum
of a register and a constant in the instruction. Eg. lw $t0,32($s3).
18. What is superscalar execution?

In this type of execution, multiple functional units are used to create parallel paths through which
different instructions can be executed in parallel. So it is possible to start the execution of several
instructions in every clock cycle. This mode of operation is called superscalar execution.
19. Define CPI.

The term clock cycles per instruction is the average number of clock cycles each instruction takes to
execute, is often abbreviated as CPI.
CPI = CPU clock cycles / Instruction count
20. Define MIPS.

MIPS is a way to measure the processor speed. The processor speed can be measured in terms of
millions instructions per second (MIPS). It is given by
MIPS rate = 1/ (Average time required for the execution of instruction x 106)
PART B
1. What is an addressing mode? What is the need for addressing in a computer system? Explain the various
addressing modes with suitable examples. / Explain direct, immediate, relative and indexed addressing
mode with examples. (May 2017 / May 2015 / Nov 2015 / May 2016 / Nov 2016)
2. Explain in detail the various components of computer system with neat diagram. (Nov 2014 / Nov 2015 /
May 2016 / Nov 2016)
3. Discuss about the various techniques to represent instructions in a computer system. (May 2015)
4. State the CPU performance equation and discuss the factors that affect performance. (Nov 2014)
5. Explain the important measures of the performance of a computer and derive the basic performance
equation. (May 2017)
6. Explain in detail about the eight ideas of computer architecture.
7. Describe the MIPS Instruction set in detail with suitable examples.
8. i) Assume a two address format specified as source, destination. Examine the following sequence of
instructions and explain the addressing modes used and the operation done in every instruction.
i. Move (R5)+, R0
ii. Add (R5)+, R0
iii. Move R0, (R5)
iv. Move 16(R5), R3
v. Add #40, R5 (Nov 2014)
ii) Consider the computer with three instruction classes and CPI measurements as given below and
Instruction counts for each instruction class for the same program from two different compilers are given.
Assume that the computers clock rate is 4GHZ. Which Code sequence will execute faster according to
execution time? (Nov 2014)
Code from CPI for this instruction class
A B C
CPI 1 2 3
Code from Instruction count for each class
A B C
Compiler 1 2 1 2
Compiler 2 4 1 1
3
UNIT II ARITHMETIC OPERATIONS
PART A
1. Define Little Endian arrangement. (Nov 2014)
Little-endian describes the order in which a sequence of bytes is stored in computer memory. Little-
endian is an order in which the "little end" (least significant value in the sequence) is stored first. For
example, in a little-endian computer, the two bytes required for the hexadecimal number 4F52 would be
stored as 524F (52 at address 1000, 4F at 1001).
2. What do mean by Subword Parallelism? (May 2015 / May 2016)

Subword parallelism is a technique that enables the full use of word-oriented data paths when dealing
with lower precision data. It is a form of low-cost, small-scale SIMD parallelism.
3. How overflow occur in subtraction? (May 2015)

When overflow occurs on integer addition and subtraction, contemporary machines invariably discard
the high-order bit of the result and store the low-order bits that the adder naturally produces. Signed integer
overflow of addition occurs if and only if the operands have the same sign and the sum has a sign opposite
to that of the operands.
4. What are the overflow/underflow conditions for addition and subtraction? (Nov 2015)
Overflow / underflow conditions will occur when result cannot be represented in the allocated number
of bits. Overflow occurs if the Result > Max value. Underflow occurs if the Result < Min value. Overflow
can occur when two positive numbers are added and result is out of range. After addition, the result will
become negative. Underflow can occur when two negative numbers are added and result is out of range.
After addition, the result will become positive. While adding a positive number with a negative number. No
overflow or underflow can occur.
Unsigned number representation using n-bits
Overflow when result > 2n 1.
Underflow when result < 0.
Signed number representation using n-bits
Overflow when result > 2n1 1.
Underflow when result < 2n1.
5. State the representation of double precision floating point number. (Nov 2015)
Double precision representation contains 1 sign bit, 11 exponent bits and 52 Mantissa nits. It is also
called excess -1023 format. Exponent E which has the range 0 E 2047 for normal values. This means
that the actual exponent E is in range -1022 E 1023.
6. Define ALU. (May 2016)

The Arithmetic and Logic Unit (ALU) is responsible for performing arithmetic operations such as add,
subtract, division and multiplication and logical operations such as AND, OR, NOT etc.
7. What is guard bit? What are the ways to truncate the guard bits? (Nov 2016)
Although the mantissa of initial operands is limited to 24 bits, it is important to retain extra bits. These
extra bits are called as guard bits. There are several ways to truncate the guard bits: Chopping, Von
Neumann rounding, Rounding.
8. What is arithmetic overflow? (Nov 2016)

In a computer, the condition that occurs when a calculation produces a result that is greater in magnitude
than which a given register or storage location can store or represent.
4
9. Write the rules to perform addition on floating point numbers? (May 2017)
i. Choose the number with the smaller exponent and shift its mantissa right a number of steps equal
to the difference in exponents.
ii. Set the exponent of the result equal to the larger exponent
iii. Perform addition on the mantissa and determine the sign of the result
iv. Normalize the resulting value, if necessary
10. Subtract (11010)2 (10000)2 using 1s complement and 2s complement method. (May 2017)
(11010)2 (10000)2 = (1010)2
11. Define Full Adder (FA) with logic diagram.

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder
adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried
in (from a past addition).The full-adder is usually a component in a cascade of adders, which add 8, 16, 32,
etc.
12. Why floating point number is more difficult to represent and process than integer?
In floating point numbers we have to represent any number in three fields sign, exponent and mantissa.
The IEEE 754 standard gibes the format for these fields and according to format the numbers are to be
represented. In case of any process the mantissa and exponent are considered separately.
13. When can you say that a number is normalized?

When the decimal point is placed to the right of the first (nonzero) significant digit the number is said
to be normalized.
14. Define Booth Algorithm.

Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers
in two's complement notation. Booth's algorithm can be implemented by repeatedly adding (with ordinary
unsigned binary addition) one of two predetermined values A and S to a product P, then performing a
rightward arithmetic shift on P.
15. What are generate and propagate function?

The generate function is given by Gi=xiyi and the propagate function is given as Pi=xi+yi.
16. Write the rules for multiply operation on floating point numbers?
Add the exponents and subtract 127.
Multiply the mantissa and determine the sign of the result.
Normalize the resulting value, if necessary.
17. Define Truncation.

To retain maximum accuracy, all extra bits during operation (called guard bits) are kept (e.g.,
multiplication). If we assume n=3 bits are used in final representation of a number, n=3extra guard bits are
kept during operation. By the end of the operation, the resulting 2n=6 bits need to be truncated to n=3 bits
by one of the three methods.
18. Write the IEEE 754 floating point format?

Single precision representation
S (Sign) E (Exponent) M (Mantissa)
1 bit 8 bit 23 bit
Double precision representation

S (Sign) E (Exponent) M (Mantissa)
1 bit 11 bit 52 bit
5
19. Draw the half adder circuit?
20. Draw the full adder circuit?
PART B
1. Explain the Booths algorithm for multiplication of signed twos complement numbers. / Define Booth
Multiplication algorithm with suitable example. (Nov 2016 / May 2016)
2. Discuss in detail about division algorithm in detail with diagram and examples. / Describe non restoring
division with an example. (Nov 2015 / Nov 2016 / May 2017)
3. Explain the sequential version of multiplication algorithm and its hardware. / Explain in detail about the
multiplication algorithm with suitable example and diagram. (May 2015 / Nov 2015 / May 2017)
4. Explain how floating point addition is carried out in a computer system. Give an example for a binary
floating point addition. / Explain briefly about floating point addition and subtraction algorithm. (May 2015
/ May 2016)
5. Divide (12)10 by (3)10 using the Restoring and Non restoring division algorithm with step by step
intermediate results and explain. (Nov 2014)
6. i) What is the disadvantage of ripple carry addition and how it is overcome in carry look ahead adder and
draw the logic circuit CLA? / Briefly explain Carry Look ahead adder. (Nov 2014 / Nov 2016)
ii) What is meant by subword parallelism? Explain. (May 2017)
7. i) Design an arithmetic element to perform the basic floating point operations. (May 2017)
ii) Multiply the following pair of signed nos. using Booths bit-pair recoding of the multiplier.
A = +13 (Multiplicand) and B = -6 (Multiplier). (Nov 2014)
8. Discuss about IEEE 754 standard for floating point operations.
6
UNIT III PROCESSOR AND CONTROL UNIT

PART A
1. What are R-type instructions? (May 2015)

R instructions are used when all the data values used by the instruction are located in registers. All R-
type instructions have the following format: OP rd, rs, rt. Where "OP" is the mnemonic for the particular
instruction. rs and rt are the source registers, and rd is the destination register.
2. What is a branch prediction buffer? (May 2015)

The buffer in which the recent branch information is stored is called branch prediction buffer.
3. What is meant by branch prediction? (Nov 2015)

Branch Instructions may introduce branch penalty. To avoid it, branch prediction is done by two ways.
Static Branch prediction
The static branch prediction, assumes that the branch will not take place and to continue to fetch instructions
in sequential address order.
Dynamic Branch prediction
The idea is that the processor hardware assesses the likelihood of a given branch being taken by keeping
track of branch decisions every time that instruction is executed. The execution history used in predicting
the outcome of a given branch instruction is the result of the most recent execution of that instruction.
4. What is a hazard? What are its types? (Nov 2015 / May 2017)
Any condition that causes the pipeline to stall is called hazard. They are also called as stalls or bubbles.
The various pipeline hazards are:
Data hazard
Structural Hazard
Control Hazard.
5. Define exception. (May 2016 / Nov 2014)

The term exception is used to refer to any event that causes an interruption otherwise an unexpected
change in the control flow. When an exception or interrupt occurs, the hardware begins executing code
that performs an action in response to the exception. This action may involve killing a process, outputting
a error message, communicating with an external device.
6. What are the advantages of pipelining? (May 2016)

The instruction cycle time of the processor is reduced increasing, instruction throughput.
Increase in pipeline stages increase number of instructions that can be processed at once which
reduces delay between completed instructions.
7. What is meant by pipeline bubble? (Nov 2016)

To resolve the hazard the pipeline is stall for 1 clock cycle. A stall is commonly called a pipeline
bubble, since it floats through the pipeline taking space but carrying no useful work.
8. What is a data path? (Nov 2016)

As instruction execution progress, data are transferred from one instruction to another, often passing
through the ALU to perform some arithmetic or logical operations. The registers, ALU, and the
interconnecting bus are collectively referred as the data path.
7
9. Give an example for data hazard. (May 2017)

Consider a program with two instructions, I1 followed by I2. When this program is executed in a
pipeline, the execution of these instructions can be performed concurrently. In such case the result of I1
may not be available for the execution of I2. If the result of I2 is dependent on the result of I1 we may get
incorrect result if both are executed concurrently.
10. Name the control signals required to perform arithmetic operations. (May 2017)
Set muxes to correct input
Operation code to ALU
Read and write to register file
Read and write to memory (load/store)
Update of program counter
11. What is meant by pipeline bubble?

To resolve the hazard, the pipeline is stall for 1 clock cycle. A stall is commonly called a pipeline
bubble, since it floats through the pipeline taking space but carrying no useful work.
12. What is meant by data hazard in pipelining?

Any condition in which either the source or the destination operands of an instruction are not
available at the time expected in the pipeline is called data hazard.
13. What is Instruction or control hazard?

The pipeline may be stalled because of a delay in the availability of an instruction. For example, this
may be a result of a miss in the cache, requiring the instruction to be fetched from the main memory. Such
hazards are often called control hazards or instruction hazard.
14. Define structural hazards.

This is the situation when two instruction require the use of a given hardware resource at the same
time. The most common case in which this hazard may arise is in access to memory.
15. Define Pipeline speedup.

The ideal speedup from a pipeline is equal to the number of stages in the pipeline.
Speedup= Time per instruction on unpipelined machine / Number of pipe stages
16. Why is branch prediction algorithm needed?

The branch instruction will introduce branch penalty which would reduce the gain in performance
expected from pipelining. Branch instructions can be handled in several ways to reduce their negative
impact on the rate of execution of instructions. Thus the branch prediction algorithm is needed.
17. What is pipelining?

The technique of overlapping the execution of successive instruction for substantial improvement in
performance is called pipelining.
18. What are the major characteristics of a pipeline?

The major characteristics of a pipeline are:
Pipelining cannot be implemented on a single task, as it works by splitting multiple tasks into a
number of subtasks and operating on them simultaneously.
The speedup or efficiency achieved by suing a pipeline depends on the number of pipe stages and
the number of available tasks that can be subdivided.
8
19. What are the types of data hazards?

RAW (read after write) hazard
WAW (write after write) hazard
WAR (write after read) hazard
20. How addressing modes affect the instruction pipeling?

Degradation of performance is an instruction pipeline may be due to address dependency where
operand address cannot be calculated without available information needed by address mode for e.g. an
instructions with register indirect mode cannot proceed to fetch the operand if the previous instructions is
loading the address into the register. Hence operand access delay degrades the performance of pipeline.
PART B
1. Explain Data path and its control in detail. (Nov 2014)
2. What is Hazard? Explain its types with suitable examples. / Explain the different types of pipeline hazards
with suitable examples. (Nov 2014 / May 2016 / Apr 2015)
3. What is pipelining? Discuss about pipelined data path and control. (May 2016 / May 2017)
4. Explain how the instruction pipeline works? What are the various situations where an instruction pipeline
can stall? Illustrate with an example. (Nov 2015 / Nov 2016)
5. Explain the basic MIPS implementation with necessary multiplexers and control lines. (Nov 2015)
6. Why is branch prediction algorithm needed? Differentiate between the static and dynamic techniques. (Nov
2016)
7. Explain in detail how exceptions are handle in MIPS architecture.(April 2015)
8. i) Explain the hazards caused by unconditional branching statements. (May 2017)

ii) Describe operand forwarding in a pipeline processor with a diagram. (May 2017)
9
UNIT IV PARALLELISM
PART A
1. What is Instruction level parallelism (ILP)? (Nov 2015 / May 2016 / May 2017 / Nov 2016)
ILP is a measure of how many of the operations in a computer program can be performed
simultaneously. The potential overlap among instructions is called instruction level parallelism. There are
two primary methods for increasing the potential amount of instruction-level parallelism. 1. Increasing the
depth of the pipeline to overlap more instructions. 2. Multiple issue.
2. What is Flynns Classification? (Nov 2014)

Michael Flynn uses the stream concept for describing a machines structure. A stream is nothing but a
sequence of items (data or instruction). Flynn divides computers into four major groups
i. Single Instruction, Single Data stream (SISD)
ii. Single Instruction, Multiple Data streams (SIMD)
iii. Multiple Instruction, Single Data stream (MISD)
iv. Multiple Instruction, Multiple Data streams (MIMD)
3. What is the need for Speculation? (Nov 2014)

It is one of the most important methods for finding and exploiting more ILP. It is an approach that
allows the compiler or the process to guess about the properties of an instruction, so as to enable execution
to begin for other instructions that may depend on the speculated instruction.
4. Compare UMA and NUMA multiprocessors.(May 2015)

The main difference between the NUMA and UMA memory architecture is the location of the Memory.
The UMA architecture nodes have first and second cache memory levels joint with the processor, next
levels of the memory hierarchy are "in the other side" of the interconnection network. The NUMA
architecture defines the node as the Processing Element, with cache lines and a part of the main memory.
Then, each node is connected to each other by the network.
5. Differentiate between Strong scaling and weak scaling.(May 2015)

Strong scaling:
Speed-up is achieved on a multi-processor without increasing the size of the problem.
Weak scaling:
Speed-up is achieved on a multi-processor while increasing the size of the problem proportionally to the
increase in the number of processors.
6. Define a superscalar processor. (Nov 2015)

Superscalar is an advanced pipelining technique that enables the processor to execute more than one
instruction per clock cycle by selecting them during execution. Dynamic multiple-issue processors are also
known as superscalar processors, or simply superscalars.
7. What is Fine grained multithreading? (May 2016)

Switches between threads on each instruction, causing the execution of multiples threads to be
interleaved,
i. Usually done in a round-robin fashion, skipping any stalled threads.
ii. CPU must be able to switch threads every clock.
iii.
8. What is multithreading? (Nov 2016 / Nov 2014)
Multithreading allows multiple threads to share the functional units of a single processor in an overlapping
fashion. To permit this sharing, the processor must duplicate the independent state of each thread.
10
9. Distinguish implicit multithreading and explicit multithreading. (May 2017)

Implicit multithreading: Implicit multithreading refers to concurrent execution of multiple threads
extracted from a sequential program.
Explicit multithreading: Explicit multithreading refers to concurrent execution of instructions from
different explicit threads, either by interleaving instructions from different threads on shared pipelines or
by parallel execution on parallel pipelines.
10. Define Static multiple issue.

It is an approach to implement a multiple-issue processor where many decisions are made by the
compiler before execution.
11. Define Dynamic multiple issue.

It is an approach to implement a multiple-issue processor where many decisions are made during
execution by the processor.
12. What is Speculation?

One of the most important methods for finding and exploiting more ILP is speculation. It is an approach
whereby the compiler or processor guesses the outcome of an instruction to remove it as dependence in
executing other instructions. For example, we might speculate on the outcome of a branch, so that
instructions after the branch could be executed earlier.
13. What is Loop unrolling?

It is a technique to get more performance from loops that helps in accessing the arrays, in which multiple
copies of the loop body are made and instructions from different iterations are scheduled together.
14. Define Register renaming.

The renaming of registers is done by the compiler or hardware to remove anti-dependences. Renaming
removes WAW/WAR hazard.
15. Define Multicore processors.

A multi-core processor is a processing system composed of two or more independent cores. The cores
are typically integrated onto a single integrated circuit die or they may be integrated onto multiple dies in a
single chip package.
16. Define Commit unit.

It is a unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the
result of an operation to programmer visible registers and memory.
17. Define Out of order execution.

A situation in pipelined execution when an instruction blocked from executing does not cause the
following instructions to wait is called Out of order execution.
18. What is Speculation?

One of the most important methods for finding and exploiting more ILP is speculation. It is an approach
whereby the compiler or processor guesses the outcome of an instruction to remove it as dependence in
executing other instructions. For example, we might speculate on the outcome of a branch, so that
instructions after the branch could be executed earlier.
19. Define Multiple Instruction, Single Data stream (MISD).

Multiple instructions operate on a single data stream. It is uncommon architecture which is generally
used for fault tolerance. Heterogeneous systems operate on the same data stream and must agree on the
result. Examples include the Space Shuttle flight control computer.
11
20. Define Multiple Instruction, Multiple Data streams (MIMD).

Multiple autonomous processors are simultaneously executing different instructions on different data.
Distributed systems are generally recognized to be MIMD architectures; either exploiting a single shared
memory space or a distributed memory space. A multi-core superscalar processor is an MIMD processor.
PART B
1. Explain in detail Flynns classification of parallel hardware. / Discuss about SISD, MIMD, SIMD, SPMD
and VECTOR systems. (Nov 2016 / May 2016 / Nov 2015 / May 2017)
2. Explain Instruction Level Parallel Processing. State the challenges of parallel processing. (Nov 14/ Nov 16)
3. Explain the term: (i) Multicore Processor (ii) Hardware Multithreading (Nov 2014 / Nov 2015 / May 2016)
4. What is hardware multithreading? Compare and contrast Fine grained multithreading and Coarse grained
multithreading.(May 2015)
5. Explain the four principal approaches to multithreading with necessary diagrams. (May 2017)
6. Discuss shared memory multiprocessor with neat diagram. (Nov 2016)
7. Describe dependency and the various types of dependencies in detail.
8. Discuss briefly about the motivation of Multi-core computing.
12
UNIT V MEMORY AND I/O SYSTEMS

PART A
1. What is the need to implement Memory as Hierarchy? (May 2015)

It is a structure that uses multiple levels of memory with different speeds and sizes.
They are used for storing system programs, large data files, and other backup information.
Only programs and data currently needed by the processor reside in main memory.
2. Differentiate Programmed I/O and Interrupt I/O. (Nov 2014)

In programmed I/O all data transfers between the computer system and external devices are completely
controlled by the computer program. Part of the program will check to see if any external devices require
attention and act accordingly. Interrupt I/O is a way of controlling input/output activity in which a peripheral
or terminal that needs to make or receive a data transfer sends a signal that causes a program interrupt to be
set.
3. What is the purpose of Dirty/Modified bit in Cache memory? (Nov 2014)

During Write back the information is written only to the block in the cache. The modified cache block
is written to main memory only when it is replaced. To reduce the frequency of writing back blocks on
replacement, a dirty bit is commonly used. This status bit indicates whether the block is dirty (modified
while in the cache) or clean (not modified). If it is clean the block is not written on a miss.
4. Point out how DMA can improve I/O speed? (May 2015)
Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems
to access main system memory (RAM) independent of the central processing unit (CPU).
5. What are the various memory technologies? (Nov 2015)

SRAM, DRAM, Hard Disk Drives, Magnetic Tapes, Optical drives, Flash based storage devices.
6. Define Hit ratio. (Nov 2015)

The percentage of accesses where the processor finds the code or data word it needs in the cache
memory is called the hit rate or hit ratio.
7. What is DMA? (Nov 2014)

DMA (Direct Memory Access) provides I/O transfer of data directly to and from the memory unit and
the peripheral. The following DMA transfer combinations are possible:
Memory to memory
Memory to peripheral
Peripheral to memory
Peripheral to peripheral
8. Define memory interleaving. (May 2017)

Interleaved memory is a design made to compensate for the relatively slow speed of dynamic random-
access memory (DRAM) or core memory, by spreading memory addresses evenly across memory banks.
That way, contiguous memory reads and writes are using each memory bank in turn, resulting in higher
memory throughputs due to reduced waiting for memory banks to become ready for desired operations.
13
9. Summarize the sequence of events involved in handling an interrupt request from a single device.
(May 2017)
i. The device raises an interrupt.
ii. The processor interrupts the program currently being executed.
iii. Interrupts are disabled by changing the control bits in the PS.
iv. The device is informed that its request has been recognized, and in response, it deactivates the
interrupt request signal.
v. The action requested by the interrupt is performed by the interrupt service routine.
vi. Interrupts are enabled and execution of the interrupted program is resumed.
10. Define memory hierarchy. (May 2016)

The memory hierarchy in computer storage separates each of its levels based on response time. Since
response time, complexity, and capacity are related, the levels may also be distinguished by their
performance and controlling technologies.
11. State the advantages of virtual memory. (May 2016)

It allows to load and execute a process that requires a larger amount of memory than what is
available by loading the process in parts and then executing them.
It eliminates external memory fragmentation.
12. What is meant by address mapping? (Nov 2016)

Address mapping is defined as the smallest unit of addressed data (from the persistent store) that can
be mapped independently to an area of the virtual address space.
13. What is cache memory? (Nov 2016)

Cache memory is random access memory (RAM) that a computer microprocessor can access more
quickly than it can access regular RAM. This memory is typically integrated directly with the CPU chip or
placed on a separate chip that has a separate bus interconnect with the CPU. The basic purpose of cache
memory is to store program instructions that are frequently re-referenced by software during operation. Fast
access to these instructions increases the overall speed of the software program.
14. What is principle of locality?

The principle of locality states that programs access a relatively small portion of their address space at
any instant of time. Two different types of locality have been observed:
Temporal locality: states that recently accessed items are likely to be accessed in the near future.
Spatial locality: says that items whose addresses are near one another tend to be referenced close together
in time.
15. Define Hit and Miss.

The performance of cache memory is frequently measured in terms of a quantity called hit ratio. When
the CPU refers to memory and finds the word in cache, it is said to produce a hit. If the word is not found
in cache, then it is in main memory and it counts as a miss.
16. Distinguish between memory mapped I/O and I/O mapped I/O.
Memory mapped I/O: When I/O devices and the memory share the same address space, the arrangement
is called memory mapped I/O. The machine instructions that can access memory is used to transfer data to
or from an I/O device.
14
I/O mapped I/O: Here the I/O devices the memories have different address space. It has special I/O
instructions. The advantage of a separate I/O address space is that I/O devices deals with fewer address
lines.
17. Compare Static RAM and Dynamic RAM.

Static RAM is more expensive, requires four times the amount of space for a given amount of data than
dynamic RAM, but, unlike dynamic RAM, does not need to be power-refreshed and is therefore faster to
access. One source gives a typical access time as 25 nanoseconds in contrast to a typical access time of 60
nanoseconds for dynamic RAM. Static RAM is used mainly for the level-1 and level-2 caches that the
microprocessor looks in first before looking in dynamic RAM.
Dynamic RAM uses a kind of capacitor that needs frequent power refreshing to retain its charge.
Because reading a DRAM discharges its contents, a power refresh is required after each read. Apart from
reading, just to maintain the charge that holds its content in place, DRAM must be refreshed about every
15 microseconds. DRAM is the least expensive kind of RAM.
18. What is virtual memory?

In modern computers, the OS moves program and data automatically between the main memory and
secondary storage. Techniques that automatically swaps program and data blocks between main memory
and secondary storage device are called virtual memory. The address that processor issues to access either
instruction or data are called virtual or logical address.
19. What is TLB?

A translation lookaside buffer (TLB) is a memory cache that stores recent translations of virtual memory
to physical addresses for faster retrieval. When a virtual memory address is referenced by a program, the
search starts in the CPU. First, instruction caches are checked. If the required memory is not in these very
fast caches, the system has to look up the memorys physical address. At this point, TLB is checked for a
quick reference to the location in physical memory.
20. What are the functions of typical I/O interface?

An interface is necessary to coordinate the transfer of data between the CPU and external devices. The
functions performed by an I/O interface are:
i. Handle data transfer between much slower peripherals and CPU or memory.
ii. Handle data transfer between CPU or memory and peripherals having different data formats and
word lengths.
iii. Match signal levels of different I/O protocols with computer signal levels.
iv. Provide necessary driving capabilities sinking and sourcing currents.
PART B
1. Elaborate on the various memory technologies and its relevance. (May 2015)
2. What is virtual memory? Explain in detail about how virtual memory is implemented with neat diagram? /
Explain virtual memory address translation in detail with necessary diagrams.(May 2015 / Nov 2015 / Nov
2016 / May 2017)
3. Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer
between memory and peripherals? / What is meant by DMA? Explain the use of DMA controllers in a
computer system. (Nov 2015 / May 2016 / Nov 2016 / May 2017)
15
4. (i) Explain mapping functions in cache memory to determine how memory blocks are placed in cache. /
Define cache memory? Explain the various mapping techniques associated with cache memories. (8 / 16)
(May 2017 / Nov 2014 / May 2016 / May 2017)
(ii) Explain in detail about the Bus Arbitration techniques in DMA. (May 2017 / Nov 2014)
5. (i) Draw different memory address layouts and brief about the technique used to increase the average rate
of fetching words from the main memory. (Nov 2014)
(ii) Explain in detail about any two standard input and output interfaces required to connect the I/O device
to the Bus.(Nov 2014)
6. Design and explain a parallel priority interrupt hardware for a system with eight interrupt sources. (15) (Nov
2016)
7. What is an interrupt? Explain the different types of interrupts and the different ways of handling the
interrupts.
8. (i) Explain in detail about the basic structure of a memory level hierarchy with suitable diagram.
(ii)Write short note on I/O processor. What is the need for an I/O interface?
16

CS6303 Computer Architecture Instruction Set and Addressing Modes

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

CS6303 Computer Architecture Instruction Set and Addressing Modes

Încărcat de

Drepturi de autor:

Formate disponibile

CS6303 COMPUTER ARCHITECTURE DEPARTMENT OF EIE 2017 - 2018

CS6303 COMPUTER ARCHITECTURE

UNIT I OVERVIEW & INSTRUCTIONS

2. Distinguish pipelining from parallelism. (May 2015)

3. What is Instruction set architecture (ISA)? (Nov 2015)

5. How to represent instruction in a computer system? (May 2016)

7. State Amdahls Law.(Nov 2014)

8. Brief about relative addressing mode with an example. (Nov 2014)

9. What is an instruction register? (Nov 2016)

10. List the major components of a computer system? (May 2017)

12. Define addressing modes and its various types.

13. What is program counter?

14. What is RISC and CISC?

15. List out the methods used to improve system performance?

17. Define Based or Displacement mode addressing.

18. What is superscalar execution?

19. Define CPI.

20. Define MIPS.

UNIT II ARITHMETIC OPERATIONS

2. What do mean by Subword Parallelism? (May 2015 / May 2016)

3. How overflow occur in subtraction? (May 2015)

6. Define ALU. (May 2016)

8. What is arithmetic overflow? (Nov 2016)

11. Define Full Adder (FA) with logic diagram.

13. When can you say that a number is normalized?

14. Define Booth Algorithm.

15. What are generate and propagate function?

17. Define Truncation.

18. Write the IEEE 754 floating point format?

Double precision representation

19. Draw the half adder circuit?

20. Draw the full adder circuit?

8. Discuss about IEEE 754 standard for floating point operations.

UNIT III PROCESSOR AND CONTROL UNIT

1. What are R-type instructions? (May 2015)

2. What is a branch prediction buffer? (May 2015)

3. What is meant by branch prediction? (Nov 2015)

5. Define exception. (May 2016 / Nov 2014)

6. What are the advantages of pipelining? (May 2016)

7. What is meant by pipeline bubble? (Nov 2016)

8. What is a data path? (Nov 2016)

9. Give an example for data hazard. (May 2017)

11. What is meant by pipeline bubble?

12. What is meant by data hazard in pipelining?

13. What is Instruction or control hazard?

14. Define structural hazards.

15. Define Pipeline speedup.

16. Why is branch prediction algorithm needed?

17. What is pipelining?

18. What are the major characteristics of a pipeline?

19. What are the types of data hazards?

20. How addressing modes affect the instruction pipeling?

7. Explain in detail how exceptions are handle in MIPS architecture.(April 2015)

8. i) Explain the hazards caused by unconditional branching statements. (May 2017)

2. What is Flynns Classification? (Nov 2014)

3. What is the need for Speculation? (Nov 2014)

4. Compare UMA and NUMA multiprocessors.(May 2015)

5. Differentiate between Strong scaling and weak scaling.(May 2015)

6. Define a superscalar processor. (Nov 2015)

7. What is Fine grained multithreading? (May 2016)

9. Distinguish implicit multithreading and explicit multithreading. (May 2017)

10. Define Static multiple issue.

11. Define Dynamic multiple issue.