COMPUTER ORGANISATION

CS201P
PROJECT REPORT
GROUP-12
MAEGHEL PURI
ABHISHEK KUMAR MISHRA
ARPIT KARWASARA
SAGAR KAUSHAL
PROBLEM STATEMENT: To design and simulate a 32 bit MIPS pipelined
processor.

INTRODUCTION:
SMIPS is a 32 bit Instruction Set Architecture (ISA) with Integer operations only. In
this project we have designed a 5 stage pipelined processor based on SMIPS ISA.
The processor is implemented using Harvard Architecture consisting of separate
Instruction and Data Memories. The main motivation behind pipelining the
processor is to increase the throughput. However, this adds additional complexity
to the control unit design that was not present in the non-pipelined version. Our
design efficiently handles all possible data and control hazards which arise as a
result of pipelining the processor.
CIRCUIT DIAGRAM:

COMPONENTS:

1) MEMORY: 128 X 8 (DATA MEMORY)

2)4 PIPELINED REGISTERS

3)THREE REGISTERS Rs,Rt,Rd

4) ALU WITH 32 BIT ADDER AND SUBTRACTOR

5) INSTRUCTION MEMORY

6) 32 BIT AND GATE, OR GATE

7) DECODER (INSTRUCTION SPLITTER)

SIMULATION RESULTS:

1) INPUT: 3 in decimal+ 3 in decimal

OUTPUT: 6 in decimal

ADDITION
2) INPUT: 3 in decimal, 3 in decimal

OUTPUT: 0 in decimal

SUBTRACTION
COMPARISON(NORMAL AND PIPEPLINED):

Let us concentrate on one example which compares the single cycle,

multi cycle and pipelined CPU. Please note the detail of pipelined CPU
structure is explained in detail in chapter 2. Example: Assume 10ns is
the required time to perform any operations: memory access, register
file access and ALU operation. In this example we will consider
negligible delay for multiplexer, registers and look up tables. [2] 1. Since
10ns is the required time to perform any operation and we are
considering 5 stages of operation for RISC architecture, the total time
for single cycle CPU operation will take 50ns and 10 ns for both multi
clk cycle as well pipeline CPU/ 2. Let us calculate CPI for all three types
of implementation, let us assume a CPU is executing following
instructions.

Instruction Execution Frequency Jump 7% Store 5% Load 12%

Arithmetic, logical and comparison 60% Branch 16%

CPI in case of single cycle = 1 CPI in case of multi cycle = .07*3 + .05*4 +
.12*5 + .16*3 + .6*4 = 3.89

CPI in case of pipelined = .16 *3 + .85 *1 = 1.32 Now, let us calculate the
speedup 1. In case of single cycle CPU = (50)/(1.3*10 = 3.846 2. In case
of multi cycle CPU = (3.89 *10) / (1.32 *10) =2.946 Here, we can
determine that pipelined CPU is the fastest among all.