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clk
1
Timing Parameters
r, the radix
n, the number of digits input/output
, the initial delay (online delay)
number of addition cycles before first digit is produced
T, total execution time
time from first input digit to last result digit
T=+n+1
Serial Addition/Subtraction
Radix 2
LSD-First
Radix 16
LSD-First
2
Bit-Serial Multipliers
3
Semi-Systolic #1:
A parallel, X serial (LSB first)
a3 a2 a1 a0
Dependence x0
Isotemporal line.
Connects operations Graph
performed at the same time. x1
x2
x3
Allocation box.
Encloses operations 0 AND, full add,
performed on the same latch operation
processor.
0 Same operation,
(4 processors) these nodes are
used to propagate
0 carries and shift out
results.
0
Semi-systolic Design #1
4
Modified Design #1
Allows a new problem to be started 4 cycles earlier.
a3 a2 a1 a0
PL
AND, Add
X
Delay Elements
PH
Serial Adder
Semi-Systolic #2:
A parallel, X serial (LSB first) a3 a2 a1 a0
x0
x1
x2
x3
0
Winter 2006 ECEn 621 Computer Arithmetic
Slide #10 Dr. Doran Wilde
5
Semi-systolic Design #2
Systolic Design
A parallel, X serial (LSB first)
a3 a2 a1 a0
x0
x1
x2
x3
6
Systolic Design
Systolic Design
A serial and X serial (LSB first)
a3 a2 a1 a0
x0
x1
x2
x3
7
Bit-Serial Multiplier
in Dot Notation
Output
(5:3] Counter
Column Reduction
Output
Winter 2006 ECEn 621 Computer Arithmetic
Slide #15 Dr. Doran Wilde
Bit-Serial Multiplier
8
Both Inputs Serial, LSB First (Algebraic Derivation)
Let a ( i ) = 2i ai + a (i 1) , a ( 0) = a0
x ( i ) = 2i xi + x (i 1) , x ( 0 ) = x0
m (i ) = a (i ) x (i )
= (2i ai + a ( i 1) )(2i xi + x ( i 1) )
= 2 2i ai xi + 2i (ai x ( i 1) + xi a ( i 1) ) + a (i 1) x (i 1)
= 2 2i ai xi + 2i (ai x ( i 1) + xi a ( i 1) ) + m (i 1)
2 214
( i +1)
2m 3 = 2 ai xi + ai x
4
(i ) i ( i 1)
+ xi a (i 1) + 21i
42
( i 1)
m4 3
p(i ) p ( i 1)
2 p ( i ) = 2i ai xi + ai x (i 1) + xi a (i 1) + p (i 1)
Winter 2006 ECEn 621 Computer Arithmetic
Slide #17 Dr. Doran Wilde