Jedd Emille Chua

Adrianne Jasper Lazaro

ECE 280

NAND and NOR Gates

I. Design a NAND Gate using CMOS and using default W/L ratio for each MOS.
Calculate the Rise/Fall Time of the inputs and output and the slew rate of output.

A. Design

The following is the circuit implementation of the NAND Gate using CMOS:
Using the default W/L ratio:
PMOS: W = 2m, L = 0.5m
NMOS: W = 12m, L = 0.5m
 The Symbol created is as follows:

B. Simulation
The Testbench set is as follows:
Input A (pulse): Amplitude = 1.2V, Period = 40ns, time delay = 10ns
Input B (pulse): Amplitude = 1.2V, Period = 80ns, time delay = 10ns
Vdd = 1.2V

Doing the simulation, with settings Transient: Start = 0ns, Stop = 200ns, step =
1ns:
 C. Results
The following are the calculated values for the simulation:
Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 745ps
Slew Rate 1.34V/ns

This circuit correctly designs a NAND gate, with the following truth table:
Time Input A Input B Output
0ns 0 0 1
10ns 1 1 0
30ns 0 1 1
55ns 1 0 1
70ns 0 0 1
90ns 1 1 0

Also, based on the waveform produced, at 50ns, when the rise time of Input A
produces a delay on off state, as well as the fall time of Input B has produces a
delay on on state; the circuit will then see a 11 on 50ns through it should still
transition to 10, therefore, a glitch occurred where the output will produce a short 0
state from a supposedly continuous 1 state.

It is also observed that at some intervals, like at 70ns or 150ns, some distortions in the
output can be seen, though not as much significant.

Also notice that using the default W/L ratio will still produce a significant rise/fall
time (745ps as opposed to the ideal 0ps).

II. Design a NOR Gate using CMOS and using default W/L ratio for each MOS.
Calculate the Rise/Fall Time of the inputs and output and the slew rate of output.

A. Design

The following is the circuit implementation of the NOR Gate using CMOS:
 Using the default W/L ratio:
PMOS: W = 2m, L = 0.5m
NMOS: W = 12m, L = 0.5m

The Symbol created is as follows:

B. Simulation
The Testbench set is as follows:
Input A (pulse): Amplitude = 1.2V, Period = 40ns, time delay = 10ns
Input B (pulse): Amplitude = 1.2V, Period = 80ns, time delay = 10ns
 Vdd = 1.2V

Doing the simulation, with settings Transient: Start = 0ns, Stop = 200ns, step =
1ns:

C. Results
The following are the calculated values for the simulation:
Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 643ps
Slew Rate 1.58V/ns

This circuit correctly designs a NOR gate, with the following truth table:
Time Input A Input B Output
0ns 0 0 1
10ns 1 1 0
30ns 0 1 0
55ns 1 0 0
70ns 0 0 1
 90ns 1 1 0

Also, based on the waveform produced, at 50ns, the delay on Input A and B does not
affect much on result on output since 11 and 10 will have the same result (0).

Also notice that using the default W/L ratio will still produce a significant rise/fall
time (643ps as opposed to the ideal 0ps) as well as a relatively noticeable value for
slew rate.

III. Change W/L ratio of the NAND Gate designed and show its relationship to
performance
A. PMOS Changes
1. Decreased W (lower W/L ratio)
The PMOS is changed as follows:
W = 1m (W/L ratio is halved)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 1470ps
Slew Rate 0.695V/ns

Since 1470ps > 745ps and the ideal rise/fall time is 0ps, lowering down W
in PMOS can degrade performance of the NAND gate.

Also, since 0.695V/ns < 1.34V/ns and the ideal slew rate is (pure vertical
slope), lowering down W in PMOS can degrade performance of the NAND
gate.

2. Increased W (higher W/L ratio)

The PMOS is changed as follows:
W = 4m (W/L ratio is doubled)
The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 553ps
Slew Rate 1.78V/ns

Since 553ps < 745ps and the ideal rise/fall time is 0ps, raising W in PMOS
can improve performance of the NAND gate.

Also, since 1.78V/ns > 1.34V/ns and the ideal slew rate is (pure vertical
slope), raising W in PMOS can improve performance of the NAND gate.

3. Decreased L (higher W/L ratio)

The PMOS is changed as follows:
L = 0.25m (W/L ratio is doubled)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 446ps
Slew Rate 2.2V/ns
 Since 446ps < 745ps and the ideal rise/fall time is 0ps, lowering down L in
PMOS can improve performance of the NAND gate.

Also, since 2.2V/ns > 1.34V/ns and the ideal slew rate is (pure vertical
slope), lowering down L in PMOS can improve performance of the NAND
gate.

4. Increased L (lower W/L ratio)

The PMOS is changed as follows:
L = 1m (W/L ratio is halved)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 1680ps
Slew Rate 0.617V/ns

Since 1680ps > 745ps and the ideal rise/fall time is 0ps, raising L in PMOS
can degrade performance of the NAND gate.

Also, since 0.617V/ns < 1.34V/ns and the ideal slew rate is (pure vertical
slope), raising L in PMOS can degrade performance of the NAND gate.

B. NMOS Changes
1. Decreased W (lower W/L ratio)
The NMOS is changed as follows:
W = 6m (W/L ratio is halved)

The following waveform is produced:

 The following are the calculated values for the simulation:
Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 541ps
Slew Rate 1.83V/ns

Since 541ps < 745ps and the ideal rise/fall time is 0ps, lowering down W in
NMOS can improve performance of the NAND gate.

Also, since 1.83V/ns > 1.34V/ns and the ideal slew rate is (pure vertical
slope), lowering down W in NMOS can improve performance of the NAND
gate.

2. Increased W (higher W/L ratio)

The NMOS is changed as follows:
W = 24m (W/L ratio is doubled)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 1290ps
Slew Rate 0.774V/ns
 Since 1290ps > 745ps and the ideal rise/fall time is 0ps, raising W in NMOS
can degrade performance of the NAND gate.

Also, since 0.774V/ns < 1.34V/ns and the ideal slew rate is (pure vertical
slope), raising W in NMOS can degrade performance of the NAND gate.

3. Decreased L (higher W/L ratio)

The NMOS is changed as follows:
L = 0.25m (W/L ratio is doubled)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 578ps
Slew Rate 1.73V/ns

Since 578ps< 745ps and the ideal rise/fall time is 0ps, lowering down L in
NMOS can improve performance of the NAND gate.

Also, since 1.73V/ns > 1.34V/ns and the ideal slew rate is (pure vertical
slope), lowering down L in NMOS can improve performance of the NAND
gate.

4. Increased L (lower W/L ratio)

The NMOS is changed as follows:
L = 1m (W/L ratio is halved)

The following waveform is produced:

 The following are the calculated values for the simulation:
Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 1220ps
Slew Rate 0.840V/ns

Since 1220ps>745ps and the ideal rise/fall time is 0ps, raising L in NMOS
can degrade performance of the NAND gate.

Also, since 0.840V/ns < 1.34V/ns and the ideal slew rate is (pure vertical
slope), raising L in NMOS can degrade performance of the NAND gate.

C. Trends in Changes of W/L ratio to NAND gate

Therefore, the following trend can be predicted to the performance of a NAND
gate:
MOS W or L changed W/L Performance
PMOS W higher High Better
PMOS W lower Low Worse
PMOS L lower High Better
PMOS L higher Low Worse
NMOS W higher High Worse
NMOS W lower Low Better
NMOS L lower High Better
NMOS L higher Low Worse

IV. Change W/L ratio of the NOR Gate designed and show its relationship to
performance
A. PMOS Changes
1. Decreased W (lower W/L ratio)
The PMOS is changed as follows:
W = 1m (W/L ratio is halved)

The following waveform is produced:

 The following are the calculated values for the simulation:
Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 893ps
Slew Rate 1.12V/ns

Since 893ps > 643ps and the ideal rise/fall time is 0ps, lowering down W in
PMOS can degrade performance of the NOR gate.

Also, since 1.12V/ns < 1.58V/ns and the ideal slew rate is (pure vertical
slope), lowering down W in PMOS can degrade performance of the NOR
gate.

It is also noticed that the rising edge seems to be more distorted than that of
the default, which is a clear indication of degraded performance.

2. Increased W (higher W/L ratio)

The PMOS is changed as follows:
W = 4m (W/L ratio is doubled)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
 Rise/Fall Time of Output 523ps
Slew Rate 1.97V/ns

Since 523ps < 643ps and the ideal rise/fall time is 0ps, raising W in PMOS can
improve performance of the NOR gate.

Also, since 1.97V/ns > 1.58V/ns and the ideal slew rate is (pure vertical slope),
raising W in PMOS can improve performance of the NOR gate.

3. Decreased L (higher W/L ratio)

The PMOS is changed as follows:
L = 0.25m (W/L ratio is doubled)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 399ps
Slew Rate 2.48V/ns

Since 399ps < 643ps and the ideal rise/fall time is 0ps, lowering L in PMOS can
improve performance of the NOR gate.

Also, since 2.48V/ns > 1.58V/ns and the ideal slew rate is (pure vertical slope),
lowering L in PMOS can improve performance of the NOR gate.

4. Increased L (lower W/L ratio)

The PMOS is changed as follows:
L = 1m (W/L ratio is halved)

The following waveform is produced:

 The following are the calculated values for the simulation:
Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 1800ps
Slew Rate 0.585V/ns

Since 1800ps >> 643ps and the ideal rise/fall time is 0ps, raising L in PMOS
can degrade performance of the NOR gate.

Also, since 0.585V/ns << 1.58V/ns and the ideal slew rate is (pure vertical
slope), raising L in PMOS can degrade performance of the NOR gate.

It is also noticed that the rising edge seems to be more distorted than that of the
default, which is a clear indication of degraded performance.

B. NMOS Changes
1. Decreased W (lower W/L ratio)
The NMOS is changed as follows:
W = 6m (W/L ratio is halved)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
 Rise/Fall Time of Output 531ps
Slew Rate 1.94V/ns

Since 531ps < 643ps and the ideal rise/fall time is 0ps, lowering down W in
NMOS can improve performance of the NOR gate.

Also, since 1.94V/ns > 1.58V/ns and the ideal slew rate is (pure vertical
slope), lowering down W in NMOS can improve performance of the NOR
gate.

2. Increased W (higher W/L ratio)

The NMOS is changed as follows:
W = 24m (W/L ratio is doubled)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 820ps
Slew Rate 1.22V/ns

Since 820ps > 643ps and the ideal rise/fall time is 0ps, raising W in NMOS can
degrade performance of the NOR gate.

Also, since 1.22V/ns < 1.58V/ns and the ideal slew rate is (pure vertical slope),
raising W in NMOS can degrade performance of the NOR gate.

It is also noticed that the rising edge seems to be more distorted than that of the
default, which is a clear indication of degraded performance.

3. Decreased L (higher W/L ratio)

The NMOS is changed as follows:
L = 0.25m (W/L ratio is doubled)

The following waveform is produced:

The following are the calculated values for the simulation:
Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 610ps
Slew Rate 1.63V/ns

Since 610ps < 643ps and the ideal rise/fall time is 0ps, lowering L in NMOS
can improve performance of the NOR gate.

Also, since 1.63V/ns > 1.58V/ns and the ideal slew rate is (pure vertical slope),
lowering L in NMOS can improve performance of the NOR gate.

4. Increased L (lower W/L ratio)

The NMOS is changed as follows:
L = 1m (W/L ratio is halved)

The following waveform is produced:

The following are the calculated values for the simulation:

Rise/Fall Time of Input 800ps
Rise/Fall Time of Output 621ps
Slew Rate 1.69V/ns
 Since 621ps < 643ps and the ideal rise/fall time is 0ps, raising L in NMOS can
improve performance of the NOR gate.

Also, since 1.69V/ns > 1.58V/ns and the ideal slew rate is (pure vertical slope),
raising L in NMOS can improve performance of the NOR gate.

However, upon further inspection, increasing further L will eventually degrade

performance of the NOR gate in terms of stability of waveform. Though rise/fall
time and slew rate will indicate improvement of performance, the waveform like
the one below shows that distortions/instabilities will occur when L is greatly
increased in an NMOS. Below shows the output waveform when L = 2m.

C. Trends in Changes of W/L ratio to NOR gate

Therefore, the following trend can be predicted to the performance of a NOR
gate:
MOS W or L changed W/L Performance
PMOS W higher High Better
PMOS W lower Low Worse
PMOS L lower High Better
PMOS L higher Low Worse
NMOS W higher High Worse
NMOS W lower Low Better
NMOS L lower High Better
NMOS L higher Low Worse