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SAP
SAP1 1
(SIMPLE AS POSSIBLE)
OBJECTIVES:
INTRODUCTION:
The term "architecture" is used to define the components of the circuit, its
conceptual structure and even depicts how data flows and how it could be controlled. In
addition, it is under the umbrella of architecture to show the logical design of the system
made up from discrete integrated circuits, most of which are available in the Philippine
market. A SAP1 is an 8-bit computer with four address lines which is able to hold sixteen
It is the most basic model of a microprocessor for the design only contains the
basic requirements for a functional processor. It could be thus said that the primary
function of the SAP1 is to provide a model that could explain how a microprocessor works,
how it could interact with other parts of the system such as the Input and Output thus the
A single instruction cycle may be composed of several machine cycles, for SAP1,
the instruction cycle is basically the same as its machine cycle, composing of the FETCH
and EXECUTION, and below are the five instructions for SAP1:
INTRODUCTION:
The program counter (PC), commonly called the instruction pointer (IP)
in Intel x86 and Itanium microprocessors, and sometimes called the instruction address
register (IAR), the instruction counter, or just part of the instruction sequencer, is
the memory address of ("points to") the next instruction that would be executed. (In a
processor where the increment precedes the fetch, the PC points to the current instruction
being executed.)
transfer instructions change the sequence by placing a new value in the PC. These
include branches (sometimes called jumps), subroutine calls, and returns. A transfer that
is conditional on the truth of some assertion lets the computer follow a different sequence
A branch provides that the next instruction is fetched from somewhere else in
memory. A subroutine call not only branches but saves the preceding contents of the PC
resuming sequential execution with the instruction following the subroutine call.
MATERIALS:
1pc Breadboard
2pcs IC 74LS107
4pcs LEDs
SCHEMATIC DIAGRAM:
PIN CONFIGURATION:
74LS107
The expected output should appear as if the LED lights are counting from 1 to 15
SIMULATION:
The circuit trainer has built in control switches and value switches. For this run,
you must make sure that the value switches are all off (low) and RUN and AUTO are on
(high).
QUESTION/S:
Observe and explain the transition of the LED lights and write your observation below.
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ADDITIONAL TASK:
After you have effectively created a working program counter, incorporate the use
of a SEVEN SEGMENT DISPLAY. You can use a decoder in order to effectively show
the expected output (which is the same, but this time it must be displayed on its decimal
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INSTRUCTORS SIGNATURE
OBJECTIVES:
functions
INTRODUCTION:
The INPUT and MAR includes the address and data switch registers. Switch
registers are part of input unit, allows us to send 4 address bits and 8 data bits to the
RAM.
The memory address register (MAR) is the part of SAP-1 memory. During a
computer run, the address in the program counter is latched in to the MAR. A bit later, the
MAR applies this 4-bit address to the RAM where a read operation is performed.
MATERIALS:
1pc 74LS173
1pc 74LS157
4pcs LED
MULTISIM:
74LS173
74LS157
EXPECTED OUTPUT:
When LM is on, MAR is active. It will get its input from the Program Counter,
In the control switches, set the PROGRAM, AUTO, CLEAR and WRITE to on
(high).
You could observe that there are individual switches dedicated exclusively to the
QUESTION/S:
1. Why do you think that there is a need to set the switches off during this RUN?
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2. What will be the output when you set the PROGRAM in the control switch high
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3. What will be the output when you set the AUTO in the control switch high while
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5. What will be the output when you set the WRITE in the control switch high while
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NAME: _____________________________
___________________________________ GRADE
INSTRUCTORS SIGNATURE
OBJECTIVES:
INTRODUCTION:
access memory device allows data items to be read or written in almost the same amount
of time irrespective of the physical location of data inside the memory. In contrast, with
other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the
older drum memory, the time required to read and write data items varies significantly
RAM contains multiplexing and demultiplexing circuitry, to connect the data lines
to the addressed storage for reading or writing the entry. Usually more than one bit of
storage is accessed by the same address, and RAM devices often have multiple data
although many efforts have been made to develop non-volatile RAM chips. Other types
do not allow write operations or have other kinds of limitations on them. These include
MATERIALS:
2pcs 74LS189
8pcs LEDs
SCHEMATIC DIAGRAM:
74LS189
EXPECTED OUTPUT:
The key to understand the RAM is to know that this is an independent circuit, which
means either we remove the clock source or we connect it, we will achieve the same
output. The expected output is whatever the input in its respective address, with or without
SIMULATION:
The main point of the microprocessor is to interpret and run instruction, thus we
initialize the instruction through inputting data. Using the Switching Module (there are
control switches and value switches) follow through the instructions below:
The control switches, set the PROG, AUTO, CLEAR and WRITE to ON (high). You
could observe that there are individual switches dedicated exclusively to the MAR.
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Turn the switch WRITE on (high) then immediately turn it to READ on (high)
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NAME: _____________________________
___________________________________ GRADE
INSTRUCTORS SIGNATURE
INTRODUCTION:
It is the part of a CPU's control unit that stores the instruction currently being
the instruction register which holds it while it is decoded, prepared and ultimately
each stage of the pipeline does part of the decoding, preparation or execution and then
passes it to the next stage for its step. Modern processors can even do some of the steps
instruction, determining where its operands are in memory, retrieving the operands from
The output of IR is available to control circuits which generate the timing signals
that control the various processing elements involved in executing the instruction.
In the Instruction cycle, the instruction is loaded into the Instruction register after
the processor fetches it from the memory location pointed by the Program Counter.
1pc breadboard
2pcs 74LS173
1pc 8pin DIP switch
SCHEMATIC DIAGRAM:
MULTISIM:
74LS173
SIMULATION:
Whatever data you input will also be the output. Refer to LEDs.
QUESTION/S:
1) With the same settings for the switches in the previous runs, observe the LED
depicting how the Instruction Register separates the 8-bit data to two sets of 4
bits. Why does the IR need to do this?
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___________________________________ GRADE
INSTRUCTORS SIGNATURE
INTRODUCTION:
Before each computer runs, a CLR signal is sent to the program counter and CLK
signal to the instruction register. This resets the program counter to 0000 and wipes out
A clock signal CLK is sent to all buffer registers; this synchronizes the operation of the
computer ensuring that things happen when they are supposed to happen.
The 12-bit that comes out of the controller sequencer form a word controlling the rest
of the computer (like a supervisor telling others what to do). The 12 wires carrying the
control word are called the control bus. The control word has the format of: CON =
CP EP LM CE L1E1 LA EA SUEULBLO.
This word determines how the registers will wait to the next positive CLK edge. For
example, a high EP and a low LM means that the program counter are latched into the
MAR on the next positive clock edge. As another example, a low CE and a low LA means
2pcs breadboard
2pcs 74LS04 IC
5pcs 74LS08 IC
3pcs 74LS32 IC
SCHEMATIC DIAGRAM:
PIN CONFIGURATION:
74LS04
74LS32
SIMULATION:
With the same settings as the previous runs using AUTO and MAR Address is
T2
T3
T4
T5
T6
EXPECTED OUTPUT:
The expected output is same as the theory. It must be able to show the states
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NAME: _____________________________
___________________________________ GRADE
INSTRUCTORS SIGNATURE
INTRODUCTION:
computer runs. It has two output. The first one goes directly to the Adder-Subtractor. The
on a control signal. It is also possible to construct a circuit that performs both addition and
asynchronous, which means that its contents can change as soon as the input word
change.
MATERIALS:
74LS83
74LS173
16pcs LEDS
MULTISIM:
ACCUMULATOR:
74LS173
74LS83
EXPECTED OUTPUT:
Accumulator: When La is on, the Accumulator must be loaded, thus the input
must be taken from the W-bus (or in this case, the switches). When EA is on, the 74LS126
will function and thus it will either enable the output or not.
With the same settings as the previous runs, pre-load the SAP1 Trainer with two
different decimals.
NAME: _____________________________
___________________________________ GRADE
INSTRUCTORS SIGNATURE
OBJECTIVES:
INTRODUCTION:
The B register is also a buffer register. A low LB and positive CLK edge load the
word on the W-bus into the B-register. The two state output of the B register drives the B-
register.
At the end of a computer run, the accumulator contains the answer to the problem
being solved.
At this point, we need to transfer the answer to the outside world. This is where the
output register is used. When EA is high, is low, the next positive clock edge loads the
word of the accumulator into the output register. The output register is often called an
output port processed data can leave the computer through these register.
MATERIALS:
2pcs 74LS173
2pcs 74LS83
8pcs LEDs
MULTISIM:
B REGISTER:
74LS173
EXPECTED OUTPUT:
The B-Register, from its name itself must serve as a buffer, thus whatever input is
the output.
The Output Register, when LO is on, must display the final output, no matter which
NAME: _____________________________
___________________________________ GRADE
INSTRUCTORS SIGNATURE
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3. Why does the SAP1 Circuit rarely use direct connections and uses the W-Bus?
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Photos:
Google Images
Stock Photos
Content:
ABADILLA, DOMINIQUE B.
CABASAL, LLOYD B.
CAIDO, CAMILLE C.
ESPINOZA, ROLLY B.
GUILLEN, JERRYSON A.
MEDALLE, ZEBRED G.
ORBINO, JACKIELYN
PACHECO, KEVIN T.
RODRIGUEZ, REGINALD
TAPALGO, REYNALDO P.
ADVISER: