Dept.

of Electronics & Communication Engineering

Siksha O Anusandhan University

LOGIC DESIG LAB (EET1021)

PIN SPECIFICTION FOR IC

S.
IC IC NAME
No.

1. 7400 Quad 2 input NAND gates

2. 7402 Quad 2 input NOR gates

3. 7404 Hex Inverter

4. 7408 Quad 2 input AND gates

5. 7432 Quad 2 input OR gates

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Siksha O Anusandhan University

6. 7486 Quad 2 input EX-OR gates

7. 7410 Tri 3-input NAND gates

8. 7420 Dual 4-input NAND gates

7447 7-Segment Control

Pin Names Description

A0 A3 BCD Inputs
Ripple Blanking Input (Active
9.
LOW)
Lamp Test Input (Active LOW)
Blanking Input or Ripple Blanking
/
Output (Active LOW)

Segment Outputs (Active LOW)

74151 8:1 Multiplexer
Pin Names Description
S0 S2 Select Inputs
Enable Input (Active LOW)
10. I0 I7 Multiplexer Inputs
Z Multiplexer Output

Complementary Multiplexer Output

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Siksha O Anusandhan University
74153 Dual 4:1 Multiplexer

Pin Names Description

S 0, S 1 Select Input
11.
Enable Input (Active LOW)

I0 I1 Multiplexer Inputs

Z Multiplexer Output

74155 Dual 1:4 Decoder

Pin Names Description

A, B, C Address Inputs
G 1, G 2 Enable Input (Active LOW)

12.

Y0 Y3 Active Low Outputs

74157 Quad 2:1 Multiplexer

Pin Names Description
S Select Input
13. Enable Input (Active LOW)
I0a I0d Multiplexer Inputs for Source 0
I1a I2d Multiplexer Inputs for Source 1
Za - Zd Multiplexer Output
74194 Bidirectional Shift Register
Pin
Description
Names
S 0, S 1 Mode Control Inputs
P0 P3 Parallel Data Inputs
14. DSR Serial (Shift Right) Data Input
DSL Serial (Shift Left) Data Input
CP Clock Input (Active HIGH)
Master Reset Input (Active LOW)
Q0 Q3 Parallel Outputs

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Siksha O Anusandhan University
74195 - Shift Register
Pin Names Description
Parallel Enable Input (Active LOW)
P0 P3 Parallel Data Inputs
J First Stage J input (Active HIGH)
15.
K First Stage K input (Active LOW)
CP Clock Input (Active HIGH)
Master Reset Input (Active LOW)
Q0 Q3 Parallel Outputs
1 Complementary Last Stage Output
7476 J-K Flip Flop

Pin Names Description

CLK Clock Input

16. J, K Data Inputs

, Data Outputs

Pre-set Output (Active LOW)

Clear Output (Active LOW)

7489 RAM
Pin
Description
Names
A0 A3 Address Input

17. Chip Select Enable Input (Active

LOW)
Write Enable Input (Active LOW)

D1 D4 Data Inputs

6 8 Data Outputs (Inverting)

18. LT 542 & segment Display

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 Dept. of Electronics & Communication Engineering
Siksha O Anusandhan University

19. 7474 Dual D Flip Flop