R5888C Quadramho A4RB

Service Manual
Quadramho
Distance Protection Type SHPM 101
Quadramho
Service Manual
R5888C
The following publications form part of this manual:

Publication R5580 Quadramho descriptive leaflet
Publication R5234 Electronic module housing
Service Manual
Quadramho
HANDLING OF ELECTRONIC EQUIPMENT

A person's normal movements can easily generate electrostatic potentials of several thousand volts.
Discharge of these voltages into semiconductor devices when handling electronic circuits can cause
serious damage, which often may not be immediately apparent but the reliability of the circuit will have
been reduced.
The electronic circuits of ALSTOM T&D Protection & Control Ltd products are completely safe from
electrostatic discharge when housed in the case. Do not expose them to the risk of damage by
withdrawing modules unnecessarily.
Each module incorporates the highest practicable protection for its semiconductor devices. However, if it
becomes necessary to withdraw a module, the following precautions should be taken to preserve the high
reliability and long life for which the equipment has been designed and manufactured.
1. Before removing a module, ensure that you are at the same electrostatic potential as the equipment
by touching the case.
2. Handle the module by its front-plate, frame, or edges of the printed circuit board.
Avoid touching the electronic components, printed circuit track or connectors.
3. Do not pass the module to any person without first ensuring that you are both at the same
electrostatic potential. Shaking hands achieves equipotential.
4. Place the module on an antistatic surface, or on a conducting surface which is at the same
potential as yourself.
5. Store or transport the module in a conductive bag.
More information on safe working procedures for all electronic equipment can be found in BS5783 and
IEC 60147-0F.
If you are making measurements on the internal electronic circuitry of an equipment in service, it is
preferable that you are earthed to the case with a conductive wrist strap.
Wrist straps should have a resistance to ground between 500k 10M ohms. If a wrist strap is not
available, you should maintain regular contact with the case to prevent the build up of static.
Instrumentation which may be used for making measurements should be earthed to the case whenever
possible.
ALSTOM T&D Protection & Control Ltd strongly recommends that detailed investigations on the electronic
circuitry, or modification work, should be carried out in a Special Handling Area such as described in
BS5783 or IEC 60147-0F.
SERVICE MANUAL R5888C
QUADRAMHO Contents
DISTANCE PROTECTION
SAFETY SECTION
THIS MUST BE READ BEFORE ANY WORK IS CARRIED OUT ON THE RELAY
CHAPTER 1 APPLICATION NOTES (R5580 included)
CHAPTER 2 DESCRIPTION, TECHNICAL DATA
CHAPTER 3 ELECTRONIC MODULE HOUSING (R5234 included)
CHAPTER 4 INSTALLATION AND HANDLING
CHAPTER 5 COMMISSIONING
CHAPTER 6 PROBLEM ANALYSIS
CHAPTER 7 MODULE IDENTIFICATION
CHAPTER 8 SPECIAL VARIATIONS

SAFETY SECTION
This Safety Section should be read before commencing any work on the equipment.
Health and safety
The information in the Safety Section of the product documentation is intended to
ensure that products are properly installed and handled in order to maintain them
in a safe condition. It is assumed that everyone who will be associated with the
equipment will be familiar with the contents of the Safety Section.
Explanation of symbols and labels
The meaning of symbols and labels which may be used on the equipment or in the
product documentation, is given below.
Caution: refer to product documentation Caution: risk of electric shock
Protective/safety *earth terminal
Functional *earth terminal.

Note: this symbol may also be used for a protective/
safety earth terminal if that terminal is part of a
terminal block or sub-assembly eg. power supply.
*Note:The term earth used throughout the product documentation is the direct
equivalent of the North American term ground.
Installing, Commissioning and Servicing

Equipment connections
Personnel undertaking installation, commissioning or servicing work on this
equipment should be aware of the correct working procedures to ensure safety.
The product documentation should be consulted before installing, commissioning or
servicing the equipment.
Terminals exposed during installation, commissioning and maintenance may
present a hazardous voltage unless the equipment is electrically isolated.
If there is unlocked access to the rear of the equipment, care should be taken by all
personnel to avoid electric shock or energy hazards.
Voltage and current connections should be made using insulated crimp
terminations to ensure that terminal block insulation requirements are maintained
for safety. To ensure that wires are correctly terminated, the correct crimp terminal
and tool for the wire size should be used.
Before energising the equipment it must be earthed using the protective earth
terminal, or the appropriate termination of the supply plug in the case of plug
connected equipment. Omitting or disconnecting the equipment earth may cause a
safety hazard.
The recommended minimum earth wire size is 2.5 mm2, unless otherwise stated in
the technical data section of the product documentation.
Before energising the equipment, the following should be checked:
Voltage rating and polarity;
CT circuit rating and integrity of connections;
Protective fuse rating;
Integrity of earth connection (where applicable)
Equipment operating conditions

The equipment should be operated within the specified electrical and
environmental limits.
Current transformer circuits
Do not open the secondary circuit of a live CT since the high voltage produced
may be lethal to personnel and could damage insulation.
External resistors
Where external resistors are fitted to relays, these may present a risk of electric
shock or burns, if touched.
Battery replacement
Where internal batteries are fitted they should be replaced with the recommended
type and be installed with the correct polarity, to avoid possible damage to the
equipment.
Insulation and dielectric strength testing
Insulation testing may leave capacitors charged up to a hazardous voltage. At the
end of each part of the test, the voltage should be gradually reduced to zero, to
discharge capacitors, before the test leads are disconnected.
Insertion of modules and pcb cards
These must not be inserted into or withdrawn from equipment whilst it is energised,
since this may result in damage.
Fibre optic communication
Where fibre optic communication devices are fitted, these should not be viewed
directly. Optical power meters should be used to determine the operation or signal
level of the device.
Older Products
Electrical adjustments
Equipments which require direct physical adjustments to their operating mechanism
to change current or voltage settings, should have the electrical power removed
before making the change, to avoid any risk of electric shock.
Mechanical adjustments
The electrical power to the relay contacts should be removed before checking any
mechanical settings, to avoid any risk of electric shock.
Draw out case relays
Removal of the cover on equipment incorporating electromechanical operating
elements, may expose hazardous live parts such as relay contacts.
Insertion and withdrawal of extender cards
When using an extender card, this should not be inserted or withdrawn from the
equipment whilst it is energised. This is to avoid possible shock or damage
hazards. Hazardous live voltages may be accessible on the extender card.
Insertion and withdrawal of heavy current test plugs
When using a heavy current test plug, CT shorting links must be in place before
insertion or removal, to avoid potentially lethal voltages.
Decommissioning and Disposal
Decommissioning: The auxiliary supply circuit in the relay may include capacitors
across the supply or to earth. To avoid electric shock or energy
hazards, after completely isolating the supplies to the relay
(both poles of any dc supply), the capacitors should be safely
discharged via the external terminals prior to
decommissioning.
Disposal: It is recommended that incineration and disposal to water
courses is avoided. The product should be disposed of in a
safe manner. Any products containing batteries should have
them removed before disposal, taking precautions to avoid
short circuits. Particular regulations within the country of
operation, may apply to the disposal of lithium batteries.
Technical Specifications
Protective fuse rating
The recommended maximum rating of the external protective fuse for this
equipment is 16A, Red Spot type or equivalent, unless otherwise stated in the
technical data section of the product documentation.
Insulation class: IEC 61010-1: 1990/A2: 1995 This equipment requires a

Class I protective (safety) earth
EN 61010-1: 1993/A2: 1995 connection to ensure user
Class I safety.
Installation IEC 61010-1: 1990/A2: 1995 Distribution level, fixed

Category Category III installation. Equipment in
(Overvoltage): EN 61010-1: 1993/A2: 1995 this category is qualification
Category III tested at 5kV peak,
1.2/50s, 500, 0.5J,
between all supply circuits
and earth and also between
independent circuits.
Environment: IEC 61010-1: 1990/A2: 1995 Compliance is demonstrated

Pollution degree 2 by reference to generic safety
EN 61010-1: 1993/A2: 1995 standards.
Pollution degree 2
Product safety: 73/23/EEC Compliance with the

European Commission Low
Voltage Directive.
EN 61010-1: 1993/A2: 1995 Compliance is demonstrated

EN 60950: 1992/A11: 1997 by reference to generic safety
standards.
Quadramho Distance Protection
Type SHPM 101
Service Manual
Chapter 1
Application
SERVICE MANUAL R5888B
QUADRAMHO Chapter 1
Contents
1. GENERAL 1
2. RELAY CHARACTERISTICS 1
3. SCHEMES AVAILABLE ON RELAY 1
4. CHOICE OF CHARACTERISTIC 2
5. CHOICE OF ZONE 1 IMPEDANCE REACH 2
8. POWER SWING BLOCKING FEATURE (PSB) 4
9. CHOICE OF RESISTIVE REACH OF QUADRILATERAL CHARACTERISTIC 4
10. AUTOMATIC COMPENSATION OF QUADRILATERAL REACH
LINE ANGLE 4
11. CHOICE OF ASPECT RATIO (LENTICULAR ZONE 3 CHARACTERISTIC) 5
12. CHOICE OF RELAY CHARACTERISTIC ANGLES 5
13. ZONE TIME DELAY SETTINGS 5
14. SWITCH-ON-TO-FAULT TRIPPING FEATURE (SOTF) 5
14.1 Performance of relay for earth faults 6
15. SELECTION OF SCHEME LOGIC PROGRAMS 7
16. SETTING OF SCHEME OPTION SWITCHES 7
17. DISCUSSION ON APPLICATION OF VARIOUS DISTANCE SCHEME
OPTIONS 7
17.1 Basic (see Figure 3) 7
17.2 Zone 1 extension (see Figure 4) 8
17.3 Permissive underreach transfer tripping (PUR see Figure 5) 8
17.4 Permissive overreach transfer tripping (POR see Figures 6 and 7) 8
17.5 Blocking (see Figure 8) 9
18. TIMER SETTINGS FOR DISTANCE SCHEME LOGIC OF QUADRAMHO 9
18.1 Permissive underreach scheme 9
18.2 Permissive overreach scheme 10
18.3 Blocking scheme 11
19. CURRENT TRANSFORMER REQUIREMENTS 12
19.1 Worked example No. 1 12
19.2 Data 13
19.3 Calculation of maximum and minimum source impedance at MAY 60kV 13
19.4 Selecting Zone 1 reach 14
19.7 Ground fault compensation settings 16
19.8 Setting restrictive reach of ground fault comparators 17
19.9 Checking minimum relay voltage for a fault at the Zone 1 reach point 17
19.10 Checking relay current sensitivity for faults at the Zone 3 reach point 18
19.11 Sketching relay characteristics 19
QUADRAMHO Chapter 1
Contents
19.12 Circuit transformer requirements 19

19.13 Worked example No. 2 21
19.14 Data 21
19.17 Selecting Zone 3 Reach 23
19.18 Ground fault compensation settings 23
19.19 Checking minimum relay voltage for a fault at the Zone 1 reach point 24
19.20 Sketching relay characteristics 26
19.21 Circuit transformer requirements 26
APPENDIX A 1
Figure 1: Basic relay characteristics 1
Figure 2: Principle of zone-1 reach line angular compensation 2
Figure 3: Basic-simplified distance scheme logic 3
Figure 4: Z1 EXT-simplified distance scheme logic 4
Figure 5: PUR-simplified scheme logic 5
Figure 6: POR-simplified distance scheme logic (with open terminal signal
echo feature) 6
Figure 7: POR-simplified distance scheme logic (with open terminal signal
echo feature and week infeed signal echo and trip feature) 7
Figure 8: PUR-simplified distance scheme logic 8
APPENDIX B 1
SKETCHING RELAY CHARACTERISTICS 1
QUADRAMHO Chapter 1
Page 1 of 27
Section 1. GENERAL
The Quadramho has been developed for use on medium to high voltage
transmission and distribution lines where traditionally switched distance schemes
have been used.
The relay is a full 3 zone distance scheme which eliminates the need for starting
and switching circuits, but which remains as compact as a switched relay because
it employs modern components and circuit techniques. A full distance scheme
allows better reliability and faster operating times than a switched distance
scheme.
Section 2. RELAY CHARACTERISTICS
There are two versions of the Quadramho to choose from, with the following
impedance characteristics:
Type A (mho) Zone 1, Zone 2 phase and ground fault : shaped partially
cross-polarised mho.
Zone 3, phase and ground fault : offset lenticular shape.
Type B (quad) Zone 1, Zone 2 ground fault : quadrilateral, with partially
cross-polarised directional line and load flow compensated
reach line.
Zone 3 ground fault : offset quadrilateral with load flow
compensated reach line.
Zone 1, Zone 2 phase fault : shaped partially cross-polarised
mho.
Zone 3 phase fault : offset circular mho.
See Figure 1 Appendix A, for examples of impedance
characteristics.
Note: Voltage transformer supervision and power swing blocking feature are
included with both models.
Section 3. SCHEMES AVAILABLE ON RELAY
There are 5 schemes available and each scheme can be selected as a three phase
tripping scheme or a single and three phase tripping scheme:
Basic three zone distance protection
Zone 1 extension scheme
Permissive underreach transfer tripping scheme
Permissive overreach transfer tripping scheme
Blocking scheme
QUADRAMHO Chapter 1
Page 2 of 27
Section 4. CHOICE OF CHARACTERISTIC
The Type A (mho) relay is suitable for protecting most lines, where their length and
source impedances are such that the resulting shaped Zone 1 characteristics
provide the required resistive coverage. The longer the line is, the higher the
Zone 1 and Zone 2 reach settings, hence the greater the resistive coverage will be
for ground faults. Also the higher the source impedance behind the relay, the
greater the Zone 1 and Zone 2 resistive expansion will be.
For the case of a long heavily loaded line, it may be that with the Zone 3 reach
settings required, the load impedance could encroach upon the Zone 3
characteristics if they were purely of the offset mho type or, if being used, the load
could encroach upon the power swing blocking starter characteristic. For such a
case the Type A (mho) allows the resistive reach of the Zone 3 and power swing
blocking starter characteristics, to be reduced with respect to their forward reach
(lenticular facility). This means that desired forward reaches can be attained
without problems of load encroachment.
For very short lines, where distance relay reach settings would be low, particularly
when there is a low source impedance behind the relay, the shaped Zone 1 and
Zone 2 impedance characteristics may not provide the required ground fault
resistive coverage. In such a case, the Type B (quad) relay could be used which
has a quadrilateral ground fault characteristic. This would allow the ground fault
resistive reach to be increased or decreased independently of the forward reach,
and source impedance behind the relay so that the required ground fault resistive
coverage can be achieved.
Section 5. CHOICE OF ZONE 1 IMPEDANCE REACH
Although in most applications the reach accuracy of the relay distance

comparators is 5%, greater errors can occur as a result of voltage and current
transformer errors and inaccuracies in line data from which the relay settings are
calculated. To prevent the possibility of relays tripping instantaneously for faults in
the next line, it is usual practice to set the Zone 1 reach of the relay to 80% of the
protected line section and rely on Zone 2 to cover the remaining 20% of the line.
With a signal aided distance protection scheme arrangement, the Zone 2 distance
comparators could provide fast triping at both ends of the line for end-zone faults.
If the Zone 1 extension scheme is used, it is usual practice to set the Zone 1
extension to 150% of the normal Zone 1 reach.
As a general rule, the Zone 2 impedance reach is set to cover the protected line
plus 50% of the shortest adjacent line. The reasoning behind the value of 50% is
that Zone 2 should cover at least 20% of the adjacent line, even in the presence of
typical additional infeed at the remote terminal of the protected line.
One case of additional infeed at the remote line terminal occurs when the
protected line is paralleled by another line. When a fault occurs in the adjacent
line, approximately equal currents will flow in each of the parallel lines. The relay
on the protected line, looking towards the fault, will see an impedance which will
QUADRAMHO Chapter 1
Page 3 of 27
be the sum of the protected line impedance, plus, twice the impedance of the
adjacent line to the fault. If the Zone 2 reach is set to cover 50% of the adjacent
line impedance, then in this parallel infeed case, Zone 2 will effectively cover 25%
of the adjacent line.
In most situations, if the relay reaches at least 20% into the adjacent line, then
faults at the remote terminal of the protected line will be well within Zone 2 reach
and so fast operation of the Zone 2 comparators will be achieved. This is
important if signal aided tripping schemes are used.
In some situations where the protected line is long and the adjacent line is short,
then a 50% reach into the adjacent line will only be a very small overreach of the
protected line. If the protected line is paralleled by another line, then it may be that
the zero sequence mutual coupling, between the two lines, will be sufficient to
prevent the Zone 2 comparators from seeing a ground fault at the remote terminal
of the line until the remote circuit breaker trips, preventing ground fault current
flowing in the healthy parallel circuit. In such a case the Zone 2 setting may need
to be increased slightly, to avoid sequential or time delayed clearance of the fault
at the terminal remote from the fault.
In a parallel line situation, a fault on one line which is cleared sequentially can
cause a fault current reversal in the healthy line. If the Zone 2 settings are greater
than 150% of the protected line impedance and the permissive overreach or
blocking scheme is being used, then a fault current reversal in the healthy circuit
could cause that circuit to be incorrectly tripped, unless special steps are taken.
The permissive overreach and blocking schemes both have current reversal guards
incorporated to prevent such maloperations. The operation of these current reversal
guards is explained in detail later, when considering some logic timer settings.
The Zone 3 forward reach should normally be set to cover the protected line
section, plus the longest adjacent section and 25% of a third section, to provide an
overall time delayed back-up protection. The reverse Zone 3 offset provides back-
up protection for the busbars behind the relay and would typically be set to 25%
of the Zone 1 setting.
When the blocking scheme or permissive overreach with weak infeed scheme is
being used, Zone 3 is required to provide a blocking function when it operates
without Zone 2, to prevent the protection scheme operating for reverse faults.
The reverse Zone 3 reach in this case must be set to reach further than Zone 2 of
the relay at the other end of the line. It must also be ensured that any resistive faults
behind the relay that are seen by Zone 2 of the remote end relay, are also seen by
Zone 3 of the local relay, to prevent tripping of healthy line for external faults.
As a general guide for most applications, it is recommended that the reverse Zone
3 reach is set to the same value as the Zone 2 setting of the remote end relay.
The forward Zone 3 reach should be set to minimum unless the power swing
blocking facility is also being used.
If the power swing blocking feature is to be used with the permissive overreach
scheme with weak infeed feature, or the blocking scheme, then the forward Zone 3
reach should be set to 120% of the Zone 2 reach. This could mean that the
overall diameter of the Zone 3 characteristic will be large, which could lead to
encroachment problems on the power swing blocking starter characteristic, which
QUADRAMHO Chapter 1
Page 4 of 27
is ganged to the Zone 3 setting. This situation is only likely to arise on long lines
where the type A (mho) relay will be in use. Full advantage will need to be taken
of the Zone 3 and power swing blocking lenticular facility in order to avoid load
encroachment problems.
Section 8. POWER SWING BLOCKING FEATURE (PSB)
The power swing blocking feature can be enabled or disabled by an option switch
and the individual distance zones to be blocked are also selectable via switches.
The inner power swing blocking impedance characteristic is formed by the A B
Zone 3 phase fault characteristic. The additional PSB starter characteristic has its
settings automatically ganged to the relay Zone 3 settings, so that the PSB
characteristic is concentric with the Zone 3 characteristic, but its dimensions are
such that its forward reach is 30% greater than the Zone 3 forward reach.
If the power system A B phase impedance locus enters the operating area of the
starter characteristic, but takes longer than 50ms to pass through into the Zone 3
operating area, then the PSB unit will block the selected zones if the A B phase
impedance does eventually pass into the Zone 3 operating area.
If the PSB feature is to be used, then when setting the Zone 3 impedance
characteristic, it must be ensured that the resulting PSB starter characteristic will not
be encroached upon by the minimum phase to phase load impedance (a 10%
impedance safety margin should be observed).
Section 9. CHOICE OF RESISTIVE REACH OF QUADRILATERAL CHARACTERISTIC
The resistive reach should be set to cover the desired level of ground fault
resistance, which would comprise arc resistance and tower footing resistance.
A 10% impedance margin should be observed between the resistive reach and the
minimum load impedance.
In addition to ensure Zone 1 reach accuracy, the resistive reach should not be set
greater than 15 times the Zone 1 ground loop reach.
Section 10. AUTOMATIC COMPENSATION OF QUADRILATERAL REACH

LINE ANGLE
For the quadrilateral ground fault characteristics, the phase current is in phase with
the resistive axis of the R/X diagram. The reach line for the Zone 1 characteristic is
in phase with the residual or neutral current measured (with a 3 droop). Thus if
there is a difference in angle between the measured phase current and neutral
current, then the Zone 1 reach line will be at a corresponding angle to the resistive
axis. This feature ensures that resistive ground faults on a double end fed loaded
system will not result in underreach or overreach of the relay.
The Zone 2 and Zone 3 reach lines and the Zone 3 offset lines are in phase with
the resultant angle of the measured neutral current, plus the relevant phase current.
A qualitative analysis of the purpose of reach line compensation for Zone 1 is
given in Figure 2.
QUADRAMHO Chapter 1
Page 5 of 27
Section 11. CHOICE OF ASPECT RATIO (LENTICULAR ZONE 3 CHARACTERISTIC)
The Zone 3 aspect ratio of the type A (mho) relay will need to be adjusted when it
is envisaged that there will be load encroachment problems on the Zone 3, or
power swing blocking starter characteristic for a long line application. The Zone 3
aspect ratio a/b should be set so that with the required Zone 3 forward and reverse
reach settings, the Zone 3 characteristic or, if used, the power swing blocking
starter characteristic has a 10% safety margin separating it from the load
impedance region.
Section 12. CHOICE OF RELAY CHARACTERISTIC ANGLES
Maximum accuracy and sensitivity is obtained by setting the relay angle Ph equal
to, or to the nearest setting above the line positivie sequence angle ( ZL1) and N
equal to, or to the nearest value above KN.ZL1 where KN is the neutral
compensation vector (see worked examples).
Section 13. ZONE TIME DELAY SETTINGS
The time settings tZ2 and tZ3 determine the time delay from detection of a fault by
the relevant zone to the operation of the trip output device.
The relay operates for the majority of Zone 1 faults within 16 30ms. The Zone 2
time delay should be set to allow for the longest Zone 1 operating time, or if
applicable, the longest aided trip time and the circuit breaker operating times.
Generally a Zone 2 time delay setting of 0.2 0.3s is satisfactory, but longer times
may be required if the Zone 2 reach overlaps slower forms of protection.
Zone 3 is generally intended to provide back-up protection even if it is being used
as a reverse looking blocking element. It may be overlapping other forms of
protection such as inverse definite minimum time overcurrent relays. The Zone 3
time delay will depend on the system to which the relay is applied, but in any case
it will be longer than the Zone 2 time delay and will typically have a setting of 1s.
Section 14. SWITCH-ON-TO-FAULT TRIPPING FEATURE (SOTF)
This feature is enabled by the scheme logic when the line circuit breaker has been
open for a certain time. To determine whether the line circuit breaker is open, the
relay looks for an all poles dead condition (voltage and current level detectors
have reset on each phase). For the case where a busbar VT is used, pole dead
signals will not be produced, but a normally closed circuit breaker auxiliary
contact can be used via an opto-isolator input, to inform the relay that the circuit
breaker is open. For single pole tripping applications, the circuit breaker auxiliary
contacts of each breaker pole should be wired in series and connected to the
relay, so that the relay is only made aware that all three poles of the breaker are
open.
The SOTF feature becomes enabled 200ms or 110s after the relay detects that the
local circuit breaker has opened, depending on the setting of an option switch on
the front of the relay.
QUADRAMHO Chapter 1
Page 6 of 27
In the majority of applications, the SOTF enable timer switch will be set to the
200ms position, so that the feature will be available as soon as possible after the
line becomes dead. With this short time setting, the SOTF feature will be enabled
during autoreclose dead times, so that upon reclosure a SOTF trip is possible.
This is usually advantageous for most distance schemes, since a persistent fault in
the remote end of a protected line section can be cleared instantaneously after
reclosure of the local breaker, rather than after the Zone 2 time delay.
Where it is desired that a SOTF indication is not given after autoreclosure, or dual
shot autoreclosing is to be employed, then the 110s SOTF enable timer setting
should be used. This will ensure that the SOTF feature could not be enabled during
autoreclosure dead times. If a SOTF trip was allowed to occur on autoreclose, the
distance relay would also give a block autoreclose signal to the autoreclose relay
and any second autoreclose shot would be prevented.
SOTF tripping is only possible for the initial 240ms after line circuit breaker
closure. During this time with an option switch set to one position, the operation of
any distance comparator will give an instantaneous trip. With the option switch set
to the other position, the pick-up of any current level detector without its
corresponding voltage level detector picking-up within 20ms, will give an
instantaneous trip.
With the relay set to give a SOTF trip for any distance comparator operation, then
any fault existing on the protected line, including a close-up, 3 phase bolted fault
would be cleared. For the latter fault, where line VTs are used, there would be no
memory voltage to allow Zone 1 or Zone 2 distance comparator operation, but
Zone 3 will operate as it has a fixed offset. Faults at the remote end of the line will
also be cleared instantaneously by a SOTF trip when the local circuit breaker is
closed.
In some situations, it may be possible for the magnetising inrush current of banked
transformers at the end of a line, or particularly of teed-off transformers, to cause
transient operation of the Zone 3 comparators on line energisation, resulting in an
incorrect SOTF trip. In such a situation, the SOTF trip option switch should be set,
so the SOTF tripping will only occur when a current level detector picks up without
the corresponding voltage level detector picking up.
On versions of Quadramho, for use with miniature circuit breakers, the switch-on-
to-fault feature is blocked via the opto coupler when the MCB is open.
14.1 Performance of relay for earth faults
On resistance-earthed systems, the quadrilateral characteristic is beneficial for
ground fault protection in that, unlike the cross-polarised mho characteristic, its
faults resistance coverage is not reduced with increased earthing resistance behind
the relaying point.
Quadramho requires its low-set neutral current detector to operate before its
ground fault impedance elements are enabled. In an application where a system is
insulated behind the relaying point, the neutral current produced in the relay for
forward ground faults would be below the sensitivity of the low-set neutral current
detector, which would prevent operation of the ground fault impedance elements.
For reasons given in Chapter 2, the low-set neutral current detector has a sensitivity
which is biased according to the magnitude of the greatest phase difference
current, (vectoral difference).
QUADRAMHO Chapter 1
Page 7 of 27
For ground faults on multiple-earthed systems, it is possible, due to healthy phase

current levels, for the magnitude of the greatest phase difference current to be
larger than the neutral current at the relaying point. It is extremely unlikely,
however, for the ratio of these two currents to exceed the level of 10, which would
need to be reached before the low-set neutral detector failed to operate for a
ground fault.
Section 15. SELECTION OF SCHEME LOGIC PROGRAMS
The distance scheme logic programs are selected by setting two coded selector
switches to a particular two-digit number. A list of scheme codings is given in
Chapter 2.
Section 16. SETTING OF SCHEME OPTION SWITCHES
SW1 (LEFT) SOTF tripping initiated by comparators

(RIGHT) SOTF tripping initiated by level detectors
SW2 (LEFT) SOTF enable time = 110s
(RIGHT) SOTF enable time = 200ms
SW3 (LEFT) VTS indicates only
(RIGHT) VTS indicates and blocks relay
SW4 (LEFT) Normal block autoreclose action
(RIGHT) Block autoreclose also for Z1 and aided trip 3 phase faults
SW5 (LEFT) Self checking feature disabled
(RIGHT) Self checking feature enabled
SW6 (LEFT) Normal block autoreclose
(RIGHT) Block autoreclose also for signalling channel out of service
SW7 (LEFT) Disable trip by weak infeed feature
(RIGHT) Enable trip by weak infeed feature
SW8 (LEFT) POR weak infeed feature disabled
(RIGHT) POR weak infeed feature enabled
SW9 (LEFT) Power swing blocking function disabled
(RIGHT) Power swing blocking function enabled
Section 17. DISCUSSION ON APPLICATION OF VARIOUS DISTANCE

SCHEME OPTIONS
17.1 Basic (see Figure 3)

This scheme does not require signalling channels.
A major disadvantage is that not all the faults within a protected section
can be cleared instantaneously by distance relays at both ends.
Scheme is suitable for a single circuit radial line where a distance relay
would be used at the source end only.
QUADRAMHO Chapter 1
Page 8 of 27
If the relay is for use with miniature circuit breaker to break the VT supply, then the
opto used for reset Zone 1 extension is on case terminals A9 and A10 shared
function with signal received if an aided scheme is selected.
17.2 Zone 1 extension (see Figure 4)
This scheme does not require a signalling channel.
Normally Zone 1 phase and ground fault comparator reaches are extended by
an amount to overreach the remote end of a protected line section.
Scheme is intended for use with autoreclose equipment. After a fault occurs, the
autoreclose equipment gives a reset signal to the extension facility so that
Zone 1 phase and ground fault reaches fall back to normal setting.
Scheme provides fast clearance of most transient faults. On the basis that most
overhead line faults are transient in duration, the scheme will allow fast
clearance of most faults along the protection section and also those just out of
the section. Lack of discrimination does not matter as autoreclosure of the
protection section circuit breaker(s) will take place.
The operation of the autoreclose relay is used to reset the extension facility so
that if the fault is permanent, upon reclosure, the faulted section of line will be
cleared permanently by its own protection as in the BASIC scheme.
Scheme would not normally be used for cable circuits although its use might be
considered for hybrid circuits.
17.3 Permissive underreach transfer tripping (PUR see Figure 5)
This scheme requires only one signalling channel for both relays, as channel is
keyed by underreaching Zone 1 elements.
Provided underreaching Zone 1 element reaches "overlap", fast clearance of
faults along the whole line section will be effected. If a line terminal is open,
then a fast tripping will only occur for faults within the Zone 1 reach of the
closed end relay.
If the signalling channel fails, the line relays will still provide BASIC protection.
Fast clearance will not occur for all faults along the protected line section if
there is little or no infeed at one terminal.
17.4 Permissive overreach transfer tripping (POR see Figures 6 and 7)
This scheme requires duplex signalling channels; one frequency for each relay,
as channel is keyed by overreaching Zone 2 elements.
This scheme may be more advantageous than PUR for protecting short lines
the resistive coverage of the Zone 2 mho circles would be greater than that of
the Zone 1 reach set to a small value. Thus POR enables fast tripping for higher
resistance faults along a line than does PUR.
For standard POR schemes, if a line terminal is open, then as with PUR, fast
tripping will only occur for faults within the Zone 1 reach of the closed end
relay. However, with Quadramho a "signal echo" feature is included in the
scheme logic, which is initiated when the local line terminal is open (CB aux
contact initiation). By such means the closed end relay will be able to provide
fast tripping for faults along the whole length of the line.
If the signalling channel fails the line relays will only provide BASIC protection.
QUADRAMHO Chapter 1
Page 9 of 27
For standard POR schemes, fast clearance will not occur for all faults along the
protected line section if there is weak or no infeed at one terminal. It is possible
with Quadramho to switch in a weak infeed feature which will allow aided
tripping of the strong infeed relay and three phase tripping of the weak infeed
relay. The feature used undervoltage logic and Zone 3 elements set to be
reverse looking.
17.5 Blocking (see Figure 8)
This scheme requires only one signalling channel for both relays.
Two forward zones of protection are available, as Zone 3 elements are required to
be reverse looking, for initiating blocking signal.
This scheme will provide similar resistive fault coverage to POR.
If a line terminal is open, fast tripping will still occur for faults along the whole of
the protected line length.
If the signalling channel fails, fast tripping will occur for faults along the whole of
the protected line, but also for some faults within the next line section.
Fast tripping will still occur at a strong source line terminal, for faults along the
protected line section, if there is weak or no infeed at the other terminal.
Section 18. TIMER SETTINGS FOR DISTANCE SCHEME LOGIC OF QUADRAMHO
18.1 Permissive underreach scheme

Operating conditions:
Zone 1 operation > instantaneous trip + signal transmit
Zone 2 operation + signal receive > instantaneous trip
Special aspects to consider:
A B A Open B
a) Fault occurs busbar voltage b) End A relay clears fault and

low so negligible fault current current starts feeding from
via end B. end B.
SINGLE END FED DOUBLE CCT LINE, FAULT CLOSE UP

In the situation outlined above, end B receives a permissive trip signal from the
faulted circuit relay at end A. A trip cannot occur at end B however, because it
sees negligible fault current. When end A trips, end B sees a Zone 2 fault, but end
QUADRAMHO Chapter 1
Page 10 of 27
A has ceased to transmit a signal. It may be that end B will cease to receive a
signal before its Zone 2 element picks up, in which case there would not be a fast
trip. It is therefore necessary to have a delay on reset of the signal received, so
that in the case above, end B will be allowed to fast trip when its Zone 2 element
picks up.
Time delay t = 100ms
Refer to Figure 68, Chapter 2 for block diagram of permissive underreach scheme.
18.2 Permissive overreach scheme
Zone 1 operation > instantaneous trip
Zone 2 operation > signal send
Zone 2 operation + signal receive > instantaneous trip
A B A Open B
Strong Strong
Weak Weak
a) Fault occurs b) End A relay trips
CURRENT REVERSAL AFTER NEAREST CB OPENS

The current reversal guard incorporated in the scheme logic is initiated when a
healthy circuit relay receives a permissive trip signal, but does not have a Zone 2
element picked up. A delay on pick up (tp) of the current reversal guard is
necessary in order to allow time for Zone 2 elements to pick up, if they are going
to time, for an internal fault.
Recommended setting tp = 30ms signalling channel P/U time
(or nearest setting above this value)
Once the current reversal guard has picked up (healthy circuit relay at end A),
transfer tripping is inhibited. The reset of the guard is initiated by either the loss of
permissive trip signal or by the pick up of a Zone 2 element. A time delay (tD) for
the reset of the reversal guard, is required in case the Zone 2 element (end A)
picks up before the permissive trip signal from the other relay (end B) has reset
which could cause healthy circuit tripping.
Recommended setting tD = signalling channel D/O time + 25ms
(or nearest setting above this value)
Refer to Figures 69 and 70, Chapter 2, for block diagram of permissive overreach
scheme.
QUADRAMHO Chapter 1
Page 11 of 27
18.3 Blocking scheme

Zone 1 operation > instantaneous trip
Reverse Zone 3 operation without Zone 2 operation > transmit blocking
signal
Zone 2 operation without signal received > instantaneous trip
Special aspects to consider:
A delay on instantaneous tripping (tP) after Zone 2 operation is required to allow
time for a possible blocking signal to arrive from the relay at the other line end.
Recommended setting:
tP = signalling channel P/U time + x (or nearest setting above this value)
x = 25ms for quad/mho relay
= 30ms for mho/lenticular relay, a/b = 1
= 35ms for mho/lenticular relay, a/b = 0.69
= 40ms for mho/lenticular relay, a/b = 0.41
A B A Open B
Strong Strong Weak
Weak
Block Block
a) Fault occurs b) End A relay trips
CURRENT REVERSAL AFTER NEAREST CB OPENS

In case (a) the healthy line end B relay has its Zone 2 element operated, but
instantaneous operation is blocked by carrier signal transmitted from end A. When
the relay near the fault trips, current reversal takes place in the healthy circuit and
end A ceases to transmit a blocking signal. However, it takes Zone 2 at end B a
few ms to reset. If this relay loses the blocking signal before Zone 2 has reset, an
instantaneous trip will occur on the healthy circuit. A slight delay on reset of the
signal received is therefore required to allow the relay Zone 2 elements to reset on
current reversal.
Recommended setting:
tD = 0 if signalling channel reset time is 10ms or greater
tD = 12ms if signalling channel reset time is less than 10ms
Refer to Figure 71, Chapter 2, for block diagram of blocking scheme.
QUADRAMHO Chapter 1
Page 12 of 27
Section 19. CURRENT TRANSFORMER REQUIREMENTS
Class X CT are required to meet the following specification:

a) VK IF(1 + X/R) (ZR + RCT + RL) for phase faults
IFe(1 + Xe/Re) (ZRe + RCT + 2RL) for ground faults
where VK = required CT kneepoint voltage
IF = maximum secondary fault current for a 3 phase fault at the
Zone 1 reach point
IFe = maximum secondary fault current for a ground fault at the
Zone 1 reach point
X/R = system reactance/resistance ratio between source and a three
phase fault
Xe/Re = system reactance/resistance ratio between source and a
ground fault
ZR = relay burden for a phase
ZRe = relay burden for a ground fault
RCT = CT secondary winding resistance
RL = resistance of one lead between CT and relay
b) Ie 0.1 In at VK
where Ie = CT exciting current
In = CT rated secondary current
Where necessary, ALSTOM T&D Protection & Control Ltd, can supply details of
reduced CT requirements on some systems.
19.1 Worked example No. 1
To protect a 10km single circuit, wooden pole, 60kV overhead line using a
permissive overreach transfer tripping scheme or Zone 1 extension scheme.
150/60kV
50MVA
April 60kV 12.5%
May 60kV
30km
2 x 150/60kV July 60kV
50MVA June 60kV
12.5%
10km 20km
150/60kV
R 10MVA
10%
EXAMPLE SYSTEM
QUADRAMHO Chapter 1
Page 13 of 27
19.2 Data
Line to be protected: 10km, 60kV, single circuit between MAY 60kV and JUNE
60kV substations.
Note: Sample calculations will be presented for MAY relay only.
Special requirement: Line protection must be able to clear ground faults with up to
40 ohms fault resistance.
Assumptions: 150kV fault level is infinite at each bulk supply point.
Transformers have an X/R ratio equivalent to 87.
Line data:
Positive sequence series impedance (Z1) = 0.5 /70 ohm/km
= (0.171 + j0.47) ohm/km
Zero sequence series impedance (Z0) = 2.0 /68 ohm/km
= (0.749 + j1.85) ohm/km
Voltage transformer ratio = 60,000/110 volt
Current transformer ratio = 200/5A
Line length = 10km
Relay selected: Quadramho type B, with quadrilateral ground fault
impedance characteristics. This is because the line is short
and a high resistive coverage is required for ground faults.
Scheme to be used: Permissive underreach transfer tripping scheme which
requires only a single signalling channel. Alternatively the
Zone 1 extension scheme may be selected if a signalling
channel is not available.
19.3 Calculation of maximum and minimum source impedance at MAY 60kV
a) Minimum source impedance is when both 50MVA transformers at MAY are
switched in and the 50MVA transformer at APRIL is switched in.
Positive and zero sequence impedances of each 50MVA transformer:
2
= 0.125 x 60 = 9.0/87 = (0.47 + j8.99) ohms
50
Positive sequence impedance of each APRIL MAY line:
= 30 x (0.171 + 0.47) = (5.13 + j14.1) ohms
Zero sequence impedance of each APRIL MAY line:
= 30 x (0.749 + j1.85) = (22.5 + j55.5) ohms
Positive sequence impedance of APRIL MAY line in parallel plus the APRIL
transformer impedance:
= (5.13 + j14.1) + (0.47 + j8.99) = (3.04 + j16.04) ohms
2
Zero sequence impedance of APRIL MAY lines in parallel plus APRIL
transformer impedance:
= (22.5 + j55.5) + (0.47 + j8.99) = (11.7 + j36.74) ohms
2
QUADRAMHO Chapter 1
Page 14 of 27
Positive and zero sequence impedance of MAY transformers in parallel:

= (0.47 + j8.99) = (0.24 + j4.5)
2
Overall minimum MAY positive sequence source impedance:
= (3.04 + j16.04) in parallel (0.24 + j4.5)
= (0.287 + j3.52) = 3.53 /85.3 ohms
Overall minimum MAY zero sequence source impedance:
= (11.7 + j36.7) in parallel (0.24 + j4.5)
= (0.32 + j4.05) = 4.06 /85.5 ohms
b) Maximum source impedance at MAY 60kV is when both 50MVA transformers
at MAY are switched out, the 50MVA transformer at APRIL is switched in and
only one of the parallel lines between APRIL and MAY is switched in.
Maximum MAY positive sequence source impedance:
= (0.47 + j8.99) + (5.13 + j14.1)
= (5.6 + j23.1) = 23.8 /76.4 ohms
Maximum MAY zero sequence source impedance:
= (0.47 + j8.99) + (22.5 + j55.5)
= (22.97 + j64.5) = 68.5 /70.4 ohms
19.4 Selecting Zone 1 reach
Required Zone 1 reach is to be 80% of the MAY JUNE line impedance.
Ratio of secondary impedance to primary impedance:
= 110 x 200 = 0.073
5 60 x 103
Required Zone 1 reach:
= 0.8 x 10 (0.171 + j0.47) ohms primary
= 4.0 /70 ohms primary
= 0.292 /70 ohms secondary
The relay coarse reach (ZPh) should be set to the nearest value below the required
Zone 1 reach. It is important to set ZPh as high as possible since the relay current
level detector sensitivities are inversely proportional to ZPh and it is best to have the
most sensitive settings possible.
K1 + K2
ZPh = Ph in this case rated current In = 5A
In
Select Ph = 70
K1 + K2 0.292 K1 + K2 1.46
5
Select K1 = 1
K2 = 0.4
Actual ZPh = 0.28 /70
QUADRAMHO Chapter 1
Page 15 of 27
With K1 + K2 = 1.4 current level detector sensitivities:

= 4.8 x base settings = 3.43 x base settings
1.4
Required Zone 1 multiplier setting = required Zone 1 reach
ZPh
= 0.292 x In = 0.292 x 5 = 1.043
(K1 + K2) 1.4
Zone 1 multiplier = (K11 + K12 + K13) K14

Select K11 = 1
K12 = 0.0
K13 = 0.04
K14 = 1
Actual Zone 1 setting = (K11 + K12 + K13) K14 x ZPh
= 1.04 x 1 x 1.4 = 0.291 /70 ohms
5
Required Zone 2 reach = +50% (JUNE JULY line impedance) MAY JUNE
line impedance.
Required Zone 2 reach = (10 + 0.5 x 20) (0.171 + j0.47) ohms
= 10.0/70 ohms primary
= 0.73/70 ohms secondary
ZPh
= 0.73 x 5 = 2.61
1.4
Zone 2 multiplier = (K21 + K22) K24
Select K21 = 2
K22 = 0.6
Actual Zone 2 setting = (K21 + K22) K24 x ZPh
= 2.6 x 1 x 1.4 = 0.728 /70 ohms
5
Required Zone 3 forward reach = +125% (JUNE JULY line impedance) MAY
JUNE line impedance.
Required Zone 3 forward reach = (10 + 1.25 x 20) (0.171 + j0.47)
Required Zone 3 forward reach multiplier
= required Zone 3 forward reach
|ZPh|
QUADRAMHO Chapter 1
Page 16 of 27
= 1.28 x 5 = 4.57
1.4
Zone 3 forward multiplier = (K31 + K32) K33
Select K31 = 4
K32 = 0.6
K33 = 1
Actual Zone 3 forward reach = (K31 + K32) K33 x ZPh
= 4.6 x 1 x 1.4 = 1.29 ohms
5
Required Zone 3 reverse reach = 25% zone 1 reach
Zone 1 reach = 0.219 ohms secondary
Required Zone 3 reverse reach = 0.25 x 0.291 = 0.073 ohms secondary
Required Zone 3 reverse reach multiplier
= required Zone 3 reverse reach
|ZPh|
= 0.073 x 5 = 0.26
1.4
Zone 3 reverse reach multiplier = (K35 + K36) K33 x K37
Select K35 = 1
K36 = 0.0
K37 = 0.25
Actual Zone 3 reverse reach = (K35 + K36) K33 x K37 x ZPh
= 1.0 x 1 x 0.25 x 1.4 = 0.07 /70 ohms

5
19.7 Ground fault compensation settings
Ground loop impedance of line ZLE = (1 + KN) ZL1
ZL0 ZL1
where KN =
3ZL1
Neutral impedance coarse setting ZN = KN = ZPh
(0.749 + j1.85)
ZLO ZL1 = (0.171 + j0.47) = 1.5 /67.3
(0.578 + j1.38)
1.5 /67.3
KN = = 1.0 /2.7 (100% compensation)
3 x 0.5 /70
Compensation setting = KN x ZPh
= 1.0 /27 x 1.4 /70 = 0.28 /67.3
5
Select (K4 + K5 +K6) = 0.28
5
(K4 + K5 +K6) = 1.4
QUADRAMHO Chapter 1
Page 17 of 27
Select K4 =1
K5 = 0.4
K6 = 0.00
N /KN.ZPh N 67.3
Select N = 70
Actual ZN = 0.28 /70 ohms
Coarse ground loop impedance = ZPh + ZN = 0.28 /70 + 0.28 /70
= 0.56 /70 ohms
19.8 Setting restrictive reach of ground fault comparators
Required primary resistive coverage for ground faults = 40 ohms
40 ohms primary = 2.92 ohms secondary
Minimum load impedance likely to be seen by ground fault distance comparators
60 x 103
= = 173 ohms primary
3 x 200
=12.6 ohms secondary
There will, therefore, be no problems of load encroachment on the ground fault
comparator operating regions, if the comparators are set to see 40 ohms primary
fault resistance.
Select nearest resistive reach setting above that required.
RS = K3 = K3 = 2.92 ohms
In 5
Select K3 = 16
Actual resistive reach = 3.2 ohms secondary = 43.8 ohms primary
Check on ratio of resistive reach/Zone 1 forward ground loop reach
3.2
= = 5.49
(0.56 /70) x 1.04
The above ratio is within the limit of 15 (see Section 9)
19.9 Checking minimum relay voltage for a fault at the Zone 1 reach point
Maximum positive sequence impedance behind relay = 23.8 /76.4 ohms
Impedance to Zone 1 reach point = 4 /70
Overall source to fault impedance = (5.6 + j23.1) + (1.37 +j3.76)
= (6.97 + j26.9) = 27.8/75.5
Relay voltage for a phase fault at the Zone 1 reach point
= 4.0 x 110 = 15.8 volts
27.8
Maximum zero sequence impedance to the Zone 1 reach point is 16 /68 ohms
Source ground loop impedance = 2 x (5.6 + j23.1) + (22.94 + j64.4)
3
= (11.34 + j36.87) = 38.6 /72.9
QUADRAMHO Chapter 1
Page 18 of 27
Ground loop impedance to Zone 1 reach point

= 2 x (1.37 + j3.76) + (5.99 + j14.8)
3
= (2.91 + j7.44) = 7.99 /68.6
Source to fault ground loop impedance
= (11.34 + j36.87) + (2.91 + j7.44)
= (14.25 + j44.31) = 46.55 /72.2
Relay voltage for a ground fault at the Zone 1
Reach point = 7.99 x 63.5 = 10.91 volts

46.55
For 5% reach accuracy with the Zone 1 multiplier set to unity Quadramho
requires at least 2.05 volts for the ground fault measurement or at least 3.55 volts
for phase fault measurement. For 10% accuracy the required voltages are 1.04
and 1.8 volts respectively. For Zone 1 multipliers greater than unity, the required
relay voltages for accuracy vary linearly with the multiplier setting.
In this, the Zone 1 multiplier = 1.04. Thus the required voltages for 5% reach
accuracy are:
1.04 x 2.05 = 2.13 volts for ground faults
1.04 x 3.55 = 3.69 volts for phase faults
Both voltage requirements are met in this application.
19.10 Checking relay current sensitivity for faults at the Zone 3 reach point
The worst case will be for an ground fault at the Zone 3 reach point.
Maximum source ground loop impedance behind relay.
= 38.6 /72.9 = (11.35 + j36.9)
Relay Zone 3 earth fault setting = (ZPh + ZN) x Z3 multiplier
= (1.4 + 1.4) /70 x 4.6 = 2.58 /70 ohms secondary

5 5
= (12.1 + j33.2) ohms primary
Overall source to fault ground loop impedance (including 40 ohms fault resistance)
= (11.35 + j36.9) + (12 .1 + j33.2) +40
= (63.5 + j70.1) ohms
= 94.6 /47.8
Current for a fault at the Zone 3 reach point
60 x 103
= = 366A = 183% of CT rating (200/5A)
3 x 94.6
ZPh
Relay current level detector sensitivities = max x base level
ZPh
QUADRAMHO Chapter 1
Page 19 of 27
For the low set phase current level detectors in this application:
Sensitivity = 4.8 x 5% = 17.1%

1.4
The low set phase current level detectors, therefore, have adequate sensitivity for
faults at the Zone 3 reach point.
19.11 Sketching relay characteristics
Using the methods described in Appendix B, the relay characteristics can be
sketched. It is unlikely that the power swing blocking facility would be used in this
particular application, but the power swing blocking characteristics have been
sketched for completeness.
19.12 Circuit transformer requirements
The requirements for the Class X CTs are given in Section 19.
a) Phase fault condition
Minimum positive sequence source impedance behind relay
= (0.287 + j3.52) = 3.53 /85.3 ohms
Positive sequence impedance to Zone 1 reach point
Overall minimum source to Zone 1 reach point phase fault impedance
= (0.287 + j3.52) + (1.37 + j3.76) ohms
= (1.66 + j7.28) ohms
= 7.47 /77.2 ohms
X/ ratio = 7.28 1.66 = 4.39
R
Maximum 3 phase fault current at Zone 1 reach point
60 x 103
= = 4637A primary
3 x 7.47
= 4637 x 5 = 116A secondary

200
Relay burden for a phase fault is 0.03 ohms
Assuming: CT resistance = 0.06 ohms
CT lead resistance = 15m of 6.0 mm2 copper
(3.09 ohms/km)
= 0.046 ohm
CT kneepoint voltage requirement for a 3 phase fault is given by:
VK 116 (1 + 4.39) (0.03 + 0.06 + 0.046)
VK 85 volts
QUADRAMHO Chapter 1
Page 20 of 27
b) Ground fault condition

Minimum zero sequence source impedance behind relay
= (0.32 + j4.05) = 4.06 /85.5 ohms
2ZS1 + ZS0
Source ground loop impedance =
3
Minimum source ground loop impedance
= 2(0.287 + j3.52) + ( 0.32 + j4.05)
3
= (0.298 + j3.7)
= 3.71 /85.4
= (2.91 + j7.44 = 7.99 /68.6 ohms
Primary overall minimum source to Zone 1 reach point
Ground loop impedance = (0.298 + j3.7) + (2.91 + j7.44)
= (3.21 + j11.14)
= 11.6 /74
Xe/ ratio + 11.14 = 3.47
Re
3.21
Maximum ground fault current at Zone 1 reach point
60 x 103
= = 2986A primary
3 x 11.6
= 2986 x 5 = 74.7A secondary

200
Relay burden for a ground fault is 0.056 ohms
CT lead resistance = 0.046 ohms
VK 4.7 (1 + 3.47) (0.056 + 0.06 + 0.092)
VK 69.5 volts
It is also required that at the CT kneepoint voltage (which according to preceding
calculations should be at least 85V) the CT exciting current should be less than
500mA.
QUADRAMHO Chapter 1
Page 21 of 27
19.13 Worked example No. 2

To set distance protection at one end of 60 km double circuit 132kV line on steel
towers for use in a directional comparison blocking scheme.
max 5000MVA 500MVA

min 700MVA R equivalent
equivalent source
source 20km 60km 40km
Jan 132 Feb 132 March 132 Aug 132
19.14 Data
Line to be protected: 60km, 132kV double circuit between FEB 132 and March
132 (settings for FEB relay only) using Quadramho Type A.
Line data:
Positive sequence series impedance = Z1 = 0.44 /69 ohms/km
= (0.16 + j0.41) ohm/km
Zero sequence series impedence = Z0 = 1.09 /72 ohms/km
= (0.34 + j1.03) ohms/km
VT ratio = 132000/110V
CT ratio = 500/1A
Source data:
JAN 132 min source impedance = 3.48 /88
max source impedance = 24.9 /88
ZS0/ZS1 = 1.0 /0
AUG 132 source impedance = 34.8 /88
ZS0/ZS1 = 1.0 /0
Required Zone 1 reach is to be 80% of FEB MARCH line impedance
Ratio of secondary impedance to primary impedance
= 110 x 500 = 0.417
1 132 x 103
Required Zone 1 reach
= 0.8 x 60 x 0.44 /69 ohms primary
QUADRAMHO Chapter 1
Page 22 of 27
The relay coarse reach (ZPh) should be set to the nearest value below the required
Zone 1 reach. It is important to set ZPh as high as possible since the relay current
level detector sensitivities are inversely proportional to |ZPh| and it is best to have
the most sensitive settings possible.
ZPh = K1 + K2 ; Ph in this case rated current = 1A

In
Select Ph = 70
K1 + K2 = 8.8
Select K1 = 4
K2 = 0.8
Actual ZPh = 4.8 /70
With K1 + K2 = 4.8 (max value) current level detector sensitivities are at their
base values.
Required Zone 1 multiplier setting
= required Zone 1 reach
|ZPh|
= 8.8 = 1.83
4.8
Select K11 = 1
K12 = 0.8
K13 = 0.02
K14 = 1
Actual Zone 1 setting = (K11 + K12 + K13) K14 x ZPh
= 1.82 x 1 x 4.8 /70
Required Zone 2 reach =
FEB MARCH line impedance + 50% (MARCH AUG line impedance)
Required Zone 2 reach
= 60 x 0.44 /69 + 0.5 x 40 x 0.44 /69
|ZPh|
= 14.68 = 3.06
4.8
Select K21 = 3
K22 = 0.1
Actual Zone 2 reach = (K21 + K22) ZPh
= 3.1 x 4.8 /70 = 14.88 /70 ohms secondary
QUADRAMHO Chapter 1
Page 23 of 27
19.17 Selecting Zone 3 Reach

Blocking scheme is to be used so reverse Zone 3 reach should be set to Zone 2
reach of remote end relay (at MARCH 132 substation).
Zone 2 reach of remote end relay would be:
= MARCH FEB line impedance + 50% (FEB JAN line impedance)
= 60 x 0.44 /69 + 0.5 x 20 x 0.44 /69
Thus required Zone 3 reverse reach = 30.8 /69 ohms primary
Required Zone 3 reverse reach multiplier
= required reverse reach
|ZPh|
= 12.84 = 2.68
4.8
Select K35 = 2
K36 = 0.7
K33 = 1
K37 = 1.0
Actual Zone 3 reverse reach = (K35 + K36) K33 x K37 x ZPh
= 2.7 x 1 x 1 x 4.8 /70
Required Zone 3 forward reach = minimum possible if power swing blocking is
not required
Select K31 = 1
K32 = 0.0
Actual Zone 3 forward reach = (K31 + K32) x K33 x ZPh
= 1.0 x 1 x 4.8 /70
Alternatively if power swing blocking is required, the required Zone 3 forward
reach 120% of Zone 2 forward reach. Use of the Zone 3 lenticular settings may
be required to prevent load impedance encroaching on the Zone 3 and power
swing blocking impedance characteristics.
19.18 Ground fault compensation settings
Ground loop impedance of line ZLE = (1+KN) ZL1
ZL0 ZL1
where KN = Neutral impedance coarse setting = ZN = KN ZPh
3ZL1
ZLO ZL1 = (0.34 + j1.03) (0.16 + j0.41)

= (0.18 + j0.62) = 0.65 /73.8
KN = 0.65 /73.8 = 0.492 /4.8 (49% compensation)
3 x 0.44 /69
QUADRAMHO Chapter 1
Page 24 of 27
Compensation setting = KN x ZPh

= 0.492 /4.8 x 4.8 /70
= 2.36 /74.8
ZN = K4 +K5 + K6 /QN
In
Select K4 = 2
K5 = 0.3
K6 = 0.06
N = 75
Actual ZN = 2.36 /75
Course ground loop impedance = ZPh + ZN
= 4.8 /70 + 2.36 /75
= (1.64 + j4.5) + (0.61 + j2.28)
= (2.25 + j6.78) = 7.14 /71.6
19.19 Checking minimum relay voltage for a fault at the Zone 1 reach point
a) Phase faults:
Maximum positive sequence impedance behind relay is a maximum JAN source
impedance plus one circuit only of JAN FEB line.
= 24.9 /88 + 20 x 0.44 /69
= (0.87 + j24.88) + (3.15 + j8.22)
= (4.02 + J33.1) = 33.3 /83.1
Impedance to Zone 1 reach point = 8.74 /70 ohms secondary
Total source to Zone reach point impedance
= (4.02 + j33.1) + (7.17 + j19.7)
= (11.19 +j52.8)
For a phase fault voltage seen by relay
= 20.96 /70 x 110
53.97 /78
Magnitude = 42.7V
QUADRAMHO Chapter 1
Page 25 of 27
b) Ground faults:
Maximum ground loop impedance behind relay is maximum JAN source
ground loop impedance plus ground loop impedance of a JAN FEB circuit.
Ground loop impedance of JAN source = 24.9 /88 ohms max
Ground loop impedance of JAN FEB circuit
= 20 x (2 x 0.44 /69 + 1.09 /72
3
= 20 x (0.32 + j0.82) + (0.33 + j1.04)
3
= (4.33 + j12.4) = 13.13 /70.8 ohms primary
Ground loop impedance behind relay
= 24.9 /88 + 13.13 /70.8
= 37.6 /82.1
= (K11 + K12 + K13) K14 x (ZPh + ZN)
= 1.82 x 7.14 /71.6
= 13.0 /71.6 ohms secondary
= 31.16 /71.6 ohms primary
Source to Zone 1 reach point ground loop impedance
= (5.17 + j37.2) + (9.84 + j29.6)
= (15.01 + j66.8)
= 68.5 /77.3 ohms
For a ground fault voltage seen by relay
= 31.16 /71.6 x 63.5
68.5 /77.3
Magnitude = 28.9 volts
For 5% reach accuracy with the Zone 1 multiplier set to unity, Quadramho
requires at least 2.05V for ground fault measurement, or at least 3.55V for phase
fault measurement. For 10% accuracy the required voltages are 1.04 and 1.8V
respectively. For Zone 1 multipliers greater than unity, the required relay voltages
for accuracy vary linearly with the multiplier setting.
In this case the Zone 1 multiplier = 1.82. Thus the required voltages for 5% reach
accuracy are:
1.82 x 2.05 = 3.73 volts for ground faults
1.82 x 3.55 = 6.46 volts for phase faults
Both voltage requirements will be met in this application.
QUADRAMHO Chapter 1
Page 26 of 27
19.20 Sketching relay characteristics

Using the methods described in the Appendix B the relay impedance
characteristics can be sketched.
19.21 Circuit transformer requirements
The requirements of the Class X CT are given in Section 19.
a) Phase fault condition:
Minimum positive sequence source impedance behind relay (neglecting small
infeed via parallel FEB MARCH circuit from AUG source) is the minimum JAN
source impedance plus the impedance of the two JAN - FEB circuits in parallel.
20
= 3.48 /88 + x 0.44 /69
2
= (0. 12 + j3.48) + (1.58 + j4.11)
= (1.7 + j7.59) = 7.78 /77.4 ohms primary
Impedance to Zone 1 reach point (already calculated)
= 20.96 /70 = (7.17 + j19.7) ohms primary
Source to fault impedance = (1.7 + j7.59) + (7.17 + j19.7)
= (8.87 + j27.29) = 28.7/72
Maximum relay current for a phase fault at the Zone 1 reach point
132 x 103
= = 2655A primary
3 x 28.7
1
= 2655 x = 5.31A secondary
500
X/ ratio = 27.29 = 3.08
R
8.87
Relay burden for a phase fault is 0.26 ohms.
CT load resistance = 15 m of 2.5 mm2 copper
(7.41 ohms/km)
= 0. 11 ohms
CT kneepoint voltage requirement for a 3 phase fault is given by:
VK 5.31 (1 + 3.08) (0.26 + 2.5 + 0.11)
VK 62.2 volts
QUADRAMHO Chapter 1
Page 27 of 27
b) Ground faults:
Minimum ground loop impedance behind relay is minimum JAN source ground
loop impedance plus ground loop impedance of two JAN FEB circuits in
parallel.
Minimum JAN source ground loop impedance
= 3.48 /88 = (0. 12 + j3.48) ohms primary
Ground loop impedance of two JAN FEB circuits
= (4.33 + j12.4) = (2.17 + j6.2) = 6.57 /70.7ohms primary
2
Ground loop impedance behind relay
= (0. 12 + j3.48) + (2.17 + j6.21)
= (2.29 + j9.68) = 9.95 /76.7 ohms primary
= (9.84 + j29.6) = 31.16 /71.6 ohms primary
Source to Zone 1 reach point ground loop impedance
= (2.29 + j9.68) + (9.84 + j29.6)
= (12.13 + j39.3) = 41.1 /72.8 ohms primary
Maximum fault current for a ground fault at the Zone 1 reach point
132 x 103
= = 1854A primary
3 x 41.1
= 1854 x 1 = 3.71A secondary

500
X/ ratio = 39.3 = 3.24
R
12.13
From Chapter 2 page 158 of manual relay burden for a ground fault is 0.53
ohms.
CT load resistance = 0. 11 ohms
CT kneepoint voltage requirement for a ground fault is given by:
VK 3.71 (1 + 3.24) (0.53 + 2.5 + 0.22)
VK 51.1 volts
It is also required that at the CT kneepoint voltage (which should be at least 63
volts according to preceding calculations) the CT exciting current should be less
than 100mA.
QUADRAMHO Chapter 1
Appendix A
Page 1 of 8
TWO SHPM TYPES
Both have 18 measuring elements + PSB
Type a: Mho Type b: Quadrilateral
Z3
Gr Z3
Gr
Z2
Z2
Z1
Z1 Z1
Z2
Z3
Ph PSB Ph PSB
Z3 Z3
Z2
Z2
Z1
Z1
Figure 1: Basic relay characteristics

QUADRAMHO Chapter 1
Appendix A
Page 2 of 8
Pre-fault power flow

A
X X
jx
B
KRF R
F
X
R
A
a) Preventing Zone 1 overreach
Pre-fault power flow
X X
R
R
F
jx
X
KRF
R
A
b) Preventing Zone 1 underreach
Figure 2: Principle of Zone 1 reach line angular compensation

QUADRAMHO Chapter 1
Appendix A
Page 3 of 8
Zone -3
Zone -2
Zone -1
Z B
X X X X X X X X
Zone -1
Zone -2
Zone -3
Relay A Relay B
Zone -1 Zone -1
OR Trip A Trip B OR
Zone -2 tZ2 tZ2 Zone -2
Figure 3: Basic-simplified distance scheme logic

QUADRAMHO Chapter 1
Appendix A
Page 4 of 8
Zone -3
Zone -2
Zone -1 extended Zone -1

Z B
A
X X X X X X X X
Zone -1 Zone -1 extended
Zone -2
Zone -3
Relay A Relay B
Auto-reclose reset Auto-reclose reset
Zone-1 ext Zone-1 ext
AND AND
Zone -1ext Zone -1ext
Trip A Trip B
Zone -1 OR OR OR OR Zone -1
Figure 4: Z1 EXT-simplified distance scheme logic

QUADRAMHO Chapter 1
Appendix A
Page 5 of 8
Zone -3
Zone -2
Zone -1
Z B
X X X X X X X X
Zone -1
Zone -2
Zone -3
Relay A Relay B
AND AND
Trip A Trip B
Zone -1 OR OR Zone -1
Figure 5: PUR-simplified scheme logic

QUADRAMHO Chapter 1
Appendix A
Page 6 of 8
Zone -3
Zone -2
Zone -1
Z B
X X X X X X X X
Zone -1
Zone -2
Zone -3
Relay A Relay B
CB AND AND CB
contact contact
OR OR
Zone -1 OR Trip A Ttrip B OR Zone -1
= Signaling
channels
CB contact closed when circuit breaker is open
Figure 6: POR-simplified distance scheme logic (with open terminal signal echo feature)
QUADRAMHO Chapter 1
Appendix A
Page 7 of 8
Zone -2 Zone -3
Zone -1
Z B
X X X X X X X X
Zone -1
Zone -2
Zone -3
Relay A Relay B
Undervoltage Undervoltage
detector detector
AND AND
CB CB
AND AND contact
contact
OR OR
Zone -1 OR Trip A Trip B OR Zone -1
Signaling
=
channels
CB contact closed when circuit breaker is open
Figure 7: POR-simplified distance scheme logic (with open terminal signal echo feature and weak
infeed signal echo and trip feature)
QUADRAMHO Chapter 1
Appendix A
Page 8 of 8
Zone -3
Zone -2
Zone -1
Z B
X X X X X X X X
Zone -1
Zone -2
Zone -3
Relay A Relay B
AND AND
AND AND
Trip A Trip B
Zone -1 OR OR Zone -1
Figure 8: PUR-simplified distance scheme logic

QUADRAMHO Chapter 1
Appendix B
Page 1 of 2
SKETCHING RELAY CHARACTERISTICS
Cross polarized mho, characteristics

The mho impedance characteristics for unbalanced faults are unique due to the
addition of square wave cross polarizing signals to the sinusoidal comparator
voltages (see Chapter 2).
It can be seen from figures quoted that the boundary of comparator operation
when progressing in a clockwise direction from the vertical axis on an impedance
diagram, initially follows a fully cross polarized mho circle. Then at the capture
point, the characteristic pulls in to meet a 16% partially cross polarized mho
circle on the source impedance vector.
In order to sketch the unique cross polarized mho impedance characteristic it is
necessary to be able to plot the following:
i) the 16% cross polarized mho circle (offset differs slightly from that of a 16%
sine wave cross polarized mho circle).
ii) the 100% fully cross polarized mho circle.
iii) the impedance vector to the capture point (ZC).
To plot the 16% and 100% cross polarized circles, their offset points along the
source impedance vector need to be established. Table 1 gives the offset point
factors K 1 and K2 for phase or ground fault impedance characteristics.
Table 1 also gives details of how to find the capture point impedance vector.
For phase fault elements the capture point impedance vector can be plotted by
calculating the angle a and the magnitude [ZC] from the formulae given.
The portion of the impedance characteristic between the captive impedance
vector[ZC] and the 16% offset point must be sketched by hand.
QUADRAMHO Chapter 1
Appendix B
Page 2 of 2
Comparator K1 K2 Length of captive point vector to 100% cross-polarised characteristic

type
Phase fault 0.138 1.0 (|ZS| 0.16|ZR|sin)2
= cos 1
(0.16|ZS|+ 0.16|ZR|cos)2 + (|ZS|0.16|ZR|sin)2
|ZC| = ([|ZS|sin)2 + (|ZR|cos( ))2])
Earth fault * K.(3p) (3p) Determined interactively using:

(2 + q) (2 + q) (2 + p) Y = 0.16x
ZC sin = 0.16 . ZS + ZC
(2 + q) (Figure 2)
*K is found from 6.25 = (2 + p) p p Z Z

p = S0 q = R0
3K.|p| |p| ZS1 ZR1
= Angle between (ZS + ZR) or (ZS' + ZR) and ZS or ZS'

= Angle between ZS or ZS' and ZR
ZSC
p =
ZS
ZR = Positive sequence impedance reach setting of mho element
ZS = Source impedance behind relaying point
ZC = Captive point impedance vector
Note: For sketching characteristic in second quadrant use in formula to find
new value of
Quadrilateral ground fault characteristics

A typical Zone 1/Zone 2 quadrilateral ground fault characteristic is shown in
Figure 19. The reach line has a nominal 3 clockwise angle with respect to the
horizontal axis. The reach line will vary however, for fault conditions where the
neutral current IN is not in phase with the particular phase current IPh. The resistive
axis of the impedence diagram is in phase with the particular phase current IPh.
For Zone 1 elements, the reach line is in phase with the neutral current IN with the
3 variation. For Zone 2 and Zone 3 elements the reach line is in phase with the
combined current IPH + IN.
For Zone 1 and Zone 2 the cross polarized directional line is at right angles to the
relay set characteristic angle and passes through the offset point along the source
impedance vector according to the constant K1 given in table 1 for mho ground
fault elements times p. For Zone 3 the reverse offset line is offset from the origin
along the set characteristic angle according to the reverse offset setting and it is
parallel to the Zone 3 reach line.
The impedance ZRE is the ground loop reach setting of the quadrilateral element
and is determined from the relay phase and neutral coarse impedance settings
acted on by the fine zone multiplier settings. ZSE is the Source ground loop
impedance behind the relay.
Type SHPM 101
Service Manual
Chapter 2
Description, Technical Data
QUADRAMHO Chapter 2
Contents
1. INTRODUCTION 1
2. MAIN FEATURES 2
2.1 Quadramho Models Available 2
3. MECHANICAL LAYOUT 3
4. MODULE DESCRIPTIONS 4
4.1 Relay block diagram 4
4.2 The voltage input module RFV 04 4
4.3 The current input module RFC 15 5
4.4 Phase and neutral module RRZO7 6
4.5 Level detector board ZH0729 6
4.6 Phase and neutral and IR setting board ZH0730 7
4.7 Zone1/Zone2 module RRM 08 8
4.7.1 Setting board (ZH0732) 8
4.7.2 Comparator board ZH0731 9
4.8 Zone 3 module RRM 09 10
4.8.1 Setting board ZH0734 10
4.8.2 Comparator board ZH0733 10
4.9 Scheme logic module RCL 10 11
4.9.1 Scheme logic functions 11
4.9.2 Scheme logic settings and indications 12
4.9.3 Indications 12
4.9.4 Code switches 12
4.9.5 Switch banks 12
4.9.6 Push button 13
4.9.7 Test socket 13
4.9.8 General description of microcontroller associated hardware 14
4.9.9 Microcontroller and program memory 14
4.9. 10 Programmable peripheral interface 14
4.9.11 Multiplexed port 14
4.9.12 Hardware reset of microcontroller and peripheral 15
4.9.13 +5V rail monitor 15
4. 9.14 Monitoring of scheme logic software 15
4.9.15 Inoperative alarm 16
4.9.16 Zone 1 interrupt gating logic 16
4.9.17 Synchronised polarising (memory) hardware 16
4.9.18 Indication 16
4.9.19 Opto isolators 17
4.9.20 Zero sequence voltage level detector 17
4.9.21 High set current level detectors 17
4.9.22 Power swing blocking hardware 18
4.9.23 Scheme logic software 18
4.9.24 INIT subroutine 18
4.9.25 The main loop 18
4.9.26 Z1 NT subroutine 19
4.9.27 FTRIP subroutine 19
QUADRAMHO Chapter 2
Contents
4.9.28 LOAD subroutine 19

4.9.29 LLAD subroutine 20
4.9. 30 PDTIM subroutine 20
4.9.31 VTS subroutine 20
4.9.32 LOAD 1 subroutine 20
4.9.33 FLOC subroutine 20
4.9.34 SOTF subroutine 20
4 9.35 BASIC subroutine 21
4.9.36 OPT subroutine 21
4.9.37 MFAST subroutine 21
4.9.3S PSMIS subroutine 21
4.9.39 EXOP subroutine 22
4.9.40 ENF subroutine 22
4.9.41 OP subroutine 22
4.9.42 LTIM timer interrupt routine 22
4.9.43 Basic interrupt principle 22
4.9.44 Principle of timer operation 22
4.9.45 Loop timers 24
4.9.46 Scheme logic test program 24
4.9.47 The auxiliary relay module RVC 53 31
4.9.48 Power supply unit ZRE 01 31
5. PRINCIPLES OF OPERATION 33
5.1 The comparator 33
5.1.1 Fundamentals of the comparator 33
5.1.2 Action of the comparator counter 34
5.1.3 Exclusion of noise 35
5.1.4 Phase shifting circuit 35
5.2 Polarising arrangements 35
5.2.1 Partially cross-polarised MHO 36
5.2.2 Synchronous polarising 38
5.3 Offset MHO characteristic 39
5.4 The lenticular characteristic 40
5.5 The quadrilateral characteristic 40
5.6 Two-phase-to-ground faults (quadrilateral characteristic) 41
5.7 The 0ffset quadrilateral 42
5.8 Level detectors 42
5.9 Inhibition of the comparator 43
5.10 Single pole tripping 44
5.11 Phase selection 44
5.12 Other level detectors 45
5.13 Power swing blocking 45
5.14 Current input circuits 46
5.15 Operation with saturated CTs 47
5.16 Voltage transformer supervision (fuse failure) 47
QUADRAMHO Chapter 2
Contents
5.16.1 Purpose 47
5.16.2 Principle 48
5.16.3 Outputs 48
5.16.4 Level detector settings 48
5.16.5 Speed of operation 48
5.16.6 Implementation 48
5.16.7 Output seal-in 49
5.16.8 Operation for indication and alarm only 49
5.16.9 Resetting 49
5.16.10 Line de-energisation (line VTs) 49
5.16.11 Busbar voltage transformers 50
5.16.12 Single-pole tripping 50
5.16.13 Switch on to fault 50
5.16.14 Weak infeed (POR scheme option) during fuse failure conditions 50
5.16.15 Scheme logic module 51
5.16.16 Level detector pole dead logic 51
5.16.17 Comparator level detector checks 51
5.16.18 Voltage bandpass filter switching 51
5.16.19 Control of hysteresis in impedance measurement 51
5.16.20 Self testing 52
5.16.21 Operation of standard schemes and input/output interfaces 52
5.16.22 Standard scheme options 52
5.16.23 Basic scheme 53
5.16.24 Permissive underreaching scheme (PUR) 53
5.16.25 Permissive overreaching scheme (POR) 54
5.16.26 Weak infeed feature (POR scheme only) 54
5.16.27 Blocking scheme with reverse looking Zone 3 elements (BLOCK) 55
5.16.28 Zone 1 extension scheme (Z1EXT) 56
5.16.29 Opto-isolator inputs to scheme logic 56
5.16.30 Scheme logic control of auxiliary relay outputs 57
5.16.31 Trip A, Trip B and Trip C contacts 58
5.16.32 Trip three phase contacts 94T1 and 94T2 58
5.16.33 Any trip contacts 941 and 942 58
5.16.34 Block auto reclose contacts 961 58
5.16.35 Fault locator start contacts 19A1, 19B1, 19C1 and 19E1 59
5.16.36 Zone 2 trip contacts Z21 59
5.16.37 Zone 3 trip contact Z31 59
5.16.38 Aided trip contact 94Y1 59
5.16.39 Switch on to fault contact 981 59
5.16.40 Relay inoperative alarm 97Y1 61
5.16.41 Scheme logic control of indication 61
5.16.42 Test facilities 62
5.16.43 Operation of Quadramho with capacitor voltage transformers 63
5.16.44 Typical logic symbols used 65
QUADRAMHO Chapter 2
Contents
6. TECHNICAL DATA 66
6.1 Input ratings 66
6.2 Impedance setting ranges 66
6.3 Resistive reach setting range (quadrilateral earth fault units only) 67
6.4 Lenticular aspect ratio setting range (lenticular zone 3 only) 67
6.5 Summary of K-factors 67
6.6 Accuracy of impedance measurement 68
6.7 Current sensitivity of impedance measuring units. 68
6.8 Returning ratio of impedance measuring units 68
6.9 Characteristic angle setting ranges and accuracy 68
6.10 Timer setting ranges 69
6.11 Polarising 69
6.12 Switch-on-to-fault 69
6.13 Operating and reset times 70
6.14 Voltage transformer (fuse failure) supervision 70
6.15 Power swing blocking 70
6.16 Operative ambient temperature range 70
6.17 Operative frequency range 70
6.18 Burdens and current transformer requirements 71
6.19 Output contact ranges 71
6.20 DC supply ratings and operative range 72
6.21 Auxiliary dc supply for optically-coupled isolators 72
6.22 DC power consumption 72
6.23 Inbuilt continuouys monitoring and periodic self-test 72
6.24 Voltage withstand 72
6.25 Environmental withstand 73
6.26 Dimensions 73
APPENDIX A
Figure 1: Quadramho 1
Figure 2: Quadramho module earthing arrangement 2
Figure 3: Outline drawing and module layout 3
Figure 4: Block diagram 4
Figure 5: Voltage input module RFV04 5
Figure 6: Action of switched bandpass filter in voltage supply 6
Figure 7: AC current input module RFC15 7
Figure 8: Nameplate details RFC15 8
Figure 9: Level detectors ZH0729 9
Figure 10: Board ZH0730 phase and neutral and IR setting 10
Figure 11: Nameplate details RRZ07 11
Figure 12: Zone 1/Zone 2 setting board ZH0732 12
Figure 13: Zone 1/Zone 2 comparators (MHO version) 13
Figure 14: Zone 1/Zone 2 comparators (Quad version) 14
Figure 15: Layout of ULA 15
Figure 16: Comparator inputs 16
Figure 17: Nameplate details RRM08 17
QUADRAMHO Chapter 2
Contents
Figure 18: Zone 3 setting board ZH0734 18

Figure 19: Zone 3 comparators (Lenticular) 19
Figure 20: Zone 3 comparators (QUAD version) 20
Figure 21a: Comparator inputs 21
Figure 21b: Comparator inputs continued 22
Figure 22: Nameplate details RRM09 23
Figure 23: Block diagram board ZH0735 24
Figure 24: Block diagram board ZH0736 25
Figure 25: Main loop program flowchart 26
Figure 26: Nameplate details RCL10 27
Figure 27: Auxiliary relay module RVC 53 28
Figure 28: Power supply block diagram 29
Figure 29: Sequence comparator voltages for MHO characteristic 30
Figure 30: Comparator logic variables 30
Figure 31: Action of counter in comparator 31
Figure 32: Effect of high-frequency interference 32
Figure 33: Effect of expotential offset 32
Figure 34: Flowchart of sequence comparator 33
Figure 33a: Flowchart of sequence comparator 34
Figure 33b: Flowchart of sequence comparator 35
Figure 35: Polarising phase shift 36
Figure 36: Action of synchronous polarising 37
Figure 37: Resistive expansion of partially cross-polarised MHO 38
Figure 38: Typical MHO Zone 1 operating times 38
Figure 39: AG polarising mixing circuit 39
Figure 40: BC polarising mixing circuit 39
Figure 41: Comparison of polarised characteristics 40
Figure 42 41
Figure 43 42
Figure 44: Synchronous polarising healthy live line conditions 43
Figure 45: Synchronous polarising faulty line conditions 43
Figure 46: Sequence comparator voltages for offset MHO characteristic 44
Figure 47: Lenticular characteristics 44
Figure 48: Lenticular Zone 3 45
Figure 49: Lenticular characteristic block diagram 45
Figure 50: Quadrilateral Zone 1 46
Figure 51: Typical quadrilateral Zone 1 operating times 46
Figure 52: Behaviour for AG fault 47
Figure 53: Guard Zone logic 48
Figure 54: Quadrilateral Zone 3 48
Figure 55: Gating of comparator output 49
Figure 56: Level detector 49
Figure 57: Inhibition of comparators 50
Figure 58: Biased neutral current level detectors 51
Figure 59: Power swing blocking characteristic 52
QUADRAMHO Chapter 2
Contents
Figure 60: Power swing blocking logic 52

Figure 61: Flux summation in transphasor 53
Figure 63: Voltage transformer supervision and miniature circuit breaker 54
Figure 64: Level detector pole dead logic 55
Figure 65: Level detector gating of comparators 56
Figure 66: Bandpass filter switching logic 57
Figure 67: External connection diagram:
Quadramho static distance protection relay
1 and 3-phase tripping 58
Figure 68: Permissive underreach scheme 59
Figure 69: Permissive overreach scheme 60
Figure 70: Week infeed feature POR scheme 61
Figure 71: Blocking scheme 62
Figure 72: Trip output logic 63
Figure 73: Block auto-reclose logic 64
Figure 74: Fault locator logic 65
Figure 75: Switch on to fault logic 66
Figure 76: Indication logic 67
Figure 77: Some test features of Quadramho 68
Figure 78: Zone 1 typical operating times for 50Hz relays at SIR 30 69
QUADRAMHO Chapter 2
Page 1 of 74
Section 1. INTRODUCTION
The Quadramho protection scheme, has been designed to satisfy the demand for a
cost effective distance relay for medium and high voltage transmission and
distribution lines. The relay is a high performance full scheme design having many
advantages over the switched relays traditionally used in this application.
Three zones of protection are incorporated, each having separate measuring
elements for each type of phase and ground fault. The full scheme arrangement
uses 18 comparators, eliminating the need for starting relays and switching
circuits, thereby providing better reliability and faster operating times.
For short line applications involving strong sources of power infeed, quadrilateral
ground fault characteristics for all three zones can be specified, ensuring adequate
tolerance to arcing and tower footing resistance. Alternatively, partially cross
polarised mho characteristics with strong resistive expansion for Zone 1 and 2 and
a lens-shaped Zone 3 characteristic may be specified. Synchronous polarising (an
advanced digital memory system) is provided to allow correct response to three
phase close-up faults.
Quadramho contains interfacing and scheme logic to allow signalling between
relays at the ends of a transmission line, via a signalling channel, for rapid
clearance of faults anywhere within the whole of the protected section of line.
Several different tripping schemes are incorporated in the relay, selectable by
switches on the front panel. Integral tripping relays give three pole or single and
three pole tripping, as required, and other relays are present for interfacing with a
signalling channel, auto-reclose equipment, remote alarms, fault recorder and fault
locator. Optical isolators are used for input signals such as from the signalling
channel. Visual indications are provided by 10 light emitting diodes.
Either busbar or line voltage transformers can be used and these can be either
capacitor VT or electromagnetic types. The design is highly tolerant of saturated
current transformers, so that the CT requirements are moderate.
The distance relay has inbuilt continuous self-monitoring and periodic self-testing
features designed to announce a failure of the relay or its supplies.
A comprehensive injection and test monitoring system simplifies commissioning,
routine testing, and fault finding operations on the relay. The system permits the use
of programmable portable test equipment so that on-site testing can be performed
by personnel who do not have detailed training on distance relays.
Quadramho owes its high performance and compact size to a new type of
comparator is physically implemented as a ULA (uncommitted logic array)
integrated circuit. This comparator is used in conjunction with input filters to give
fast and accurate operation even under conditions of noisy and harmonically
distorted waveforms commonly encountered in power distribution systems.
QUADRAMHO Chapter 2
Page 2 of 74
Section 2. MAIN FEATURES
Full scheme 3 Zone distance relay with 18 measuring elements.

Characteristic shapes to suit all line lengths and fault levels.
Fast operating times over a very wide range of fault conditions.
Digital synchronous polarising for close-up 3 phase faults.
Microprocessor scheme logic with wide range of built-in schemes selected by code
selection switches.
Ample input/output facilities 24 output contacts, 5 optically-coupled inputs, 10
light-emitting diodes.
Full range of test features for easy commissioning, routine testing and problem
analysis. Built-in interfacing enabling automatic field test equipment to be used if
required.
Continuous self-monitoring, on-demand and periodic self-test if required.
Built-in Voltage Transformer Supervision and Power Swing Blocking feature as
standard.
2.1 Quadramho models available
Two types of characteristic are available:
i) Zone 1 and 2: shaped partially cross polarised mho with
partially cross polarised directional line
Zone 3: offset lens (can be set as offset circular mho)
ii) Zone 1 and 2: ground faults quadrilateral with partially
cross polarised directional line
Zone 1 and 2 phase fault: shaped partially cross polarised mho with
partially cross polarised directional line
Zone 3 ground faults offset quadrilateral
Zone 3 phase faults offset circular mho
Each type includes Voltage Transformer Supervision and Power Swing Blocking
features as standard and is suitable for both three-pole and single-and three-pole
tripping.
QUADRAMHO Chapter 2
Page 3 of 74
Section 3. MECHANICAL LAYOUT
In order to ensure that the distance protection is unaffected by conditions of severe

high frequency interference, such as can occur in a high voltage substation, certain
precautions have been taken in designing the physical layout. These are:
a) separation of interface modules from measuring and control modules.
The interface modules occupy the right hand side of the subrack and provide
isolation between all connections with the outside world and the measuring and
control modules which occupy the left hand side of the subrack (see Appendix A
Figure 1).
The interface modules provide galvanic isolation to 5kV peak and filter out high
frequency common-mode and transverse-mode noise signals. The measuring
and control modules therefore operate in a relatively quiet electrical
environment. The need for galvanic isolation of circuits in the quiet space is
eliminated and so the relay internal dc supply centre rail is connected to the
case. The case earth stud is in turn connected to the relay room earth.
b) within the interface modules, isolating transformers have screens to minimise
primary to secondary capacitance coupling, thereby attenuating common-mode
interference. The efficiency of any screen is defined more by the electrical
strength of the connection to the common rail or earth than by the design of the
screen itself, so the larger transformers are mounted on metal plates and the
transformer screens are connected directly to the plates by short thick wires.
A special 4mm heavy-duty plug and socket arrangement allows each plate to
be connected to the earth stud of the case by multi-strand wire of thick cross
section (50/0.2mm wire). This ensures a low inductance between the screens
and earth. A low inductance is more important than low resistance because of
the high rates of rise of currents that exist in screen connections under
interference conditions.
c) three different categories of currents flow to earth. These are signal currents,
power supply currents and screen surge currents. To eliminate cross-coupling
effects, these are conducted by separate wires to the case earth stud. For
convenience, the signal and power supply earths are connected to a common
ground plane on the four layer pcb backplane which is employed to provide
interconnection of module signals. The ground plane also affords good
screening of the intermodule connections.
The ground plane is connected to the relay case at each mounting point and is
also connected to the case earth stud by a short thick wire.
Figure 2 shows the basic schematic of the relay earthing and screening
arrangements and paths of current flow for some typical common mode surges.
QUADRAMHO Chapter 2
Page 4 of 74
Section 4. MODULE DESCRIPTIONS
To provide the user with a thorough understanding of the operating principle of the
relay and the function of the individual modules within the relay, the following sub-
sections describe the operating functions of each module. Where necessary,
references to more detailed descriptions in Section 5 are given.
4.1 Relay block diagram
Figure 3 shows the relative positions of the modules within the relay case and
Figure 4 shows the overall relay block diagram.
4.2 The voltage input module RFV 04
The voltage input module isolates and filters the ac inputs from the transmission line
voltage transformers. Reference to Figure 5 reveals that the module has three
phase-neutral connected isolating transformers insulated to 5kV peak. These have
interwinding screens to attenuate common-mode high frequency interference.
The output from each transformer is passed through an overvoltage surge
protection circuit which limits overvoltages due to lightning strikes, cross country
faults and other high voltage transients, to within limits which are safe for the
electronic circuitry contained within the relay.
The signals are then filtered by low-pass filters with cut-off frequencies of 300Hz.
The purpose of the filters is to remove unwanted high frequency signals such as
line reflections following the incidence of a fault and also interference induced on
substation wiring by switching operations. Each output is then passed to a
calibrated attenuator and a band pass filter. The filters are of second order with
centre frequencies equal to the nominal supply frequency and Q values of 0.5.
This type of filter is very effective in eliminating unwanted exponential and high
frequency components of the input voltage.
Under normal conditions the distance measuring elements use the voltage signal
produced by the attenuator. However, the measuring elements are automatically
switched to the filtered output of the band-pass circuits after a predetermined
interval from the incidence of a fault. This ensures that, if the comparator operating
time has been slowed by abnormally severe exponential or high frequency
components of the voltage signal, the comparators have the opportunity of
remeasuring on a relatively uncontaminated voltage signal.
This arrangement prevents any possibility of excessively long comparator operating
times which might otherwise occur under certain extreme conditions, such as (a)
severe CVT transient errors with high SIR and high fault position, (b) severe
travelling wave distortion on a long line at high fault position (c) large mismatch
between source and line time constants with high SIR and high fault position.
An example is shown in Figure 6.
The voltage level detectors are used as fault detectors for the purpose of controlling
the transfer from normal to band pass filtered voltage signal. Solid state switches
are used under the control of input ENF for the signal transfer circuits. The reset
time of the voltage level detectors is approximately 12 to 22ms depending on
point-on-wave of fault incidence and a further delay of 14ms is introduced by a
software timer. Resetting of any voltage level detector causes all three phases of
voltage signal to be transferred to the band pass filter outputs.
QUADRAMHO Chapter 2
Page 5 of 74
The time delay of 26 to 36ms between fault inception and signal transfer is
sufficient to allow fast tripping to occur, if electrical conditions permit, before the
intervention of the filters. If fast tripping does not occur, the 26 to 36ms delay is
long enough for the transient errors of the band pass filters, caused by the
collapsing voltage, to have decayed away before signal transfer to the band pass
outputs.
At the instant of switching in the band pass filters, a step in the voltage waveform
may arise and to ensure that this causes no confusion to the comparators a
momentary inhibit pulse is sent to all the comparators. The voltage supply is
switched back to normal when (a) the fault is removed by a remote breaker so that
the voltage is restored to normal and the voltage level detectors pick up again, (b)
when the fault is cleared by de-energising the line such that one or more pole-dead
level detectors operate. This control logic is performed by software in the scheme
logic module (see Section 5.16.18 and Figure 66).
When the relay trips the circuit breaker, a logic signal is sent from the scheme
logic module to the input labelled TRIP to instruct the relay reach to be increased
by 5% by reducing the gain of the voltage buffer amplifiers, which produce outputs
VA, VB and VC, by 5%. This hysterisis control defines the reset ratio of the relay and
prevents chatter of relay output contacts for faults on the boundary of operation
(see Section 5.16.19).
The outputs VA, VB and VC are buffered by operational amplifiers which produce
outputs VA', VB' and VC' respectively.
The C phase output from the band pass filter is buffered to drive the memory
facility of the relay, see Section 4.9.17, on output Vmem.
The overall transfer functions for the voltage input module with healthy line
conditions at the nominal power system frequencies are:
Vout = 0.066304 /10 (50Hz models)
Vin
Vout = 0.065854 /12 (60Hz models)
Vin
4.3 The current input module RFC 15
This module receives current from the line current transformers on inputs IA, IB, IC
and IN via the heavy duty plug bridge piece 1Y on the side of the module and
produces the replica impedance signals IA1 and IA2, IB1 and IB2, IC1 and IC2,
IN1, IN2 and IN3 (see Block Diagram Figure 7).
Replica impedance signals are generated by the mixing of magnetic fluxes in the
transphasor units, as described in detail in Section 5.14. Each transphasor
arrangement produces an output voltage of 0.34 V/A (1A relay) across a 5k
load located in the phase and neutral module. The residual compensation
arrangement produces an extra output on IN1 IN2 of 0.068 V/A (1A relay)
across a 1k load, also located in the phase and neutral module. Each output is
calibrated at the factory by use of the trimpot T.
The replica phase angles are set by switches /Ph and /N on the relay facia
(see Figure 8) which have a setting range of 45 to 85 in 5 steps. These switches
control the variable resistors shown in Figure 7. The angle setting for currents IA, IB
and IC are ganged.
QUADRAMHO Chapter 2
Page 6 of 74
The quadrilateral version of Quadramho requires additional signals of IAR, IBR and
ICR. These are derived from three current transformers placed in series with the
three phase transphasors, as shown in Figure 7. They have a transfer ratio of
0.544 V/A (1A relay).
All transphasor and current transformer primaries are electrically isolated to a level
of 5kV peak from their corresponding secondary and the relay case. In addition
each device is fitted with a screen which helps to couple any common mode
electrical noise, present on the relay current input terminals, to ground. This noise
is further reduced for outputs IA, IB and IC by the capacitors labelled C, which
couple the noise to ground on IA, IB and IC COMMON. These capacitors and
those shown in the neutral circuit, also attenuate high frequency transverse noise
present on the transphasor secondary.
Zener diodes, labelled D on the diagram, limit the circuit voltages at the module
outputs and across the angle setting potentiometers (/) to non-damaging levels
when heavy surges of current are present on the transmission line.
4.4 Phase and neutral module RRZO7
Introduction
This is a two board module which contains the level detectors and the coarse reach
settings. The two versions available are a quadrilateral and a lenticular, both in 50
and 60Hz. The two nameplates are shown in Figure 11 and the switch functions in
Table 1.
4.5 Level detector board ZH0729
The left hand board contains seven level detectors and three clock divider circuits
as shown in Figure 9. A detailed description of the level detector function and
operation is given in Section 5.8.
The main clock MCK is generated in the Zone 1/2 module (See Section 4.7) and
divider circuits on this board produce MCK/7, MCK/14 and MCK/28. These
signals are used by the level detectors on this board and also those in the Zone 3
module. As part of the continuous monitoring the MCK/28 signal is monitored and
an alarm via LDALARM is given if it should fail.
The seven identical level detector elements are designed to pick up for an input
voltage of 2.933V rms. This level is set by the magnitude of the positive voltage
reference which is calibrated by ALSTOM T&D Protection & Control and the length
of the pick up time t1. As part of the continuous monitoring the negative reference
is monitored and an alarm given if it is not within the required tolerance.
Three level detectors are used as overvoltage detectors LDOVA, LDOVB and
LDOVC with a setting of 70% Vn. The pick up timer t1 is 0.275 cycle and the drop
off time t2 is 1.1 cycles.
Three level detectors are used as low set phase current detectors with a setting of
5% of In at K1 + K2 = 4.8. This setting is obtained by amplifying the input signals
LDIA, LDIB and LDIC by gain G1. Timers t1 and t2 are both 0.275 cycle.
QUADRAMHO Chapter 2
Page 7 of 74
The seventh level detector is the high-set neutral LDHSN. The neutral current is
produced by summing and amplifying by G3 the three phase currents. This gives a
setting of 16% In at K1 + K2 = 4.8. Timer t1 is 0.155 cycle and time t2 is 1.1
cycles. The reference for the high set neutral and the low set neutral (see Zone 3
module) is modified by the phase-phase currents to give a variable pick up level,
as described in Section 5.11.
The reference is the largest instantaneous value of the three precision rectified
phase-phase currents. The signal, smoothed by the R and C and limited by zener
diode D is buffered and split into two signals for the high set and low set level
detectors. In each case the negative reference is obtained by inverting the positive.
To prevent chatter each level detector has10% hysterisis. This is achieved by
reducing the reference on individual level detectors when they operate. The
hysterisis for the low set neutral is also on this board, controlled by the level
detector in the Zone 3 module.
4.6 Phase and neutral and IR setting board ZH0730
The right hand board sets the basic reach of the relay in conjunction with the zone
multiplier modules. In addition, for the quadrilateral relay, it sets the relay resistive
reach. See Figure 10.
The signals present on inputs IA1, IA2, IB1, IB2, IC1 and IC2 are attenuated by the
resistor networks controlled by switches K1 and K2 on the relay facia, to produce
the relay phase setting ZPh (ganged for all phases). Similarly the signals on IN1,
IN2 and IN3 are attenuated under the control of K4, K5 and K6 to produce the
neutral compensation factor setting, ZN.
A summary of the function and resolution of each of the switches above is given in
table 1.
Each of the attenuated signals is passed through a low pass filter and a band pass
filter. The first order low pass filter has a cut-off frequency of 300Hz and the band
pass filter has a centre frequency equal to the power system frequency and a Q
factor of 0.5. The resulting signals, IA ZPh~, IB ZPh~, IC ZPh and +IN ZN are
output from the pcb directly and also further processed by the squaring operational
amplifiers which mix the +IN ZN~ with each of the other ZPh signals to produce
square waves labelled IAZPh IB ZPh and = ~IcZPh.
Sinusoidal signals LDIA, LDIB and LDIC which are used by the level detectors are
extracted after the low pass filters and before the band pass filters.
For the quadrilateral relay only, signals VA, VB and VC are attenuated by the
resistor networks controlled by K3 to produce the relay resistive reach (see Table
1). These signals are mixed with the signals IAR, IBR and ICR which have been
filtered as above to produce the (V + IR), (V IR) and IR voltage vectors for each
phase. The neutral IR sinusoid is produced by summing the three phase IR
sinusoids.
When the relay carries out a self checking procedure it is necessary for the IAR,
IBR and ICR and INR signals to be replaced by the VA CP, VB CP, VC CP and VN CP
signals respectively. This is achieved using digital switches controlled by the
scheme logic.
QUADRAMHO Chapter 2
Page 8 of 74
The respective output voltages are:

50Hz:
IAZPh = K1+K2 x (IA1 IA2) x 0.9848 /10
5
+INZN = [(K5 + K6) x (IN1 IN2) + K4 x (IN3 IN COM)] x 0.98480 /10
5
IAR' = (IAR IAR COM) x 0.9781 /13
60 Hz:
K1 + K2
IAZPh = x (IA1 IA2) x 0.9781 /12
5
+INZN = [(K5 + K6) x (IN1 IN2) + K4 (IN3 IN COM)] x 0.9781 /12
5
IAR' = (IAR. IAR COM) x 0.9636 /15.50
Note: Phases B and C output voltages are derived similarly
Relay facia Function Range covered
switch reference by switch
K1 Coarse ZPh 0 to 4 in steps of 1
K2 Fine ZPh 0 to 0.8 in steps of 0.2
K3 RS 8, 16, 32, 40 and 48
K4 Coarse ZN 0 to 4 in steps of 1
KS Fine ZN 0 to 0.9 in steps of 0.1
K6 Very fine ZN 0 to 0.08 in steps of .02
Table 1: Phase and neutral module switch functions
4.7 Zone 1/Zone 2 module RRM 08

Introduction
This is a two board module which contains the reach settings, the polarising
circuits and the comparators for Zone 1 (Z1), Zone 1 extension (Z1X) and Zone 2
(Z2).
The phase fault elements have shaped mho characteristics. The ground fault
elements can be either shaped mho or quadrilateral. This module is power system
frequency dependent and is available in either 50 or 60Hz versions.
The nameplates are shown in Figure 17.
4.7.1 Setting board (ZH0732)
The right hand board contains the fine reach settings for Z1, Z1X and Z2.
The settings are obtained by attenuating each of the phase-neutral voltages with
switches and resistor networks. A block diagram is shown in Figure 12.
The switches for each of the three phases are ganged together. The switches
labelled K11, K12, K13 and K14 set the Z1 reach. K21, K22 and K24 set the Z2
reach. The Z1X reach, which is a multiple of Z1, is controlled by K15.
An analogue switch, controlled by the scheme logic, is used to select the voltage
from Z1 or Z1X as appropriate. The attenuated voltages are mixed with the
appropriate IZ signals (from the phase and neutral module). The resultant IZ
QUADRAMHO Chapter 2
Page 9 of 74
signals are squared up and level shifted to generate the (V IZ) signals.
These form one input to the comparator. Three additional squaring amplifiers are
required to generate three phase phase IZ square waves. These are used in the
directional line for the phase-phase elements.
The guard zone for the quadrilateral version requires a forward setting which is
twice that of the Z1 ground fault setting. This is obtained by attenuating the Z1
voltages, after the Z1/Z1X selector, by a factor of two, mixing with the
appropriate IZ signal and squaring to produce three (V IZ) square waves.
4.7.2 Comparator board ZH0731
A block diagram for the mho version of this board is shown in Figure13 and for
the quadrilateral version in Figure14. The functions of the left hand board of this
module are as follows:
a) The clock signals
A total of seven clocks at different frequencies are required by the various circuits
(ie. level detectors, polarising and comparators). These are all derived from one
clock, labelled MCK, by a number of divider circuits.
The main clock is divided by 4, 5 and 8 to derive three other frequencies, and a
further three are generated on the level detector board. As part of the continuous
monitoring of the relay MCK/5 and MCK/8 are monitored, and an alarm given if
either should fail.
b) The polarising circuits
The polarising signals required for the shaped mho characteristics are described in
Section 5.2.2. They consist of mixing the three phase-neutral voltages and the
memory signals and digitally phase shifting. The exact proportions are given in
Section 5.2.1. The memory is described in Section 5.2.2. When the memory is not
available it is replaced with a small percentage of the IZ signal. This provides a
restraining influence in the polarising for close-up three phase faults after the
memory has expired. This prevents operation of Z1 and Z2 elements for close-up 3
phase reverse faults.
c) Comparators
The comparators required for Z1 and Z2 are located on this board.
The principle on which the sequence comparator operates is described in
Section 5.1. The comparator is implemented in a customer designed ULA
(uncommitted logic array). Each ULA contains two main comparators and two
inhibit comparators as shown in Figure15. In addition, each ULA has nine
inhibit inputs which when active, force a main comparator to restrain.
Inhibits 1 4 act on main comparator 1, inhibits 8 9 on main comparator 2,
and inhibits 5 7 are common to both.
Two clocks (MCK and MCK/5) are required and the two main comparators
may be reset by a signal from the scheme logic (MRI). Each ULA has a self
checking feature controlled by the scheme logic using inputs SC and MRI.
This is described in Section 6.23. The twelve comparators required for Z1 and
Z2 are arranged as shown in Figure 16. Each ULA is used for a ground fault
element and a phase-phase fault element. One inhibit comparator per ULA is
used for a directional line. The quadrilateral version also requires the two side
lines as described in Section 5.5. The remaining inhibit comparators are used
for this. The side lines are also sent to the Z3 comparators. The additional
circuits required to generate the guard zone logic are described in Section 5.6.
QUADRAMHO Chapter 2
Page 10 of 74
4.8 Zone 3 module RRM 09

Introduction
This is a two board module which contains the forward and reverse reach settings,
polarising, and comparators for Zone 3 (Z3) and Zone 6 (Z6) the power swing
blocking zone. The two versions available are offset lenticular for phase and
ground faults, or offset mho for phase faults with offset quadrilateral for ground
faults. The two nameplates showing the setting details are shown in Figure 22.
4.8.1 Setting board ZH0734
The right hand board is common to both versions except the addition of a switch
labelled a/b for the lenticular version. This switch controls the aspect ratio.
A block diagram is shown in Figure 18.
The forward Z3 reach is obtained by attenuating each of the phase-neutral
voltages by switches and resistor networks. The switches labelled K31, K32 and
K33 set the forward reach. The attenuated voltages are mixed with the appropriate
IZ signals and the resultant squared and level shifted to produce the six (V IZ)
square waves. The reverse Z3 reach is similarly obtained by switches labelled
K33, K35 and K36 and resistor networks. An additional switch K37 controls an
amplifier to give fractional settings. The six (V + IZ) square waves required for Z3
polarising are obtained by mixing the attenuated voltages with the appropriate IZ
signals and squaring the resultant and level shifting.
The power swing blocking zone (Z6) surrounds the Z3 AB phase-phase element.
The forward reach is set to 130% of Z3 forward reach by attenuating the Z3
voltage and mixing with the appropriate current to give (V IZ)ABZ6. The reverse
Z6 reach is set to be Z3 reverse +30% of Z3 forward. The (V + IZ)ABZ6 square
wave is obtained by scaling and mixing appropriate voltages and currents.
This requires extra switches ganged to the Z3 setting switches.
The low set neutral level detector is located on this board. It operates in
conjunction with the reference level and hysteresis circuits on the level detector
board in the same way as the high set neutral described in Section 4.4.
For this level detector t1 = 0.155 cycle and t2 = 1.1 cycles
4.8.2 Comparator board ZH0733
A block diagram for the lenticular version of this board is shown in Figure 19 and
for the quadrilateral version in Figure 20. The functions of the left hand board can
be divided into two areas:
a) The polarising circuit
The polarising signals required to produce the offset lenticular and circular
characteristics are described in Section 5.2.2. The (V + IZ) signals are phase
shifted by the appropriate angles using digital shift registers.
Digital multiplexers are used to select the appropriate signals for the aspect
ratio selected by the switch a/b.
b) Comparator
The comparators used for Z3 and Z6 are of the same design as those described
in Section 4.7 used for Z1 and Z2. Four ULA are required for the lenticular
version and five for the quadrilateral.
The lenticular characteristic described in Section 5.4 is constructed using a main
comparator and an inhibit comparator. The quadrilateral characteristic is
QUADRAMHO Chapter 2
Page 11 of 74
constructed by logically ANDing the outputs of a forward main comparator

and a reverse main comparator. Both comparators are inhibited by the side
lines QINHZ3 which are generated on the Z1/Z2 comparator board.
4.9 Scheme logic module RCL 10
General
The complete Quadramho scheme logic is contained in one 10" x 2" module.
This module consists of two circuit boards and one interboard screen:
a) The left hand board is the scheme logic microcontroller board which contains
the microcontroller, expansion input and outputs, four switch banks, eight LED
indications, the interconnecting wiring on the two code switches and the socket
SK1.
b) The right hand board contains the five opto-isolators, three high set phase
current level detectors, the zero sequence voltage level detector used by the VTS
and also the power swing components which consist of the four way switch
bank and the PSB LED. See Figure 24.
c) The centre board is a blank board with copper plating on one side; this board
is earthed and forms a screen between the opto inputs and the scheme logic.
4.9.1 Scheme logic functions
The scheme logic performs the following functions:
a) Provides five standard schemes, these are Basic, Permissive Underreach,
Permissive Overreach, Blocking and Zone 1 extension which are selectable by
using the code switches.
b) Switch onto fault logic.
c) Voltage transformer supervision.
d) Selectable power swing blocking logic.
e) Synchronous polarising.
f) Time delayed Zone 2 and Zone 3 tripping.
g) Block auto reclose logic.
h) Indications logic.
i) Fault locator logic.
j) Pole dead logic.
k) Comparator level detector checks.
l) Band pass filter switching logic.
m) Amplitude and angular hysteresis control.
n) Tripping and latching logic.
o) Selectable minor options.
p) Self test features.
q) Processor fail monitor.
r) Relay inoperative alarm
s) Comprehensive test options.
The majority of these features are described in Section 5.16
QUADRAMHO Chapter 2
Page 12 of 74
4.9.2 Scheme logic settings and indications

An illustration of the frontplate layout is shown in Figure 26.
4.9.3 Indications
The scheme logic provides nine indications, the function of each indication is
described below:
Indication name plate legend Function of indication
A Fault involving A phase
B Fault involving B phase
C Fault involving C phase
Z2 Zone 2 time delayed trip
Z3 Zone 3 time delayed trip
AIDED TRIP Signal aided trip (PUR, POR or BLOCK)
SOTF Line is energised on to a fault
V~ FAIL Fuse failure condition
POWER SWING Power swing condition
4.9.4 Code switches
The code switches allow selection of the five standard schemes with associated
tripping modes and also the test options (See Section 5.16.22 and 4.9.46
respectively).
The left hand code switch is labelled X while the right hand switch is labelled Y.
4.9.5 Switch banks
The top switch bank tZ2 (see Figure 26) is used to set the Zone 2 time delayed trip
time. The timer has a range of 0 to 250ms in increments of 10ms. The timer is set
by moving the required switches to the right hand position. The total time is the
summation of the individual switches.
The second switch bank tZ3 is used to set the Zone 3 time delayed trip time
The timer has a range from 0 to 580ms in increments of 40ms. The timer also has
an infinity position which is selectable via the top switch. Setting of the timer is
similar to the Zone 2 timer.
The third switch bank (tp and td) is used to set the tp and td current reversal guard
timers. The top four switches correspond to tp while the lower four switches
correspond to td. Both tp and td can be set in the range 0 to 90ms in increments of
6ms. Setting of the timers is similar to Zone 2 timer
The fourth switch bank contains the minor options that are available (see Table 2).
The switch bank at the top right hand side of the module is used for the power
swing blocking circuitry. The top three switches are used to block Zones 1, 2 and
3 individually. Blocking is performed with the switches in the right hand positions.
The bottom switch, SW9, is used to select the PSB option when in the right hand
position.
QUADRAMHO Chapter 2
Page 13 of 74
Switch number Left hand function Right hand function

SW9 Power swing blocking Power swing blocking
disabled enabled
SW8 Disable weak infeed Enable weak infeed option
option (POR) only
SW7 Disable weak infeed Enable weak infeed trip if trip
weak infeed option selected
SW6 Normal A/R action Block A/R if CIS not energised
for schemes 02 to 07 inclusive
SW5 Disable self-checking Enable self-checking
SW4 Normal A/R action Block A/R for 3Ph Z1/AT
faults
SW3 VTS indication only VTS indication and Block
SW2 SOTF dead time 110s SOTF dead time 200ms
SW1 SOTF for any comparator SOTF for current and no volts
operation on any phase
4.9.6 Push button
The push button is used to clear the indications, manually run the comparator self
check and in the test option routine.
4.9.7 Test socket
The test socket SK1 on the front of the module is provided so that the code switches
and push button can be overridden electrically for use with automatic test
equipment.
Pins 1 to 8 of SK1 allow the Code Selection Number (XY) to be overridden.
The number XY is in binary coded decimal form with one input of SK1
corresponding to each bit (see Table 3). Any code selected with the exception of
58 can be overridden by applying the correct code to SK1. Any of the input. pins
which require a 0 should be connected to SK2 pin 2 (0V). The normal state of
the socket (No input present) is FF Hexadecimal (All inputs at high state 1).
SK1 pin no. Override function
1 CSW Y Bit 0 Test socket 1 pinout
2 CSW Y Bit 1
3 CSW Y Bit 2 5 4 3 2 1
4 CSW Y Bit 3
9 8 7 6
5 CSW X Bit 0
6 CSW X Bit 1
7 CSW X Bit 2
8 CSW X Bit 3
9 Pushbutton
For example to select Code 41 (01000001) Connect SK22 to the following pins
of SK1; 2, 3, 4, 5, 6 & 8. In addition to this the pushbutton can be electrically
driven by connecting SK1 9 to SK2 2.
QUADRAMHO Chapter 2
Page 14 of 74
4.9.8 General description of microcontroller associated hardware

The scheme logic is implemented using an 8 bit microcontroller operating under
software control. The microcontroller used is the 8039HL member of the MCS 48
family. This device has 27 Input/Output (I/O) lines. Further I/O expansion is
obtained by using three 8255A programmable peripheral interfaces (PPI).
Each PPI has 24 I/O lines made up of 3 x 8 bit ports and is addressed under
software control. An extra six outputs are obtained by using a Hex D type flip
flop. A functional diagram of the scheme logic is given in Figure 23. The scheme
logic software is stored in 4k bytes of standard EPROM type D2732A.
The microcontroller operates using a 10.7MHz crystal which gives a cycle time of
approximately 1.40s.
4.9.9 Microcontroller and program memory
Each byte of program has a specific address within the EPROM. This address has
12 bits and is generated by the microcontroller. The lower 8 bits of the address are
present on the microcontrollers 8 bit data bus which is multiplexed with other
data. The address is demultiplexed using an 8 bit latch. The higher 4 bits of the
address are present on the lower half of the microcontroller port 2. When the
complete address has been established and latched, the microcontroller reads the
EPROM data and is then able to perform the instruction contained in the data.
4.9.10 Programmable peripheral interface
Each PPI has to be programmed to the required mode of operation before data
can be transferred between the PPI and the microcontroller. Data is written to each
PPI to specify the configuration required.
The configuration used for three PPI is shown below:
PPI 0 has 24 input lines (3 x 8 bit input ports)
PPI 1 has 24 output lines (3 x 8 bit output ports)
PPI 2 has 8 input lines and 16 output lines
(1 x 8 bit input port, 2 x 8 bit output ports)
Data can only be transferred between the microcontroller and any one port of the
PPI at any given instant. Also, because there are three PPI on the data bus (as well
as other devices) only one of these PPI must be enabled at any one time.
Each PPI port (A, B or C) is selected using two address lines, while the PPI is
selected by using another address line to produce the required state on the CS
(chip select) pin. The address is generated by the microcontroller when a read or
write operation is performed. A D type flip-flop is used to obtain an extra six
outputs and is addressed in a similar way to the PPI.
4.9.11 Multiplexed port
Port 1 of the microcontroller is an 8 bit port which is used to read the data from the
following:
a) 4 switch banks
b) 2 code switches
c) SOCKET 1
d) 4 other inputs
QUADRAMHO Chapter 2
Page 15 of 74
The data from the above is multiplexed on to the port in the following way:
Each of the 4 switch banks is enabled by an output line from PPI 1 port A.
See Figure 23. This output allows the data on each switch to be read by the
microcontroller via port 1. The code switches are also enabled by an output line
from PPI 1port A. Each code switch produces the BCD equivalent of the selected
number and requires 4 input lines to be read. The code switch Y is multiplexed on
to the lower 4 bits of port 1, while code switch X is multiplexed on to the higher 4
bits of port 1. The two code switches are enabled together
The test socket is also enabled by an output from PPI 1 port A, when selected data
is transferred from the test socket inputs to port 1.
The 4 other inputs operate similarly to the above. These inputs are routed to the
higher 4 bits of port 1 when they are enabled by microcontroller port 2 bit 7.
For all of the above only 1 of these functions is enabled at any given instant.
The data from the switches and other inputs to port 1 are read during the running
of the software main loop. The enable is generated by the microcontroller.
4.9.12 Hardware reset of microcontroller and peripheral
In order to ensure correct operation of the scheme logic, the microcontroller and
peripherals must be correctly initialised after power supply rails have stabilised.
A reset pulse of duration 50ms is applied to the microcontroller and peripherals
after power up procedure. After power reset, the initialisation of software registers
begins (See Section 4.9.24).
The reset pulse is also applied if either of the following conditions occur:
a) +5V rail drops below approximately 4.5V.
b) microcontroller fails to execute the software.
4.9.13 +5V rail monitor
The microcontroller PPI and other devices operation +5V. If this rail drops in
voltage then a partial reset may occur To ensure a full reset the +5V rail is
monitored. When this drops below approximately 4.5V, a continuous reset is
applied to the microcontroller and PPI. If the voltage rises above this level then a
power up reset is performed. Thus ensuring all devices are reset completely for
interruptions in the dc supply. The loss of the +5V rail will cause the Relay
Inoperative alarm contacts to close.
4. 9.14 Monitoring of scheme logic software
The scheme logic software executed by the microcontroller is monitored to detect
and correct any maloperation that may occur. When the intended software loop is
being run, the code switches are always read at the beginning of the loop
regardless of the scheme selected (See Section 4.9.23).
As mentioned in Section 4.9.11, an enable output is sent to allow the
microcontroller to read the code switches. This enable is monitored by the code
switch monitor circuit which detects if the enable ceases to occur. If so, the reset
circuit is activated which resets and allows re-initialising of the PPI and the
microcontroller. Failure of the microcontroller or software will cause the Relay
Inoperative alarm contacts to close.
QUADRAMHO Chapter 2
Page 16 of 74
4.9.15 Inoperative alarm

The relay inoperative alarm circuit on the scheme logic board monitors a pulse
which is normally present on Port 2 bit 6 of the microcontroller. If the
microcontroller fails to execute the normal scheme loop, the pulse ceases to be
present causing the Relay Inoperative alarm to operate. Removal of the pulse is
caused by the following:
a) Failure of the microcontroller.
b) Selection of a non-valid scheme option.
c) Failure of the +5V rail.
d) Operation of VTS with SW3 set to right hand position.
e) Failure of comparator during self test routine.
f) Energisation of the miniature circuit breaker open opto coupler (MCB version
only).
The inoperative alarm circuit also monitors the +12V rails; if this drops below
approximately 7.5V then the Relay Inoperative alarm will be given.
4.9.16 Zone 1 interrupt gating logic
The Zone 1 interrupt gating logic is a hardware gating of the Zone 1 comparator
outputs with the corresponding low set current level detectors (LDLS) and the high
set neutral level detector (LDHSN). This ensures that an interrupt can only take
place when a trip condition occurs on Zone 1.
4.9.17 Synchronised polarising (memory) hardware
The operation of the synchronous polarising (digital memory) is described in
Section 5.2.2.
The basic hardware associated with the memory is as follows. The memory uses
one phase (VC) of the input 3 phase volts to the relay. This input is squared and
then level shifted before being input to the microcontroller. Only 1 phase of the
memory output (VMC) is produced by the microcontroller, the other two (VMA and
VMB) are derived from this using external hardware components.
Voltage VMA is produced by first shifting VMC by 90 and then by a further 30 to
give VMC /120 (VMA)
Voltage VMB is produced by inverting VMC (giving VMC /180 ) and then shifting
by 60 to give VMC /240 (VMB).
4.9.18 Indication
The indications of the scheme logic are given by nine LEDs. All these indications
are driven by the scheme logic microcontroller. Eight of the indications are
controlled by PPI 1 port B and are contained on the scheme logic processor board.
The ninth LED is controlled by PPI 2 port B bit 5 and is contained on the opto
isolator board.
All nine indication LEDs are buffered by transistors to enable sufficient current to be
provided for a good level of illumination.
The eight indications of the scheme logic processor board also supply external
outputs which are available on socket 2 on the miniature relay module (see also
Sections 5.16.41 and 5.16.42).
QUADRAMHO Chapter 2
Page 17 of 74
4.9.19 Opto isolators

There are three different operating voltages as given in the following table:
Nominal Operative range Absolute max
48/54V 37.5 60V 64.8V
110/125V 87.5 137.5V 150V
220/250V 175 275V 300V
There are five opto isolator inputs available in the scheme logic module; all of
these are fitted on all voltage versions of the board. The opto isolator inputs are
used in the schemes and the functions of these are described in Section 5.16.29.
The opto isolators have a defined minimum operating voltage of greater than 10V
(all voltage versions). Transient suppressors are fitted on the inputs to prevent
damage to the opto isolators. A time delay of between 0.3 and 1.1ms is
incorporated into the output circuit of each opto isolator, this is to prevent transient
operation of the scheme logic inputs. A guard ring (earthed) is used to protect the
output side of the opto isolator from noise that may be present on the input side.
4.9.20 Zero sequence voltage level detector
The zero sequence voltage level detector (LDVO) is used by the VTS to detect an
imbalance in the system voltage. This level detector is designed to operate for a
voltage drop of 45% or greater in any one phase. The level detector is designed to
operate over the frequency range 47 to 61Hz.
The input level of pick up voltage for the frequency range is as follows:
50Hz (47 51) P/U = 38 52% of rated volts
60Hz (56 61) P/U = 40 57% of rated volts
A block diagram of the level detector is shown in the main block diagram of the
scheme logic opto board (See Figure 24).
Operation and circuit description
The three phase voltages VA', VB' & VC' are added together to produce the zero
sequence voltage (if all phase voltages are present then this summation will be
zero). This is then passed through an input amplifier and low pass filter. The input
amplifier matches the input signal level to the reference level of the voltage
comparator while the low pass filter is used to reject harmonics. The voltage
comparator detects if the input voltage exceeds the reference level; if this occurs,
the output of the level detector is set high. The voltage comparator uses two
reference levels, one for the positive half cycle and one for the negative half cycle.
Hysteresis is added to ensure no chatter exists on the output which could occur if
the input signal level is on the threshold of operation of the level detector. A drop
off timer (9 12ms) is used to hold the output high when the input signal level
drops below the reference level, thus filling in the gaps between the half cycles.
4.9.21 High set current level detectors
The high set phase current level detectors (LDHSA, B & C) are used to improve
stability of operation in the Blocking and Permissive Overreach (with Weak Infeed)
schemes.
The operating principle is identical to the zero sequence voltage level detector
(LDVO). The only difference is that the summing amplifier has been replaced by a
high gain input stage to match the low input signal levels produced by the current
measuring circuitry (see Figure 24) to the level required by the level detector.
QUADRAMHO Chapter 2
Page 18 of 74
The input levels to operate the level detectors are as follows:

50Hz (47 51) P/U = 10.1 14.0% of rated current at reference setting
60Hz (56 61) P/U = 10.7 15.2% of rated current at reference
The high set current level detector lowest setting (tolerance) is designed to be 10%
greater than the highest pick up level of the low set current level detector.
4.9.22 Power swing blocking hardware
The power swing blocking hardware consists of the ninth LED, the 4 way switch
bank and associated drive circuitry. The switch bank function is to allow the
blocking signal produced by the scheme logic processor board to be routed
though to the correct comparators by selection of the appropriate switch.
4.9.23 Scheme logic software
The complete software for Quadramho is contained in a 2732A EPROM
(4k x 8 bit). This allows changes to be made to suit individual customer
requirements.
There is only 1 version of software which is standard for all Quadramho versions.
The software used in Quadramho is constructed in modular form in which each
subroutine performs individual, or groups, of well defined functions. This allows
changes to be made to specified areas of program without complication.
All main subroutines within the scheme logic are common for all schemes.
However, the option subroutine (OPT) will use additional routines depending on the
scheme selected. The main program loop is shown in Figure 25.
4.9.24 INIT subroutine
After a hardware reset has occurred the microcontroller executes an initialisation
routine called INIT. It should be noted that the INIT routine is only run once.
The operations performed by this routine are shown below:
a) Allows a set time for all components to settle down
b) Sets the PPI to the correct mode of operation (see Section 4.9.10).
c) Sets microcontroller ports so that input data can be read.
d) Sends a master reset pulse (MRI) to reset all comparator elements.
e) Initialises all internal microcontroller memory.
f) Enables timer and external Zone 1 interrupts.
g) Initialises inoperative alarm and code switch monitor circuits (See Section
4.9.15).
h) Sets the self check registers to indicate that a self check has not yet taken place
(see test options Section 4.9.46).
4.9.25 The main loop
After the initialisation procedure has been performed the main loop is then
executed by the microcontroller
The general operation principle of the main loop is as follows:
Firstly all input ports and switch banks are read by the microcontroller at the
beginning of the loop and then stored in registers which are designated as input
registers. This data is then processed by subroutines within the main loop which,
depending on these inputs, set bits in registers that are designated output registers.
QUADRAMHO Chapter 2
Page 19 of 74
At the end of the loop these output registers are then output via the appropriate
output ports.
The above is true when the standards scheme options are selected. If an invalid
scheme or a test option is selected then only parts of the main loop are run, see
Section 4.9.46.
Most of the software timers are not run in the main loop, but in the timer interrupt
routine. (This is described later on in this section).
During normal scheme operation the loop time (time taken to travel once round the
loop) including the servicing of the timer interrupt is approximately 3.1 3.8ms
depending on the scheme selected. The exception to this is when a Zone 1
interrupt takes place. The loop time will also change if a test option or invalid
scheme is selected.
4.9.26 Z1 NT subroutine
This feature is present to speed up tripping when a Zone 1 fault is detected.
This feature uses the microcontroller external interrupt, which is driven by the
Zone 1 comparator outputs gated with the low set current level detectors and high
set neutral level detector.
After an interrupt has taken place, the Z1 INT routine is entered; interrupt is
disabled to prevent another interrupt occurring until after the present one has
finished, also a flag is set to indicate that an interrupt has taken place. If any main
loop trip is in progress or the SOTF feature is enabled, the interrupt will return to
the main loop. The main program will be run from the point when the interrupt
occurred (see timer interrupt section). If the SOTF feature is not enabled and no
main loop trip is in progress then when the interrupt routine has been completed,
the microcontroller executes the FTRIP routine.
4.9.27 FTRIP subroutine
The FTRIP routine reads the Zone 1 comparators and performs level detector checks
on these. If no fault (after level detector checks) is present then the software is
executed from the beginning of the main loop. If a fault is present the following
then occurs:
a) Fault locator outputs are set.
b) Hysteresis is sent.
c) Correct tripping contacts are closed (see tripping logic Section 5.16.31).
d) Carrier is transmitted if PUR scheme is selected.
e) The trip drop off timer is run.
After the above the software is executed from the beginning of the main loop.
4.9.28 LOAD subroutine
The LOAD routine performs the following:
Firstly the code switch number (CSN) and the code switch number override
(CSN O/R) (pins 1 to 8 of socket 1) are stored in two registers. The CSN O/R is
tested to determine if an override is required. If an override is required then the
CSN O/R will determine which scheme is run. If no override is required then the
CSN will determine the scheme. The CSN or CSN O/R is then tested to see if a
valid scheme option is selected (0009). If this is not true, then the test option
software is run (See Section 4.9.46).
QUADRAMHO Chapter 2
Page 20 of 74
4.9.29 LLAD subroutine

The LOAD routine now runs another routine called LLAD. This reads all the input
ports of the microcontroller and peripherals and stores all these inputs in internal
memory for use later on in the program. The inputs loaded consist of the following:
a) tp and td switch bank settings.
Zone 2 switch bank settings.
Zone 3 switch bank settings.
OPTION switch bank settings.
b) All level detector outputs.
c) Push button state.
This routine also clears all the registers that are designated output registers
(described earlier).
4.9. 30 PDTIM subroutine
The PDTIM subroutine runs the pole dead pick up timers and sets the pole dead
outputs and internal flags. These flags are used by several subroutines within the
main loop. The pole dead logic is explained in Section 5.9.
4.9.31 VTS subroutine
The voltage transformer supervision (VTS) is described in Section 6.
4.9.32 LOAD 1 subroutine
The LOAD 1 subroutine reads the Zone 1, 2 and 3 comparators and performs level
detector checks on them (See Section 5.8). The comparator 6 bit format (A, B, C,
AB, BC & CA) is converted to 4 bit format (A, B, C & N). It also sets internal
flags to indicate that a fault has occurred in a particular zone. If the VTS has issued
a block comparator signal then the comparators will be software inhibited within
this routine.
4.9.33 FLOC subroutine
The FLOC subroutine generates the fault locator outputs (see Figure 74 for the logic
equivalent). For all schemes the fault locators normally operate based on the
Zone 1 and Zone 2 comparators (Zone 3 is not used), but this can be overridden
by the SOTF (SWITCH ON TO FAULT) Feature
The FLOC subroutine also sets an internal flag which indicates that any comparator
has operated.
4.9.34 SOTF subroutine
The SOTF operation is described in Section 5.16.39 Sotf fault locators.
Under normal scheme operation the fault locators operate on the comparator
information as mentioned earlier
If the SOTF feature is selected to operate on current and no volts (CNV) during the
SOTF enable time the fault locators will operate on the CNV condition that has
caused the trip. The fault locators will follow the CNV condition for the SOTF
enable time (240ms after all poles established) or until the CNV condition has
been removed, whichever is the longest.
The SOTF feature disables the basic scheme and prevents the carrier schemes from
issuing a trip. It should be noted that if a SOTF trip is still present after the SOTF
enable timer has run out, the SOTF will remain enabled until the fault has been
cleared.
QUADRAMHO Chapter 2
Page 21 of 74
4 9.35 BASIC subroutine

The basic scheme is not run if SOTF is enabled. The basic scheme is run for all
valid scheme options and is described in Section 5.16.23.
4.9.36 OPT subroutine
The OPT subroutine allows selection of any of the five standard tripping schemes
available via the code switches. If the basic scheme is selected then the program
bypasses the scheme options.
The carrier aided schemes (PUR, POR and BLOCK) all use a smaller subroutine
called AT (Aided Tripping). This small subroutine sets indications based on the
Zone 2 comparators. It also sets the tripping mode, depending on the CSN.
The carrier aided schemes also use another subroutine called BCIS.
This subroutine performs the following if the channel in service (CIS) opto isolator
input is not energised:
a) Allows only 3 phase tripping.
b) Blocks the auto reclose equipment if SW6 is set to right hand position.
4.9.37 MFAST subroutine
The purpose of this subroutine is to re-enable the synchronous polarising as soon
as possible after all conditions for re-start are satisfied. The synchronous polarising
is described in Section 5.2.2.
Under normal operating conditions the synchronous memory can lock on to an
input signal at 80.75/s @ 50Hz. This would mean that for a 180 (inverted)
maximum phase difference between input and output, the locking on time would
be 2.23s. The locking rate at 60Hz is 116.28/s.
The above means that unless further action is taken, the synchronous polarising
would be unlikely to be enabled until well after the SOTF enable time had elapsed.
However, the MFAST subroutine solves this problem and operates in the following
way. If the synchronous polarising has run out and is no longer required to run
(See Section 5.2.2) then a timer of length 140ms is run to allow several cycles of
synchronous polarising input to be established. When the timer runs out, the
synchronous polarising enable flag is reset and the timer interrupt (described later)
is delayed by approximately 80s, so that synchronous polarising registers can be
pre-set.
The synchronous polarising output is delayed by 4 interrupt cycles (4 x 179s)
from the input waveform, so that when an interrupt occurs the output can follow
any changes of state that occur in the input. If this is not done the output may get
out of phase with the input and would only phase lock at the normal synchronous
polarising run lock-on rate.
4.9.3S PSMIS subroutine
The PSMIS subroutine runs several functions, the main feature being the power
swing blocking (PSB) scheme. PSB is described in Section 5.13.
The functions performed by the PSMIS subroutine are:
a) runs power swing blocking scheme (PSB).
b) resets VTS blocking and indication latches and power swing indicator latch if
the push button is operated.
c) performs trip latching logic and runs trip drop off timer.
QUADRAMHO Chapter 2
Page 22 of 74
d) runs the BAR drop off timer.

e) sets various output register flags.
f) re-enables Zone 1 interrupt feature after previous interrupt has been terminated.
g) sends a master reset pulse to the comparators after an All Poles Dead
condition is detected.
4.9.39 EXOP subroutine
This subroutine performs several functions, these are listed below:
a) clearing and latching of the scheme logic indications
b) runs the comparator self check routine.
4.9.40 ENF subroutine
The ENF subroutine performs the band pass switching logic. This logic is used to
improve performance of the relay and is explained in Sections 4.2 and 5.16.18.
4.9.41 OP subroutine
The OP subroutine transfers the data that is stored in the output registers to the
correct output ports.
The OP subroutine also runs a test to determine if the timer interrupt is running;
if not, the interrupt is re-enabled.
4.9.42 LTIM timer interrupt routine
The timer interrupt is an internal interrupt that is generated within the
microcontroller. The digital synchronous polarising and software timers are
contained within the timer interrupt routine.
The timer interrupt occurs at regular intervals of approximately 179s.
The synchronous polarising is serviced on every timer interrupt which gives a
resolution (jitter) of the memory output VMC of 3.2 (for a detailed description of
the memory see Section 5.2.2).
The timers are serviced in six groups which contain two or three timers.
Each group of timers is serviced once in every eleven timer interrupts which gives a
timer resolution of 11 x 179.44 = 1.974ms.
4.9.43 Basic interrupt principle
When an external or timer interrupt request is made, the main loop continues
executing the current instruction. After this has finished, the address of the next
instruction to be executed within the main loop is stored automatically by the
microcontroller. The interrupt routine is then entered and the data being processed
within the main loop at the point of interrupt is then stored temporarily. This allows
restoration of data when the interrupt returns from the main loop. Normally the
interrupt returns to the address stored when the interrupt occurred. This is true for
the timer interrupt, but within the scheme logic the external (Zone 1) interrupt is
sometimes forced to return to the beginning of the loop (See Section Z1 INT
routine).
4.9.44 Principle of timer operation
There are 16 timer interrupt timers which all operate using the same principle.
The basic operation is as follows. Four internal microcontroller registers are
allocated for use by the timers, two of these are designated timer start registers
(TSR) which contain 16 timer start bits (one for each timer). Similarly the other two
QUADRAMHO Chapter 2
Page 23 of 74
registers are designated timer run out registers (TROR) and contain the timer run
out bits.
The timer start bit is set in the main loop when the timer is required to run.
Similarly this bit is set when the timer is to be reset. When the appropriate timer is
serviced by the timer interrupt, the timer start bit will be tested to see if the timer is
to be run. If a run condition is required then the timer will perform a counting
sequence in a register that has been designated a timer register.
The count within this register is incremented every time the timer is serviced by the
timer interrupt routine (every 1.974ms). When the timer has reached the required
count, the timer routine sets a bit in the timer run out register, this is the timer run
out bit. Every time the program executes the main loop the timer run out bit will be
tested to see if the timer has finished. If a reset condition is required, the timer run
out bit and the timer register are reset when the timer is next serviced by the
interrupt routine. Thus the timer is ready to be run when required. A list of all the
interrupt timers is given in Table 4.
Each of the 16 timers is allocated at least one timer register; long timers such as
the VTS 5.5s timer require more than one timer register.
The settable Zone 2 and Zone 3 delayed trip timers use multiples of a basic timer
length (eg. Z2 basic length is 10ms). The appropriate switches are used to provide
the multiplication factor. There is a 17th interrupt timer which is used to generate
the 2 week automatic self check delay.
4.9.45 Loop timers
Several of the shorter timers used within the scheme logic are loop timers.
These timers are run completely within the main loop. The operating principle of
these timers is described below.
When the timer is required to run, a register which is designated a timer register is
incremented once every time the main loop is executed. This is then tested to
determine if the timer has finished, if it has, then the timer register is reset. A list of
all the loop timers is given in Table 5.
TIMER FUNCTION TIMER LENGTH TIMER RESOLUTION
SIGNAL RECEIVE DROP OFF 100ms
td 0 90ms 6ms
tp 0 90ms 6ms
BLOCK AUTO 100ms
RECLOSE DROP OFF
ANY POLE DEAD 240ms
DROP OFF
VTS ACCELERATED 20ms
INDICATION PICK UP
SYNCHRONOUS 140ms
POLARISING (MEMORY)
ENABLE PICK UP
(POR) CIRCUIT BREAKER 60ms
OPEN PICK UP
SOTF DEAD TIME 200ms or 110s
SOTF ENABLE TIME 240ms
QUADRAMHO Chapter 2
Page 24 of 74
Timer function Timer length Timer resolution

SOTF CURRENT NO 20ms
VOLTS PICK UP
ZONE 2 DELAYED 0 250ms 10ms
TRIP PICK UP
ZONE 3 DELAYED 0 580ms 40ms
TRIP PICK UP
TRIP DROP OFF 60ms
VTS PICK UP 5.5s
PSB PICK UP 50ms
SELF CHECK ENABLE 2 weeks
(CONTINUOUSLY RUN)
Table 4: Interrupt timer
Timer function Timer length

ZONE 1 PHASE COMPARATOR BLOCK 35ms
ZONE 2 PHASE COMPARATOR BLOCK 35ms
POLE DEAD A PHASE PICK UP 20ms
POLE DEAD B PHASE PICK UP 20ms
POLE DEAD C PHASE PICK UP 20ms
BAND PASS FILTER VOLTAGE DROP OFF 14ms
WEAK INFEED ANY COMPARATOR DROP OFF 100ms
POR/WEAK INFEED CARRIER ECHO TIME 100ms
COMPARATOR CHECK PICK UP TIMER 10ms
Table 5: Loop timers
4.9.46 Scheme logic test program

The scheme logic test program is a group of options that are selectable via the
code switches. These options are divided into two groups:
a) input test options.
b) output test options.
The input test options are listed in Table 6, indication is given on the 8 LEDs (A, B,
C, Z2. Z3, AIDED TRIP, SOTF, V~FAlL) when the correct CSN is set. The 8 LED
outputs are available on socket 2 (See Section 5.16.42).
The output test options are listed in Table 7.
To set any output, firstly the correct CSN corresponding to the test option required
must be selected. The appropriate option switch must be set to the right hand
position and the push button should be operated. Only one group of outputs (one
test option number) can be energised at any one time.
All the TRIP contact output test options are put in a separate option (88) away from
the others to prevent inadvertent operation of circuit breakers, etc.
QUADRAMHO Chapter 2
Page 25 of 74
When a test option is selected (or an invalid scheme) the relay inoperative alarm
contact will close and the relay available LED will extinguish.
The full schemes do not run when a test option is selected. Below is a list of the
features that are run when a test option is selected:
a) Digital synchronous polarising.
b) Pole dead logic.
c) Master reset pulse on All Poles Dead conditions.
d) Band pass filter switching logic.
Test LED
option Test and method indications Comments
no.
40 Zone 1 comparators gated AN A Amplitude and
with low set current BN B angular hysteresis
level detectors CN C operate on any
Zone 1 comparator.
(Secondary Inject AB Z2 No tripping will
Zone 1 Fault) BC Z3 occur
CA AIDED TRIP
Breaker open opto input
(Apply rated volts to A3A4) SOTF
Reset Zone 1 extension opto
input (Apply rated volts to V~ FAIL
A1A2)
The Zone 1 extension opto is
redesignated as miniature
circuit breaker open opto
when this version has been
supplied.

with low-set current BN B angular hysteresis
(Secondary inject AB Z2 Z2 comparator
Zone 2 fault) BC Z3 No tripping will
CA AIDED TRIP occur.
Signal receive opto input
(Apply rated volts to A9A10) SOTF
Channel in service opto input V~ FAIL
(Apply rated volts to A7A8)
The signal receive opto also
can be used to reset Zone 1
extension for the appropriate
thumbwheel selection option,
QUADRAMHO Chapter 2
Page 26 of 74
Test LED
no.
42 Zone 3 comparators gated AN A Amplitude
with low-set current BN B hysteresis operates
level detectors CN C on any Zone 3
comparator.
No tripping will
occur.
(Secondary inject AB Z2
Zone 3 Fault) BC Z3
CA AIDED TRIP
Zero Sequence voltage level SOTF
detector (secondary inject)
Inhibit PSB opto input
(Apply rated volts to A5A6) V~ FAIL
43 Overvoltage level AN A
detectors BN B
(secondary inject voltage) CN C
Pushbutton & pushbutton Z2
override
(operate push-button or
apply 0V to SK1 Pin9)
Low set current level A Z3
detectors B AIDED TRIP
(Secondary inject current) C SOTF
N V~ FAIL
45 Self check of Zone 1 AN A The LED lights for
comparators BN B the appropriate
CN C comparator if it
AB Z2 passed the last
BC Z3 self check. If all
CA AIDED TRIP 8 LEDs are
illuminated, self
check has not
occurred.
46 Self check of Zone 2 AN A As option 45
comparators BN B
CN C
AB Z2
BC Z3
CA AIDED TRIP
QUADRAMHO Chapter 2
Page 27 of 74
Test LED
no.

comparators BN B
CN C
AB AB Z2
BC Z3
CA AIDED TRIP
Self check of Zone 6 AB SOTF
comparator
50 Zone 1 comparators AN A As option 40.

(Secondary inject BN B
Zone 1 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Breaker open opto input SOTF
Reset Zone 1 extension opto input V~ FAIL
(Apply rated volts to A1 A2)
The Zone 1 extension opto
is redesignated miniature circuit
breaker open opto when this
version has been supplied.

Zone 2 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Signal receive opto input SOTF
(Apply rated volts to A9 A10)
(Apply rated volts to A7 A8).
The signal receive opto also can
be used to reset Zone 1 extension
for the appropriate thumbwheel
selection option.
QUADRAMHO Chapter 2
Page 28 of 74
Test LED
no.
52 Zone 3 comparators AN A As option 42

Zone 3 fault) CN C
AB Z2
CA AIDED TRIP
Zero sequence voltage level detector SOTF
(Apply low voltage and increase to
pick up)
Inhibit PSB opto input V~ FAIL
53 Memory input volts VC B* Option 53, LED B

(Apply rated volts to C phases) may be latched on
or off when rated
volts are not
present.
Monitor memory
on monitor output
socket pin 2 & 24,
disregard LED B
indication
Zone 6 comparator AB C
(secondary inject AB
Zone 6 fault) SW9 Z2 LED on when
Option setting switch SW9 Z2 switches in right
High set current level A Z3 hand position.
(secondary inject content) C SOTF
N V~ FAIL
54 Zone 2 Timer switch 1280 A Indications lit

640 B when switches in
320 C right hand position.
160 Z2
80 Z3
40 AIDED TRIP
20 SOTF
10 V~FAIL
55 Zone 3 Timer A As option 54

Switch Settings 2560 B
1280 C
640 Z2
320 Z3
160 AIDED TRIP
80 SOTF
40 V~FAIL
QUADRAMHO Chapter 2
Page 29 of 74
Test LED
no.
56 tp timer switch setting 48 A As option 54.

24 B
12 C
6 Z2
td timer switch setting 48 Z3
24 AIDED TRIP
12 SOTF
6 V~ FAIL
57 Option switch setting SW8 A As option 54.

SW7 B
SW6 C
SW5 Z2
SW4 Z3
SW3 AIDED TRIP
SW2 SOTF
SW1 V~FAIL
58 Socket 1 inputs PIN 8 A This option will

PIN 7 B override the normal
PIN 6 C function of the test
PIN 5 Z2 socket except when
PIN 4 Z3 option F0 is
selected.
PIN 3 AIDED TRIP
PIN 2 SOTF
PIN 1 V~FAIL
99 EPROM Identifier number 8 A The EPROM

(Press push button) 4 B identifier number is
2 C indicated
1 Z2 in binary coded
8 Z3 decimal form
4 AIDED TRIP Information given
2 SOTF is intended for
1 V~FAIL ALSTOM Protection
& Control Ltd use.
FO Code Selection CSNX 8 A The binary coded

Number Enter F0 4 B decimal form of
to socket) 2 C each code switch
1 Z2 number
CSNY 8 Z3 is given.
4 AIDED TRIP
2 SOTF
1 V~ FAIL
Table 6: Input test options

QUADRAMHO Chapter 2
Page 30 of 74
Test Output tested and switch to be Output given on the rear terminals
option set to the right and/or the monitor point box
no.
60 A indication SW8 Pressing the reset button SK225
B indication SW7 causes the voltage on the SK224
C indication SW6 monitor point box terminals SK223
Z2 indication SW5 (2 is 0V reference) to fall SK222
Z3 indication SW4 from 24V to zero. Use a SK221
AIDED TRIP indication SW3 high impedance SK220
SOTF indication SW2 voltmeter SK219
V FAIL indication SW1 SK218
61 Fault Iocator A SW8 19A1 C1C2

B SW7 19B1 C3C4
C SW6 19C1 C5C6
N SW5 19E1 C7C8
Power swing timer SW4 As for 60 SK27
Hysteresis SW1 Internal
62 Signal send SW8 85X1,85X2,B1B2,B3B4 SK217

CRX annunciate SW6 SK29
Zone 2 trip alarm SW5 Z21 C910
Zone 3 trip alarm SW4 Z31 C11C12
Aided trip alarm SW3 94Y1 C13C14
SOTF trip alarm SW2 981 C15C16
Fuse fail alarm SW1 97X1 C17C18
63 MRI SW8 Internal

Self Check SW7 Internal
POWER SWING indication SW6
Any Z,Z2,Z3 SW5 Any Z1,Z2,Z3 SK26
Block A/R SW4 961 B25B26
SK213
Extend Zone 1 SW3 Internal
Power swing alarm SW2 951 C19C20
64 Pole dead C SW6 Internal

Pole dead B SW5 Internal
Pole dead A SW4 Internal
SOTF Enable SW3 SK25
DICO SW2 Internal
ENF SW1 Internal
88 Any trip SW5 941,942, B21B22,B23B24,

SK211
Trip 3 phase SW4 94T1,94T2, B17B18,B19B20,
SK212
Trip A SW3 94A1, 94A2, B5B6, B7B8
Trip B SW2 94B1,94B2, B9B10, B11B12
Trip C SW1 94C1,94C2, B13B14,B15B16
Table 7: Output test options

QUADRAMHO Chapter 2
Page 31 of 74
Note: No contact will close until the appropriate SW switch is to the right and
the reset button is pressed.
4.9.47 The auxiliary relay module RVC 53
The two main functions of this module are to produce all the relay output contacts
and to produce a number of test signals at the test socket SK2 on the relay facia.
These functions are illustrated on the right and left, respectively, of the block
diagram, Figure 27.
The eighteen auxiliary relay units contained in this module are controlled directly
by the scheme logic module. The majority of the contacts are single, normally open
type, however, CTX, TRIP A, TRIP B, TRIP C, TRIP 3 PH and ANY TRIP each provide
two normally open contacts. The Relay Inoperative alarm contact is a single
normally closed type.
All contacts have the following rating:
Make and carry for 0.2s 7500 VA with maxima of 30A and 300V ac or dc.
Carry continuously 5A ac or dc.
Break: ac 1250VA
dc 50W resistive with maxima 5A, 300V
25W L/R =0.04s
Each contact is electrically isolated from all other contacts and ground to a proof
voltage of 2kV rms for 1 minute and can withstand 1kV for 1 minute across its
normally open terminals.
During commissioning of Quadramho it is possible to inhibit the operation of the
contacts in two ways. The first is to replace the heavy duty test plug 1Z with a plug
with an open circuit on 1Z10. This breaks the output relays common connection
to the relay coils. The second way is to connect pin 1 to pin 2 of the test socket
SK2 via a wire link. This opens the solid state switches in the module which
operate the relay coils. On the diagram these elements are represented by a set of
normally closed contacts linked to pin 1 of SK2.
Whenever the relays are inhibited the LED labelled Relay Available on the relay
facia and D on the diagram, is extinguished and the Relay Inoperative alarm
contact closed. This also happens when the relay is set to a test option or when an
internal fault in the relay is detected by the continuous monitoring circuits.
Further details of this feature are given Section 5.16.40.
Eighteen of the pins on the test socket, SK2, take outputs via a buffer circuit,
labelled B on the diagram, from the scheme logic module. Each output consists
of a pull down transistor and a pull up resistor of 22k. The logic levels of these
outputs is either 0V or +24 V. These outputs are not inhibited with the auxiliary
relay. Five other outputs are taken to the test socket via 10K resistors. These are
used to monitor the dc rails of the relay and the highest division of the master clock
frequency, MCK/28.
Since all the pins on the socket, except 0V on pin 2, have resistors connected in
series with them it is impossible to damage Quadramho by inadvertently shorting
together any number of pins via a wire link.
4.9.48 Power supply unit ZRE 01
The single pcb power supply unit is contained within a ventilated enclosure which
is mounted on the back of Quadramho. It can be detached from the main relay
QUADRAMHO Chapter 2
Page 32 of 74
case by removing six screws and releasing two plugs. Upon replacing the
backpack the silicon rubber dust sealant must be renewed.
Three versions of the power supply are available, for nominal input voltage ratings
48/54, 110/125 and 220/250V dc. These versions have operating ranges of
37.5 60, 87.5 137.5 and 175 275V dc respectively. All three versions
produce regulated output voltage rails of +24V, +12V and +5V at a current of up
to 1A, and 12V at a current of up to 0.5A. Any output can be short-circuited for
a brief time with no resultant power supply damage.
The operation of the unit is now described with the aid of block diagram,
Figure 28.
The dc supply from the secure station battery, is used as a power source for the
production of the isolated, smooth and regulated internal supply rails. The dc is
firstly passed through a filtering section which attenuates electrical noise and
voltage spikes and ensures that Quadramho is immune to interference generated
by other equipment connected to the station battery. It also prevents the power
supply from transmitting interference to this same equipment.
The filtered voltage is sensed by the voltage detector and when this exceeds a
minimum value the internal voltage rail of the power supply electronics is
energised. This eliminates the danger of power supply maloperation for input
voltages less than the minimum operating voltages given above.
The feed forward principle is used in the pulse width modulator section to
produce a 40kHz square wave with a mark to space ratio (duty factor) which
varies inversely with the filtered supply voltage. This ensures that the power supply
output voltages remain relatively constant despite differing or changing input
supply voltages. The switching transistor is driven on and off by the pulse width
modulator to energise the primary of the transformer with current from the filtered
voltage supply. The transformer electrically isolates the station supply from the relay
electronics (2kV for 1 minute) and transforms the primary voltage to a level suitable
for the outputs. Screens are incorporated on the transformer to render the relay
insensitive to common mode interference between the station battery supply and
the relay case/ground.
Pulsed voltage waveforms produced at each of the transformer secondaries are
smoothed by L C low pass filters to produce near constant dc voltages.
It is then necessary to regulate these voltages since small variations in them occur
due to ripple, input voltage variation and load regulation. This is accomplished by
the use of solid state regulator devices which also feature overcurrent and thermal
overload protection.
If some part of the power supply fails, such that a large current is drawn from the
station battery, then a fusible resistor, connected in series with the station battery
voltage supply, operates and disconnects the battery voltage. Before replacing or
repairing this device the fault resulting in its operation must be investigated.
QUADRAMHO Chapter 2
Page 33 of 74
Section 5. PRINCIPLES OF OPERATION
5.1 The comparator

The important requirements of high speed and high stability have both been
satisfied in the comparator design. Usually these two requirements are in
contention because the faster the operating speed, the greater the risk of false
operation caused by contaminated relay input signals. Signal contaminations
include harmonic components, switching surges, lightning impulses, travelling
waves, exponential decays, saturated current transformer waveforms, coupling
capacitor voltage transformer transient errors and interference voltages induced on
low voltage wiring due to switching on the high voltage system.
The comparator resolves the speed/stability contention by checking its own input
signals to verify that they are dominated by components consistent with power
system frequency waveforms. If verification is obtained, full operating speed is
allowed. If verification is not obtained, the comparator demands more data before
tripping can be allowed, thereby automatically extending the signal processing
time sufficiently to ensure that no maloperation can occur. By suitable filtering and
preconditioning of the comparator input signals, the relay design ensures that the
comparator is able to operate at its highest speed for the majority of transmission
line faults.
5.1.1 Fundamentals of the comparator
The comparators in Quadramho are used to produce a variety of different
characteristic shapes, such as quadrilateral, mho, offset mho, lenticular etc.
The easiest to explain is the mho (or circular) characteristic, so this will be
described first.
For simplicity describing a self-polarising characteristic, the comparator inputs are
as shown in Figure 29, such that:
A = V IZ
B = V / 90
and the condition for operation is that A lags B by 0 to 180. As the operation of
the comparator must be independent of the magnitude of A and B, these two
quantities are changed to square waves using high gain amplifiers before being
supplied to the comparator The squared up signals convey only the phase angle
information of the original signals.
The comparator treats the input square waves as logic variables which can each
have a high or a low logic state at any time. To facilitate the following explanation,
signal A will be described as A or A depending on its logic state at a particular
instant of time and signal B will be described as B or B . There are four possible
combinations of state, A.B, A .B, A.B , and A. B . If both signals have unity
mark/space ratios and equal periods but different phases, then the four
combinations occur in a cyclic manner.
There are only two possible sequences of these combinations as shown in
Figure 30. These are:
1) If signal A leads signal B: A.B, A .B, A.B , A. B , A.B
2) If signal A lags signal B: A.B, A. B , A.B , A .B, A.B
From these the following logic statements can be deduced.
QUADRAMHO Chapter 2
Page 34 of 74
1) If signal A leads signal B, when A changes it gains the opposite state from B,
while when B changes it gains the same state as A.
2) If signal A lags signal B, when A changes it gains the same state as B, while
when B changes it gains the opposite state from A.
The comparator has a logic circuit which examines the input signals at each
change of state to see which of the two statements is true and thus determines
whether the sequence is progressing in a restrain or a tripping direction. The circuit
can identify the direction of the progression from a single change of logic state of
either input and from any starting point in the logic sequence.
Because the presence of noise can introduce false changes of state unconnected
with the true signals at the power system frequency, a single change of state
matching the trip sequence does not necessarily represent a fault condition within
the protected section of line. Greater security is obtained if the criterion for tripping
is to receive a number of successive changes of state, each of which matches the
tripping sequence. The comparator therefore has a counter for determining
whether one, two, three or four such changes have been observed.
Each acceptable change matching the tripping sequence adds to the total count
(up to a maximum of four) while every change matching the restrain sequence,
subtracts from the total count (down to a minimum of zero). The criterion for
operation is a count of three. The action of the counter for a typical fault within
Zone 1 is shown in Figure 31.
5.1.2 Action of the comparator counter
Figures 30 and 31 show pure power frequency signals, but it is obvious that the
presence of noise would change the situation. To illustrate the point, Figure 32
shows a restrain condition of the power frequency signals, with a burst of high
frequency noise superimposed on a comparator input. Because the noise happens
to coincide with a change of state of the other comparator input, a count up
situation occurs at high frequency. To prevent the comparator from tripping
wrongly, the rate of counting up is deliberately limited, preventing a count of more
than one from being registered.
The device for restricting the rate of counting up is a timing circuit. This is initiated
by any change of state which fits the tripping sequence and runs for a nominal
time period of 0.15 cycle. If another change of state in the operate sequence
occurs while the timer is running, the timer is restarted. While the timer is running,
the counter cannot be incremented further. Each change of state in the restrain
sequence decrements the counter and terminates any timing period running, so
there is no restriction on the rate of counting down.
The restriction on the rate of counting up effectively limits the operating bandwidth
of the comparator, eliminating maloperation on high frequency interference.
The same restriction also prevents the possibility of transient overreach occurring
when the VIZ comparator input has an exponential offset which distorts the mark/
space ratio of the square wave, as shown in Figure 33 Note that the exponential
component of the current does not cause a significant exponential offset in IZ,
because the signal is differentiated with a short time constant by the current input
devices (transphasors) described later. The voltage supply can have an exponential
component which is reflected in VIZ but not in VPOL because the latter is normally
dominated by healthy phase components.
The distance relay contains a total of eighteen full comparators, that is, three
ground fault and three phase fault comparators per zone. Each full comparator
QUADRAMHO Chapter 2
Page 35 of 74
contains its own logic circuits, counter, constraint timer etc. Figure 34 shows a
flowchart of the sequence comparator logic process.
5.1.3 Exclusion of noise
The following interfacing and preconditioning measures ensure that the full high
speed performance potential of the comparator is achieved even with severely
contaminated relay input signals:
1) Good physical layout and electrical filtering have been used to exclude high
frequency noise generated in the substation. The relay terminals and all of the
relay modules which interface with the outside world are concentrated in the
right hand side of the relay case. The interface modules provide electrical
isolation to 5kV peak, using isolating transformers with screens to shunt high
frequency currents to earth and so attenuate common mode interference.
Transverse mode interference is attenuated by low pass filters. The measuring
and control modules which occupy the left hand side of the relay case, therefore
operate in a quiet electrical environment.
2) Other high frequency signals, such as travelling wave effects and high harmonic
frequencies, are attenuated by low pass filters which cut off at about 120Hz.
3) Exponential components of the current supply are attenuated with a short time
constant (typically less than 1ms) by the main current input devices of the relay,
known as transphasors, described later. In the quadrilateral version of
Quadramho, current transformers are also used, together with band pass filters
to remove exponential components.
4) Coupling capacitor voltage transformer (CVT) transients are prevented from
having any effect on the polarising signal by the dominant effect of sound
phase or synchronous polarising, described later. Switched band pass filters are
used to eliminate excessive effects of CVT transients in other relay signals
derived from the voltage supply.
5.1.4 Phase shifting circuit
To develop impedance characteristics such as the mho, the phase comparator
needs its polarising quantity to be phase shifted by a lagging angle (See Figure
35). Because the comparator operates at high speed the design avoids energy
storing phase shift circuits, for instance capacitor-resistor networks, which have
poor transient response. As the comparator deals with square waves which can be
regarded as logic variables, the phase shifts are obtained by using shift register
logic circuits driven by a clock pulse generator. Each shift register introduces a time
delay which depends on the number of bistables (or bits) in the register and the
clock pulse frequency. The required clock pulse frequency depends on the nominal
power system frequency.
5.2 Polarising arrangements
To simplify the description, the mho characteristic has been described in Section
5.1.1 as if it were self polarised. In fact, partial healthy phase cross polarising and
partial synchronous polarising components are used. The term synchronous
polarising refers to an advanced digital memory system which is described in
Section 5.2.2. These extra polarising components are used in order to satisfy the
following requirements:
1) To maintain a correct polarising (ie. directional reference) signal for the relay
comparators under conditions of close-up faults of all types even in the presence
QUADRAMHO Chapter 2
Page 36 of 74
of large transient voltage errors from the CVTs, so that correct directional response
can be ensured.
2) To enable a fast operating time to be obtained for close up faults of all types in
the forward direction of the relay.
3) To provide expansion of the resistive coverage of the mho for faults with low
infeed currents, where arc resistance may be large.
Both the healthy phase and synchronous components are square wave signals of
amplitude 16% of the peak prefault voltage supply. Under unbalanced fault
conditions, the proportion of healthy phase polarising is enough to overcome the
effects of normal CVT transients. Under 3 phase fault conditions, the synchronous
polarising works in a similar way. Figure 36 shows that by adding a 16% square
wave to the CVT error, the correct zero crossings of the polarising voltage are
restored. The polarising signal is squared up and phase retarded by 90 to
become input B of the comparator
The unique shapes of the partially cross polarised mho practical polar
characteristics, shown in Figure 37, have been achieved by suitable choice of the
wave shape of the signals involved in the polarising mixing circuits.
In conventional polarising mixing circuits, all the signals are sinewaves, but in the
Quadramho the synchronous polarising and sound phase cross polarising
components are square waves. The advantages of these unique polar
characteristics are obtained with only one two input comparator, enabling
optimum operating time to be obtained. Due to the partial synchronous polarising
component, the resistive expansion is maintained for 3 phase faults. The top line of
the expanded characteristic is part of a fully cross polarised circle and moves with
prefault power flow so as to avoid overreach or underreach. Operating time
contours over the area of the characteristic are shown in Figure 38.
5.2.1 Partially cross-polarised MHO
The polarising quantity, VPOL, is formed by squaring and summing circuits supplied
with the phase-ground voltages and the synchronous polarising signal. The circuits
are so arranged that the effect of synchronous polarising only becomes significant
when the phase-ground voltages are reduced under low voltage three phase fault
conditions. This is explained by reference to Figures 39 and 40, which show
circuit details for two typical phases of the polarising mixing circuits.
Taking first the AG phase, Figure 39, the sinewave quantities VB and VC are
summed using two equal value resistors R1 and R2 and supplied to the inverting
input of a high gain amplifier IC1. The square wave synchronous polarising
voltage VMA is potentially divided with R3 and R4 and supplied to the non-
inverting input.
The resistor values are chosen so that the peak value of the waveform on the non-
inverting input is 16% of the peak value of the waveform on the other input under
healthy supply conditions. The square wave output VKA from IC1 retains the phase
information of the zero voltage crossings of the sum of the input waveforms.
The phase of VKA is dominantly controlled by the cross polarising signal VB + VC
for most types of fault, the exceptions being low voltage three phase and low
voltage BCG faults, where the synchronous polarising signal VMA becomes the
controlling quantity.
A proportion of VKA is then added to the self voltage VA using R5 and R6 and a
second high gain amplifier IC2. The values of R5 and R6 are arranged so that the
QUADRAMHO Chapter 2
Page 37 of 74
peak value of the square wave VKA produces the same voltage at the input of IC2
as 16% of the peak value of the sinewave VA under healthy supply conditions.
The squared output VQA from IC2 is phase shifted 90 by a shift register (which is
not shown in Figure 39) and the resultant signal VPOL is then supplied to the
comparator. The phase of VQA is dominated by input VA throughout all types of
fault except ground fault conditions involving the A phase and three phase faults
which cause the supply to collapse. For these conditions of low VA voltage the VKA
input predominates. Indeed if VA collapses to less than 16% of rated voltage, VA
ceases to have any influence at all on the polarising signal and the comparator
becomes effectively fully cross polarised. The resistive expansion of the
characteristic for low voltage ground faults is, therefore, much stronger than for a
conventional partially cross polarised mho relay. (See Figure 41). The synchronous
polarising also causes similar large resistive expansion for low voltage three phase
faults.
The BC polarising mixing circuit is explained with the aid of Figure 40.
Under BC and three phase fault conditions, VKA has the same phase as the
memory signal VMA and as explained the square wave voltage VKA is mixed with
the sinewave VA on resistors R5 and R6. The values of these resistors are selected
so that, under a state of healthy supply voltage, the peak value of VKA has 16% of
the effect of the peak value of VA at the input of the amplifier 1C2. The resultant
squarewave at the output of IC3 is phase retarded by 90 using a shift register to
produce a squarewave VNA. A set of resistors R9, R10, R11, R12 are used to mix
VNA with VB and VC in such proportions that the peak value of VNA corresponds to
16% of the peak value of VBVC at this input of squaring amplifier IC4. The output
VQBC of IC4 is phase shifted through a lagging angle of 90 by a shift register (not
shown) and is then supplied to the comparator.
The phase of VQBC is determined largely by the zero crossings of VBVC under all
types of fault conditions except BC, BCG and three phase faults which cause
the BC voltage to collapse. For these conditions of low BC voltage the VNA input
dominates the phase of the polarising signal. VNA in turn is controlled by VA if this
fault involves the BC or BCG phases, or by VMA if the fault involves all three
phases. Therefore, if VBVC collapses below 16%, the BC unit is effectively fully
cross polarised and consequently the resistive expansion of the impedance
characteristic is greater than for a conventional partially cross polarised relay.
Also the resistive expansion also applies to three phase faults.
The combination of the sinewave faulty phase voltage with the square wave cross
polarising (or synchronous polarising) voltage results in a phase displacement of
the resultant polarising signal from its prefault position, which is different from that
of a conventional partially cross polarised mho. Figure 41 shows the relationship
of phase displacements of the faulty phase and polarising signals for Quadramho
and conventionally polarised comparators, drawn for a typical fault voltage
amplitude. In Quadramho the displacement of the polarising signal is zero until the
faulted phase is displaced by more than a critical angle , the capture angle.
Once the critical angle is exceeded, the polarising voltage phase displacement
rises linearly with the faulted phase voltage displacement.
The explanation for this behaviour is shown in Figures 42 and 43. Figure 42,
shows an example of the composition of the polarising signal in Quadramho.
The faulted phased sinewave is drawn here for a fault voltage of 25%, displaced
by 30 lagging, relative to the prefault values. This signal is summed with the
square wave cross polarising signal the magnitude of which is 16% of the prefault
QUADRAMHO Chapter 2
Page 38 of 74
sinewave peak voltage. The zero crossings of the resultant signal remain in phase
with those of the cross polarising signal, that is, no displacement from the prefault
position.
Figure 43 shows conditions similar to Figure 42, but with the faulted phase voltage
displaced by 60. Under these conditions the resultant polarising signal is
displaced by about 20 from its prefault position, because the faulted phase
displacement exceeds the captive angle by this amount.
When the displacement of the faulted phase voltage is just equal to the captive
angle ;
Vpk sin = VPOL
VPOL
Captive angle . = sin1
Vpk
provided that Vpk VPOL
If Vpk < VPOL, the sinewave has no effect on the polarising signal, so the
characteristic becomes fully cross polarised.
Since the displacement of the resultant polarising signal is zero if the faulted phase
voltage is less than the captive angle, the boundary of the characteristic over this
range is the same as that of a fully cross polarised mho (See Figure 41).
For high values of displacement of the faulty phase, the curves of the resultant
polarising signal for a conventional partially cross polarised mho and for
Quadramho are asymptotic. This means the reach of Quadramho in the capacitive
reactance region is the same as for a relay with 16% sinewave cross polarising
(See Figure 41).
Although Figure 41 is drawn for a constant fault voltage, the principles remain the
same for constant SIR conditions. The higher the SIR the lower the fault voltage and
the larger the capture angle. Hence the relay becomes progressively more cross
polarised as the SIR rises, as previously shown in Figure 37.
A simple graphical method showing how to determine the practical polar plots
may be found in the application notes.
5.2.2 Synchronous polarising
The synchronous polarising signal is available for 8 cycles following a 3 phase
close-up fault. This time is sufficient to keep the Zone 1 comparators in a stable
condition for a reverse fault, until it is cleared by other protection. In the case of a
forward fault, 8 cycles is more than sufficient to allow Quadramho to trip and clear
the fault.
Under three phase close up fault conditions, the polarising signal is controlled by
the synchronous polarising signal VMA (See Figure 39). After 8 cycles this power
system frequency signal is replaced by 0.3% of IA ZPh. This limits the directional
sensitivity of the comparator once the synchronous polarising has reduced to
approximately 1.3% of rated voltage, for 3 phase faults.
The synchronous polarising system is implemented as a software control feature of
the microprocessor in the scheme logic module (see Section 4.9.23) and the basis
of the system is a set of 32 registers of 8 bits each, which may be imagined as
being arranged in a carousel as shown in Figure 44. The carousel may be
regarded as rotating anti-clockwise under healthy live conditions on the
transmission line.
QUADRAMHO Chapter 2
Page 39 of 74
Phase C voltage is used as a reference signal for pre-fault phase information, after
being squared by a high gain amplifier. The length of one half cycle is measured
in units of 179s (the timer interrupt period of the microprocessor scheme logic)
and the number of units is stored in a register. When this half cycle finishes, the
carousel is rotated anti-clockwise by one register and the length of the next half
cycle measured and stored. This process continues indefinitely, with new data
overwriting the old when all 32 registers are full.
To generate the synchronous polarising output signal, an examination is made of
the data held in the 8th register anti-clockwise from the present input register.
This number is then used to determine the length of the output half cycle required.
When the output half cycle has been produced the polarity of the output is
reversed and another examination is made of the data held in the register which is
at the present 8th position. The next half cycle is generated accordingly.
This process is repeated indefinitely, producing the synchronous polarising output
wave.
This method allows the reproduction of the frequency of the input signal VC.
The output is phase locked with the input by effectively adjusting the number in the
output register by plus or minus one, every fourth output edge, to bring the output
into phase with VC as closely as possible.
When any voltage level detector resets or any comparator operates, this is deemed
to be a faulty or dead line condition and the memory is allowed to run out.
Under these circumstances, the direction of rotation of the carousel is reversed
(See Figure 45) and the output is maintained from data previously stored, for 16
half cycles, after which the synchronous polarising output is disconnected from the
polarising mixing circuits. The data in the most recently recorded registers are not
used, because distorted voltage may be present in the period just before the
voltage level detector resets, or the comparator operates. During the 16 half cycles
of memory run-out, the phase lock is disabled to protect the synchronous polarising
from any undesirable change in frequency.
A period of 140ms is allowed, after all voltage level detectors become operated
and all comparators are reset, before the synchronous polarising is reconnected.
This period allows the registers to fill with healthy phase information. Immediately
before the 140ms expires, a comparison is made between the number in the
current input register (equivalent to the elapsed time of the current half cycle) and
the number in the next anti-clockwise register (equivalent to the length of the
previous half cycle) The difference in time is effectively put into the output register,
so that when the synchronous polarising is reconnected, the output is immediately
in phase with the input. At this instant of reconnection, several cycles of accurate
synchronous polarising are already available for Zone 1 comparator operation,
this being an advantage over other methods.
The synchronous polarising signals for the A and B phases are obtained from VMC
by phase shifting.
5.3 Offset MHO characteristic
The offset mho characteristic for Zone 3 is produced by the same type of phase
comparator as for Zones 1 and 2, but using different input quantities as shown in
Figure 46 ie:
A1 = VIZ
B1 = (V+IZ) /90
QUADRAMHO Chapter 2
Page 40 of 74
5.4 The lenticular characteristic

An offset lenticular characteristic is available for Zone 3 for long line applications
where load impedance may encroach on to an offset mho characteristic.
The lenticular characteristic is produced by the intersection of two circles as shown
in Figure 47. The two circles are generated by two comparators using the same
signals as for a normal offset circular characteristic, but using different phase shifts.
The inputs to the comparators then become:
A1 = VIZ ) comparator Cl
B1 = (V+IZ') /180 ) (main comparator)
A2 = VIZ ) comparator C2
B2 = (V+IZ) / (inhibit comparator)
The intersections of the two circles occur on the characteristic angle of the relay
and determine the forward and reverse reach of the lenticular characteristic.
The reach remains independent of the comparison angles.
The aspect ratio, or ratio of the length of the minor and major axes of the lenticular
shape, is determined by the angle . The aspect ratio can be set to 0.41, 0.67
and 1.00 (Figure 48).
The block diagram is shown in Figure 49. The comparator consists only of basic
circuitry for determining whether changes of state of the input signals constitute an
operate or a restrain sequence. There is no counter associated with C2, as its
purpose is only to provide a signal for the inhibit terminal of the main comparator
C1 which therefore, only produces a trip signal for faults within the lenticular
characteristic.
5.5 The quadrilateral characteristic
The quadrilateral characteristic, available as an option for the ground fault
comparators, offers an increased coverage of fault resistance for short lines with
strong infeed, where the resistive expansion of the partially cross polarised mho
may not be sufficient to cover high tower footing or ground contact resistance.
Only a single main comparator is needed to produce a quadrilateral
characteristic, thus avoiding the race problems associated with characteristics
produced by multiple comparators. As shown in Figure 50, the main comparator
of Zone 1 produces the top or reactance line of the quadrilateral from inputs:
A1 = V IZ and
B1 = INR, where INR = (IAR + IBR + ICR) /3
The vector INR is obtained from the line currents by three current transformers
supplying small resistive burdens. The replica signals are band pass filtered to
remove exponential and high frequency components before being mixed to
produce an IR signal representing the residual current component. The top line
moves with active power flow to avoid the overreach or underreach problems
associated with phase current polarised reactance characteristics.
The other three sides of the Zone 1 quadrilateral are formed by three inhibit
comparators, that is, comparators without counters, arranged to inhibit the main
comparator. The main comparator can only count up when the three inhibit
comparators all agree that the impedance is within the operating zone. The signals
used are as follows:
QUADRAMHO Chapter 2
Page 41 of 74
A2 = V IR
right hand resistance line
B2 = IZ
A3 = IZ
left hand resistance line
B3 = V+IR
A4 = IZ
directional line
B4 = VPOL
Throughout, V is the faulty phase voltage, VPOL is the partially cross polarised
voltage described under polarising mixing circuits and IZ is the residually
compensated vector (IPhZPh + INZN) from the transphasors. The IR signal for the
resistance lines is derived from the phase current only, the absence of residual
compensation permitting good phase selection for single pole tripping purposes.
The method of producing a quadrilateral characteristic has several advantages
over other methods:
a) independent settings for reach and resistance coverage
b) relay characteristic angle can be set to line angle giving fastest operating speed
for solid faults and optimum control of reach accuracy
c) good operating speed over the whole of the characteristic as shown in
Figure 51.
5.6 Two-phase-to-ground faults (quadrilateral characteristic)
The operation of the quadrilateral characteristic during two phase to ground faults
presents special problems. This type of fault may be measured in three ways:
1) operation of the corresponding phase-phase element
2) operation of the leading ground fault element
3) operation of the lagging ground fault element
The operation of the phase-phase elements is practically independent of the fault
resistance to ground. However, the measurement of the ground fault elements
under these conditions, is affected by the resistance of the fault to ground.
The effect being that the leading phase-ground element will tend to overreach and
the lagging phase-ground element will tend to underreach. Arc resistance between
phases and to ground can also have the effect of making the leading phase-ground
element underreach and the lagging phase-ground element overreach. (See Figure
52).
The amount of overreach, or underreach depends on the arc and ground
resistances, the prefault load current and the type of polarisation used for the top
or reactance line. In Quadramho the polarisation of the Zone 1 reactance line is
optimised for single phase faults and a technique is employed to inhibit the
operation of the ground fault comparators for two phase to ground faults.
The phase fault comparators, with their partially cross polarised shaped
characteristics, are allowed to operate on two phase to ground faults.
The technique used to prevent operation of the quadrilateral ground fault
comparators is as follows:
The three Zone 1 ground fault comparators each have a corresponding guard
zone, of the characteristic shape of which comprises the same side and directional
lines as Zone 1. The top line of the guard zone has twice the reach of Zone 1
QUADRAMHO Chapter 2
Page 42 of 74
and has different polarisation (IPhR + INR). The guard zone is generated entirely
from inhibit comparators and so its operating speed is only a fraction of a cycle.
Due to the different polarisation employed for the reactance lines, under two phase
to ground fault conditions the reactance lines of the Zone 1 and corresponding
guard zone tilt with respect to each other (See Figure 52).
This action is used to advantage with the logic of Figure 53 to prevent operation of
the ground fault comparator. The ground fault comparators are allowed to operate
only if the corresponding guard zone, operates. For example, for the external
ABG fault condition depicted in Figure 52 which is 30% beyond Zone 1 reach
setting, it can be seen that the B phase Zone 1 reach line tilts such that the
measured BG impedance appears within the B phase Zone 1 ground fault
characteristic.
The measured BG impedance is also within the B phase guard zone
characteristic. This would cause the B phase Zone 1 ground fault element to
operate if it was not for the fact that the measured AG impedance appears within
the A phase guard zone characteristic. The operation of the A phase guard zone
in conjunction with the B phase guard zone ensures that all ground fault Zone 1
comparators are inhibited due to logic action as depicted in Figure 53.
The guard zone system allows correct Zone 1 operation on single phase faults,
since the phase selection properties of the guard zone comparators ensure that
only the faulty phase guard Zone comparators operate. The 2:1 ratio of the
guard zone reach/Zone 1 reach ensures that the resistive coverage of Zone 1 is
not seriously affected by any angular droop of the guard zone reactance line
under load exporting conditions, caused by its non-optimum polarising quantity for
single phase faults.
Overreach of Zones 2 and 3 under two phase to ground fault conditions is less
serious than overreach of Zone 1 and can be tolerated provided that grading
problems between time delayed Zone 2 and Zone 3 back up trips do not occur.
To avoid having to provide guard zones for Zones 2 and 3, the polarising signal
(IPhR + INR) for these two zones provides a compromise between single phase and
two phase to ground fault requirements. Any consequent errors are bounded by
the accuracy claims for Zones 2 and 3.
5.7 The offset quadrilateral
The offset quadrilateral characteristic of Zone 3 is produced in a similar way to
that of Zones 1 and 2, except that no directional line is involved and a further
main comparator is used for the reverse reach, having vectors:
A5 = IPhR + INR
B5 = V+IZ
This is shown in Figure 54.
The outputs of the Zone 3 forward main comparator and Zone 3 reverse main
comparator are ANDed to obtain the complete Zone 3 characteristic shape.
5.8 Level detectors
On de-energising a transmission line, line VTs can supply one input terminal of the
comparators with low frequency voltage waveforms, particularly if electro-magnetic
transformers are connected to the isolated line. To avoid the risk of false operation
of the relay comparators caused by the continuing presence of synchronous
polarising of the other input of the comparators, phase current level detectors are
QUADRAMHO Chapter 2
Page 43 of 74
provided. These have a very fast reset time and are connected so as to block
comparator operation when the line is de-energised, as shown in Figure 55.
The actual blocking operation is performed under software control in the scheme
logic module.
The principle of operation of the current level detectors is explained with the help
of Figure 56. If the instantaneous amplitude of the input voltage (VIN) exceeds a
threshold setting VREF either on a positive half cycle or on an inverted negative half
cycle, a timer t1 is started. If t1 finishes before the non-inverted or the inverted input
signal has fallen below VREF, the input sinewave is known to be greater than the
level detector setting and the output is set high.
At the same time as the output is set, a second timer t2 is started, whose purpose is
to bridge the time interval between the positive and negative half cycles. So While
t2 is running, the output cannot reset. When the level VREF is exceeded on the next
half cycle, the output is kept in the operated state. Only if the threshold level fails to
be exceeded on the next half cycle, is the output reset after t2 finishes. The output
also resets if the input signal becomes a unidirectional signal greater than VREF,
after both t1 and t2 have timed out. Positive feedback is applied from output to
input to give a reset/operate ratio of 0.90 to prevent chatter when the input signal
is at the pick-up level.
The current level detectors are designed to restrict the operative range of the relay,
preventing excessive sensitivity, although because they have a low setting (5% of
rated current at the relay reference setting), this restriction does not constitute any
practical disadvantage. Hence the maximum SIR for ground faults is 131 and for
phase faults is 228. The operating time of the level detector circuit is fast enough
not to limit the minimum operating time of the relay. The maximum reset time of the
level detector is less than the fastest practical comparator operating time.
The current level detector design is such that it can only operate on signals at
around the power system frequency, a characteristic which complements the
operating principle of the comparator. The level detector operation is little affected
by high levels of harmonic, low frequency and exponential contamination of the
power frequency input signal and therefore the input signals can be taken from
before the band pass filters. This eliminates the problems of stored energy slowing
the level detector reset times.
5.9 Inhibition of the comparator
With bus bar VTs, the comparator returns naturally to a restrained condition when
the circuit breaker is opened. However, when line VTs are used the relay must take
special measures to ensure the comparators reset when the line is de-energised.
In addition to the current level detectors, the relay contains voltage level detectors
operating on a similar principle, with a setting of approximately 70% of rated
voltage. If the transmission line is de-energised, the voltage and current level
detectors of the de-energised poles reset, a pole dead signal is produced and
after 20ms is supplied to the inhibit terminals of the relevant comparators as
shown in Figure 57. This terminal, when activated, causes the counter of the
comparator to register all changes of state of each input A and B as down counts.
The counters of any comparators which have operated, will be rapidly
decremented to zero when the transmission line is de-energised (See also
Figure 34). The implementation of the pole dead signals is performed by
software operations in the scheme logic module.
QUADRAMHO Chapter 2
Page 44 of 74
5.10 Single pole tripping

The level detectors are also beneficial when single pole tripping of the circuit
breakers is required when using line VTs. Following a single phase to ground fault
and a single pole trip, the output of the ground fault comparator is blocked by the
resetting of the relevant phase current level detector and the comparator is forced
to count down by the relevant pole dead signal. Thus the relay resets correctly
even though the presence of residual current due to load and the presence of
sound phase cross polarising, may appear as an impedance within the relay
characteristic.
5.11 Phase selection
A problem with full scheme distance relays is that heavy close-up single phase
faults can sometimes intrude into the operating characteristics of the phase fault
comparators, causing a three pole trip where a single pole trip would be
appropriate. In Quadramho a special neutral current level detector is used to block
the phase fault comparators to prevent this type of incorrect trip.
This neutral current detector, known as the high set (LDHSN), has a setting level
which is biased by the maximum amplitude of phase difference current flowing at
any time. The three signals IAIB. IBIC and ICIA are rectified by a precision three
phase full wave rectifier and a peak level formed by a fast charge slow discharge
smoothing circuit. A fixed proportion of this level is then used as the value VREF in a
level detector of the type previously described. See Figure 58.
In order to prevent chatter of the output and also to give the level detector a
minimum sensitivity under no load or very low load conditions, a fixed minimum
reference level is ORed with the variable reference.
For practical reasons, an upper limit to the reference level is used to ensure that
under very heavy fault current conditions the detector will operate correctly and not
be limited by internal power supply rails.
The signal input to the neutral detectors is derived by summing together the
individual phase current replica signals, in order to maintain the relay sensitivity
independent of residual compensation setting.
A similar low set neutral current detector (LDLSN) is used to enable the ground
fault comparators, thereby preventing wrong operation of a ground fault
comparator under heavy close up phase-phase fault conditions. See Figure 58.
The low set neutral detector is also used by the Voltage Transformer Supervision
feature since it has a high degree of immunity from operational unbalanced load
conditions.
Biasing the neutral current detector has distinct advantages. The detector can be
set sensitive enough to operate for all single phase faults which could cause phase
fault comparator maloperation, without any risk of the detector picking up on
neutral spill current during phase-phase faults. Neutral spill current arises from
mismatched current transformers, CT saturation, etc. The biasing also ensures that
the phase fault comparators are general]y enabled during two phase to ground
faults, permitting the relay to give its fastest possible three pole trip. For two phase
to ground faults with high resistance in the neutral, only the phase fault
comparators are enabled, avoiding possible measuring errors which ground fault
comparators can exhibit under these conditions. For conditions where the fault
resistance places the fault impedance just outside the ground fault comparator
characteristic, but with sufficient neutral spill current to still block the phase fault
QUADRAMHO Chapter 2
Page 45 of 74
comparators, a special logic feature is employed (See Figure 65) whereby if the
high set detector operates for 35ms without any Z1/Z2 ground fault comparator
operating, then the high set block of the phase fault comparator is removed.
5.12 Other level detectors
When the operating requirements of level detectors are not as stringent as for those
previously described, an alternative level detector design has been used which
offers lower cost. These level detectors are used in the VTs function and for the
Blocking scheme and permissive overreach scheme with weak infeed.
5.13 Power swing blocking
The power swing blocking (PSB) feature utilises two sets of phase-phase (AB)
connected comparators producing two concentric characteristics. One comparator
is the AB phase comparator of Zone 3 and the outer characteristic (Z6) is
produced by the other comparator whose reach settings of which are related to
those of Zone 3.
If the Zone 3 AB phase characteristic is the offset mho version then Z6 will also
be offset mho. if the Zone 3 AB phase characteristic is lenticular, then so will be
the Zone 6 characteristic. Also, for the lenticular version, the aspect ratios of Zone
3 and Zone 6 will be the same.
The action of the PSB is independent of Zones 1 and 2, provided that Zone 3 is set
to completely surround these zones. Three switches are provided on the scheme
logic module frontplate, so that blocking can be applied selectively to Zone 1
and/or Zone 2 and/or Zone 3, as required. A further switch, SW9, on the scheme
logic module, allows the PSB feature to be disabled if not required. With SW9 in
the left hand position, the PSB feature is disabled and with SW9 in the right hand
position, the PSB feature is enabled.
The Zone 6 forward reach is 1.3 times the Z3 forward reach and the Zone 6
reverse reach is equal to the Zone 3 reverse plus 0.3 times the Zone 3 forward
setting ie:
Z6F = 1.3 x Z3F
Z6' = Z3' + (0.3 x Z3F)
The equivalent hardware logic diagram of the PSB is shown in Figure 60.
This logic is implemented as software in the scheme logic microcomputer module.
Figure 59 also shows an example of how a power swing can pass through the
characteristics of the relay. The impedance of the power swing is detected initially
by Zone 6 and in the absence of any other comparator operating a 50ms timer is
started. When the 50ms timer expires a bistable is set. When the power swing
impedance then enters the Zone 3 characteristic the output bistable is set,
producing the signal PS which is used to inhibit Zone 1 and/or Zone 2 and/or
Zone 3 as required. Resetting of the Zone 3 comparator has not effect on the
inhibit signal produced by the logic, due to the action of the outpur bistable.
The power swing inhibit signal PS is only removed when the power swing
impedance passes outside the Zone 6 characteristic. This arrangement ensures that
the PSB cannot produce a blocking signal for fault conditions which appear inside
Zone 6 alone, or inside any Z1/Z2/Z3 comparator.
The power swing blocking in inhibited during the following conditions:
1) When the A or B poles of the circuit breaker are open. This ensures that the PSB
feature does not block tripping if the measurement of the PSB feature is affected
QUADRAMHO Chapter 2
Page 46 of 74
by the A or B phases of the transmission line being de-energised. This inhibition

is brought about by the action of the low set current level detector LDLSA and
LDLSB.
To extend this period of non operation to the first 240ms after the line is
re-energised, the ANY POLE DEAD signal is used. The pole dead A (PdA) and
pole dead B (PdB) signals also inhibit the Zone 6 AB comparator.
2) When a signal is received from the auto reclose unit via the inhibit power swing
blocking opto isolator, signifying that the distance relay has tripped, but the
circuit breaker has not yet reclosed, that is, dead time is in progress.
This inhibition of the PSB feature ensures that if a power swing develops during
the dead time of a single phase auto reclose cycle, the distance relay can give
an immediate three phase trip.
3) When the low set neutral current level detector LDLSN operates. This level
detector remains unoperated during balanced power swing conditions, but can
operate to prevent incorrect PSB operation under the following conditions:
i) if a ground fault occurs during a power swing.
ii) if a heavy ground fault occurs such that the impedance seen by the AB
comparators lies between the boundaries of Zone 6 and Zone 3.
iii) if a power swing develops during the dead time of a single phase auto
reclose cycle.
4) Under conditions of loss of a voltage supply, provided that the voltage
transformer supervision feature has been set to indicate and block the relay
(SW3 in right hand position).
Operation of the PSB feature is indicated by the relevant LED on the scheme logic
module and an output contact (951) is provided to give a remote alarm of a
power swing condition. The indication logic (see Section 6.41) latches the PSB
indication. This may be reset by operating the reset button on the scheme logic
module.
Two test points (SK PS and SK TPS) are provided on test socket SK2 of the auxiliary
relay module, to allow thorough testing of the Zone 6 comparator and the PSB
logic.
5.14 Current input circuits
A novel electro-magnetic coupling device known as the transphasor is used for
each current input circuit of Quadramho. This circuit produces the IZ vectors for
each phase and for the neutral, as required by the comparators and level
detectors.
The transphasor is based on the summation of two magnetic fluxes. One flux is
fixed phase and amplitude while the other flux is variable in both phase and
amplitude. The variable flux originates from the current flowing in a constant
inductance and variable resistance circuit, following a semicircular locus as the
resistance is changed from infinity to zero.
When the two fluxes are added, the total flux phasor also follows a semicircular
locus. If the magnitude of the fixed flux phasor is made equal to the radius of the
variable flux locus, the total flux phasor forms the radius of this new semicircle.
Hence the magnitude of the total flux remains constant as its phase angle is varied
over 180.
QUADRAMHO Chapter 2
Page 47 of 74
The circuit is shown in Figure 61. Two separate ferromagnetic cores are used,
each with an air gap to minimise the reluctance of the magnetic circuit. The flux
summation occurs on core 2. The constant flux originates from the current flowing
in primary 2. The function of the windings on core 1 is to provide an additional
current source to derive the variable flux. The output voltage of the device is taken
from a coil which senses the rate of change of flux on core 2.
There are two main advantages in using a transphasor instead of a conventional
transformer-reactor (transactor) input circuit:
a) The constant amplitude phase shifting allows the relay characteristic angle to be
varied without changing the relay reach setting.
b) The transphasor has a much shorter time constant than a transactor circuit. This
is extremely advantageous when the effect of a transient dc decrement in the
input current must be removed quickly from the output voltage so as to maintain
fast comparator operating times.
For relays with quadrilateral ground fault characteristics further current input
signals are required. Since these signals do not require phase shifting,
conventional current transformers are used.
5.15 Operation with saturated CTs
Quadramho incorporates circuits which permit smaller and more econonomical
line current transformers to be used in most applications, compared with other
distance relays. These circuits are:
1) The transphasor current input circuit (an electro-magnetic coupling device),
differentiates the current input waveform to produce the IZ vector. The effect of
saturation is much less on the zero crossings of IZ than on the average current
level.
2) The signal preconditioning filters reduce the distortion in the IZ signals caused
by saturation.
3) The comparator can tolerate some timing errors in one or more of its input
signals and still respond correctly.
5.16 Voltage transformer supervision (fuse failure)
5.16.1 Purpose
The Voltage Transformer Supervision (VTS) feature is used to detect failure of the ac
voltage supply. Such failure can occur by short circuit to ground, or open circuit, in
the voltage transformer itself, in the secondary wiring, in the fuses, or within the
distance relay circuits. The VTS gives visual and electrical alarms and can, if
required, be set to block any unwanted operation of the distance relay
comparators arising from the failure.
Use of miniature circuit breakers (mcb) instead of fuses can be accommodated by
using a normally open contact (mcb closed) to energise an opto coupler connected
to case terminals A1/A2. When the mcb opens removing all three phases of the
VT supply the following events occur:
i) a 15ms delay in drop off of the zero sequence voltage level detector ensures
sufficient time for the opto coupler mcb to pick up and take over the blocking of
the relay from the VTS circuitry.
ii) the relay inoperative alarm contact 97Y1 operates and the green relay
available LED is extinguished.
QUADRAMHO Chapter 2
Page 48 of 74
iii) the indication LED operates and latches.

iv) the alarm contact 97X1 closes.
v) the comparators are held reset and blocked.
vi on the permissive overreach scheme the weak infeed echo feature is blocked.
vii) the switch on to fault is blocked.
5.16.2 Principle
The VTS feature operates by detecting the zero phase sequence voltage (V0)
arising from failure of the voltage supply. The VTS is stopped from operating on
ground faults on the transmission line (which also gives rise to V0) by a circuit
which detects zero phase sequence current. Zero phase sequence current is only
caused by line faults.
5.16.3 Outputs
The VTS provides visual indication by the V~FAIL LED on the scheme logic module
and remote alarm via the auxiliary relay contact 97X1. If the VTS is required to
block the tripping action of the relay, switch SW3 on the scheme logic module
must be set to the right hand position. Since the distance relay cannot perform
correctly if the voltage supply is faulty, the green Relay Available LED is
extinguished and the Relay Inoperative alarm contact 97Y1 closes if VTS is set
to block the relay. The following descriptions assume that SW3 is set to the right
hand position, unless otherwise stated.
5.16.4 Level detector settings
The zero phase sequence voltage level detector settings must be above the
maximum level of V0 possible in a healthy three phase voltage supply (10% Vn)
and below the mimimum amount of V0 produced when there is an open circuit or
short circuit in the voltage supply (33% Vn). A level of V0 = 15% Vn has been
chosen as the setting.
The zero phase sequence current level detector is the low set neutral current unit.
This level detector LDLSN has a self compensating setting which adjusts to the
amount of phase-phase current flowing in the line and therefore cannot be picked
up by unbalance in load current (see Section 5.8). This is the same level detector
which is used for checking ground fault comparator operation, so there is no
degradation in distance relay sensitivity when the feature is used for blocking
comparator operation.
5.16.5 Speed of operation
The circuit is required to respond to loss of voltage faster than the relay
comparators, in order that maltrips can be blocked. The V0 detector therefore has
to be reasonably fast in operation. However, for ground faults of the transmission
line, the I0 detector has to store the comparators from producing an output (which
would delay tripping) and so the I0 detector (LDLSN) must be quicker than the V0
detector.
5.16.6 Implementation
The feature is contained in the scheme logic module, with the exception of the
output relay circuits and the current level detectors. The level detectors are
implemented as hardware circuits. The rest of the logic, described in the following
sections, is effected by software in the microprocessor scheme logic.
The block diagram, Figure 63, is drawn as a logic equivalent circuit.
QUADRAMHO Chapter 2
Page 49 of 74
5.16.7 Output seal-in

If a failure of the voltage supply occurs, the VTS instantaneously blocks the distance
relay from tripping. It is necessary to seal in the blocking action, since otherwise if
a ground fault were to occur on the transmission line later, the I0 would reset the
VTS. A 5.5s delay is provided before sealing in the blocking action, so that the
VTS can tolerate temporary voltage failures without permanently blocking the
distance relay. An example of a temporary failure is a momentary short circuit on
the voltage supply. A failure which lasts for over 5.5s is deemed to be permanent
and in the case of a short circuit, usually results in a fuse blocking. The visual
indication and electrical alarms are only given after the 5.5s has elapsed, so that
an alarm is only given for permanent failures.
5.16.8 Operation for indication and alarm only
If switch SW3 is set to the left hand position, so that the VTS can only indicate and
give an alarm, a failure of the voltage supply may cause this distance relay to trip
immediately. The ac supply would then be removed and the V0 level detector reset
before the 5.5s had elapsed.
A means of accelerating the indication and alarm is therefore provided which only
operates if a comparator operates when the VTS detects a voltage supply failure.
This is shown on the block diagram. It can be seen that there is a 20ms delay
before the accelerated indication is allowed. this prevents any possibility of a
transient pulse from the detection circuits causing incorrect alarms.
Such pulses (typically up to 23ms) can sometimes occur for transmission line faults
under conditions where the I0 level detector is slowed and also when faults are
cleared by opening the circuit breaker, when there is a race between resetting of
the I0 and V0 and low set current level detectors.
5.16.9 Resetting
The equivalent of bistable circuits are used to seal in the block and indication/
alarm outputs of the VTS. It is necessary to visit the relay room and press the RESET
pushbutton on the relay to reset the bistables. This can conveniently be done at the
same time as repairing the voltage supply failure and/or replacing the faulty fuse.
If the RESET pushbutton is pressed while the voltage supply is still faulty and the
line energised, the comparators remain blocked and the indication/alarm output
will be retained.
5.16.10 Line de-energisation (line VTs)
After all three poles of the circuit breaker have been opened, there may be
sufficient unbalance in any induced voltage from an adjacent line to cause the V0
detector to operate. The line may remain in a de-energised state for longer than
5.5s and so a circuit is provided to prevent the block and indication/alarm outputs
from sealing in.
The circuit is shown in the block diagram and uses the ALL POLES DEAD signal,
derived from the current and voltage level detectors or BREAKER OPEN opto to
block the input to the 5.5s timer.
If the pole scatter on opening of the breakers is sufficiently spread, transient
operation of the V0 detector may occur. To prevent this bringing up an indication
via the logic, a latch is provided which ensures that the indication can only pass to
the output latch provided that the V0 detector operated before the comparators
picked up.
QUADRAMHO Chapter 2
Page 50 of 74
5.16.11 Busbar voltage transformers

When the relay is supplied from a busbar VT there is no loss of ac voltage when
the circuit breaker is opened. However, there may be a transient depression of the
voltage on reclosing the breaker, caused by line charging current, magnetising
inrush, etc. Energisation of the BREAKER OPEN opto isolator is therefore
arranged to inhibit the instantaneous output of the VTS (via the ANY POLE DEAD
logic).
5.16.12 Single-pole tripping
An additional feature is provided for power systems with single pole tripping of
single phase to ground faults. When a single pole of a transmission line is de-
energised, the unbalance in the voltage is likely to cause the V0 detector to
operate. The single pole dead condition will not last for as long as 5.5s, so there is
no need to stop the time delayed output from the VTS. However, the instantaneous
output must be stopped, otherwise the relay comparators would not be able to trip
if a phase-phase fault were to occur on the remaining live phases, since a phase-
phase fault does not cause any I0 to reset the VTS.
The instantaneous output is stopped by an ANY POLE DEAD signal obtained
from the three POLE DEAD signals (or BREAKER OPEN OPTO if connected).
A 240ms delay on drop off of this ANY POLE DEAD inhibition is provided
because line charging transients and CVT transients may cause the V0 detector to
remain operated for a short time after breaker reclosure.
A side effect is that if a single phase of the voltage supply fails at a time when
there is insufficient line current to operate the low set current detector of that phase,
an ANY POLE DEAD signal is produced. The instantaneous blocking output is
then inhibited, though the time delayed sealed-in output is still produced after 5.5s.
This is not a practical disadvantage, since no comparator maloperation can occur
if the low set phase current detector has not operated.
5.16.13 Switch on to fault
If the transmission line is energised with one or two VT fuses missing, the
subsequent action depends on the load current flowing in the line. If the load
current is high enough to pick up one or more low set phase current detectors
within the first 240ms of the line being live, a switch-on-to-fault trip results.
However, if none of the low set phase current detectors operates in this time, the
VTS blocks the relay from tripping and seals-in and gives alarm and indication
after 5.5s.
If the transmission line is energised with all three fuses missing, the switch-on-to-fault
feature remains enabled until the load current is high enough for one or more low
set current detectors to operate, whereupon a switch on to fault trip is produced.
When the relay is used with miniature circuit breakers the switch-on-to-fault circuit is
blocked when the mbc is open.
5.16.14 Weak infeed (POR scheme option) during fuse failure conditions
For a weak infeed fault condition, the VTS can also operate and hence the
instantaneous output cannot be used to inhibit weak infeed logic. However, for true
fuse failure conditions the output from the time delayed (5.5s) signal can be used
for inhibiting weak infeed operation.
The opening of the miniature circuit breaker will block operation of the weak
infeed circuit.
QUADRAMHO Chapter 2
Page 51 of 74
5.16.15 Scheme logic module

A general description of the scheme logic module is given in Section 4.9 and
Figure 23, shows the module in block diagram form including the associated
inputs and outputs. The general arrangement shown in Figure 23, is common to all
Quadramho relays and includes a common standard software program which
performs many functions of the distance relay such as control functions, scheme
operation and output relay control.
5.16.16 Level detector pole dead logic
The level detector pole dead logic is used to inhibit the relay comparators during
pole dead conditions (See Section 5.9) and is also utilised for other features, such
as, PSB, SOTF, weak infeed feature, band pass filter switcher, etc. Figure 64,
provides a logic equivalent of the software implementation of the pole dead logic.
5.16.17 Comparator level detector checks
As mentioned in Section 5.8, phase current level detectors are used to prevent
spurious operation of the comparator during line de-energisation. Figure 65,
Appendix A, gives the logic equivalent of this feature for each zone.
5.16.18 Voltage bandpass filter switching
Figure 66 gives the logic equivalent function. The inhibit comparator pulse of
0.15ms is used to negate any spurious edges which may occur at the instant of
switching from low pass filters to band pass filters.
5.16.19 Control of hysteresis in impedance measurement
The threshold of operation of the comparator described in Section 5.1 occurs when
the two input signals A and B are in phase or 180 out of phase. This is true
irrespective of the conditions immediately before crossing the threshold of
operation, that is, whether A was formerly lagging B (comparator operated) or
leading B (comparator reset). The inherent reset/operate ratio of impedance
measurement of the mho comparator is therefore unity.
In the practical distance relay a reset ratio of unity would give rise to discontinuous
operation of the comparator for faults on the boundary of operation in the
presence of random noise in the comparator input signals (random noise includes
high freqency components caused by clocking the input signals at discrete
intervals. A reset ratio greater than unity is therefore necessary. Too high a reset
ratio, on the other hand, is undesirable because with large reach settings
(particularly of Zone 3) the encroachment of load impedance may prevent the
comparator resetting after a fault is cleared.
In Quadramho circuits are provided to give the relay a reset ratio of nominally
105%, measured on the relay characteristic angle. Two separate controls are
involved:
1) Amplitude hysteresis, controlled by a single logic signal from the scheme logic
which is produced when the relay trips. This decreases the gain of the voltage
input module by 5%, thereby increasing the relay reach (See Section 4.2).
2) Angular hysteresis, provided to control the impedance reset ratio for highly
resistive faults on the Zone 1 or Zone 2 mho boundary under conditions of low
infeed to the fault. Under these conditions the shaped mho characteristic is
expanded in the resistive direction and decreasing the size of V has little
additional effect. Angular hysteresis is controlled by the scheme logic when a
trip occurs, resulting in the synchronous polarising signal being advanced by
QUADRAMHO Chapter 2
Page 52 of 74
approximately 6. This action expands the right hand portion of the mho polar
characteristic without affecting the reach at the characteristic angle.
5.16.20 Self testing
Periodic self testing of all relay comparators is done automatically every 2 weeks
or on demand, by pressing and releasing the pushbutton on the front of the relay.
In the event of a comparator failure, diagnostic information is stored in the relay
and may be read by a test option facility (See Section 4.9.46) to simplify fault
finding. In order for a self check to be performed, all voltage level detectors must
be operated (ie. picked up) to ensure that the comparators are receiving signals on
their inputs. The microcontroller first issues a reset pulse and then a signal (SC)
instructing the comparators to ignore their inhibit inputs (See Section 5.1 and
Figure 34).
A short time later (40ms) the microcontroller reads the comparator outputs and
stores this information. The microcontroller then issues a further signal (MRI) which
in conjunction with the previous signal (SC) forces the comparators to reverse their
state (i.e. those in restrain move to operate, and those operated move to restrain).
A short time later (40ms) the microcontroller again reads the status of the
comparator outputs and this information is Exclusive ORed with the previous
state of the comparator, to ensure that all comparators can operate and are not
operated for both conditions. Should any comparator output not meet these
requirements it is considered to be faulty. If a faulty comparator is detected, then
the Relay Available LED is extinguished and an alarm given by closing the
Relay Inoperative contact. The self check routine takes approximately 85ms.
Once the self check routine has been completed the SC signal is removed just
before the MRI signal. This has the effect of resetting all comparators before the
relay is returned to normal operation. The SC signal is also used to change the
polarising of the quadrilateral ground fault comparators to a signal which only
requires voltages (as described in Section 4.4) since there may not be sufficient
current to correctly polarise the quadrilateral ground fault comparators.
The self testing feature is selectable by means of switch SW5 set to the right to
enable and set to the left to disable self checking.
5.16.21 Operation of standard schemes and input/output interfaces
The arrangement of the auxiliary relay trip outputs differs slightly depending on
whether the relay is to be used in a single- and three-pole tripping mode, or in a
three-pole only tripping mode. The standard external connection diagram for the
former case is given by Figure 67, Appendix A.
In addition to the standard schemes, special scheme logic software may be
designed to meet the requirements of individual customers. The functions of the
relay input and output interfaces may differ if these special schemes are in use and
the standard diagrams then no longer apply. Details of special schemes will be
given as an appendix to this manual, if applicable.
5.16.22 Standard scheme options
Five standard scheme options are offered by the scheme logic of Quadramho.
The options are based on a permissive underreaching scheme (PUR), a permissive
overreaching scheme (POR), a blocking scheme (BLOCK) and a Zone 1 extension
scheme (Z1EXT). A basic scheme (BASIC) controlling the normal Zone 1, time
delayed Zone 2 and Zone 3 and SOTF action, is common to all options and may
also be selected as a scheme in its own right. A choice of single phase tripping for
QUADRAMHO Chapter 2
Page 53 of 74
single phase to ground faults, with 3 phase tripping for other faults, or 3 phase
tripping for all faults is also provided.
To set up the relay for a particular scheme option requires the correct code
selection number (CSN) to be set on the code switches, which are positioned on
the frontplate of the scheme logic module. Details are given in Table 8.
CSN Scheme Comments
(XY)
00 BASIC with single phase/3 phase tripping Provides basic
Zone 1
Z2t, Z3t and
SOTF action
01 BASIC with 3 phase tripping only Basic action as per 00
02 PUR with single phase/3 phase tripping Includes basic
action
03 PUR with 3 phase tripping only
04 POR with single phase/3 phase tripping
05 POR with 3 phase tripping only
06 BLOCK with single phase/3 phase tripping Includes basic action
07 BLOCK with 3 phase tripping only
08 Z1EXT with single phase/3 phase tripping
09 Z1EXT with 3 phase tripping only
Table 8: The standard scheme options
The first digit of the CSN is the left switch labelled X on the relay nameplate,
while the second digit is the switch labelled Y. The range of code selection
numbers available for scheme options is in the range 00 to 39. Positions 40 to 99
are for test options (see Sections 6.42 and 4.54). If a CSN is selected in the range
00 to 39 which does not have a scheme allocated to it, the Relay Available LED
is extinguished and the output contact Relay Inoperative (97Y1) closes.
5.16.23 Basic scheme
This scheme controls the normal Zone 1 action, the Zone 2 and Zone 3 time
delayed trip action and the SOTF trip action. The time delays associated with Zone
2 faults (Z2t) and those for Zone 3 faults (Z3t) are set by switches on the frontplate
of the scheme logic module.
5.16.24 Permissive underreaching scheme (PUR)
The underreaching directional Zone 1 elements are used to initiate tripping and to
send a signal (85X1 and 85X2) to the remote end of the transmission feeder.
Operation of the overreaching Zone 2 elements plus receipt of the channel signal
(via opto isolator input CRX), gives an accelerated trip for faults occurring in the
end zones of the protected feeder. Once issued, the aided trip is only removed
when the Zone 2 elements reset. This is to allow time for breaker failure protection
operation in the event of a local breaker failure for a fault near the remote end of
the line. A delay on reset of the signal received (CRX), is needed to ensure that the
relays at both ends of a single end, fed faulted line of a parallel feeder circuit have
time to trip when the fault is close up at one end. A preset 100ms is used for this
delay. Figure 68 gives the equivalent logic diagram.
QUADRAMHO Chapter 2
Page 54 of 74
5.16.25 Permissive overreaching scheme (POR)

The overreaching directional Zone 2 elements are used to send a signal (85X1
and 85X2) to the remote end of the feeder. The Zone 2 elements permit tripping
on receipt of a channel signal (via opto isolator input CRX) and in this way,
instantaneous tripping via the Zone 2 elements will only occur for internal faults.
A duplex (two frequency) channel is essential for this scheme. The trip is sealed-in
until the Zone 2 elements reset.
There is also a requirement with the overreaching scheme for a current reversal
guard feature to prevent inadvertent tripping of the circuit breaker associated with
the healthy line of a faulted parallel feeder circuit. Such a feature (tp and td) forms
part of the Quadramho scheme logic action. Should this feature not be required it
is easily disabled (set td = 0).
A further feature is provided which enables fast tripping to be maintained along
the whole length of the protected line, even when one terminal is open. This is the
ECHO feature and it is initiated 60ms after the Breaker Open opto isolator has
been energised. The 60ms time delay is provided to ensure that the received signal
is not echoed back for busbar faults. However, there will be no time delay
introduced in echoing the signal when the breaker is already open. Figure 69,
Appendix A, gives an equivalent logic diagram.
5.16.26 Weak infeed feature (POR scheme only)
When one end of the line is connected to a weak infeed terminal, the distance
measuring elements at the weak infeed end cannot operate and consequently the
operation of the scheme is affected.
In the permissive overreach scheme, the relay at the strong infeed end terminal
would not be able to operate instantaneously, in the absence of a channel signal
from the weak infeed end terminal. Also the weak infeed end fails to trip during
such conditions. However, with certain additional scheme logic, it is possible to
achieve rapid tripping of both ends for faults anywhere within the line, even during
weak infeed conditions of one terminal (see Figure 70). SW8 is provided to
enable the weak infeed feature, if required. With SW8 in the left hand position
the weak infeed feature is disabled and in the right hand position it is enabled,
provided that the scheme chosen is the permissive overreach scheme (CSN 04 or
05).
The Zone 3 measuring elements at the weak infeed terminal are set to look in the
reverse direction to cover the reach of the Zone 2 elements from the strong infeed
end.
The weak infeed condition is detected by the receipt of a channel signal and the
failure of operation of Zone 3 measuring elements. For an external fault, behind
the weak infeed terminal, when the fault infeed is from the strong infeed terminal
source, the reverse looking Zone 3 would operate and block the operation of weak
infeed circuit. However, for an internal fault, the distance measuring elements at
the weak infeed terminal do not operate, thus enabling the weak infeed circuit.
When a channel signal is received by the relay at the weak infeed end, 10ms and
60ms timers are energised, provided that:
i) there has been no operation of any distance measuring units.
ii) the breaker is closed.
iii) the alarm has not operated.
QUADRAMHO Chapter 2
Page 55 of 74
After the 10ms time delay, a signal is sent, provided that at least one of the voltage
level detectors has reset, which confirms a fault condition.
Since a fast time of 10ms is not desirable for tripping of the local end, a time delay
of 60ms is selected for local tripping and after this delay the trip relay is
energised, after ensuring that at least one of the voltage level detectors has reset.
Aided Trip LED indication is also energised.
For a fault near the remote end (strong infeed), the relay at that end may reset
within 60ms (for a fast breaker operation and relay reset) and signal receive at the
weak infeed terminal may reset before the 60ms time delay of the weak infeed trip
is elapsed and the weak infeed trip may not be achieved. To ensure tripping at the
weak infeed end, a time delay on reset of 100ms is provided on Signal Receive.
The weak infeed feature is provided as a standard arrangement with the
permissive overreach scheme, so the weak infeed features, when selected, should
not cause maloperation/malflagging during normal operation of the distance relay
(ie. single phase trip by distance, followed by a three phase trip by weak infeed
with Aided Trip indication).
If the distance relays operate normally at both ends, the signal receive signal will
still be available even after the relay reset subsequent to fault clearance, due to
delay in the reset of the channel signal. This condition can operate the weak infeed
circuit, causing weak infeed trip and Signal Send, unless further action is taken.
To prevent this, a latch circuit is provided to inhibit the weak infeed feature, if any
of the Zone 1/Zone 2 distance elements operate and trip the breaker. Before the
channel signal is received from the other end, the comparators may reset after a
fault clearance, and hence a time delay on drop off of 100ms is provided in the
Zone1/Zone 2 inhibit circuit. The latch resets only after the channel signal resets.
When high source impedances are present, there is the possibility of inadvertent
operation of the weak feed circuit for external faults due to the reverse looking
Zone 3 elements failing to operate to generate the required inhibit signal.
To safeguard against this problem, high set current level detectors of the same
phase as any Zone 2 element must have also operated before the channel signal is
sent to the other end.
A high set current level detector is included in the signal send circuit of the
permissive overreach scheme only when weak infeed is selected by the switch
SW8, (see Figure 69). Since this feature is required at the strong infeed terminal,
the weak infeed feature has to be selected at both ends when required.
When a single/three phase auto reclose is provided at the strong infeed terminal,
tripping at the weak infeed end may not be desirable, since this provides only 3
phase trips. SW7 is therefore provided to disable the weak infeed trip, but still
provide the weak infeed echo facility to maintain fast clearances at the strong
infeed end.
5.16.27 Blocking scheme with reverse looking Zone 3 elements (BLOCK)
The directional Zone 2 units are required to trip the circuit breakers, provided a
blocking signal (opto isolator input CRX) has not been received from the remote
end of the feeder, indicating that the fault is beyond the remote busbars.
The reverse looking Zone 3 elements are required to send the blocking signal
(85X1 and 85X2) for all external faults. However, since the Zone 3 relay will
normally have a certain degree of offset, a blocking signal could be sent for some
internal faults. The directional forward-looking Zone 2 relays are thus used to
cancel the blocking signal for these circumstances.
QUADRAMHO Chapter 2
Page 56 of 74
In practice a time delay on pick up for the tripping signal is required for faults
detected by the Zone 2 elements. This is to allow time for a blocking signal to be
sent from the remote end, should it prove necessary, and to be received at the
local end. Such a pick up timer is provided by Quadramho scheme logic and is
user adjustable by the positions of 4 switches (tp) selected on the frontplate of the
scheme logic module. A range of 090ms in 6ms steps may be set for tp.
A delay on drop-off for the signal received (CRX) is also provided in the blocking
scheme, to safeguard against inadvertent tripping out of the healthy section of a
faulted double circuit line, during a possible reversing current situation.
This timer is also user adjustable by means of 4 switches (td) on the frontplate of
the scheme logic module, to give a range of 090ms in 6ms steps. Figure 71 gives
the equivalent logic diagram of the blocking scheme.
When very high source impedances are present, there is the possibility of
inadvertent tripping occurring for external faults due to the reverse Zone 3
elements failing to operate to generate the required blocking signal. To safeguard
against this problem, high set current level detectors (LDHS) of the same phase as
any Zone 2 element must also have picked up before an accelerated aided trip
action can be initiated.
5.16.28 Zone 1 extension scheme (Z1EXT)
This scheme does not require a signalling channel.
The Zone 1 relays are normally in the Zone 1 extend mode and are reset to the
Zone 1 reach when the circuit breakers have tripped and are about to be reclosed
by auto-reclose action. The signal to reset from the extended Zone 1 to the normal
Zone 1 is generated by the auto-reclose equipment, via the opto isolator input
RZ1X (reset Z1X).
The scheme provides fast clearance of most faults. On the basis that most overhead
line faults are transient in duration, the scheme will allow fast clearance of most
faults along the protected section and also those just out of the section. Lack of
discrimination does not matter as auto-reclosure of the protected section circuit
breaker(s) will take place. The operation of the auto-reclose relay is used to reset
the extension facility so that if the fault is permanent, upon reclosure the faulted
section of line will be cleared permanently by its own protection, as in the basic
scheme. Refer to application notes.
5.16.29 Opto-isolator inputs to scheme logic
Five opto isolators are provided in Quadramho. These allow the scheme logic to
access information from external equipment and take appropriate action, as
described below:
a) Breaker open opto isolator.
This is used primarily where the relay is supplied via busbar voltage
transformers and therefore the internal relay pole dead detection circuits are
inoperative (See Figure 64). It is energised from a contact on the circuit
breakers, which is closed when all poles of the breaker are open. The Breaker
Open opto is used to:
i) enable the switch-on-to-fault feature (via pole dead logic).
ii) enable the echo feature of the permissive overreach scheme.
QUADRAMHO Chapter 2
Page 57 of 74
iii) prevent the power swing blocking logic (via the pole dead logic) from
operating during the first 240ms immediately following line energisation,
when it is undesirable to prevent tripping.
b) Signal receive opto isolator.
This is energised from the signalling channel and is only effective if a signalling
scheme has been selected. In the permissive underreach and permissive
overreach schemes, receipt of a signal via the opto isolator permits Zone 2
elements to trip instantaneously, without waiting for the Zone 2 time delay
(See Figure 68 and 69, Appendix A). If the scheme selected is the blocking
scheme, then receipt of the signal via the opto isolator prevents the Zone 2 units
from issuing an instantaneous trip (See Figure 71).
This opto doubles up as Reset Zone 1 extension on some versions of the relay
suitable for use with miniature circuit breakers (mcb).
c) Channel in service opto-isolator
This input is energised when the signalling channel is in service. The absence of
the signal will force the blocking scheme to revert to the basic 3 step distance
scheme. If switch SW6 on the front of the scheme logic module is set to the right
hand position, then loss of the channel-in-service signal will cause the block auto
reclose output contact (961) to close (provided that scheme selected is a signal
aided scheme) (See Figure 73). A further feature is that absence of the channel
in service signal will force all trips in signal aided schemes to be 3 phase trips
only (See Figure 72).
d) Reset Zone 1 extension opto-isolator
This is energised from the auto reclose relay during the dead time and reclaim
time. The effect of energising this input is apparent only for the Zone 1
extension scheme, whereupon the reach of the Zone 1 measuring elements
reverts back to normal Zone 1 reach, otherwise they have extended Zone 1
reach.
When a version of the relay is supplied for use with miniature circuit breakers
(mcb) instead of VT fuses, this opto is used for this purpose. The signal receive
opto doubles up as Reset Z1 extension on some versions of the relay.
When used with mcbs this opto is energised via a normally open contact on the
mcb (mcb closed) to ensure correct blocking of the protection when the mcb
operates If there is not a normally open contact available on the mcb (mcb
closed) an interposing relay is required. This must operate in less than 10ms to
ensure correct operation of the relay.
e) Inhibit power swing blocking opto-isolator.
This is energised by the auto reclose relay during single pole auto reclosure
conditions and its action is to prevent operation of the power swing blocking
feature during such conditions (see Figure 60).
5.16.30 Scheme logic control of auxiliary relay outputs
All output contacts from the relay have fleeting closure which lasts for
approximately the duration of the line fault, with the exception of the voltage
transformer supervision contact (97X1) and the relay inoperative alarm contact
(97Y1) both of which are sealed in.
QUADRAMHO Chapter 2
Page 58 of 74
Operation of the voltage transformer supervision contact (97X1) and the power
swing alarm contact (951) are described under the appropriate descriptions of
these features.
5.16.31 Trip A, Trip B and Trip C contacts
94A1 94A2 94B1 94B2 94C1 94C2
These contacts are used to initiate single pole tripping of the breaker for single
phase-to-ground faults in Zone 1 or carrier aided Zone 2. Single pole trips can
only be obtained with even numbered scheme options (code selection numbers
X and Y). For all other types of fault, and with odd numbered scheme options, all
these contacts close simultaneously with the three phase tripping contacts 94T1
and 94T2. This also occurs if the channel-in-service opto isolator is not energised
and a signal aided scheme has been selected. The trip contacts are latched in for
a minimum of 60ms, and if a 3 phase trip has been issued, it will be maintained
until all trip signals to the trip output logic have been removed. The trip output logic
is implemented as software in the scheme logic microcomputer (see Figure 72).
The single pole tripping contacts can also be used for initiating auto-reclose and
starting the breaker fail protection. In some cases it may be necessary to provide
external repeat relays if multiple, clean contacts are needed.
5.16.32 Trip three phase contacts 94T1 and 94T2
These contacts are used for initiating three pole tripping of the circuit breaker,
initiating three pole auto-reclose and starting the breaker fail protection. If it is
intended only to use odd numbered scheme options, then six other repeat contacts
are available.
5.16.33 Any trip contacts 941 and 942
These contacts close for any trip signal (single or three pole) produced by the relay
and as such, are particularly useful for checking the relay reach, operating time,
etc, during commissioning and routine testing. In order to realise its usefulness
more fully, the contact 9401 has been routed through the heavy current plug
contacts 1Z71Z8, in order that it may be accessed from the front of the relay
whilst secondary injecting during commissioning tests, etc. (See Figure 67).
5.16.34 Block auto reclose contacts 961
The following conditions will cause the block auto-reclose contact (961) to be
closed by the scheme logic:
a) Any Zone 2 time delayed trip.
b) Any Zone 3 time delayed trip.
c) Any switch on to fault trip.
d) Signalling channel not in service (CIS opto isolator not energised) if switch SW6
is set to right hand position and scheme selected is a signal aided scheme.
e) A 3 phase (Zone 1/signal aided trip) fault occurs and switch SW4 is in the
right hand position.
The block auto-reclose logic, Figure 73, is implemented as software in the scheme
logic microcomputer.
The contact is kept closed for a further 100ms after all block auto-reclose
conditions have been removed. This represents a delay in drop off for contact
961.
QUADRAMHO Chapter 2
Page 59 of 74
5.16.35 Fault locator start contacts 19A1, 19B1, 19C1 and 19E1
These contacts are provided for data logging functions such as phase selection,
starting of fault locators, fault recorders, etc. Two or more contracts close for a fault
condition, eg:
AGround fault 19A1 and 19E1
AB Ground 19A1 and 19B1
AB Ground fault 19A1 and 19B1 and 19E1
ABC fault 19A1 and 19B1 and 19C1
If a fault is detected by Zone 1 comparators, the phase information of Zone 1
takes precedence over phase information from Zone 2. This action ensures that the
closest forward fault condition detected during any simultaneous fault situation is
used for phase selection purposes. The smaller distance relay zones also offer the
best phase discrimination.
Figure 74, shows the diagram of the fault locator logic which is implemented by
software in the scheme logic microcomputer. It also shows that is a switch-on-to-
fault trip occurs due to current and no volts (SW1 to right) then the fault locator
logic uses the appropriate current and no volts information to select the fault
locator phases.
5.16.36 Zone 2 trip contacts Z21
This contact closes for any Zone 2 time delayed trip and may be used for data
logging purposes.
5.16.37 Zone 3 trip contact Z31
This contact closes for any Zone 3 time delayed trip and may be used for data
logging purposes.
5.16.38 Aided trip contact 94Y1
Any aided trip action occurring for faults when in the permissive underreach,
permissive overreach or blocking schemes, is announced by the closure of this
contact.
5.16.39 Switch on to fault contact 981
A common type of fault is a close-up fault occurring on energising the line, caused
by inadvertently leaving grounding clamps on the line after maintenance work.
If line VTs are used and if the clamps are on all 3 phases, then the Zone 1 units
would fail to detect the fault. This shortcoming is due to the lack of cross polarising
and synchronous polarising signals for the Zone 1 comparators under these
conditions. The switch-on-to-fault logic (SOTF) allows other fault detectors within the
relay to trip the circuit breakers instantaneously, eliminating the dependency on
Zone 1. Should a fault be detected during SOTF conditions then the relay sends a
signal to block auto-reclosure of the circuit breakers (see Figure 73).
Two types of fault detectors are capable of detecting 3 phase zero voltage faults.
The first type is the Zone 3 comparators which can operate without voltage, owing
to their offset characteristics: however, to allow for non standard relay
characteristics, the logic is arranged so that all comparators can be used as fault
detectors in the SOTF logic. The second type uses the voltage level detectors and
low set phase current level detectors, a fault being detected if any current level
detector operates without operation of the corresponding voltage level detector.
To allow for the circuit breaker poles not all closing together, the current and no
volts condition (CNV) has to last for more than 20ms (see Figure 75).
QUADRAMHO Chapter 2
Page 60 of 74
Switch SW1 on the scheme logic module is used to select which of the two types of
fault detectors is used.
The normal setting is with SW1 in the left hand position which selects SOTF action
via the comparators, since this produces the faster tripping times when busbar VTs
are employed. However, when energising a line with a transformer and when a
large Zone 3 setting is required, there is a risk of transient operation of the Zone 3
comparators due to the magnetising inrush current of the transformer. Under these
conditions it is preferable to set SW1 to the right hand position, with SOTF action
via the level detectors.
The SOTF feature is enabled a short time after all three poles of the transmission
line are de-energised, as detected by the pole dead logic (see Figure 64),
signals from the level detectors. This time can be either 200ms (SW2 in right hand
position) or 110s (SW2 in left hand position). The normal setting is 200ms, since
this is long enough to prevent inadvertent operation of the SOTF feature during
transient dips in the ac voltage supply, but shorter than the shortest dead time of
the transmission line.
With an enable time of 200ms the SOTF feature has the additional advantage of
giving a fast trip when the breaker closes all 3 poles on to a fault near the far end
of the line (ie. beyond Zone 1 reach) with the breaker open at the far end. Without
this feature, only a delayed Zone 2 trip would normally be produced.
However, if the blocking scheme has been selected, circumstances are different.
If the breaker is closed on to a fault near the far end of the line, with the breaker
open at the far end, a fast aided trip is initiated by the Zone 2 comparators. Since
the SOTF is redundant under these conditions, it can be effectively disabled by
selecting the 110s time (SW2 to left-hand position). This time is greater than the
longest auto-reclose dead time and smaller than the line outage time required to fit
grounding clamps to the line. By disabling the SOTF feature for this period,
confusing indications can be avoided, while still retaining SOTF tripping for
closing on to grounded lines.
Once the SOTF feature has been enabled, it remains so for 240ms after the line
has been re-energised, or until a SOTF trip has been cleared. This period is long
enough for the synchronous polarising to be etablished if the line is healthy.
However, if a fault is present, 240ms is ample time for the fault to be detected.
While the SOTF feature is enabled the basic distance scheme trips and the carrier
aided scheme trips are disabled (but not the weak infeed feature of the permissive
overreach scheme).
When a fault is detected during the SOTF enable time, the SOTF logic outputs do
not reset until the fault is cleared.
If a SOTF trip occurs, the SOTF LED is illuminated and the auxiliary relay contact
981 closes. Also, a test point is provided on socket SK2 which enables
verification of the SOTF timers and logic, for commissioning and maintenance
purposes.
When busbar voltage transformers are used to supply the relay, the Zone 1 units
operate normally if the breaker is closed on to a bolted-on close-up three phase
fault and hence the SOTF feature is not needed for tripping. However, the SOTF
logic is still useful for blocking auto-reclose, for giving visual indication and remote
alarm. Since the pole dead level detectors cannot operate if busbar VTs are
used, the breaker open opto isolator is used (See Figure 64) to enable the SOTF
feature.
QUADRAMHO Chapter 2
Page 61 of 74
5.16.40 Relay inoperative alarm 97Y1

Under healthy operating conditions this contact is held open. The following
conditions will cause the relay to close the contact to give a Relay Inoperative
alarm and will also extinguish the Relay Available LED.
a) Loss of any internal voltage rails (+24V, +12V, +5V and 12V).
b) Loss of main dc input voltage to relay.
c) Removal of heavy duty connector 1Z (See Note 4, Figure 67, Appendix A).
d) Connection of socket 2, pin 2 to pin 1 (See Section 3.8).
e) Loss of internal clock signals
f) Loss of reference voltages for level detectors.
g) Code selection number (XY) of scheme logic module not that of a valid scheme.
h) Microcomputer failing to run through program loop.
I) Failure of comparator during self test routine (See Section 4.8.5).
j) Operation of unit with SW3 set to right hand position.
k) Operation of the miniature circuit breaker (mcb).
5.16.41 Scheme logic control of indication
A main group of eight red light emitting diodes (LED) is provided on the left hand
side of the scheme logic module. A further single red LED is provided on the right
hand side of the scheme logic module for power swing blocking indication.
The operation of the green Relay Available LED, fitted to the auxiliary relay
module is described in Section 4.8.25.
Operation of the LEDs is controlled by scheme logic software. Each LED is
separately latched by software so that the appropriate ones remain energised after
the fault has been removed. The indications may be reset manually by pressing the
reset pushbutton on the front of the module. The top seven LEDs of the main group
of eight and the PSB LED are also automatically extinguished and updated with
new information when the relay issues a trip signal. (Except when the trip is due to
SOTF action). Consequently the indication always gives the information relating to
the last fault condition. When the relay is initially energised, the LEDs are all
illuminated for approximately half a second, before being extinguished.
This feature demonstrates that the relay has established correct operation and that
the LEDs function correctly. If switch SW5 is set in the right hand position and the
reset pushbutton depressed and released, a self check is carried out on the relay
comparators. During the running of the self test, the main group of eight LEDs is
illuminated. This lasts for approximately 85ms which is sufficient to verify that the
LED function correctly.
The equivalent logic diagram of the software implementation of the indications is
shown in Figure 76.
After the occurrence of a fault, one of three distinct conditions will have been
recorded by the top seven of the main group of LEDs, a normal 3 zone distance
scheme action, a SOTF operation, or an aided trip action. How each of these
conditions may be interpreted by the LED is described in the following sections.
a) 3 zoned distance scheme action recorded on LED display.
This condition may be identified by the absence of the SOTF and the aided trip
LED being energised. The interpretation given to the remaining LEDs is then as
follows:
QUADRAMHO Chapter 2
Page 62 of 74
The A, B and C LEDs indicate which phases were involved in the fault that
caused the circuit breaker to be tripped. This can be accompanied by the Z2 or
Z3 LED to show that the fault was cleared in time delayed Zone 2 (Z2t) or time
delayed Zone 3 (Z3t). If neither Z2 nor Z3 are lit, the fault was in Zone 1.
As an example, consider the case of an A, C display given after a fault
condition has occurred. This shows that a CA fault has taken place, was
detected and cleared successfully in Zone 1 time. It may be interpreted that the
fault did not remain On for a time long enough to run out the Z2t or Z3t
timers, since neither the Z2 nor Z3 LEDs were energised.
b) Switch on to fault (SOTF) action recorded by LED display.
A SOTF trip condition is recorded by the LED labelled SOTF on the module
nameplate. The previous indication on the display is not extinguished for SOTF
trips, permitting identification of the faulted phases and zones for SOTF trips
occurring in auto reclose conditions. If the LED display is extinguished prior to
the SOTF trip, then only the SOTF LED will be illuminated.
c) Aided trip action recorded by the LED display.
An underreaching scheme (PUR), overreaching scheme (POR) or blocking
scheme (BLOCK) trip action aided by a signalling channel for end zone faults,
is recorded by the energisation of the aided trip LED. Such an action is also
accompanied by the energisation of one or more of the A, B and C LEDs to
show which phases are involved in the fault (except for weak infeed aided trips,
when only the aided trip LED is illuminated). Note that under normal aided
trip conditions and when the fault has been successfully cleared, neither of the
Z2 or Z3 LED are energised. In the case of the blocking scheme, aided trip
action signifies the absence of a blocking signal from the signalling channel.
5.16.42 Test facilities
A comprehansive monitoring system is provided to enable the features of the relay
to be thoroughly tested during commissioning, routine maintenance and fault
finding operations. The monitoring system includes a 25 way test socket from
which power supply voltages, clock pulse frequency, synchronous polarising,
switch-on-to-fault and many more internal features can be checked while the relay
is on the relay panel and the line is energised. All these outputs are protected
against accidental short circuits. See Table 9 for details.
In addition, a large number of test options may be selected by the code selection
switches X and Y. The test options allow all inputs to be the scheme logic, such as
individual comparators, level detectors, timers, settings, opto isolators, etc., to be
read during secondary injection and other off-line tests on the relay. The logic
states of these inputs are displayed on the eight indication LED and are also output
via the 25 way socket on the auxiliary relay module.
Further test options enable relay outputs to be tested. Switches SW1 and SW8 are
set on or off and when the pushbutton is pressed, corresponding outputs are sent
via the relevant relay output contacts and test socket terminals. A trip test of the
circuit breaker, or test of the signalling channel, can be performed conveniently by
this method.
An additional 9 way test socket is fitted to the scheme logic module to allow the
code selection switches and the pushbutton to be overridden electrically.
This permits the use of a programmable secondary injection test set so that most
commissioning, routine maintenance, testing and fault finding operations can be
performed automatically to save line outage time.
QUADRAMHO Chapter 2
Page 63 of 74
Test Signal Equivalent Function Equivalent

socket (active low) LED auxiliary
pin relay
SK225 SK A IND A Trip for fault on A phase

SK224 SK B IND B Trip for fault on B phase
SK223 SK C IND C Trip for fault on C phase
SK222 SK Z2 IND Z2 Trip for fault in Zone 2 Z21
SK220 SK AT IND Aided Trip Aided Trip 94Y1
SK219 SK SOTF IND SOTF Switch on to fault trip 981
SK218 SK FF IND V~FAIL Fuse failure 97X1
SK217 SK CTX Signal send output 85X1, 85X2
SK216 SK + 12V + 12V supply rail
SK215 SK 12V 12V supply rail
SK214 SK + 5V +5V supply rail
SK213 SK BAR Block auto reclose output 961
SK212 SK TRIP 3PH 3 phase trip signal issued 94T1. 94T2
SK211 SK ANY TRIP Trip signal issued by 941, 942
distance relay
SK210 SK PSB ANN PSB Output of power swing 951
blocking feature
SK29 SK CRX ANN Signal receive opto energised
SK28 SK MEM EN Memory feature enabled
SK27 SK TPS Output of PSB 50ms timer
SK26 SK ANY Any comparator operated
Z1/Z2/Z3 (except PSB)
SK25 SK SOTF EN SOTF enabled
SK24 SK MCK/28 Master clock/28 = 3.6Hz @ 50Hz,
SK23 SK 24V 24V supply rail 4.32kHz @ 60Hz
SK22 SK 0V Zero volt common
SK21 SK INH MR Short to SK22 to
inhibit relays
Auxiliary relay module normal scheme option operations only
Table 9: Test Points
5.16.43 Operation of Quadramho with capacitor voltage transformers

For reasons of economy, capacitor voltage transformers (CVT) are often used in
preference to electro-magnetic voltage transformers on high voltage transmission
systems. Although the steady state performance of CVT is generally good, the
transient response can be poor. As distance relays operate under dynamic
conditions following a fault, before steady state conditions are obtained, the
transient response of CVT is an important consideration.
QUADRAMHO Chapter 2
Page 64 of 74
The effects of CVT transient errors on distance relays of the block average type are
well documented. The possible effects are:
a) Maloperation for faults in the reverse direction of the relay.
b) Transient overreach for forward faults beyond the protected zone.
c) Slow operation for faults within the protected zone.
Generally, the faster and more sensitive a distance relay is, the worse the possible
extent of these problems.
The amplitude and waveform of CVT error and hence its effect on a particular type
of relay, depend on the type of CVT, the burden on the CVT, type of ferro-
resonance damping and the point on wave of fault incidence. The system
impedance ratio (SIR) at the relaying point determines whether a given CVT error
can seriously affect the performance of the relay, since the SIR controls the
amplitude of the true relay input signals relative to the CVT error. Practically it has
been found that if the SIR is less than about 9, the effect of CVT transient errors on
most distance relays is negligible, even for CVT with a poor dynamic response.
The development program of Quadramho included a concerted effort to eradicate
the worst effects of CVT errors. The policy was:
a) To completely eliminate maloperation for reverse faults.
b) To reduce transient overreach to a negligible level.
c) To allow the relay comparators to be slowed only to the extent necessary to
prevent reverse maloperation and transient overreach.
The following techniques are used to meet these objectives:
a) Maintenance of true directional reference signal (or polarising signal) at all
times by the use of an adequate proportion of square wave cross-polarising or
synchronous polarising signals.
b) The use of a comparator which, although capable of fast operation, has built-in
safeguards against maloperation caused by non-power system frequency
components of the inputs. These safeguards inherently extend signal processing
time as the true inputs become more contaminated with low frequency CVT
errors.
c) Fitting a fast directional comparator for each phase to reinforce the action of
methods a and b for the very critical case of a close-up fault behind the relay at
high values of SIR. The directional comparator uses current and polarising
voltage as measuring quantities, both of which are independent of CVT errors.
If the directional comparator detects a reverse current flow it inhibits operation
of the quadrilateral or mho main comparator to completely eliminate the
possibility of wrong operation.
This method of using a directional unit to inhibit the main comparator avoids the
problems of slow operating times and signal races on resetting which often beset
other types of multiple comparators.
d) The use of a switched filter to pre-condition the voltage signal to the measuring
units and eliminate excessive delays to comparator operation. Such delays
would otherwise be caused by the presence of large slowly decaying low
frequency CVT errors for faults inside a comparator zone, but near to the
boundary of operation, at high values of SIR.
QUADRAMHO Chapter 2
Page 65 of 74
5.16.44 Typical logic symbols used
A A A
B
& Output
B
& Output
B
& Output
Inputs Output Inputs Output Inputs Output

A B A B A B
0 0 0 0 0 1 0 0 0
0 1 0 0 1 1 0 1 1
1 0 0 1 0 1 1 0 0
1 1 1 1 1 0 1 1 0
A A A
B
1 Output
B
1 Output
B
1 Output
Inputs Output Inputs Output Inputs Output

A B A B A B
0 0 0 0 0 1 0 0 1
0 1 1 0 1 0 0 1 0
1 0 1 1 0 0 1 0 1
1 1 1 1 1 0 1 1 1
S S
Q Output Q Output
R R
Inputs Output Inputs Output

S R Q S R Q
0 0 X 0 0 0
0 1 0 0 1 0
1 0 1 1 0 1
1 1 1 1 1 1
X = no change X = no change
5ms
0 t tp
t 0 td
20ms
Time delay on drop-off Time delay on drop-off tp = pick-up time
drop-off time = 20ms drop-off time = 0ms td = drop-off time
pick-up time = 0ms pick-up time = 5ms
QUADRAMHO Chapter 2
Page 66 of 74
Section 6. TECHNICAL DATA
6.1 Input ratings

AC voltage Vn 100 to 120 volts rms phase-phase. The relay will withstand
150% rated voltage continuously, or 250% rated voltage for
10s.
AC current In 1A or 5A rms per phase. The relay will withstand 2.4 times
rated current continuously and 100A for 1s (1A version) or
400A for 1s (5A version).
Frequency fn 50Hz or 60Hz.
6.2 Impedance setting ranges
The range of Zone 1, Zone 2 and Zone 3 forward if 0.2 to approximately 240
on a 1A relay, or 0.04 to approximately 48 on a 5A relay. The reverse reach
of Zone 3 has the same maximum setting, but a minimum of 0.05 (1A relay) or
0.01 (5A relay). These settings are achieved as follows:
ZPh Coarse reach setting common to all zones
0.1 to 4.8 in 0.2 steps (1A)
0.04 to 0.96 in 0.04 steps (5A)
ZN residual compensation setting
0.2 to 5.98 in 0.02 steps (1A)
0.004 to 1.196 in 0.004 steps (5A)
Fine settings as multiples of coarse setting
Zone 1 1 to 9.98 in 0.02 steps
Multiplied by 1 or 5
Multiplied by
Zone 3 reverse 1 to 9.9 to 0.1 steps 1 or 5
multiplied by 0.25, 0.5 or 1
Fine setting of Extended Zone 1 as multiple of normal Zone 1
1 to 2 in 0.1 steps
Switched attenuators are used for all relay reach settings. Each switch is labelled
as a K-factor for identification. K1, 2, 4, 5 and 6 are attenuators of the IZ
(operating) signal whereas all othe K-factors are attenuators of the V (restraint)
signal.
The reach is calculated as follows:
K1 + K2 Ph
Coarse reach ZPh =
In
Z4 + K5 + K6 N
Residual compensation ZN =
In
where In is the nominal current rating of the current input module.
ZL0 + ZL1 Z
Residual compensation factor = = N
3ZL1 ZPh
QUADRAMHO Chapter 2
Page 67 of 74
Zone 1 positive sequence Z1 = (K11 + K12 + K13) K14 x ZPh

Extended Zone 1 Z1X = Z1 x K15
Zone 2 Z2 = (K21 + K22) K24 x ZPh
Zone 3 Z3 = (K31 + K32) K33 x ZPh
Zone 3 reverse Z3' = (K35 + K36) K33 x K37 x ZPh
6.3 Resistive reach setting range (quadrilateral earth fault units only)
The resistive reach in both the forward and reverse direction for Zones 1, 2 and 3
are set by switch K3.
Resistive reach RS = K3
In
6.4 Lenticular aspect ratio setting range (lenticular zone 3 only)
The aspect ratio a/b of the lenticular Zone 3 phase fault and earth fault units and
of the Zone 6 power swing blocking zone is 0.41, 0.67 or 1.00, where b is the
sum of the forward and reverse reach settings and a is the maximum width of the
impedance characteristic measured perpendicular to the characteristic angle.
Aspect ratio 1.00 gives a circular characteristic.
6.5 Summary of K-factors
K1 0 to 4 step 1
K2 0 to 0.8 step 0.2
K3 8, 16, 32, 40, 38 *if fitted)
K4 0 to 5 step 1
K5 0 to 0.9 step 0.1
K6 0. to 0.8 step 0.02
K11 1 to 9 step 1 (and infinity)

K12 0 to 0.9 step 0.1
K13 0 to 0.08 step 0.02
K14 1, 5
K15 1 to 2 step 0.1 and infinity
K21 1 to 9 step 1 (and infinity)

K22 0 to 0.9 step 0.1
K31 1 to 9 step 1
K 32 0 to 0.9 step 0.1
K33 1, 5
a/b 0.41, 0.67, 1.00 (if fitted)
K35 1 to 9 step 1
K36 0 to 0.9 step 0.1
K37 0.25, 0.5, 1.0
The infinity positions of K11, K15 and K21 are used for on-load directional
checks. With the exception of K37 any unused switch positions are at the most
clockwise positions of the switch knob and have the same electrical connection as
the highest setting used.
QUADRAMHO Chapter 2
Page 68 of 74
6.6 Accuracy of impedance measurement

The accuracy is unaffected by the ZPh and ZN settings, the characteristic angle
setting or the dc supply (within the operative range).
The following accuracy claims apply under reference conditions:
Fine reach multipliers set to unity,
Ambient temperature 20C
Nominal input frequency fn.
Zone 1 accuracy 5% up to SIR = 30
Zone 1 accuracy 10% SIR = 30 to SIR = 60
SIR is the system impedance ratio defined as the total source impedance divided
by the relay setting ZPh + ZN for earth faults or 2ZPh for phase faults. At reference
settings and at a nominal source voltage of 110 phase-phase, SIR = 30
corresponds to 2.05V/0.213In for earth fault measurement and 3.55V/0.370In
for phase fault measurement and SIR = 60 corresponds to 1.04V/0.108In for
earth fault measurement and 1.80V/0.188In for phase fault measurement.
The effective accuracy range at any setting has maximum limits of 1.2 times rated
voltage and 56 times rated current.
Transient overreach is less than 1%.
The additional error caused by a departure from reference conditions, within the
operative ranges, is not more than the error allowed at reference conditions.
6.7 Current sensitivity of impedance measuring units.
Determined by low set current level detectors. The sensitivity varies inversely with
coarse reach setting ZPh and is nominally 5%In at ZPh = 4.8/In .
6.8 Returning ratio of impedance measuring units
Returning ratio is the impedance value at which the relay just returns to a reset
condition, divided by the impedance value at which the comparator just operates.
Returning ratio measured on the characteristic angle of the relay is less than 110%.
6.9 Characteristic angle setting ranges and accuracy
Characteristic angle settings
ZPh Phase 85 to 45 in 5 steps
ZN Residual 85 to 45 in 5 steps
Accuracy of phase setting is 2, independent of relay reach setting.
The impedance reach accuracy does not vary with characteristic angle setting.
The characteristic angle switches have unused positions at the anti-clockwise end of
the switch knob rotation range. The relay characteristic angle is 45 if these
unused positions are selected.
QUADRAMHO Chapter 2
Page 69 of 74
6.10 Timer setting ranges

Zone 2 timer tZ2 0 to 2.55s in 10ms steps
Zone 3 timer tZ3 0 to 5.1s in 40ms steps
Scheme timer tp 0 to 90ms in 6ms steps
Scheme timer tD 0 to 90ms in 6ms steps.
Timer settings are by a series of switches arranged in a binary series. The time
delay associated with each switch is effective only when the switch is set to the
right hand position.
Formula Link Positions Available
tZ2 = (t2) ms t2 = 10, 20, 40, 80, 160, 320, 640 & 1280
tZ3 = (t3) ms t3 = 40, 80, 160, 320, 640, 1280, 2560 &
tp = (tp) ms tp = 6, 12, 24 & 48
tD = (td) ms td = 6, 12, 24 & 48
6.11 Polarising
Proportion and type of cross polarising for Zones 1 and 2 partially cross polarised
mho and for Zones 1 and 2 directional lines.
Phase-earth faults
Phase-phase-earth faults 16% square wave from healthy phases
Phase-phase faults
Three phase faults 16% square wave from synchronous
polarising system
Synchronous polarising is effective for 8 cycles after fault incidence.
Synchronous polarising start up time is 140ms from energisation of line.
6.12 Switch-on-to-fault
The switch-on-to-fault system is enabled either 200ms or 110s (as selected by a
switch SW2) after all poles of the line have been de-energised and remains active
for 240ms after the line has been energised.
Switch-on-to-fault tripping is by any Z1/Z2/Z3 comparators or voltage and current
level detectors (as selected by a switch SW1 on the front of the relay).
Voltage level detector setting: 44.5V phase-earth (70% Vn)
Current level detector setting: 0.05In x 4.8/(K1 + K2)
Condition for fault detection: Current level detector operated and voltage
level detector not operated, on any phase,
for 20ms.
QUADRAMHO Chapter 2
Page 70 of 74
6.13 Operating and reset times

Minimum (50HZ) 14ms (60Hz) 13ms
Mho characteristic
Typical (50Hz) 1825ms (60Hz) 1623ms
Minimum (50HZ) 19ms (60Hz) 17ms
Mho characteristic
Typical (50Hz) 2533ms (60Hz) 2229ms
These times include the operating times of the electro-mechanical tripping output
relays.
The maximum reset time is 36ms with the proviso that the main trip contacts
(Trip A, Trip B, Trip C, Trip 3Ph and Any Trip) are sealed in for a minimum period
of 60ms following the initial trip.
6.14 Voltage transformer (fuse failure) supervision
The voltage transformer supervision operates when zero sequence voltage is
detected without the presence of zero sequence current. This does not limit the
current sensitivity of the distance measuring elements.
Nominal V0 detector setting 9.5V (15% Vn).
Blocking action of distance comparators can be removed by switch SW3.
When miniature circuit breakers are used the comparators are blocked when the
MCB opens regardless of the position of SW3.
6.15 Power swing blocking
Power swing blocking zone (Zone 6) has mho or lenticular characteristic.
Aspect ratio of the lens is the same as that of Zone 3. Power swing blocking may
be enabled/disabled by SW9.
Settings: Zone 6 forward = Zone 3 forward + 0.3 x Zone 3 forward
Zone 6 reverse = Zone 3 reverse + 0.3 x Zone 3 forward
Timer = 50ms
Blocking: Individual blocking of Zone 1 and/or Zone 2 and/or Zone 3 with
indication/alarm or indication/alarm only as selected by switches
on the scheme logic module. Blocking is removed if a ground fault
occurs during a power swing.
6.16 Operative ambient temperature range
The operature ambient temperature range is 25 to 55C.
6.17 Operative frequency range
The operative freqency range is: 47 to 51Hz (fn = 50Hz)
56.4 to 61.2Hz (fn = 60Hz)
QUADRAMHO Chapter 2
Page 71 of 74
6.18 Burdens and current transformer requirements

Voltage burden less than 0.1VA, 0.4 lagging power factor per phase at 63.5V
phase to neutral.
Current burden per phase with balanced three phase rated current.
0.26VA (1A relay
0.68VA (5A relay) Mho version
0.34VA (1A relay

0.75VA (5A relay) Quadrilateral version
The current transformers should have a minimum knee point output voltage VK
defined as:
VK = IF (1 + X/R) (RB + RCT + RL)
Where
IF = The maximum fault current at the relay Zone 1 reach point in
secondary terms.
X/R = Primary system ratio.
RB = Relay burden resistance.
RCT = CT internal resistance in secondary terms.
RL = Lead resistance from CTS to relay.
(lead and return for earth faults, lead only for phase faults).
The following table gives the values of relay burden resistance RB:
MHO or Lenticular Version
1A relay earth faults RB = 0.53
1A relay phase faults RB = 0.26
Quadrilateral Version
Where necessary ALSTOM T&D Protection & Control Ltd can supply details of
reduced CT requirements on some systems.
6.19 Output contact ranges
Make and carry for 0.2s 7500VA with maxima of 30A and 300V, ac or dc.
Carry continuously 5A ac or dc.
Break ac 1250VA
dc 50W resistive with maxima 5A, 300V
25W L/R = 0.04s
QUADRAMHO Chapter 2
Page 72 of 74
6.20 DC supply ratings and operative range

Three versions of the power supply are available with nominal ratings as shown
below.
DC supply Vx (1) nominal operative maximum
range withstand
48/54V 37.5 60V 64.8V
110/125V 87.5 137.5V 150V
220/250V 175 275V 300V
Effect on accuracy of impedance measurement due to dc supply variations within
the operative range of the relay is negligible.
6.21 Auxiliary dc supply for optically-coupled isolators
DC voltage Vx(2) for the opto isolators may, if required, be different from the
power supply voltage Vx(1). Available nominal voltages and operative ranges of
Vx(2) are as listed above for Vx(1). Threshold of operation for opto isolators not
less than +10V (to provide immunity from electrical noise).
6.22 DC power consumption
Typical under healthy live line conditions 25W
Maximum under tripping conditions 50W
6.23 Inbuilt continuous monitoring and periodic self-test
There is continuous monitoring of power supplies, clock pulses, scheme logic and
ac voltage supplies and a selectable periodic self test of all 18 measuring elements
(selected via SW5) every 2 weeks.
Time taken to perform self test = 0.085s
6.24 Voltage withstand
Insulation
IEC 60255-5 2kV rms for 1 minute between all case terminals
connected together and the case earth terminal.
BS142 1982 Section 1.3 2kV rms for 1 minute between independent circuit
of the scheme, including contact circuits.
1kV rms for 1 minute across normally open
outgoing contact pairs.
High voltage impulse
IEC 60255-5 5kV peak, 1.2/50s, 0.5J between all terminals
BS142 1982 Section 1.3 and case earth and between adjacent terminals.
High frequency disturbance
IEC 60255-6 Class III 2.5kV peak between independent circuits and
between circuits and case earth.
BS142 1982 Section 1.4 1.0kV peak across input circuits.
1Mhz bursts decaying to 50% of peak value after
3 to 6 cycles.
Repetition rate 400s1.
QUADRAMHO Chapter 2
Page 73 of 74
6.25 Environmental withstand

Temperature
IEC 60068-2-1 Operating 25C to +55C
IEC 60068-2-2 Storage and transit 25C to +70C
Humidity
IEC 60068-2-3 56 days (at 93% RH and +40C)
BS 2011 Part 2.1Ca
Salt mist:
IEC 60529 BS 2011 Part 2.1kB
Enclosure Protection
IEC 60052
BS5290 IP50 (dust protected)
Vibration
BS142 Section 2.2 Category S2, 0.5g between 10 and 300Hz
Mechanical durability 105 operations minimum
6.26 Dimensions
Weight 23kg.
Overall size height width depth
rack mounting case 266 483 315
panel mounting case 291 444 315
QUADRAMHO Chapter 2
Page 74 of 74
Fault Source SW1 to left SW1 to right

type impedance any Z1/Z2/Z3 Current No Volts
(ohms)
Line VT Busbar VT Line VT Busbar VT
SOTF TRIP TIMES (ms)
Min Max Min Max Min Max Min Max
ABCG 108 29 35 16 22 30 36 39 45
36 30 35 14 22 30 37 40 46
4 29 32 14 21 30 34 38 44
AG 108 29 27 21 32 32 38 36 50
Quadl 36 28 37 21 33 32 41 38 49
relay 4 28 34 22 29 31 38 38 49
AG 108 27 38 17 26 32 38 36 50
Mho 36 30 34 16 26 32 41 38 49
relay 4 28 37 14 28 31 38 38 49
Table 10: Typical SOTF trip times for close up 3 phase and single phase faults.
Relay settings: ZPh = ZN = 4.8

Ph = N = 85
Z1 multiplier = 1
Z2 multiplier = 2
Z3 multiplier = 3
QUADRAMHO Chapter 2
Appendix A
Page 1 of 71
Quiet area Interface area
Figure 1: Quadramho
Signal and power commons to modules
QUADRAMHO
SERVICE MANUAL
Ground plane on relay multilayer pcb

backplate
CURRENT
A INPUT MODE
POWER SUPPLY B
VOLTAGE
IMPUT MODULE
4mm Plug & Socket RELAY CASE
Case earth stud
Relay room earth
Source A: Common mode surge from ac current to ac voltage terminals

Source B: Common mode surge from dc supply to case terminals
Chapter 2
R5888C
Page 2 of 71
Appendix A
Figure 2: Quadramho module earthing arrangement

Terminal block detail
1 2
QUADRAMHO
SERVICE MANUAL
305 252
27 28
20
TOP VIEW 28 Way Max.

each way excepting:
2-M4 ring terminals
or
2-4.8 x 0.8 snap on terminals
or
1- Ring, 1-Snap on terminal
37.7 483
1 2 3 4 5 6 IZ
465
266 IY 190.5 T.B. T.B. T.B.

7 A B C
POWER SUPPLY
ZRE 01
FRONT VIEW
REAR VIEW
Chapter 2
R5888C
Page 3 of 71
Appendix A
Figure 3: Outline drawing and module layout

Bandpass Filter Switching
Amplitude Hysteresis
Voltage Memory
Memory Available
Clock Pulses
Zone1/2 Zone 1Extension
VIR VPOL
Polarise Zone 1Inhibits
QUADRAMHO
Self test
Reset
SERVICE MANUAL
VaVbVc
Voltage Zone 1
Inputs Setting Z1 MICROCOMPUTER
Vn ZONE
SOFTWARE LOGIC
1
FOR:
Zone 1X VIZ(Z1) comparators
Control
All Schemes
Zone 1X Schemes Timers
Setting Scheme Options
IR Comparator Level LED

Phase Indication
detector Checks
and VIZ(Z2)
Zone 2
Neutral
IZ Setting Z2 Pole Dead Logic
Setting ZONE
2 SOTF
comparators
VIZ VTS
Zone 3
Polarise VIZ(180) Power Swing
Blocking
Voltage Memory
VIZ(Z3) Z3
Zone 3 Voltage Bandpass
Setting VIZ(Z6) Filter Select
IaIbIc ZONE
3 Indications
Current Z6
comparators Auxillary Relay
In Inputs
Block Auto-Reclose Output
Level Logic Contacts
Detector
Circuits Fault Locator,
Trip and Alarm
Outputs
Self-test and other

Signalling Equipment etc. Opto Test Options
Outputs
Chapter 2
R5888C
Page 4 of 71
Appendix A
Figure 4: Block diagram

+12V 0V 0V 0V 0V +12V
5KV
PEAK ATTENUATION
QUADRAMHO
SERVICE MANUAL
EA SURGE
VA
PROTECTION
VA'
EN
0V
ATTENUATION
SURGE
EB VB
PROTECTION
INPUTS FROM LINE VTs

VB'
0V
ATTENUATION
SURGE VC
EC
PROTECTION
VC'
0V
BOARD BOARD VMEM
ZH0738 ZH0737
V/SK1
ENF TRIP
HEAVY CURRENT
EARTH
Chapter 2
R5888C
Page 5 of 71
Appendix A
Figure 5: Voltage input module RFV04

QUADRAMHO Chapter 2
Appendix A
Page 6 of 71
Waveforms represent fault in Zone 1 close

to boundary of operation with large
exponential component in voltage
VIZ
No zero crossings comparator
cannot operate
VPOL
VIZ (with switched filter)
Zero crossings re-started

comparator can operate
26-36 ms delay
before switching to
filtered supply
Inhibit pulse
Figure 6: Action of switched bandpass filter in voltage supply

QUADRAMHO Chapter 2
Appendix A
Page 7 of 71
2 APh
I 1
A
D T
C
I COMMON
A
IA
D
C
TRANSPHASORS I 2
A
I R
A
D
C.T. R
1 D
I R COMMON
A
4
IB1
INPUT CURRENT FROM LINE CTs
I COMMON
B
IB I 2
B
CIRCUIT SAME AS ABOVE
3
I R
B
I R COMMON
B
6 I 1
C
I COMMON
C
IC I 2
CIRCUIT SAME AS ABOVE C
5 I R
C
I R COMMON
C
N
7
I 1
N
D D T
IN C I 2
N
I 3
N
T
TRANSPHASORS C
8 I COMMON
N
V/SK2
HEAVY CURRENT
TERMINALS
Figure 7: AC current input module RFC15

QUADRAMHO
1
SERVICE MANUAL
45 50
2
55
60 Ph 3
85 65
80
75 70 4
5
45 50
55
6
60 N
85 65
80 7
75 70
10
In A Hz
Chapter 2
R5888C
Page 8 of 71
Appendix A
Figure 8: Nameplate details RFC15

QUADRAMHO Chapter 2
Appendix A
Page 9 of 71
1 MCK/7
MCK +7 +2 MCK/14
MCK/28
+2 Stopped
Clock
+12V Detector LD
1 ALARM
Positive 1 Negative Voltage Reference
Voltage Reference Wrong
Reference Detector
Sig VREF
Common 0V
+VREF
G1 Level
LDIA Detector
IA Common Element LDLSA
Precision
Rectifier
Level
VA Detector
VA Common Element LDOVA
G1 Level
LBDI Detector
IB Common Element LDLSB
Precision
Rectifier
Level
VB Detector
Element LDOVB
VB Common
Level
G1 Detector
LDIC
IC Common Element LDLSC
Precision
Rectifier
Level
Detector
VC Element LDOVC
VC Common
Precision Hysteresis LDLSN

Rectifier for LSN REF
G2 LDLSN
1 +LSN REF
D C +12V
0V
12V
Level
G3 Detector MCK/4
Element
LDHSN
Figure 9: Level detectors ZH0729

QUADRAMHO Chapter 2
Appendix A
Page 10 of 71
LDI
K2(a) FINE SETTING A
I Z
I 1 A PH
A
+ I Z
I 2
A - A PH
I COMMON
A K1(a) COARSE SETTING LDI
B
K2(b) FINE SETTING
I Z
B PH
I 1
B
I 2 + I Z
B - B PH
I COMMON
B K1(b) COARSE SETTING LDI
C
K2(c) FINE SETTING
I Z
C PH
I 1
C
I 2 +
C I Z
- C PH
I COMMON
C K1(c) COARSE SETTING
K6 VERY FINE SETTING I Z
N N
I 1
N +12V
I 2
N 0v
K5 FINE SETTING
12V
K4 COARSE SETTING
I 3
N SIG COMMON
I COMMON
N CIRCUIT BELOW APPLIES TO QUADRILATERAL RELAY ONLY
V K3(a) RESISTIVE REACH

A' MIXING (V + IR)
AND A
V COMMON (V IR)
A SQUARING A
V CP
A IR' FOR (IR)
A A
IR PHASE
A
A (IR)
N
IR COMMON
A
G
V
B' K3(b)
MIXING (V + IR)
RESISTIVE B
V COMMON AND
B (V IR)
V CP REACH SQUARING B
B FOR (IR)
IR B
B PHASE
IR COMMON B
B
SC
V
C' K3(c)
MIXING (V + IR)
C
V COMMON RESISTIVE AND
(V IR)
C REACH SQUARING C
V CP
C FOR (IR)
C
IR PHASE
C
C
IR COMMON
C
Figure 10: Board ZH0730 phase and neutral and IR setting

QUADRAMHO Chapter 2
Appendix A
Page 11 of 71
0 1 0 1
2 2
3 K1 3 K1
4 4
0 0.2 0 0.2
0.4 0.4
0.6 K2 0.6 K2
0.8 0.8
ZPh() = K1+K2 ZPh() = K1+K2

In In
ZLO ZL1 ZN ZLO ZL1 ZN
= =
3ZL1 ZPh 3ZL1 ZPh
RS() = K3
In
8 16
32
40 K3
48
ZN() = K4+K5+K6 ZN() = K4+K5+K6
In In
0 1 0 1
2 2
3 K4 3 K4
4 4
5 5
0 0.1 0 0.1
0.2 0.2
0.9 0.3 K5 0.9 0.3 K5
0.8 0.4 0.8 0.4
0.7 0.6 0.5 0.7 0.6 0.5
0 .02 0 .02
.04 .04
.06 K6 .06 K6
.08 .08
fn = Hz fn = Hz
Figure 11: Nameplate details RRZ07

QUADRAMHO Chapter 2
Appendix A
Page 12 of 71
Extend Z1
Zone 1 setting Zone 1 ext setting Zone 1/

Vout = Vin/ Vout = Vin/K15 Zone 1 ext
(K11 + K12 + K13)K14 selector
VA A phase
(V IZ)AZ1
VA attenuator
(V IZ)BZ1
common A phase (V IZ)CZ1
attenuator
Zone 1
VS voltage (V IZ)AG
B phase and current
attenuator (V IZ)BG
VS mixing/ (V IZ)CG
common B phase squaring
attenuator circuits
(V IZ)ABZ1
VC C phase (V IZ)BCZ1
attenuator (V IZ)CAZ1
VC
common C phase
attenuator
IAZPH
IABZPH
IBZPH
Phase-phase
ICZPH current
mixing/ IBCZPH
INZN squaring
circuits
INZN
common ICAZPH
Zone 2 setting
Vout = Vin/
(K21 + K22)K14
A phase (V IZ)AZ2
attenuator (V IZ)BZ2
(V IZ)CZ2
Zone 2
voltage
B phase and current
attenuator mixing/
squaring
circuits
(V IZ)ABZ2
(V IZ)BCZ2
C phase (V IZ)CAZ2
attenuator
+12V
0V
12V
Figure 12: Zone 1/Zone 2 setting board ZH0732

QUADRAMHO Chapter 2
Appendix A
Page 13 of 71
(V IZ)AZ1 A1 Comparator
INH4
Out 1 or AZ1
B1
IAZPH DA1
DB1 Dout 1
(V IZ)ABZ1 A2 Comparator
B2 Out 2
or ABZ1
IBZPH
INH3
ICZPH
(V IZ)AZ2 A1 Comparator
INH4
Out 1 or AZ2
B1
IABZPH DA1
DB1 Out 1
VmA
Memory (V IZ)ABZ2 A2 Comparator
VmB B2 Out 2
selector or ABZ2
VmC
INH3
Memory
enabled
(V IZ)BZ1 A1 Comparator
INH4
VA Out 1 or BZ1
B1
DA1
VB Dout 1
Z1/Z2 DB1
VC polarising
(V IZ)BCZ1 A2 Comparator
Signal B2 Out 2
or BCZ1
common
INH3
(V IZ)BZ2 A1 Comparator
INH4
Out 1 or BZ2
B1
IBCZPH DA1
DB1 Dout 1
(V IZ)BCZ2 A2 Comparator
B2 Out 2
+12V or BCZ2
INH3
+5V
0V
12V
(V IZ)C A1 Comparator
INH4
Out 1 or CZ1
Z1 1RC B1
DA1
DB1 Dout 1
(V IZ)ABZ2 A2 Comparator
B2 Out 2
or CAZ1
+6 MCK/6
INH3
Main clock +8 MCK/8

100 8kHz
@ 50Hz MCK
120 96kHz MCK/5
+5
@ 50Hz
(V IZ)CZ2 A1 Comparator
INH4
Out 1 or CZ2
B1
Clock ICAZPH DA1
LD alarm monitor In alarm DB1 Dout 1
circuit
(V IZ)CAZ2 A2 Comparator
B2 Out 2
or CAZ2
Pole dead A
INH3
Pole dead B
Pole dead C
Inhibits and control
Power swing block Z1
Power swing block Z1
Self check
Master reset/invert
Disable characters
Figure 13: Zone 1/Zone 2 comparators (MHO version)

QUADRAMHO Chapter 2
Appendix A
Page 14 of 71
IAZPH
(V IZ)AZ1 1 2 3
IBZPH A1 INH Out
INR Comparator AZ1
ICZPH B1 1
VMA V POL A DA1 Dout1
DB1
VMB Memory ULA
select (V IZ)ABZ1 A2
Out
VMC B2 Comparator ABZ1
V POL AB 2
DA2 Dout2
Memory DB2 INH 9
enable (V IR)A
1 Side line inhibit ZA
VA (V IZ)AZ2
VB Z1/Z2 IAR
polarising 1 2 3
VC V POL BC A1 INH Out Comparator AZ1
V POL C B1 1
Signal
common IABZPH DA1 Dout1
DB1
ULA
+12V (V IZ)ABZ2 A2
Out
B2 Comparator ABZ2
2
+5V
(V IR)A DA2 Dout2
0V DB2 INH 9
12V
G T/line (V IZ)BZ1
GA 1 2 3
Pole dead Inhibit A1 INH Out Comparator BZ1
PDA Guard
LH S/line zone Inhibit B1 1
A logic V POL B DA1 Dout1
RH S/line Inhibit DB1
A ULA
Direction (V IZ)BCZ1 A2
A Out Comparator BCZ1
B2
G T/line 2
GB DA2
Pole dead Inhibit (V IR)B Dout2
PDB Guard DB2 INH 9
LH S/line zone Inhibit 1 Side line inhibit ZB
B logic
RH S/line Inhibit
B
Direction (V IZ)BZ2
B 1 2 3
A1 INH Out
Comparator BZ2
G T/line IBR
GC B1 1
Pole dead Inhibit IBCZPH DA1 Dout1
PDC Guard
LH S/line DB1
zone Inhibit ULA
C logic (V IZ)BCZ2 A2
RH S/line Inhibit B2
Out Comparator BCZ2
C 2
Direction (V IR)B DA2
C
DB2 Dout2
INH 9
V POL CA
4 MCK/4
8 MCK/8
(V IZ)CZ1 1 2 3
Main clock A1 INH Out
Comparator CZ1
100kHz MCK B1 1
at 50Hz DA1 Dout1
5 MCK/5 DB1
ULA
(V IZ)CZ1 A2
Out
B2 Comparator CAZ1
2
LD alarm Clock In alarm DA2
DB2 Dout2
monitor INH 9
(V IR)C
circuit 1 Side line inhibit ZC
(V IZ)CZ2
1 2 3
ICR A1 INH Out Comparator CZ2
Power swing block Z1 Inhibits B1 1
Power swing block Z2 and ICAZPH DA1 Dout1
control DB1
Self check ULA
(V IZ)CAZ2 A2
Out
Master reset/revert B2 Comparator CAZ2
2
Distable comparators DA2 Dout2
(V IR)C
DB2 INH 9
Figure 14: Zone 1/Zone 2 comparators (Quad version)

QUADRAMHO Chapter 2
Appendix A
Page 15 of 71
DA1
Inputs Inhibit comparator 1 DOut 1
DB1
A1
Inputs
Main comparator 1 Out 1
B1
Inhibit 1
2
3
4
5
6
7
Main comparator 2
A2
Inputs
Out 2
B2
DA2
Inputs Inhibit comparator 2
D Out 2
DB2
Control
MCK MCK SC MRI

/5
Figure 15: Layout of ULA

QUADRAMHO Chapter 2
Appendix A
Page 16 of 71
Function ULA Input MHO QUAD
Zone 1 A Comp 1 A1(operate) (VIZ)AZ1 (VIZ)AZ1

B1(polarising) VA+0.16[(VB+VC) INR
+0.16VMA]
Zone 1 AB Comp 1 A2 (VIZ)ABZ1 (VIZ)ABZ1
B2 VAVB+0.16(VC+0.16 As MHO
[(VA+VB)=0.16VMC])
Zone 1 B Comp 2 A1 (VIZ)BZ1 (VIZ)BZ1
B1 VB+0.16[(VC+VA) INR
+0.16VMB]
Zone 1 BC Comp 2 A2 (VIZ)BCZ1 (VIZ)BCZ1
B2 VBVC+0.16(VA+0.16 As MHO
[(VB+VC)=0.16VMA])
Zone 1 C Comp 3 A1 (VIZ)CZ1 (VIZ)CZ1
B1 VC+0.16[(VA+VB) INR
+0.16VMC]
Zone 1 CA Comp 3 A2 (VIZ)CAZ1 (VIZ)CAZ1
B2 VCVA+0.16(VB+0.16 As MHO
[(VC+VA)=0.16VMB])
Zone 2 A Comp 4 A1 (VIZ)AZ2 (VIZ)AZ2
B1 As Zone 1 A IAR+INR
B1 As Zone 1 A B As MHO
B1 As Zone 1 B IBR+INR
B1 As Zone 1 BC As MHO
B1 As Zone 1 C ICR+INR
B1 As Zone 1 CA As MHO
A Directional 1 DA1 IAZPhINZN IAZPhINZN
DB1 As Zone 1 A As MHO
A Left hand 1 DA2 Not used IAZPhINZN
side line DB2 VA+IAR
B Directional 2 DA1 1IBZPhINZN IBZPhINZN
DB1 As Zone 1 B As MHO
B Left hand 2 DB2 Not used IBZPhINZN
side line DB2 VB+IBR
CA Directional 3 DA1 ICZPhINZN ICZPhINZN
DB1 As Zone 1 C As MHO
C Left hand 3 DA2 Not used ICZPhINZN
side line 1 DB2 VC+ICR
AB Directional 4 DA1 IABZPh IABZPh
DB1 V Pol AB V Pol AB
A Right hand 4 DA2 Not used VAIAR
side line DB2 IAZPhINZN
BC Directional 5 DA1 IBCZPh IBCZPh
DB1 V Pol BC As MHO
B Right hand 5 DA2 Not used VBIBR
side line DB2 IBZPhINZN
CA Directional 6 DA1 ICAZPh ICAZPh
DB1 As Zone 1 CA As MHO
C Right hand 6 DA2 Not used VCICR
side line DB2 ) ICZPhINZN
16 INB1 ( Left hand side line
INB2 (Not used Right hand side line
INB3 ( Guard zone
INB4 Directional G/F Directional G/F
INB5 DICO DICO
Inhibits all INB6 Power swing block Power swing block
ULAs INB7 Common pole dead Common pole dead
INB8 Pole dead Pole dead
INB9 Directional P/F Directional P/F
Figure 16: Comparator inputs

QUADRAMHO Chapter 2
Appendix A
Page 17 of 71
1
2
3
4 K11
9 5
8 7 6
0 0.1
0.4
0.9 0.3 K12
0.8 0.4
0.70.60.5
0 0.2
0.4
0.6 K13
0.8
1
1 5
5 1 5
K14
K24
Z1 = (K11 + K12 + K13) Kl4 x ZPh

Z1X = Z1 x K15
Z2 = (K21 + K22) K24 x ZPh
1 1.1
2 1.2
1.9 1.3 K15
1.8 1.4
1.7 1.61.5
1
2
3
4 K21
9 5
8 7 6
0 0.1
0.2
0.9 0.3 K22
0.8 0.4
0.7 0.60.5
fn = Hz
Figure 17: Nameplate details RRM08

QUADRAMHO Chapter 2
Appendix A
Page 18 of 71
Zone 3 forward
setting VOUT = VIN/
(K31+K32)K33
VA A phase
(V + IZ)AZ3
VA attenuator
(V + IZ)BZ3
Common Zone (V + IZ)CZ3
VB 3/6
B phase voltage (V + IZ)ABZ3
VB attenuator and (V + IZ)BCZ3
Common current (V + IZ)CAZ3
mixing/ (V + IZ)ABZ6
VC C phase squaring (V + IZ)AZ3
VC attenuator circuits (V + IZ)BCZ3
Common
(V + IZ)CZ3
Zone 3 reverse (V + IZ)ABZ3

(V + IZ)BCZ3
setting VOUT =
(V + IZ)CAZ3
VIN /(K35+K36)
(V + IZ)ABZ6
(K33 +K35)
A phase
attenuator
B phase
attenuator
C phase
attenuator
Zone 6
Signal reverse
common setting
IAZPH
IBZPH
ICZPH
INZN
IN
COMMON +LSN REF
Low set
neutral
INZPH X8 level LDSN
detector
LSN REF
MCK/4 Lenticular version only
MCK/14 = 45
Aspect .41 = 68
+12V
ratio 67 1
0V
+12V Switch a/b
12V
Figure 18: Zone 3 setting board ZH0734

QUADRAMHO Chapter 2
Appendix A
Page 19 of 71
INH1
(VIZ)AZ3 A1 Comparator
B1 OUT1
AZ3
Shift (VIZ) (180 )
(V+IZ)AZ3 DA1 DOUT1
register DB1
(VIZ)
(VIZ)ABZ3 A2
OUT2 Comparator
B2
Shift (VIZ) (180 ) ABZ3
(V+IZ)ABZ3 DA2
register DB2 DOUT2
(VIZ) INH9
(VIZ)AZ3 A1 INH1 Comparator

B1 OUT1
Shift (VIZ) (180 ) BZ3
(V+IZ)BZ3 DA1
register DB1 DOUT1
(VIZ)
(VIZ)ABZ3 A2 Comparator
Shift B2 OUT2 BCZ3
(VIZ) (180 ) DA2
(V+IZ)BCZ3 register DOUT2
DB2 INH9
(VIZ)
(VIZ)CZ3 A1 INH1
Comparator
B1 OUT1
Shift (VIZ) (180 ) CZ3
(V+IZ)CZ3 register DA1 DOUT1
DB1
(VIZ)
(VIZ)CAZ3 A2 Comparator
Shift B2 OUT2
CAZ3
(V+IZ)CAZ3 register (VIZ) (180 ) DA2
DOUT2
DB2 INH9
(VIZ)
(VIZ)ABZ6 A2
B2 OUT2 Comparator
Shift ABZ6
(V+IZ)ABZ6 (VIZ) (180 ) DA2 DOUT2
register
DB2 INH9
(VIZ)
Clock and
aspect PdA
MCK/8 control PdB
=68
=45 PdC
DIC0
PSBZ3
MCK Inhibits and
+5V MCK/5
SC
0V MRI
Figure 19: Zone 3 comparators (Lenticular)

QUADRAMHO Chapter 2
Appendix A
Page 20 of 71
Q1NHZ3A
(VIZ)AZ3 A1 INH1
OUT1 Comparator
IRA B1 & AZ3
(VIZ)ABZ3 A2
OUT2 Comparator
Shift B2 ABZ3
(V+IZ)ABZ3 (V+IZ)/90
register
Q1NHZ3B
(VIZ)BZ3 A1 INH1
OUT1 Comparator
IRB B1 & BZ3
(VIZ)BCZ3 A2
OUT2 Comparator
Shift B2 BCZ3
(V+IZ)BCZ3 (VIZ)/90
register
Q1NHZ3C
(VIZ)CZ3 A1 INH1
OUT1 Comparator
IRC B1 & CZ3
(VIZ)CAZ3 A2
OUT2 Comparator
Shift B2 CAZ3
(V+IZ)CAZ3 (V+IZ)/90
register
A1 INH1
OUT1
(VIZ)A B1
(VIZ)AG DA1 DOUT1 GA
DB1
(VIZ)ABZ3 A2
OUT2 Comparator
Shift B2 ABZ3
(V+IZ)ABZ3 (V+IZ)/90
register
A1 INH1
OUT1
MCK/8 (VIZ)B B1
(VIZ)BG DA1 DOUT1 GB
DB1
A2
(VIZ)C B2 OUT2
(VIZ)CG DA2
DB2 DOUT2 GC
+5V INH9
PdA
PdB
0V
PdC
DIC0
PSBZ3
MCK Inhibits and
MCK/5 control
SC
MRI
Figure 20: Zone 3 comparators (QUAD version)

QUADRAMHO Chapter 2
Appendix A
Page 21 of 71
Zone 3 A Comp 1 A1 (VIZ)AZ3 (VIZ)AZ3

B1 (V+IZ)A /(180) IAR+INR

B2 (V+IZ)AB /(180) (V+IZ)A /90

B1 (V+IZ)B /(180) IBR+INR

B2 (V+IZ)BC /(180) (V+IZ)BC /90

B1 (V+IZ)C /(180) ICR+INR

B2 (V+IZ)CA /(180) (V+IZ)CA /90
Zone 3R A Comp 4 A1 Not used IAR+INR

B1 (V+IZ)AZ3

B2 (V+IZ)ABZ6 /(180) (V+IZ)AB /90
Zone 3R B Comp 5 A1 IBR+INR

B1 (V+IZ)BZ3
Not applicable
Zone 3R C Comp 5 A2 ICR+INR
B2 (V+IZ)CZ3
Zone 3 A INH 1 DA1 (VIZ)AZ3

Comp DB1 (V+IZ)A /
Zone 3 AB INH 1 DA2 (VIZ)ABZ3

Comp DB2 (V+IZ)AB /
Zone 3 B INH 2 DA1 (VIZ)BZ3

Comp DB1 (V+IZ)B /
Not used
Zone 3 BC INH 2 DA2 (VIZ)BCZ3
Comp DB2 (V+IZ)BC /
Zone 3 C INH 3 DA1 (VIZ)CZ3

Comp DB1 (V+IZ)C /
Zone 3 CA INH 3 DA2 (VIZ)CAZ3

Comp DB2 (V+IZ)CA /
Figure 21a: Comparator inputs

QUADRAMHO Chapter 2
Appendix A
Page 22 of 71
A Guard Zone 4 DA1 (VIZ)AG

Not used
DB1 IAR+INR
Zone 6 AB IHN 4 DA2 (VIZ)ABZ6

Not used
Cop DB2 (V+IZ)AB
B Guard Zone 5 DA1 (VIZ)BG

DB1 IBR+INR
Not applicable
C Guard Zone 5 DA2 (VIZ)CG
DB2 ICR+INR
INHIBITS 13 INH1 G/F Lenticular QINH Z3 side lines

INH2
INH3 Not used Not used
INH4
INH5 DICO DICO
INH6 PSBZ3 PSBZ3
INH7 Common pole dead Common pole dead
INH8 Pole dead Pole dead
INH9 P/F Lenticular Not used
INHIBITS 4 INH1 QINH Z3A

INH2 PSBZ3
Not used
INH3
Not used
INH4
INH5 DICO DICO
INH6 Not used Not used
INH7 Pole dead A Pole dead A
INH8 Pole dead B Pole dead B
INH9 Z6 Lenticular Not used
INHIBITS 5 INH1 QINH Z3B

INH2 Pole dead B
INH3
Not used
INH4
INH5 Not applicable DICO
INH6 PSBZ3
INH7 Not used
INH8 Pole dead C
INH9 QINH Z3C
Figure 21b: Comparator inputs continued

QUADRAMHO Chapter 2
Appendix A
Page 23 of 71
1 1
2 2
3 3
4 K31 4 K31
9 5 9 5
8 7 6 8 7 6
0 0.1 0 0.1
0.4 0.4
0.9 0.3 K32 0.9 0.3 K32
0.8 0.4 0.8 0.4
0.7 0.6 0.5 0.7 0.6 0.5
1 5 1 5
K33 K33
.41
.67 a
b
1.0 b
Z3 = (K31 + K32)K33 X ZPh Z3 = (K31 + K32)K33 X ZPh

Z3 = (K35 + K36)K33 x K37 x ZPh Z3 = (K35 + K36)K33 x K37 x ZPh
1 1
2 2
3 3
4 K35 4 K35
9 5 9 5
8 7 6 8 7 6
0 0.1 0 0.1
0.4 0.4
0.9 0.3 K36 0.9 0.3 K36
0.8 0.4 0.8 0.4
0.7 0.6 0.5 0.7 0.6 0.5
.25 0.5 .25 0.5

1.0 1.0
K37 K37
Figure 22: Nameplate details RRM09

Zone 1
interrupt
gating
logic INT Port 1 S1
Memory input Sign wave to square EN socket
T1
QUADRAMHO
Memory input wave conversion Inoperative

P26 alarm circuits
common Inoperative S1
High set neutral current Comparator AB zone 6 P25 alarm outputs
SERVICE MANUAL
T0 Inoperative ENSB1
level detector B039
Microcontroller alarm input
Fault detected by DEF Port A0 8 bit 4k x 8 Phase
High set A S2
Contact breaker open PA1 latch D A aprom A P20P23 current Input ENSB1
Comparator CA zone 1 PA2 D D level B
buffer
Comparator BC zone 1 PA3 detectors C enable
Comparator AB zone 1 PA4 Enable Spare S3
Comparator CN zone 1 PA5 P27 ENSB1
Comparator BN zone 1 PA6 P24 Power swing
Comparator AN zone 1 PA7 S4
Block Z2T and Z3T Port B0 Code switch ENSB1
Reset
Zero sequence voltage level detector PB1 DB DB Reset enable
pulse monitor
Comparator CA zone 3 PB2
CSWX
Comparator BC zone 3 PB3 Programmable ENSB1
Reset 00 Enable filters
Comparator AB zone 3 PB4 peripheral 01 Disable filters
Comparator CN zone 3 PB5 interface 0 6 bit D Switch on to fault
Comparator BN zone 3 PB6 02 CSWY
D type flip enabled
Comparator AN zone 3 PB7 03 Pole dead A ENSB1
flop
Channel in service Port C0 CS 04 Pole dead B
Carrier received PC1 05 Pole dead C
Comparator CA zone 2 PC2 Reset
Comparator BC zone 2 PC3 Enable CSW
Port A0
Comparator AB zone 2 PC4 Enable SB1
PA1
Comparator CN zone 2 PC5 Enable SB2
PA2
Comparator BN zone 2 PC6 Enable SB3
PA3
Comparator AN zone 2 PC7 Enable SB4
PA4
PA5 Extended zone 1 reach
Reset PA6 3 phase trip
CS DB Enable SK1
CS PA7
Push button Port B0 C phase trip Port B0 FF Fuse fail indication
and push PB1 B phase trip PB1 SOTF Switch on to fault indication
button override PB2 A phase trip PB2 AT Aided trip indication
Programmable PB3 Block auto reclose Programmable PB3 Z3 Indications Zone 3 time delayed trip indication
peripheral PB4 Any comparator operated peripheral PB4 Z2 Zone 2 time delayed indication
interface 2 PB5 Power swing indication interface 1 PB5 C C phase fault indication
PB6 Self check in progress PB6 B B phase fault indication
Phase PB7 Master reset/invert comparators PB7 A A phase fault indication
N Port A0 Port CD0 Fuge fall Port C0 Amplitude hysteresis (trip)
Low set
C PA1 PC1 Switch on to fault PC1 C phase memory output
current level
B PA2 PC2 Aide trip PC2 Memory enabled
detectors 120 A phase memory output
A PA3 PC3 Zone 3 time delayed trip PC3 Power swing timer run out
PA4 PC4 Zone 2 time delayed trip PC4 Fault location Z3(PH) 120 B phase memory output
Over C PA5 PC5 Carrier received annunciation PC5 Fault location Z2(E)
voltage level B PA6 PC6 Any trip PC6 Fault location Z2(PH)
detectors A PA7 PC7 Carrier transmit PC7 Fault location Z1(PHLE)
Chapter 2
R5888C
Appendix A
Page 24 of 71
Figure 23: Block diagram board ZH0735

QUADRAMHO Chapter 2
Appendix A
Page 25 of 71
A phase Input amplifier

Summing Voltage Drop off Zero sequence voltage
B phase and low
circuitry comparator timer level detector output
C phase pass filter
ReplicaA High gain Input amplifier Voltage Drop off A phase high set current
phase amplifier and low comparator timer level detector output
pass filter
ReplicaB High gain Input amplifier Voltage Drop off B phase high set current
pass filter
ReplicaC High gain Input amplifier Voltage Drop off C phase high set current
pass filter
Fault
Input Optically Time Fault detected by DEF
detected
protection coupled isolator delay optical isotator output
by DEF
Circuit
Input Optically Time Circuit breaker open
breaker
protection coupled isolator delay optical isolator output
open
Block Z2T Input Optically Time Block Z2T and Z3T

and Z3T protection coupled isolator delay optical isolator output
Carrier
Input Optically Time Carrier channel in service
channel
in service
Carrier
Input Optically Time Carrier signal receive
signal
receive
Power swing S1A

(from scheme Block zone 1 comparators
logic) S1B
Block zone 2 comparators
S1C
Block zone 3 comparators
Power swing contact
Power swing Power S1D

swing Option switch 9
indication
indication (to scheme logic)
(from scheme logic)
Figure 24: Block diagram board ZH0736

QUADRAMHO Chapter 2
Appendix A
Page 26 of 71
Main loop
Enter
Call INIT Initialise processor
Commissioning Call load Read input ports

test options
Call POTIM Start pole dead timer
Call VTS
Call load 1
Call FLOC Establish fault locators
Call SOTF Switch on to fault
Call basic Run basic scheme
Scheme option select

Call OPT
PUR POR Block Z1E

(permissive underreach) (permissive underreach) (blocking scheme) (zone 1 extension)
Call MFAST Memory fast restart
Call PSMIS Miscellaneous functions
Call EXOP Extra minor options
Call ENF Enable band pass filters
Call output Output results
Figure 25: Main loop program flowchart

QUADRAMHO Chapter 2
Appendix A
Page 27 of 71
037
A
POWER SWING
B Z1
Z2
Z3
C SW9
Z2
RESET
Z3
AIDED
TRIP
TEST
SOTF Skt.1
V
FAIL
2560
1280
640
320 tZ2=St2ms
t2 160
80
40
20
5120
2560
1280
t3 640 tZ3=St3ms
320
160
80
48
24
tP 12 tP=Stpms
6
48
td 24 tD=Stdms
12
6
SW8
SW7
SW6
SW5
SW4
SW8
SW3
SW2
SW1
OPTION SELECT
X Y
Vx(2) V=
Figure 26: Nameplate details RCL10

QUADRAMHO Chapter 2
Appendix A
Page 28 of 71
Monitor facility Tripping function
Module test socket connections Inputs to PCB ZH0739
25 RL1-1
A IND B SK2 A IND CTX
RL1-2
24 RL2-1 Output
B IND B SK2 B IND Z1C(PH&E)
RL3-1 contacts
23 Z2(PH) from
C IND B SK2 C IND RL4-1
Z2(E) PCB
RL5-1
22 Z3(PH) ZH0743
Z2 IND B SK2 Z2 IND RL6-1
Trip A
21 RL5-2
Z3 IND B SK2 Z3 IND
Output
20 relays
AT IND B SK2 AT IND To 0V of 0V
relay coils common
19 from PCB
SOTF IND B SK2 SOTF IND
ZH0743
18 RL7-1
FF IND B SK2 FF IND Trip B
RL7-2
17 RL8-1
CTX B SK2 CTX Alarm
13 0V Output
BAR B SK2 BAR
RL9-1 contacts
12 FF from PCB
Trip 3PH B SK2 Trip 3PH RL10-1
PSB ANN ZH0742
11 RL11-1
Any trip B SK2 Any trip SOTF
RL12-1
Trip C
10 RL12-2
PSB ANN B SK2 PSB ANN
9 Output
CRX ANN B SK2 CRX ANN 0V relays
To 0V of
relay coils common
8
MEM EN B SK2 MEM EN and LED from PCB
ZH0741
7
TPS B SK2 TPS RL13-1
Trip 3PH
6 RL13-2
Z1 Z2 Z3 B SK2 Any Z1 Z2 Z3 RL14-1
AT Output
5 RL15-1
SOTF EN B SK2 SOTF EN BAR contacts
RL16-1
16 Z2 from PCB
+12V SK2 +12V RL17-1
Z3 ZH0741
RL18-1
15 Any trip
12V SK2 12V RL18-2
14
+5V SK2 +5V
Open Relay out
4 circuit of service
MCK/28 SK2 MCK/28
3
+24V SK2 +24V Short Relay in
2 circuit service
0V SK2 0V
0V
0V
0V
Figure 27: Auxiliary relay module RVC 53

Power supply ZRE01
QUADRAMHO
Plug
B
SERVICE MANUAL
Transformer
with isolation E +24V 1
Plug of 2KV for
A 1 minute Filtering
1 A +DC and
regulation F 0V 3
Input from 2 B
station Input
battery filter G +12V 2
to relay 4 C
earth stud Filtering
5 D and
regulation H 0V 4
6 N
Voltage Pulse width Switching J +5V 5

detector modulator transistor
Outputs to relays
Filtering
and
regulation K 0V 8
DC L 0V 7
Filtering
Secondary screen
and
regulation M 12V 9
Primary screen Core

Secondary
screen
PCB ZG0911
Chapter 2
R5888C
Appendix A
Page 29 of 71
Figure 28: Power supply block diagram

QUADRAMHO Chapter 2
Appendix A
Page 30 of 71
V = IZ
Fault outside
characteristic
IZ Fault on boundary
Fault inside
characteristic
V = IZ
IR
VPOL = V 90
Figure 29: Sequence comparator voltages for MHO characteristic
A B A B
Sine wave
inputs
A + V IZ
B = V 90
Squared A A
inputs
B B
Logic states AB AB AB AB AB AB AB AB AB AB
Restrain condition Operate condition
Figure 30: Comparator logic variables

QUADRAMHO Chapter 2
Appendix A
Page 31 of 71
Fault occurs
AB AB AB AB AB AB AB AB AB AB AB AB AB
4
3
2
Counter 1
Figure 31: Action of counter in comparator

QUADRAMHO Chapter 2
Appendix A
Page 32 of 71
Sinusoidal V IZ input
Burst of
Squared inputs interference
V IZ A
V B
POL
Counter
0 0
No of second up-count as
changes spaced <0.15 cycle
Figure 32: Effect of high-frequency interference
Fault occurs
outside
boundary of
operation
Sinusoidal
V IZ
input
V IZ A
Squared V
inputs POL B
1
Counter
0 0
No second up-count as
changes spaced <0.15 cycle
Figure 33: Effect of expotential offset

QUADRAMHO Chapter 2
Appendix A
Page 33 of 71
start
Read inputs
Yes No
Is reset input Is selfcheck Reset all registers Finish timer
high input high and output
No Yes
Has A or B
changed state
No
Yes
No Yes
Has input A Does B=A
changed
Yes No
No
Does A=B
Yes
A3
Fig 34 A
A2
A1
A4
Fig 34 A
Fig 34 A Fig 34 A
Figure 34: Flowchart of sequence comparator

QUADRAMHO Chapter 2
Appendix A
Page 34 of 71
Fig 34A
Fig 34A
Fig 34A
Fig 34A A4
A1
A3
A2
Yes Yes
Is selfcheck Is reset
input high input high
Yes No No
Is selfcheck Is reset
input high input high
Yes
No No
Yes
Is inhibit
Re-start timer
output high
No
No
Is timer finished
Finish timer
Yes
No
Is register
Set register
1 set No
Is register
Yes 1 set
B1 Yes
B2
Fig 34B
B4
B3
Fig 34B
Fig 34B
Fig 34B
Figure 33a: Flowchart of sequence comparator

QUADRAMHO Chapter 2
Appendix A
Page 35 of 71
Fig 34B Fig 34B Fig 34B Fig 34B
B1 B2 B3 B4
No No
Set register 2 Is register Is register Reset register 1
2 set 2 set and output
Yes Yes
No No
Is register Is register Reset register 2
Set register 3
3 set 3 set
Yes Yes
No
Set register 4 Is register
3 set Reset register 3
Yes
Set output Reset register 4
Figure 33b: Flowchart of sequence comparator

QUADRAMHO Chapter 2
Appendix A
Page 36 of 71
V 63 BIT V90
SHIFT
REGISTER
252 x fn
CLOCK
PULSE
REGISTER
Figure 35: Polarising phase shift

QUADRAMHO Chapter 2
Appendix A
Page 37 of 71
Fault incidence
Fault
phase
voltage
CVT error
16% synchronous polarising
Polarising voltage
(Before squaring and 90 phase shift)
Figure 36: Action of synchronous polarising

QUADRAMHO Chapter 2
Appendix A
Page 38 of 71
Figures are in SIRs
0 1 6 12
24 60
Figure 37: Resistive expansion of partially cross-polarised MHO
4
X
17ms 21ms 30ms 60Hz times

2 24ms 34ms 50Hz times
19ms
=75
1 2 3 4 5 6 7 8
R
Minimum operating time contours SIR = 6
Figure 38: Typical MHO Zone 1 operating times

QUADRAMHO Chapter 2
Appendix A
Page 39 of 71
(VB + VC)
E
R4 VKA = (VB + VC) + 0.16VMA
R3
0.16VMA
ICI
VMA +
VB
VC VB
R2 R6
+
VB + V C
R1
R5 E PARTIALLY CROSS-POLARISED SIGNAL

VC VQA = VA + 0.16VKA
VA
Figure 39: AG polarising mixing circuit
VKA VA
VNA = (VA + 0.16VKA) 90

R6
+
90 90
0.16VKA
IC2 R11 VNA
R5
VA
R12 VB V C
VB
VC
R10
+ IC3

R9 PARTIALLY CROSS-POLARISED SIGNAL
VQBC = VB VC + 0.16VNA
E
Figure 40: BC polarising mixing circuit

QUADRAMHO Chapter 2
Appendix A
Page 40 of 71
140 Faulted voltage = 25%

Angle of resultant polarising signal
[LAG] relative to pre-fault position
120
100% self polarised

100
80
60 16% squarewave
cross polarised
40 16% squarewave
cross polarised
20 100% cross polarised

0
0 20 40 60 80 100 120 140
Displacement of faulted-phase voltage [LAG]
relative to pre-fault position
Angle of pre-fault voltage

X
Fully cross polarised
mho circle
Characteristic

R
Extra resistive
coverage
Conventional
16% partially
cross polarised
mho circle
Figure 41: Comparison of polarised characteristics

QUADRAMHO Chapter 2
Appendix A
Page 41 of 71
30
16% A
16% B
C
16%
90 180 270 360 etc.
A Faulted phase voltage [30 displacement]
B Cross-polarising voltage
C A + B
Resultant polarising
D
[before 90 phase shift]
Figure 42
QUADRAMHO Chapter 2
Appendix A
Page 42 of 71
60
16% A
16% B
16% C
20
90 180 270 360 etc.
A Faulted phase voltage [-60 displacement]
B Cross-polarising voltage
C A + B
Resultant polarising [20 displacement]

D
[before 90 phase shift]
Figure 43
QUADRAMHO Chapter 2
Appendix A
Page 43 of 71
Elapsed time
Input
55 55 56 55 54
Synchronism checked
'Data in' is every 4th edge and
measured adjusted bit
length of 1/2- Output
cycle in units 56 55 55
of 179 ms 1/2 cycle generated
DATA IN using 'data out'
DATA OUT
55
55
56
55
55 55 56 55 54 55 55
Rotation
anticlockwise
Figure 44: Synchronous polarising healthy live line conditions
Output 56 55 55
1/2 cycle generated using
'data out'
DATA OUT
55
Rotation 55
55
reversed 41 25 39 55 54
13 55 55 56
Figure 45: Synchronous polarising faulty line conditions

QUADRAMHO Chapter 2
Appendix A
Page 44 of 71
jIX
IZ
V
IZ
V+IZ
IR
IZ'
(V+IZ') /90
Figure 46: Sequence comparator voltages for offset MHO characteristic
jIX
Main
comparator C1
Inhibit comparator C2
V IZ
IZ
180
V + IZ
IR
IZ

180
(V+IZ')/
(V+IZ') /(180)
Figure 47: Lenticular characteristics

QUADRAMHO Chapter 2
Appendix A
Page 45 of 71
a 1
=
b tan(180 )
2
Aspect ratio
a b
= 1.00 0.67
b 0.41
= 90 65.5 45 a
Boundary of load
Figure 48: Lenticular Zone 3
V IZ
A2 A1
Inhibit Inhibit Main

comparator Inverter comparator
C2 C1
B2 B1
V + IZ' Phase
Phase shift
shift
(1802)
(V + IZ'/(180)
Figure 49: Lenticular characteristic block diagram

QUADRAMHO Chapter 2
Appendix A
Page 46 of 71
IX A1 = V IZ
B1 = INR
IZ
A2 = V IZ
A3 = IZ B2 = IZ
B3 = V+ IR

IR
I
IR
A4 = IZ
B4 = VPOL
Figure 50: Quadrilateral Zone 1
4
X
3
21ms 25ms 30ms 34ms 60Hz times
24ms 29ms 34ms 39ms 50Hz times
2
1
= 75
1 2 3 4 5 6 7 8
R
Minimum operating time contours SIR = 6
Figure 51: Typical quadrilateral Zone 1 operating times

QUADRAMHO Chapter 2
Appendix A
Page 47 of 71
B-G ZONE 1
B-G
GUARD
X
APPARENT
FAULT
Z1 IMPEDANCE
NB: APPARENT TILTING OF

CHARACTERISTIC ANGLE IS DUE TO
RESIDUAL COMPENSATION APPLIED
WHICH IS CORRECT FOR SINGLE PHASE
FAULTS
A-G ZONE 1
A-G GUARD
Z1
APPARENT
FAULT X
IMPEDANCE
Figure 52: Behaviour for ABG fault

QUADRAMHO Chapter 2
Appendix A
Page 48 of 71
GUARD ZONE A
INHIBIT ZONE 1 A-G
& &
POLE DEAD A
GUARD ZONE B
& EX.OR & INHIBIT ZONE 1 B-G
POLE DEAD B
GUARD ZONE C
& & INHIBIT ZONE 1 C-G
POLE DEAD C
Figure 53: Guard Zone logic
IX
A1 = V IZ
B1 = IPHR + INR
IZ
A3 = IZ A2 = V IR
B3 = V+ IR B2 = IZ
IR
IZ'
A5 = IPHR + INR
B5 = V+IZ'
Figure 54: Quadrilateral Zone 3

QUADRAMHO Chapter 2
Appendix A
Page 49 of 71
COMPARATOR
V IZ A
B
180>arg( )>0
A
VPOL B
LEVEL & TRIP

DETECTOR
IZ |IZ| >SETTING
Figure 55: Gating of comparator output
VIN
t1 t2
VREF
START
IS
MODULUS OF NO IS
RESET TIME t1 TIMER t2
INSTANTANEOUS VALUE OF
RESET FLAG RUNNING?
VIN > VREF ? YES
YES NO
YES SET OUTPUT LOW

IS FLAG SET?
NO RESTORE VREF
IS NO HAS NO
TIMER t1 TIMER t1
RESET ? FINISHED?
INITIAL CONDITIONS
YES FLAG RESET
SET FLAG TIMERS RESET
START TIMER t1 RESET TIMER t2 VREF NORMAL
START TIMER t2 OUTPUT LOW
LET VREF=VREF X 0.9
SET OUTPUT HIGH
Figure 56: Level detector

QUADRAMHO
SERVICE MANUAL
CURRENT LEVEL
DETECTOR
IZ |IZ| >SETTING
LEVEL DETECTOR
POLE-DEAD
22ms SIGNAL
1 TO
VOLTAGE LEVEL 0
DETECTOR INHIBIT
COMPARATORS
V |V|>SETTING
Chapter 2
R5888C
Appendix A
Page 50 of 71
Figure 57: Inhibition of comparators

QUADRAMHO Chapter 2
Appendix A
Page 51 of 71
PRECISION FULL WAVE

RECTIFIER
IZA +
FAST CHARGE
SLOW CHARGE
VREF
HIGH SET
IZB +

VREF
LOW SET
IZC +
LIMITS MAXIMUM VALUE
OF VREF
BASE REFERENCE
LEVEL
BIASED REFERENCE LEVEL
GROUND-FAULT
HIGH-SET NEUTRAL
10 COMPARATORS ENABLED
CURRENT DETECTOR
(Slope = 0.76)
|NEUTRAL CURRENT | + In (AMPS)
LOW-SET NEUTRAL
CURRENT DETECTOR
1
0.16
0.1
PHASE-FAULT
COMPARATORS
ENABLED
(Slope = 0.1)
0.02
0.1 1 10 34 100
GREATEST |PHASE DIFFERENCE CURRENT|+ In (AMPS)
Figure 58: Biased neutral current level detectors

QUADRAMHO Chapter 2
Appendix A
Page 52 of 71
X Zone 6
Inhibit Zone 3
signal PS
turns off
Inhibit
signal PS
turns on
Power swing
impedance
R
Figure 59: Power swing blocking characteristic
1 Sw9
0 P.S.B Ind
Any Pole 0
240
Dead ms 1 R SK TPS
VTS Block Q 1 SK2-7
Current Detector S
LDLSN
Inhibit Power swing 50ms S
SK PS
Blocking Opto & & Q 1
0 R SK2-10
Current Detector
LDLSA Power Swing Alarm
&
Current Detector 95-1
LDLSB PSB Z1 Inhibit
Z6ABComparator
PSB Z2 Inhibit
Any Z1,Z2 or Z3 Comparator
Z3ABComparator PSB Z3 Inhibit

0
Figure 60: Power swing blocking logic

QUADRAMHO Chapter 2
Appendix A
Page 53 of 71
Core 1 R Core 2
Angle coil 2
Input current Output voltage

Primary 2
F Fixed flux from

primary 2
=
F + V
Locus of total
Variable flux in core 2
flux from
angle coil 2
Locus of V
Figure 61: Flux summation in transphasor

MINIATURE CIRCUIT BREAKER OPEN
ALL POLES DEAD 1
Sw3
QUADRAMHO
0 55.5
V.I.S. VOLTAGE
0
SERVICE MANUAL
DETECTOR LDVO 15ms & & 0 V.T.S BLOCK

CURRENT DETECTOR
1 W.I.
LDLSN
&
1 & Q
1 V.T.S BLOCK
R
1 COMP.
&
ANY Z1,Z2 OR Z3 COMPARATOR

R S
& Q 1 Q
RELAY (97Y-1)
S R 1
& INOPERATIVE
20ms V.T.S IND

0
ANY POLE DEAD & 1 (97X-1)
0
240ms
RESET
Chapter 2
R5888C
Appendix A
Page 54 of 71
Figure 63: Voltage transformer supervision and miniature circuit breaker

VOLTAGE DETECTOR LDOVA
22ms
ANY POLE DEAD
CURRENT DETECTOR LDLSA
1 0
1
QUADRAMHO
SERVICE MANUAL
POLE DEAD A
VOLTAGE DETECTOR LDOVB

22ms
CURRENT DETECTOR LDLSB

1
0 POLE DEAD B
VOLTAGE DETECTOR LDOVC

22ms
POLE DEAD C
CURRENT DETECTOR LDLSC
1
0
0.2ms
COMPARATOR
BREAKER OPEN OPTO
& RESET PULSE
0
ALL POLES DEAD

& 1
Chapter 2
R5888C
Appendix A
Page 55 of 71
Figure 64: Level detector pole dead logic

QUADRAMHO Chapter 2
Appendix A
Page 56 of 71
CURRENT DETECTOR
LDLSN
COMPARATOR LDCpAZn
CpAZn &
CURRENT DETECTOR
LDLSA &
COMPARATOR LDCpBZn
CpBZn &
CURRENT DETECTOR ZnA

LDLSB & 1
COMPARATOR LDCpCZn
CpCZn &
CURRENT DETECTOR ZnB

LDLSC & 1
COMPARATOR LDCpABZn
CpBCZn &
ZnC
& 1
COMPARATOR LDCpBCZn
CpAZn &
ZnN
& 1
COMPARATOR LDCpCAZn
CpCAZn &
VAT BLOCK
& n refers to Zone (1, 2or 3)
CURRENT DETECTOR
LDLSN
n=1
35ms or n = 2 n=3
ZnN & &
0 0
Figure 65: Level detector gating of comparators

QUADRAMHO
SERVICE MANUAL
0.15ms
INHIBIT COMPARATORS
&
VOLTAGE DETECTOR LDOVA
VOLTAGE DETECTOR LDOVB 14ms 0.05ms

& & ENABLE BANDPASS
0 0 FILTERS
VOLTAGE DETECTOR LDOVC
ANY POLE DEAD

Chapter 2
R5888C
Appendix A
Page 57 of 71
Figure 66: Bandpass filter switching logic

QUADRAMHO Chapter 2
Appendix A
Page 58 of 71
C B A1 95z-1 B1
Phase rotation Reset Z1 ext A2 B2 Signal send (1)
A3 95z-2 B3
Breaker open B4 Signal send (2)
(See note 2) A4
A5 94A-1 B5
Direction of power flow Inhibit power swing blocking B6 Trip A (1)
for operation (See note 2) A6
94A-2 B7
A7 B8 Trip A (2)
P2 P1
A Channel in service A8 94B-1 B9
S2 S1 A9
B B10 Trip B (1)
Signal receive A10 94B-2 B11
C
A11 IZ1 B12 Trip B (2)
Va 94C-1 B13
A13 IZ2
VT secondaries Vb A15 IZ3
B14 Trip C (1)
Vc 94C-2 B15 See note 7
Vn A12 IZ4 B16 Trip C (2)
ac ve A17 IZ5 94T-1 B17
A18 IZ6 B18 Trip 3PH (1)
ac ve 94T-2 B19
A19 IV1 B20 Trip 3PH (2)
A20 IV2 94-1 IZ7 B21
IZ8 B22 Any trip (1)
A21 IV3 94-2 B23
A22 IV4 B24 Any trip (2)
A23 IV5 96-1 B25
A24 IV6 B26 Block A/R
A25 IV7 19A-1 C1
A26 IV8 B2 Fault locator A
19B-1 C3
C4 Fault locator B
Output 19C-1 C5
0V IZ10 C6 Fault locator C
relays
common 19E-1 C7
(See note 4) C8 Fault locator ground fault
Z2-1 C9
C10 Zone 2 trip alarm
Z3-1 C11
(See note 5) 94V-1 C13
C14 Aided trip alarm
98-1 C15
C16 SOFT trip alarm
97X-1 C17
C18 Fuse fail alarm
95-1 C19
C20 Power swing alarm
97Y-1 C21
Relay inoperative alarm
C22
(See note 3)
Notes:
1. Heavy duty connectors 3. Under healthy operating conditions this contact is held open.
a) Closes when heavy duty connector is removed. 4. Removal of IZ heavy duty connector disables all auxiliary relay
output contacts and closes relay inoperative alarm.
b) Opens when heavy duty connector is removed. 5. Connectors shown are typical only.
c) Opens after operation of a) and b) when heavy 6. When busbar VTs and a single phase tripping scheme
duty connector is removed. incorporating P.S.B. are used this opto must be energised
during single pole dead times.
2. Breaker open opto must be connected if busbar VTs are
7. When 3 phase tripping scheme is used Trip A, Trip B, Trip C
used or if the weak infeed or echo features of the permissive
and Any Trip respond as Trip 3 Phase.
overreach scheme are required. CB auxiliary contacts must
be connected in series to indicate all poles open.
Figure 67: External connection diagram: Quadramho static distance protection relay
1 and 3-phase tripping
Z1A Z1A'
Z1B Z1B'
Z1C Z1C'
QUADRAMHO
0 CRX Ann.
CRX
SERVICE MANUAL
& & & & 1 SK2-9

100ms
CTX
Z2A
& S Aided Trip A

Q
R
Z2B
& S Aided Trip B

Q
R
Z2C
& S Aided Trip C

tZ2
Q
1 & R
0
1
SOTF En Z2t
Z3A
tZ3 Z3t
Z3B 1 &
0
Z3C
Chapter 2
R5888C
Appendix A
Page 59 of 71
Figure 68: Permissive underreach scheme

Z1A Z1A'
Z1B Z1B'
Z1C Z1C'
QUADRAMHO
1 & & & S AIDED TRIP A

& Q
R
SERVICE MANUAL
Z2A
Z2B & S AIDED TRIP B
Q
Z2C R
tZ2 tp
1 & 0 & td & S AIDED TRIP C
Q
1 R
SOTF EN.
CRX
Z3A Z2t
Z3B
tZ3 Z3t
1 & 0
Z3C
60ms 100ms CTX
BREAKER OPEN 0 & 1 tp & 1
CTX WI
CURRENT DETECTOR LDHSA & &

1 CRX ANN.
1 SK2-9
CURRENT DETECTOR LDHSB & 1
1
CURRENT DETECTOR LDHSC
&
1
1
Sw8 0
Chapter 2
R5888C
Appendix A
Page 60 of 71
Figure 69: Permissive overreach scheme

Z1A
Z1B
Z1C 1
QUADRAMHO
Z2A
SERVICE MANUAL
0 S
Z2B
1 1 & Q
Z2C 100ms R
Z3A
Z3B
Z3C
1
0 10ms
C.R.X. CTX WI
& &
100ms 0
BREAKER OPEN
SW8 SW7
VTS BLOCK WI 1 0
60ms
LDOVA 0
LDOVB
& &
LDOVC WEAK INFEED
AIDED TRIP
VOLTAGE DETECTORS
Chapter 2
R5888C
Appendix A
Page 61 of 71
Figure 70: Week infeed feature POR scheme

Z1A Z1A'
Z1B Z1B'
Z1C Z1C'
QUADRAMHO
0 CRX Ann.
CRX
SERVICE MANUAL
td
1 & & & 1 Sk2-9
Current Detector
LDHSA &
Z2A
Current Detector tp
S Aided trip A
& Q
LDHSB & 1 0 & R
Z2B
S Aided trip B
Current Detector & Q
LDHSC & & R
Z2C
S Aided trip C
tZ3 & Q
C.I.S. R
1 & 0
1 CTX
S.O.T.F.En
Z2t
Z3A tZ3
Z2t
Z3B & 0
Z3C
1
Chapter 2
R5888C
Appendix A
Page 62 of 71
Figure 71: Blocking scheme

Z2t
Z3t
S.O.T.F Any trip
1 1 94-1, 94-2
Weak infeed aided trip
QUADRAMHO
SERVICE MANUAL
C.I.S. 60ms
3 Phase trip
P.U.R. P.O.R. or 1 &
block scheme & 1 0 1 94T-1, 94T-2
Majority
T.S.N. for 3 phase trips only 1 function &
Z1A' S
Q TRIP A Outputs
Aided trip A
1 1 & R 94A-1, 94A-2
1
Z1B' S
TRIP B Outputs
Aided trip B Q
1 1 & R 94B-1, 94B-2
Z1C' S
TRIP C Outputs
Aided trip B Q
1 94C-1, 94C-2
1 & R
Chapter 2
R5888C
Appendix A
Page 63 of 71
Figure 72: Trip output logic

Z1A'
Z1B'
QUADRAMHO
Z1C'
&
SERVICE MANUAL
Aided trip A 1
Aided trip B
SW4
Aided trip C
&
0V
Z2t
0
Z3t BAR Output
1 100ms 961
S.O.T.F.
0.1ms R
Q
Weak infeed trip
0 & & S
Voltage Det. LDOVA
Voltage Det. LDOVB SW6
Voltage Det. LDOVC

1 &
0
P.U.R. P.O.R. or block scheme
C.I.S.
Chapter 2
R5888C
Appendix A
Page 64 of 71
Figure 73: Block auto-reclose logic

QUADRAMHO Chapter 2
Appendix A
Page 65 of 71
1
Z1A'
Z2A
&
1 &
1
LDLSA FLA
LDOVA
Z1B
& &
19A-1
Z2B
&
1 &
1
LDLSB FLB
LDOVB
Z1BC
& &
19B-1
Z2C
&
1 &
1
LDLSC FLC
LDOVC
Z1N
& &
19C-1
Z2N
1 &
1
FLN
LDLSN
19E-1
S.O.T.F
& &
S.O.T.F.En
&
SW16
0
Figure 74: Fault locator logic

110ms
0
SW2 S
QUADRAMHO
Q
SERVICE MANUAL
200ms
1 R
0 S.O.T.F.En
All poles dead & 1
0
240ms
1
Current detector LDLSA
Voltage detector LDOVA
&
Current detector LDLSB 20ms
MCB S.O.T.F.
Voltage detector LDOVB Open 981
& 1 0 &
SWLA
Current detector LDLSC
Voltage detector LDOVC
&
Any Z1, Z2, or Z3 Comparator
Chapter 2
R5888C
Appendix A
Page 66 of 71
Figure 75: Switch on to fault logic

QUADRAMHO Chapter 2
Appendix A
Page 67 of 71
Z1A'
Z2A
&
Z3A
& 1 S
Q
R
A
SK2-25
Z1B'
Z2B
& S
R
B
Z3B
& 1 Q SK2-24
Z1C'
S
Z2C R C
& Q SK2-23
Z3C'
& 1
S
Z2t R Z2
Q SK2-22
Z3t
Aided trip A
Aided trip B S Z3
Aided trip C R
Q SK2-21
Weak infeed aided trip

1 S
Q
R
Aided trip
SK2-20
S.O.T.F.
V.T.S. Ind
Reset button S
SK1-9
Any trip
& Q
R S.O.T.F.
SK2-19
& 1
0.1ms
0 S V-Fail
R
Q SK2-18
P.S.B. Ind S Power

R
swing
Q
Figure 76: Indication logic

Socket used by automatic Socket monitoring
in-situ tester internal signals
QUADRAMHO
SERVICE MANUAL
Trip indication and

test lamps
Sockets for secondary

injection and trip
monitoring
X Y
Thumbwheel switches to select

scheme or test option
Chapter 2
R5888C
Appendix A
Page 68 of 71
Figure 77: Some test features of Quadramho

QUADRAMHO Chapter 2
Appendix A
Page 69 of 71
ms ms
Ground faults quadrilateral Ground faults mho
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0 20 40 60 80 100 0 20 40 60 80 100
% of relay setting % of relay setting
ms ms
Phase faults mho 3-phase faults mho
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0 20 40 60 80 100 0 20 40 60 80 100
maximum
minimum
Figure 78: Zone 1 typical operating times for 50Hz relays at SIR 30
QUADRAMHO Chapter 2
Appendix A
Page 70 of 71
ms ms
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0 20 40 60 80 100 0 20 40 60 80 100
ms ms
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0 20 40 60 80 100 0 20 40 60 80 100
maximum
minimum
QUADRAMHO Chapter 2
Appendix A
Page 71 of 71
ms ms
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0 20 40 60 80 100 0 20 40 60 80 100
ms ms
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0 20 40 60 80 100 0 20 40 60 80 100
maximum
minimum
Type SHPM 101
Service Manual
Chapter 3
Electronic Module Housing
Type SHPM101
Service Manual
Chapter 4
Installation
QUADRAMHO Chapter 4
Contents
1 INSTALLATION 1
1.1 Receiving 1
1.2 Handling 1
1.3 Storage 1
1.4 Installation 1
1.5 Rack mounting 1
1.6 Panel mounting 1
1.7 Earthing 1
QUADRAMHO Chapter 4
Page 1 of 1
Section 1. INSTALLATION
1.1 Receiving
Remove the relay from the container in which it is received and inspect for obvious
damage. If damage has been sustained in transit, a claim should be made
immediately to the transport company concerned and a report sent to the nearest
ALSTOM T&D Protection & Control Ltd branch office or agent.
1.2 Handling
The relay in its case is extremely robust and no special precautions are necessary.
However, to prevent the ingress of dirt, it is strongly advised that modules are not
removed from the case.
1.3 Storage
If not required for immediate use, return the relay to its original wrapper and
carton and store in a clean dry place. The silica gel unit supplied with relays
delivered outside the United Kingdom should be heated at 60 70C for one
hour before being replaced.
1.4 Installation
Relays should be installed in a location free from excessive vibration.
The relay cases can be supplied for either rack or panel mounting.
1.5 Rack mounting
Relays for rack mounting are supplied in cases designed for housing in standard
19 inch (483mm) racks.
1.6 Panel mounting
Relays can be supplied for either flush or semi-projecting panel mounting.
Panels should be vertical to within 5. Dimensions, fixing details and cut out sizes
for the cases are shown in the relevant case outline drawing.
Flush mounted relays are inserted from the front into the panel cut out and secured
by means of the clamps provided which are bolted to tapped bosses at the back of
the case. The clamps are adjustable to accommodate different panel thicknesses.
Semi-projecting mounted relays are fitted with an extending collar and are secured
using the same clamps as described for flush mounted relays.
When installation is complete the relays must be set up and commissioned as
described in relevant instruction.
1.7 Earthing
The relay case earthing terminal on the rear of the relay case (see Figure 3,
Chapter 2) must be connected to earth (ground).
Type SHPM101
Service Manual
Chapter 5
Commissioning Instructions
QUADRAMHO Chapter 5
Contents
1. GENERAL 1
2. TEST EQUIPMENT REQUIRED 1
3. PRELIMINARY INSTRUCTIONS 2
3.1 Wiring check 2
3.2 Insulation test 2
3.3 Module data check and information on the ratings label 2
4. SECONDARY INJECTION TESTS 3
4.1 Settings 3
4.2 Isolation 3
4.3 Initial shecks, including self-check facilities 4
4.4 Level detector checks 4
4.4.1 Voltage level detectors 4
4.4.2 Fixed current level detector checks 5
4.4.3 Auto ranging low set and high set residual current level detectors 6
4.5 Zone 1 reach tests 6
4.5.1 Connections and preliminaries 6
4.5.2 Ground faults zone 1 7
4.5.3 Phase faults 8
4.6 Zone 2 reach tests 8
4.7 Zone 3 reach checks 8
4.8 Resistive reach check 9
4.9 Zone 1 operation times 9
4.12 Power swing blocking checks 10
4.12.1 Zone 6 boundaries 10
4.12.2 50ms timer check 11
4.12.3 Simulated power swing with blocking checks 11
4.13 Voltage transformer supervision 11
4.13.1 Operation on zero sequence volts 12
4.13.2 Timing check 12
4.13.3 Current checks 12
4.13.4 Instantaneous indication or blocking check 12
4.13.5 Miniature circuit breaker block check 12
4.14 Switch-on-to-fault check 13
4.15 Memory feature check (synchronous polarising) 14
4.16 Check on function of SW4 (if auto-reclose is used) 14
4.17 Trip test function check 14
5. SCHEME TESTS 15
5.1 Zone 1 extension scheme (08 or 09) 15
5.2 Permissive underreach scheme (02 or 03) 15
5.2.1 Aided trip check 15
5.2.2 Signal receive delay on drop-off 15
5.2.3 Signal send checks 15
5.2.4 Signal receive check 16
QUADRAMHO Chapter 5
Contents
5.2.5 Block auto reclose checks 16

5.3 Blocking scheme (06 or 07) 16
5.3.1 Measurement of tD 17
5.3.2 Aided trip and tp check 17
5.3.3 Signal send check 17
5.4 Permissive overreach scheme (04 or 05) 18
5.4.1 Aided trip check 18
5.4.2 Signal send check 18
5.4.3 Measurement of tp 18
5.4.4 Measurement of tD 19
5.4.7 Echo feature 19
5.4.8 Weak infeed feature 20
5.5 Signalling Channel Check (Schemes 02 to 07) 20
6. LIVE SYSTEM CHECKS 21
6.1 Signalling channel check 21
6.2 Trip test 21
6.3 Final setting checks 21
6.4 On load tests 21
6.4.1 Voltage transformmer checks 21
6.4.2 CT/VT phasing check 21
6.4.3 Directional check 22
APPENDIX A FIGURES
ADDENDUM 1 CALCULATION OF REACH SETTINGS
ADDENDUM 2 COMMISSIONING TEST RECORD
ADDENDUM 3 NEW RECOMMENDATIONS FOR TIMER SETTINGS IN THE
CURRENT REVERSAL GUARDS
ADDENDUM 4 USE OF DOBLE TEST TO COMMISSION QUADRAMHO
QUADRAMHO Chapter 5
Page 1 of 24
Section 1. GENERAL
The commissioning engineer should be supplied with all the required settings for
the relay; a chart is provided for this purpose in the application notes.
If all settings are not supplied, there are worked examples in the application notes
for guidance. (Addendum 1 provides guidance for zone reach setting
calculations).
Some specific information is given for using the ZFB distance test set but sufficient
general information is given to enable experienced commissioning engineers to
understand how to perform the tests using other suitable equipment.
An addendum on using the ZFB is included for those not familiar with the test set.
The importance of using dynamic testing is mentioned, although it may be
considered that sufficient testing of this type is done before the equipment is
despatched and it may not be really necessary for on-site tests. Some tests
described can only be carried out with dynamic testing.
Section 2. TEST EQUIPMENT REQUIRED
The Quadramho Accessory Kit 01 which contains:

2 heavy current test plugs.
1 monitor point box (25 way) with connecting plug.
1 conductive wrist strap and earthing lead.
2 module extractor tools.
2 anti-static conductive bags.
1 two tier extender card with edge connectors at 0.1 inch pitch centres.
(This is only required for problem analysis).
1 ZFB test set or alternative suitable equipment eg. Jodice F3D.
1 Interval timer (one that can work off contacts or 24V levels and has a dwell
facility).
2 Multimeters (20,000 ohms per volt on dc range).
1 Variable auto transformer capable of supplying
1 Variable resistor 0 200 ohms relay rated current.
1 Double pole switch.
2 Single pole switches.
1 Phase rotation meter.
1 Phase angle meter (with appropriate current sensitivity for on load check).
1 Electronic insulation tester (If the commissioning engineer has to perform
insulation tests).
It may be useful to have light current leads with snap-on connectors
(4.8mm x 0.8mm cross section) on one end.
QUADRAMHO Chapter 5
Page 2 of 24
Section 3. PRELIMINARY INSTRUCTIONS
3.1 Wiring check

Check all panel wiring against the scheme wiring diagram. (The general relay
external connection diagram is supplied with these instructions but it may not be
the latest issue).
3.2 Insulation test
This test may be done by the main plant contractor at an earlier date. An electronic
or brushless insulation tester should be used having a dc output not exceeding
1000 volts.
Deliberate circuit earthing links removed for these tests must subsequently be
replaced. The relay and its associated wiring may be insulation tested between:
a) All electrically isolated circuits
b) All circuits and earth
Accessible terminals of the same circuit should first be strapped together.
3.3 Module data check and information on the ratings label
i) Remove the front cover by lifting the sliding catches on the sides of the cover.
ii) The heavy current bridging plugs 1Z and 1Y can then be removed; this puts a
short on all the incoming CT circuits and isolates the equipment from the ac and
dc voltage supplies.
iii) The lower interlock bar can then be moved to the right and modules 1 and 2
removed with the extractor tool.
The modules should only be handled as described in Chapter 4. (ie. the handler
earthed by the wrist strap and only the board edges or front plate held).
iv) The rating card is now exposed in the top left hand side of the case, the
information on this incudes:
a) Ratings for frequency, current, ac volts, auxiliary dc supplies Vx(1) and
Vx(2).
b) A list of the 2 alpha identification numbers for the seven modules that can be
extracted and the power supply mounted on the back of the equipment.
These are of the form RRZ 07 000 000, on the module frontplate. There will
also be another letter at the end which indicates if any changes have been
made since the A issue.
c) The external connection diagram number; two sheet numbers are given; one
being for single and 3 phase tripping and the other for 3 phase tripping
only.
d) The 4 alpha number for the relay of the form:
QUADRAMHO Chapter 5
Page 3 of 24
SHPM101 '000'000'000 A
Meaning Relay Case None A is the first issue and other letters
Wiring indicate minor case changes
Case Mounting Type Sequential number for various combinations

R = Rack of 3 alpha module numbers 000 to 200 for
F = Flush relays with Quad characteristic 201 to 400
S = Semi-protection for relays with lenticular Zone 3.
v) Check that all the front plate information of each module relevant to that on the
rating card agree and that they are correct for the actual system.
Note: Vx(1) is given on the back of the case.
vi) Inspect each module and the case to see that no damage has occurred during
transit. Check that the serial number painted on one printed circuit board of
each module agrees with that on the hinged label at the bottom left hand side
of the front of the case.
Make sure all modules are correctly re-inserted and the interlock bars are moved
back to their left hand position.
Section 4. SECONDARY INJECTION TESTS
4.1 Settings
All settings on Quadramho are by means of switches and should now be put on
the relay. It is important that the setting chart is kept correctly marked as it is
necessary to vary the positions of some of the switches during the commissioning
tests.
As many tests as possible are done in the scheme option number selected by
switches X and Y on Module 4. The use of test option numbers will be described as
necessary.
The result sheets provided in Addendum 2 should be used.
4.2 Isolation
All the relay contacts can be prevented from operating while the rest of the relay
functions normally and gives indications, also signals for operation times could be
taken from the monitor point box. It is however necessary to check the operation of
contacts during commissioning, so alternative trip isolation must be obtained as
necessary by removing the circuit breaker trip isolation links.
The heavy current bridging plugs can now be replaced by the test plugs.
The only connections that must be made before insertion are the CT shorting links
(see Figure 1 of this section) on the red ringed terminals 1 to 2, 3 to 4, 5 to 6 and
7 to 8 of the test plug going in the 1Y position.
The notes in raised letters on the side of the test plugs should be observed.
The equipment is now effectively isolated from the system.
QUADRAMHO Chapter 5
Page 4 of 24
4.3 Initial checks, including self-check facilities

If the dc supplies are available on the panel they can be checked on test plug 1Z
red ringed terminals 5(+) and 6(). If the supply is within the required operative
range it can be linked through to the relay. If the panel supply is not available, a
suitable supply could be connected to the relay side terminals 5 and 6 of the test
plug.
The bridge on terminals 10 of the 1Z test plug should be made and the relay
available green light emitting diode (LED) on module 6 should light. (Check that the
relay inoperative alarm contact C2122 opens). If the dc is removed and
re-applied it will be seen that all the red LEDs on module 4 light while the relay
goes through its power up procedure and at the end of it, the relay available LED
lights. (A scheme option number must be selected see Figure 2). If three phase to
neutral voltages, each above 70% of 63.5 volts are connected to the relay side
terminals 1, 2, 3 and 4 of test block 1Z as shown in Figure 1, an additional self-
check on the comparators is made available if SW5 on module 4 is to the right
(see Figure 2). This feature can now be initiated by pressing and releasing the
reset pushbutton, when all the red LEDs, except power swing, will be seen to
briefly flash.
Alternatively, if the dc is switched off and then re-applied, when the power up
procedure has finished the self-check takes place and on careful observation it will
be seen that the red LEDs flash again and the relay available LED should light. This
will re-occur once every two weeks if the dc is left on and ac volts are present as
previously described.
All the following are monitored continuously when in a scheme option:
i) Internal dc voltage rails for +5V, +12V, +24V and 12V.
ii) The internal clock.
iii) The reference voltages for the level detectors.
iv) The processor running through its program.
In addition the ability of the comparators to count up in response to two square
wave inputs and reset is monitored during the additional self-check (which puts the
relay out of service for 80ms without affecting the relay available LED or alarm
contact unless a fault is found).
If a fault is detected in any of the above, the relay available LED will extinguish
and the problem analysis instructions in Chapter 6 should be consulted.
It should be noted that the inoperative alarm is given if the output relays are
inhibited by any means or if the voltage transformer supervision is set to block and
zero sequence volts are detected without zero sequence current.
4.4 Level detector checks
4.4.1 Voltage level detectors
Each phase to neutral input voltage is monitored and pick up of the level detector
is fixed at 44.45V 10%).
The scheme logic uses this information in:
a) The switch-on-to-fault feature (SOFT).
b) The decision to enable the memory and to output it.
c) The decision to perform the self-check (if selected).
QUADRAMHO Chapter 5
Page 5 of 24
d) The detection of pole dead.

e) The weak infeed feature.
Select test option 43 (W = 4, Y = 3) all the LEDs now have a different function
from that on the nameplate. Apply volts in turn to each voltage input and check
that the LED indicated lights when 49 volts is applied and does not when 40
volts is applied. If preferred the precise pick-up can be determined and the
drop-off should be within 10% of that value.
Level detector Terminals injected LED marking
A phase 1Z 14 A
B phase 1Z 24 B
C phase 1Z 34 C
Note: During test option checks, only the LEDs mentioned are of concern in a
particular test, others may be on and can be ignored; however, a full table
is given in Figure 3.
4.4.2 Fixed current level detector checks
(i) Low set current level detectors
Each phase current is monitored and the setting is changed by the value of K1
and K2 selected on module 1, the most sensitive setting is 5% In.
5 4.8
Current setting = x x In amps (10%)
100 K1 + K2
In = relay rated current
The scheme logic uses the information in:
a) Gating the comparators to limit the system impedance ratio up to which the
relay functions.
b) The switch-on-to-fault feature.
c) The detection of pole dead.
Keep test option 43 selected and inject current into each pair of phase
terminals, on the left hand side of the 1Y test block, in turn. Determine the pick-
up as indicated below, the drop-off should be within 10% of actual pick-up.
A phase 1Y 12 Z3
B phase 1Y 34 Aided trip
C phase 1Y 56 SOFT
Note: Refer to 4.4.3(i) as it is convenient to combine the tests.
(ii) High set current level detectors
These are only used in the blocking scheme or the weak infeed feature which
can be used in conjunction with the permissive overreach scheme.
If these schemes are not to be used or are not likely to be selected in the future
this test need not be done.
12.1 4.8
Current setting = x x In amps (10%)
100 K1 + K2
QUADRAMHO Chapter 5
Page 6 of 24
Select test option 53 and inject current as in previous test. Determine the pick-
up; drop-off should be within 10% of the actual pick-up.
A phase 1Y 12 Z3
B phase 1Y 34 Aided trip
C phase 1Y 56 SOFT
Note: Refer to 4.4.3(ii) as it is convenient to combine the tests.
4.4.3 Auto ranging low set and high set residual current level detectors
The auto ranging only comes into action when a minimum phase difference current
is exceeded. The residual signal is derived by summing the vectors of the voltages
in the relay which are proportional to the phase currents.
The operation level when auto ranging varies directly with the highest phase
difference current until a limit is reached. The minimum operate level varies
inversely with K1 + K2. In commissioning it is only necessary to check this fixed
level.
(i) Low-set
This is used to enable ground fault trips preventing operation of heavy close-up
phase to phase faults.
It is also used in the Voltage Transformer Supervision feature to detect the
presence of zero sequence current.
2 4.8
Minimum operate level = x x In amps (20%)
100 K1 + K2
Select test option 43, inject current into each phase in turn (as in 4.4.2 (i))
minimum operate level as indicated by the LED marked V~FAIL. Drop off
should be within 10% of the actual pick up.
(ii) High-set
The high set is used to block phase fault comparators which may cause 3 phase
tripping during heavy close-up single phase ground faults.
The auto ranging in conjunction with the voltage level detectors permits phase
fault comparators to operate for two phase-ground faults.
16 4.8
Minimum operate level = 8 x low set x x In amps (20%)
100 K1 + K2
Select test option 53 and inject current as for the low set and check the
V~ FAIL LED for operation. Drop off should be within 10% of the actual pick
up.
4.5 Zone 1 reach tests
4.5.1 Connections and preliminaries
The relay should now be connected to equipment able to supply three phase to
neutral volts and current in the correct phase relationship for a particular type of
fault on the selected relay characteristic angle. The facility for altering the loop
impedance (phase-ground fault compensation or phase-phase) presented to the
relay is essential. This may be a continuous adjustment or steps of around 1% in
the voltage or current.
QUADRAMHO Chapter 5
Page 7 of 24
The voltage supply to any test set working off 3 phase supplies should be checked
for correct phase rotation.
The test blocks should be connected as shown in Figure 1.
The particular scheme option numbers should be selected (if 08 or 09 is selected
energise RESET Z1 EXT. opto isolator input) and SW3 controlling the ability of the
VTS to block comparators should be set to the left (ie. not blocking). It may also be
advisable to set SW9 to the left. This disables the power swing blocking feature.
Note: Refer to 4.9 as it may be convenient to combine timing checks with the
reach checks.
If busbar VTs are fitted and the breaker open opto isolator input is energised, then
the SOFT feature will be operational all the time. In the POR scheme the same input
may also be used as part of the weak infeed feature.
Terminal A3 should in these circumstances be isolated and only energised when
required during commissioning.
4.5.2 Ground faults Zone 1
Commence with connections for an AN fault. To establish confidence in operation
a close-up fault with adequate source impedance to limit the current should be
applied. The LED marked A should light followed by Z2 and Z3 if the fault is left
on. (Assuming tZ3 is not set to 00).
The current should then be reversed to check that operation does not occur, except
for Z3 which always has some reverse reach.
The appropriate loop impedance should now be presented to the relay
K14 (K1 + K2 + K4 + K5 + K6) (K11 + K12 + K13)
ohms
In
or the nearest higher figure available.
Make small step adjustments to the impedance, only presenting them for less than
Zone 2 time to the relay and determine the highest impedance which gives
instantaneous illumination of the A LED (If a low Zone 2 time is set it may help to
temporarily increase it).
The measured impedance should be within 10% of the calculated value assuming
the angle of the impedance presented is within 5 of Ph and N on module 7 of
the relay. Check that the appropriate contacts operate for single or three phase
tripping as selected (see Figure 4 for the external connections and which contacts
will operate). In particular check the any trip contacts on test block 1Z terminals
7 8. They have been isolated from case terminals B21 and B22).
Repeat the tests for BN and CN including the directional checks.
Note: The indications are automatically reset when a new trip output is obtained
but it may be easier to understand what happens during commissioning by
using the manual reset on Module 4.
If Ph and N differ by more than allowed above then the vector sum of the
coarse phase reach and the neutral compensation must be found to give
the basic ground fault loop impedance and the required ground fault
angle. This must be applied to all zones by use of the appropriate zone
multiplier.
QUADRAMHO Chapter 5
Page 8 of 24
4.5.3 Phase faults

The appropriate loop impedance is now:
(K1 + K2) (K11 + K12 + K13)
2 x K14 ohms
In
Carry out the tests as for the ground faults, starting with AB and proceeding to
BC and CA faults.
Note: If using a ZFB, VTS indication will now be obtained. Also the relay may
fail the self-check, see Section 4.15.
If scheme 08 or 09 is selected carry out 5.1 next.
4.6 Zone 2 reach tests
When checking Zone 2 reaches the effect of the expansion of the reach when any
trip occurs may be apparent.
If a fault is applied less than 5% outside the Zone 2 boundary and inside the
Zone 3 boundary, then if Zone 3 times out giving a trip output, Zone 2 indication
will also be seen if the fault is maintained for Zone 2 time after the Zone 3 trip
occurs.
The ground fault loop impedance required is:
(K1 + K2 + K4 + K5 + K6) (K21 + K22) K24
ohms
In
and for phase faults the loop impedance required is:
2 x (K1 + K2) (K21 + K22) K24
ohms
In
The reach for each type of phase-ground and phase-phase element of the relay
should be checked as in Section 4.5 and the operation of the appropriate
outgoing contacts confirmed.
Note: At the Zone 2 boundary some chatter of the fault locator contacts may be
heard prior to the trip, causing expansion of the zones.
4.7 Zone 3 reach checks
If has been set on tZ3, the switch must temporarily be moved to the left to enable
the reach checks to be done. Zone 3 has the facility for setting forward and
reverse reaches on the line angle up to the same impedance. There are three
different shapes available as selected by the customer when ordering the relay.
These are circular, lenticular or a quadrilateral for ground faults.
The presence of the lenticular shape is indicated on Module 3 by a switch labelled
a/b which controls the aspect ratio as illustrated on the frontplate. When a/b is set
to 1 the characteristic is circular.
The presence of the quadrilateral shape is indicated on Module 1 when a switch
(K3) for the setting of the resistive forward rach of Zones 1, 2 and 3 is fitted.
(see Figure 5). The resistive check will be described later.
The ground fault loop impedance required for forward checks is:
(K1 + K2 + K4 + K5 + K6) (K31 + K32) K33
ohms
In
QUADRAMHO Chapter 5
Page 9 of 24
and for reverse reach ground faults is:

(K1 + K2 + K4 + K5 + K6) (K35 + K36) K33 x K37
ohms
In
The phase fault loop impedances required are; for forward faults:
2 x (K1 + K2) (K31 + K32) K33
ohms
In
and for reverse phase faults:
2 x (K1 + K2) (K35 + K36) K33 x K37
ohms
In
The reach checks should be made for each element of the relay and the
appropriate outgoing contacts checked.
Note: The fault locator contacts do not operate for Zone 3 trips. For the reverse
reach an additional tolerance of 15% is allowed.
4.8 Resistive reach check (if quadrilateral characteristic is fitted, see Figure 5)
Checks are done using resistive faults, thus in the forward direction all zones will
be seen to operate at the same loop impedance.
The required loop fault resistance is:
K3
ohms
In
The checks should be done for all phase to ground faults and results should be
within 15% of the selected setting.
4.9 Zone 1 operation times
Zone 1 operation times should be checked by applying a fault at 50%
(approximately) of the Zone 1 reach.
An interval timer should be started when the fault is applied and stopped from the
contacts brought out on the left hand side terminals 7 and 8 of the 1Z test plug.
The following points should be noted:
i) To obtain fast operating times it is essential to use dynamic tests starting with
all phase-neutral voltages above the level detector setting, when connected for
phase faults do not have resistors fitted which tie down the neutral point, check
phase-neutral voltages with 100% potential setting. If this is not done filters in
the voltage circuits will already be switched in and the operation times will be
slower.
ii) If the polarising quantities are not correctly provided by the test set some slower
times may be measured.
iii) The times vary with the point on wave of fault application. It is thus suggested
that 10 operations be done for each type of fault.
iv) Times vary with the type of characteristic being used and the SIR.
v) Typical times expected are:
a) Shaped mho characteristic 15 30ms
b) Quadrilateral characteristic 20 35ms
QUADRAMHO Chapter 5
Page 10 of 24
If the polarising quantities are not correct or if the voltage filters are in initially,
times may increase by 10 15ms. Times on 60HZ are approximately 10% faster.
The operation times should be checked for each phase-ground and each phase-
phase element.
Make sure the correct time is selected by the tZ2 switches. (Also check tZ3 is
greater). Apply a fault just outside Zone 1 and check the operation time as in
Section 4.9. This need only be done for one type of fault. The time measured will
be that of the software timer plus the comparator time plus the output contact
operation time.
The actual measured time should be within 40ms of the set time. Check for correct
indications and contact operation.
Note: The set time is the sum of the times of all the t2 switches set to the right.
Check that 3 phase trips are given. Check that the block auto reclose
contact operates, if used (B25B26).
If Zone 3 is not to be used for tripping then should be selected on the tZ3
switches and no timing tests need be done.
If a time is set, check the setting as in Section 4.10 but applying a fault just outside
Zone 2.
The actual time should be within 40ms of the set time.
Check that correct indications are given and the appropriate contacts operate.
4.12 Power swing blocking checks
If this feature is to be used it can now be enabled by moving switch SW9 to the
right and the following checks carried out. The feature works from comparators on
AB and utilises a Zone 6 in conjunction with Zone 3.
Zone 6 is automatically set with the Zone 3 switches to give:
Zone 6 forward (Z6) = Zone 3 forward + (0.3 x Zone 3 forward)
Zone 6 reverse (Z6') = Zone 3 reverse + (0.3 x Zone 3 forward)
A power swing is detected by an impedance being seen between Zone 3 and
Zone 6 for a time exceeding 50ms and then being seen inside Zone 3.
To check the Zone 6 boundary and the 50ms time it is necessary to utilise some of
the outputs that are made available by plugging the 25 way monitor point box into
socket 2 on Module 6. (Figure 6 gives all socket 2 outputs).
4.12.1 Zone 6 boundaries
A high impedance dc voltmeter should be connected from monitor point 2() to
7(+), when an impedance is seen inside Zone 6 the voltage will drop from about
24V to zero. For the forward boundary the required loop impedance is
2.6 x (K1 +K2) (K31 + K32) K33
ohms
In
and for the reverse boundary the required loop impedance is:
2 x (K1 +K2) K33 [(K35 + K36) K37 + 0.3 (K31 + K32)]
ohms
In
QUADRAMHO Chapter 5
Page 11 of 24
These impedances must be prepared as AB phase faults.

The boundary may be determined either by momentarily applying the fault or by
gradually decreasing the impedance until the voltmeter reading fails. For the
reverse reach an additional tolerance of 15% is allowed.
Note: Ensure that CN post-fault voltage is maintained at greater than 70% of
63.5V. If this condition is not met, PSB will be blocked by the Any Pole
Dead feature. See Figure 60 Chapter 2 of this manual.
It should be possible to meet the above condition by manipulating fault
and source impedances on the test set.
4.12.2 50ms timer check
The voltage out of the monitor point box has been chosen so that the digital timer
will treat it as a contact, the voltage present being treated as an open contact.
An impedance should be presented to the relay approximately midway between
Zone 3 and Zone 6, start the timer when it is applied and stop it when the voltage
on the monitor point box terminals 27 falls. (On the timer terminal 2 must be
connected to the common on the timer and the timer set for normally open to start
and stop).
The time measured will be that of the Zone 6 comparator + 50ms + processing
time; the comparator will vary with point-on-wave of fault application.
Take five timings, find the average and subtract x ms which should give 50ms
(10ms).
Where x = 25ms for quad/mho version
30ms for mho/lenticular version
Note: Each phase to ground pre-fault voltage must be greater than 70% of
63.5V. If this condition is not met, 240ms is added to the measured time.
This can be seen from Figure 60 in Chapter 2.
4.12.3 Simulated power swing with blocking checks
It is now necessary to simulate a power swing for the AB element of the relay.
Set the power swing blocking switches Z1, Z2, Z3 to the right. Press the indicator
reset, apply an impedance just outside Zone 3 and reduce the impedance without
switching off (say 1% steps) until power swing indication is obtained (this should
be when the Zone 3 boundary is crossed). Check that the alarm contact operates
(C19 to C20).
Still maintaining the fault, set K11 and K21 to , then in turn check (starting with
Z1) that removing the blocks enables the correct LED indications after the
appropriate time delays.
Put the blocking switches to their required positions.
Make sure the correct settings are put back on K11 and K21. If the optical isolator
input for inhibiting power swing blocking is to be used, check that putting the
required volts on terminals A56 inhibits the feature.
4.13 Voltage transformer supervision
Operation occurs when zero sequence voltage above a set level is detected
without any zero sequence current being detected above a set level. If set for
indication only, instantaneous indication will be given if operation conditions are
satisfied and a comparator is operated, otherwise time delayed indication will be
QUADRAMHO Chapter 5
Page 12 of 24
given. If set for blocking this can take place instantaneously if a comparator
operates.
4.13.1 Operation on zero sequence volts
Apply balanced 3 phase-neutral volts and reduce the voltage on one phase until
V~FAIL indication is obtained.
The operation time is 5.5s (tolerance 0.1s). The zero sequence voltage setting is
15% of 63.5V, thus the required voltage reduction on one phase is 45% of 63.5V
(28.6V tolerance 20%). The phase-neutral voltage required for operation should
thus be between (70% of VN). (For 60Hz the limits are 27 to 46 volts).
4.13.2 Timing check
Timing is checked by using a double pole switch to remove one healthy voltage
and start a timer which is stopped by the alarm contacts (C1718). The time
obtained should be stated as above.
4.13.3 Current checks
The zero sequence current level detector has already been checked for its
operation level (Section 4.4), thus it is now only necessary to inject a current
above this low set neutral level into one phase while one phase-neutral voltage is
below (70% of VN) and to check that the V~Fail indication can be reset. It is
recommended that the variac and resistor are used for supplying the current when
a ZFB is used to supply the volts. Check that when V~Fail is indicated, that moving
SW3 to the right causes the relay available LED to extinguish.
4.13.4 Instantaneous indication or blocking check
Conect the relay as if an AG fault were to be applied, but instead of returning the
current through the neutral take it in the reverse direction through B phase.
(The current path is into 1Y1 out of 1Y2 link to 1Y4 out of 1Y3, all being the relay
side terminals of the lower test block). The result of this is that fault application will
not produce any residual current. Choose the source and fault impedance such that
when the fault is applied, the AN volts will fall below 25 volts, causing the zero
sequence voltage level detector to pick up.
To be sure of getting a Zone 1 comparator operating (AB) set K11 to . SW3
should still be set to the left. Apply the fault and instantaneous indication will be
obtained for an AB fault and V~Fail.
Set SW3 to the right and apply the fault until time delayed V~Fail indication only is
obtained.
Set SW3 in the required position and return K11 to the correct setting.
Note: When is selected the comparator self-check may cause the relay
available LED to go off.
4.13.5 Miniature circuit breaker block check
Energise the opto coupler connected to case terminals A1 and A2. (Zone 1
extension reset opto on non-MCB versions of Quadramho). Check the following:
i) The VT indication operates and latches.
ii) The 97X1 contact on case terminals C17 and C18 closes.
iii) The relay available green LED extinguishes.
iv) The relay inoperative alarm 97Y1 on case terminals C21 and C22 opens.
QUADRAMHO Chapter 5
Page 13 of 24
Now with the opto coupler still energised, apply a Zone 1 ground fault, a Zone 2
phase fault and a Zone 3 reverse (if offset) earth fault. No operation should occur.
De-energise the MCB opto coupler and normal operation will occur but note the
VTS light requires resetting.
4.14 Switch-on-to-fault check
The feature is enabled when all poles (volts and current) have been dead or the
breaker open opto isolator is energised for either 200ms or 110ms as selected by
switch SW2. (To the right gives 200ms).
When the poles dead signal ceases the feature remains available for 240ms.
Switch SW1 controls the method of detecting a switch-on-to-fault:
i) With SW1 to the right, a trip is caused by a current being detected above the
low set phase current level detector threshold and volts being below the voltage
level detector setting on the same phase.
ii) With SW1 to the left, a trip is caused by the operation of any Zone 1, Zone 2
or Zone 3 comparator.
It should be noted that no phase indication is given; only the SOTF LED will
illuminate and a 3 phase trip with auto reclose blocked occurs. A time delay of
20ms is included in (i), to allow for pole scatter and the different pick-up time of the
level detectors.
Any existing indications are not automatically erased for a SOTF trip. Start tests
with SW2 to the right (nearly all applications will have this setting). Tests should be
done using AN faults and if desired can be repeated on BN and CN.
To check (i). Go from a poles dead condition to a fault condition with the required
level detector conditions.
Confirm that SOTF indication is obtained and that the trip time is 40 50ms
approximately.
To check (ii), go from a pole dead condition to a fault condition in Zone 1
(preferably close up), confirm that SOTF indication is obtained and that the trip
time is less than 30ms approximately.
If busbar VTs are to be used, the opto isolator input for breaker open (Terminals
A34) should be energised. Faults can then be applied in the normal way giving
SOTF indication and the times already indicated. Do not forget to remove the opto
isolator signal after completing the tests.
If SW2 is to be set to the left, set it there and confirm that after the next SOTF trip,
another cannot be obtained for the 110s (try the first trip after poles dead for 120s
and the next after 100s).
Normal trips will occur when SOTF trips do not. If this check is being done for
busbar VTs, the opto isolator signal should be switched off and back on for the
appropriate time in between each trip to obtain correct operation.
iii) With SW1 to the right (switch-on-to-fault operation via current and no volts level
detectors) repeat check (i) but with the miniature circuit breaker opto energised
(case terminals A1/A2) switch-on-to-fault will be blocked.
iv) With SW1 to the left (switch-on-to-fault via comparators) repeat check (ii) but
with the MCB opto energised (case terminals A1/A2) switch-on-to-fault will be
blocked.
QUADRAMHO Chapter 5
Page 14 of 24
Note: If SW1 is set to the left the fault current may be reversed to confirm Zone 3
comparators are part of the SOTF feature.
4.15 Memory feature check (synchronous polarising)
The memory is mainly to deal with 3 phase close up faults but is made to run out
when any voltage level detector resets or when any comparator operates. There is
nominally 8 cycles of memory polarising which is all derived from C phase volts.
The memory is re-connected 140ms after all voltage level detectors pick up and
comparators have reset.
We thus have to satisfy the above conditions and make the relay behave as though
it is seeing a 3 phase close up fault.
This is achieved by applying a close up CN fault after removing the A and B
voltage inputs and connecting test plug 1Z terminals 1, 2 and 3 together
(see Figure 1).
If the dwell time of the trip contacts is now measured this will give a measure of the
memory time.
On 50Hz the time measured should be 180 220ms.
With these voltage connections a self-check may bring up the relay inoperative
alarm. This condition will disappear when the voltage connections are normal and
another self-check is made. Remember that a self-check is made every time the
reset button is pressed if the feature has been selected by SW5 and all voltage
level detectors are picked up.
4.16 Check on function of SW4 (if auto-reclose is used)
If in schemes 02 to 09 set SW6 to the left.
Apply a 3 phase Zone 1 fault and check that the block auto reclose contact
(terminals B2526) closes when SW4 is set to the right and does not when SW4 is
set to the left. Set the switch to the desired position.
Note: Some customers may only consider it necessary to use test option 57 to
check that the switch position is being correctly put into the scheme logic.
4.17 Trip test function check
If the code selection switches are set to 88 and the reset pushbutton is pressed, the
trip outputs given are controlled by SW15.
SW1 to the right gives trip C Terminals B1314
B1516
SW2 to the right gives trip B Terminals B910
B1112
SW3 to the right gives trip A Terminals B56
B78
SW4 to the right gives trip 3 phase Terminals B1718
B1920
SW5 to the right gives any trip Terminals B2122
B2324
These should be checked so that if a trip test is carried out later, the engineer will
be aware of what is necessary and will have confidence that the required contacts
QUADRAMHO Chapter 5
Page 15 of 24
will operate. Any combination of SW15 can be selected to give the trip contacts
required for single or three phase tripping as required later.
Check that removing the link on the 1Z 10 test block terminals stops any contact
operation and the relay available LED ceases to be illuminated.
Note: All output tests are shown on Figure 7
Section 5. SCHEME TESTS
The appropriate tests should be made for the selected scheme option.
5.1 Zone 1 extension scheme (08 or 09)
In test 4.5 the non extended reaches were checked. Check that the opto isolator
input for reset Zone 1 extension (terminals A12) is not now energised. All the
Zone 1 ground and phase fault reaches will be increased by the setting on K15.
The nominal loop impedances required to check the reaches will be those given in
4.5.2 and 4.5.3, multiplied by K15. (Typically 20% of the second line section
would be covered by the extended reach).
The new reaches are found as in Section 4.5 for each fault condition.
When this scheme is being used with a relay specified for use with miniature
circuit breakers (MCB) instead of VT fuses, the reset Zone 1 extension opto is
shared with the carrier receive opto (according to the thumbwheel selection
number chosen) so instead of relay case terminals A1/A2, use A9/A10.
5.2 Permissive underreach scheme (02 or 03)
Note: that if the channel in service opto isolator is not energised 3 phase trips
will be given in scheme 02. Connect a double pole switch so that one
pole of it can be used to energise the signal receive opto isolator input
(Terminals A910) and the other pole to start a timer.
5.2.1 Aided trip check
Energise the opto isolator input and check that application of a Zone 2 fault gives
an instantaneous aided trip. Make sure a Zone 2 time delayed trip is obtained
when the signal receive is removed.
5.2.2 Signal receive delay on drop-off
This delay is fixed at 100ms and a signal is available from the monitor point box
(Terminals 29) for checking it. The signal is active low falling from 24 volts, timers
will treat it as a contact provided terminal 2 is connected to the common terminal
of the timer.
Start the timer when de-energising the opto isolator input and stop it from the
monitor point box signal when it changes to 24V. (The timer should be set to
normally closed for start and stop). The measured time should be 90110ms.
5.2.3 Signal send checks
Check that applying a Zone 1 fault causes the signal send contacts (B1B2 and
B3B4) to close.
There is also a test option which can be used to give signal send which is useful for
checking the signalling channel on the system. Select test option 62 and if SW8 is
QUADRAMHO Chapter 5
Page 16 of 24
to the right, check that the signal send contacts will close when the reset button is
pressed.
Note: other contacts may also operate, depending on the position of the other
SW switches.
5.2.4 Signal receive check
There is another test option which enables the checking of the signal receive.
If test option 41 is selected, the LED labelled SOTF will illuminate when the opto
isolator input is energised.
5.2.5 Block auto reclose checks
Switch SW6 controls whether or not auto reclose is blocked when the channel is
out of service.
If SW6 is set to the right, check that the block auto reclose contact (Terminals
B2526) is closed.
Energise the channel in service input (A78) and check that the block auto reclose
contact opens.
If SW6 is set to the left, check that the block auto reclose contact does not close if
the channel in service signal is present.
5.3 Blocking scheme (06 or 07)
Note that if the channel in service opto isolator is not energised, 3 phase trips will
be given in scheme 06.
In this scheme a block signal is sent when a particular Zone 3 comparator
operates and the corresponding Zone 2 comparator does not.
The Zone 3 will generally have a larger reverse reach than forward reach.
(The smallest forward phase fault reach is ZPh and if PSB is used greater than
Zone 2). An aided trip occurs when a Zone 2 comparator operates, the channel in
service opto isolator is energised and no block signal is received, certain time
delays are necessary to prevent maloperations. These time delays have to be set to
take into account different signalling channel times, comparator operation times
and logic processing times.
tp is the set time delay tripping after the Zone 2 comparator has operated to allow
a possible blocking signal to be received from the relay at the other line end.
The recommended setting is:
tp = channel pick up time + 25ms for Quadramho with mho
30ms for lenticular with a/b = 1
35ms for lenticular with a/b = 0.67
40ms for lenticular with a/b = 0.41
or the nearest available higher setting.
For current reversal conditions, a small delay on drop-off of the blocking signal is
required to prevent unwanted trips while the Zone 2 comparator is resetting.
The inherent relay processing time, the reset time of the send contact and the
channel reset time mean that only an exceptionally fast channel reset time makes a
setting of anything other than tD = 0 necessary.
QUADRAMHO Chapter 5
Page 17 of 24
The recommended setting is:

tD = 0 if the channel reset time is 10ms or greater than 10ms.
tD = 12ms if the channel reset time is less than 10ms.
Note: If td is set to 0 or 6ms, the time actually measured can be as high as 5 or
6ms. This is due to the effect of the microprocessor loop execution time
and the point where it is interrupted.
When td is set to 12ms times of 10 to 15ms will be obtained.
5.3.1 Measurement of tD
Connect a double pole switch so that one pole can energise the signal receive
opto isolator input (A9(+) to A10) and the other pole to start a timer set to start
from a normally closed contact.
A signal is available from the 25 way monitor point box (terminals 2 to 9) to stop
the timer. When the voltage is removed from A9 the voltage on the monitor points
2() and 9(+) will go from zero to 24V, (timers will treat this as a normally closed
contact if 2 is connected to the common connection of the timer).
The rising voltage is used to stop the timer. When the double pole switch is opened
the appropriate time for tD will be obtained in the range previously described.
5.3.2 Aided trip and tp check
Connect a single pole switch to energise the channel in service opto isolator input
terminals A7(+) to A8. Check that the double pole switch used for test 5.3.1. is
closed.
Apply a Zone 2 fault and check that a trip is obtained in Zone 2 time. Open the
double pole switch and check that an instantaneous aided trip is obtained. Set tp to
zero (ie. all tp switches to the left) apply a Zone 2 fault and measure the aided trip
operating time. This should be repeated 5 to 10 times and the average operation
time calculated.
Put the required setting on the tp switches and find the new average aided trip
operation time. The difference between the two average times will give 6ms less
than the set tp time (6ms is the average processing and loop time when tp = 0) with
a tolerance of 5ms.
5.3.3 Signal send check
Apply a reverse Zone 3 fault and check that the signal send contacts (B1B2 and
B3B4) close. There is also a test option which can be used to cause the signal
send contact to close which is useful for checking the signalling channel on the
system. Select test option 62 with SW8 to the right and check for signal send.
Note: that other contacts may operate depending on the position of the other
SW switches.
There is another test option 41 which enables the checking of the signal receive.
With the test option selected the LED labelled SOTF will illuminate when the opto
isolator input (A9(+) to A10) is energised. This is also used later for checking the
system signalling channel.
QUADRAMHO Chapter 5
Page 18 of 24
out of service.
If SW6 is set to the right, check that the block auto reclose contact (Terminals
B2526) is closed when the channel in service opto isolator is not energised.
Check that energising the opto isolator causes the contact to open. If SW6 is set to
the left, check that the contact does not close for either state of the opto isolator
input.
Note: that if the channel is out of service, the relay reverts to a basic scheme.
5.4 Permissive overreach scheme (04 or 05)
Note: that if the channel in service opto isolator input is not energised, three
phase trips will be given in scheme 04.
Commence tests with the weak infeed feature out (SW8 to the left). Connect a
double pole switch so that one pole can be used to energise the signal receive
opto isolator input (terminals A9(+) A10) and the other pole to start a timer.
5.4.1 Aided trip check
In this scheme Zone 2 comparator operation causes signal send and an
instantaneous aided trip is obtained by Zone 2 comparator operation plus signal
receive.
Apply a Zone 2 fault and check a trip is obtained in the set Zone 2 time.
Energise the optical isolator and re-apply the Zone 2 fault; check that aided trip
indication is obtained immediately and that the alarm contact (C1314) closes.
5.4.2 Signal send check
Check that the signal send contacts (B1B2, B3B4) close immediately a Zone 2
fault is applied
Test option 62 can also be made to close the signal send contacts, check that with
SW8 to the right; pressing the reset button causes the contacts to close. This will be
used in the signalling channel check later.
Note that other contacts may operate depending on the other SW switch positions.
5.4.3 Measurement of tp
The current reversal guard in the scheme is initiated when a healthy circuit relay
receives a permissive trip signal; however a certain delay tp is required to give
time for a Zone 2 comparator to pick up.
The recommended setting for tp is 30ms minus channel pick up or the nearest
available higher setting.
Due to processing times and the point on the program loop when a signal is
applied, the measured times vary as follows:
tp = 0 or 6 10 to 15ms
tp = 12 15 to 20ms
tp = 18 21 to 26ms
tp = 24 27 to 34ms
The time is measured from the closing of the switch energising the signal receive
opto isolator to the signal receive enunciate on the monitor point box terminals 2()
to 9(+) going from 24V to zero.
QUADRAMHO Chapter 5
Page 19 of 24
Note: Timers will treat the voltage as a normally open contact provided terminal
2 goes to the common terminal on the timer.
5.4.4 Measurement of tD
When the current reversal guard is picked up, transfer tripping is inhibited until the
permissive trip signal is removed or the Zone 2 comparator operates. A delay on
reset (tD) is required in case the Zone 2 comparator picks up while the permissive
trip signal is resetting which would otherwise cause a healthy circuit trip.
The recommended setting for tD is channel drop-off time plus 25ms or the nearest
available setting above.
The time is measured from the removal of the volts from the signal receive opto
isolator to the volts on monitor points 2() to 9(+) returning to about 24V.
The measured time should be within 6ms of the set tD.
Note: Application Engineers should advise if the feature is not necessary in
which case tD tripping should be set to zero, which will give the smallest
possible delays to tripping.
Timers will treat the signal from the monitor point box as a normally closed
contact provided terminal 2 goes to the common terminal on the timer.
Select test option 41 and check that the LED labelled SOTF is illuminated when the
double pole switch is closed.
This facility will be used in the signalling channel check later. Re-select the scheme
option.
Connect a single pole switch so that the channel in service opto isolator input
(A7(+) A8) can be energised.
out of service. If SW6 is set to the right, check that the block auto reclose contact
(B25 to B26) is closed. Energise the channel in service input and check that the
block auto reclose contact opens.
If SW6 is set to the left, check that the block auto reclose contact does not close if
the channel in service signal is present or not.
5.4.7 Echo feature
To make this functional an opto isolator input has to be available to inform the
relay when the breaker is open. The feature causes signal send for 100ms on
receipt of carrier once the breaker has been open for 60ms.
If the feature is to be used check it as follows:
Connect a double pole switch so that one pole can be used to energise the
breaker open opto isolator input (A3(+) to A4) and the other pole to start a timer,
the switch should be open initially. A signal send contact (B1B2 or B3B4) should
initially be connected to stop the timer.
Energise the signal receive opto isolator (A9(+) to A10) then close the double pole
switch. A time of 65 to 75ms should be obtained.
Re-connect the timer to measure the dwell time of the signal send contact, open the
double pole switch, on reclosing the switch a time of 100 to 110ms should be
obtained.
QUADRAMHO Chapter 5
Page 20 of 24
5.4.8 Weak infeed feature

If this is to be used SW8 should now be moved to the right.
If it is also to be used to give a direct 3 phase aided trip, SW7 will also be set to
the right later.
If SW7 is set to the left, a weak infeed echo feature only will be available to
enable fast end zone clearances at the strong infeed end.
i) Check on weak infeed echo feature
The normal echo feature is not enabled when the breaker at the weak infeed
end is closed. Thus make sure the breaker open opto isolator input is not
energised.
Commence with SW7 set to the left.
No ac volts should be supplied to the relay.
There is a 10ms delay on the echo once the signal receive opto isolator is
energised. To check this, start a timer from a double pole switch energising
terminals A9(+) to A10 and stop the timer from a signal send contact (B1B2 or
B3B4). The time measured should be 15 20ms.
Check that no signal send occurs if normal 3 phase volts are applied to the
relay. Remove the volts.
Measure the dwell time of the signal send contact when closing the two pole
switch; 105 115ms should be obtained.
Check the normal echo feature is not enabled when the miniature circuit breaker
(mcb) opto coupler (case terminals A1/A2).
ii) Weak infeed three phase tripping
These test need only be carried out if tripping is required.
The logic contains a delay on tripping of 60ms and a delay on drop-off of the
signal receive of 100ms.
Move SW7 to the right if tripping is required. To check the 60ms timer:
With no ac volts on the relay, connect a double pole switch to start a timer and
to energise the signal receive opto isolator input (A9+ to A10). Connect the any
trip contact on the 1Z test plug terminals 7 and 8 to stop the timer; the time
measured should be 65 75ms. Aided trip indication should be obtained and
3 phase trips given.
Check that no trip is given if normal 3 phase ac volts are present.
To check the 100ms timer:
With no ac volts on the relay, connect the timer so that it will start on switch off
of the signal receive input and stop when the any trip contact opens.
The time measured should be 105 115ms.
Check the aided trip indication and 3 phase trip is blocked when the miniature
circuit breaker (mcb) opto coupler (case terminals A1/A2).
5.5 Signalling channel check (schemes 02 to 07)
This test should be applied to any scheme using a signalling channel when the
channel is available and in service.
QUADRAMHO Chapter 5
Page 21 of 24
An engineer will be required at each end of the protected line and some form of
verbal communication is necessary.
The test options to be used in the channel check have already been checked in
Sections 5.2, 5.3 or 5.4.
At end B select test option 41 and the signal receive will be indicated by the LED
marked SOTF. At end A select test option 62 and set SW8 to the right. When the
reset button is pressed, the signal send contact will close and the signal receive
indication should be obtained at end B.
The procedure should then be reversed.
Section 6. LIVE SYSTEM CHECKS
6.1 Signalling channel check

If the scheme requires the use of a signalling channel and the check has not been
done recently then test 5.5 should be repeated.
6.2 Trip test
Auto reclose should be inhibited.
If test option 88 is then selected (its function has already been checked in
Section 4.17) the appropriate trip contacts can be made to operate by moving the
corresponding SW switches to the right as shown on Figure 7.
When the reset button is pressed, the selected trip contacts will close and the
circuit breaker will operate if the trip links have been inserted and the breaker is
closed.
6.3 Final setting checks
The check list Figure 8 should now be used to ensure that all the switches are
correctly set on the relay. Test options 54, 55, 56 and 57 should be selected in
turn to check that the LED information agrees with the switch positions on the check
list.
If schemes 00, 01, 02, 03, 08 or 09 are being used, test option 56 need not be
checked as the settings for tp and tD are not used in the schemes.
6.4 On load tests
6.4.1 Voltage transformer checks
Insert a test plug in the 1Z position without any links. The relay available LED will
not be illuminated.
i) With the line energised, check the voltage input to the protection across each
pair of phases and between each phase and neutral. (The red test plug
terminals, see Figure 1).
ii) Check for correct phase rotation with a phase rotation meter.
6.4.2 CT/VT phasing check
To ensure that the corresponding voltage and current go to a given relay element,
it is necessary to check the phase angle between them agrees with the known load
power factor. If the information available is in terms of import/export MW and
MVAR, Figure 10 gives guidance.
QUADRAMHO Chapter 5
Page 22 of 24
Connect AN volts (1Z 14 red terminals) to a phase angle meter voltage input
terminals, giving careful attention to polarity.
Use another test plug to connect the phase angle meter current terminals in series
with the A phase current.
Before inserting the 1Y test plug link through 2, 3, 4, 5, 6, 7 and 8. Connect the
red 1Y1 terminal to the phase angle meter current input terminal (the polarity
indication should correspond to that used for the A voltage input) and complete the
current path from the phase meter to the relay side of the 1Y1 test plug.
The test plug can now be inserted in the 1Y position (the lower rack).
Check that the angle measured gives reasonable agreement with the known load
power factor.
This procedure must be repeated on another phase.
Remove the 1Y test plug.
Connect the phase meter current inputs to the 1Y3 terminals. Link through the 1Y1
terminals. Move the one voltage input wire for the phase angle meter from the red
1Z1 test plug terminal to the red 1Z2 terminal.
Insert the 1Y test plug and check that the measured phase angle again gives
reasonable agreement with the known load power factor.
If these tests are satisfactory, terminals 1 to 6 inclusive of the 1Z test plug can be
linked through.
As the 1Z10 terminals are not linked, trips will not occur for the next test, also the
relay available LED will not be illuminated.
6.4.3 Directional check
i) The test must be carried out with the relay energised from the line voltage
transformers and current transformers with the load current above the level
detector setting and preferably at a lagging power factor in the tripping
direction.
Test option 43 can be used to determine which low set current level detectors
are picked up. No comparator can operate unless the appropriate low set
phase current level detectors are picked up. These level detectors are most
sensitive when K1 + K2 = 4.8, thus a temporary change in setting might help.
ii) To perform the directional check, the restraint voltage has to be removed from
the measuring circuits of Zone 1. This is achieved by rotating K11 to the
position
An instantaneous Zone 1 trip on all three phases will be indicated if the relay is
looking in the correct direction and the load angle falls within the straight line
directional characteristic passing through the origin and covering approximately
90 either side of the relay characteristic angle.
The ideal conditions for the load are shown in Figure 11A. The operating
region is most easily determined by drawing in the RCA leading the load
current by Ph and then drawing the boundary lines at 90 to the RCA.
Any voltage vector which falls within the 180 operation area, if injected into
the relay VA input will give operation. This is illustrated in Figure 11B where
injecting VB from the line into the relay VA input, etc, will give operation (see
Figure 9C).
QUADRAMHO Chapter 5
Page 23 of 24
In this case it can also be seen that operation would be obtained by reversing
the current and voltage rotation need not be carried out.
To enable any load condition to be understood Figure 11C provides the facility
for drawing the characteristic.
If the load vector is near the directional characteristic boundary, eg. an RCA of
85 and a load power factor of unity or slightly leading, then the load test may
not appear conclusive as some phases may not operate.
This may be made more conclusive by lowering the RCA temporarily by means
of Ph.
An alternative method of making the directional check conclusive for a similar
condition is by rotating the voltage vectors through 120 by means of a heavy
duty test plug inserted in the 1Z position as shown in Figure 9B.
If voltage rotation is necessary it is best to select on K11 after inserting the
test plug with the rotation connections on it.
iii) A check must also be made to ensure that operation does not occur in the
reverse direction. This is achieved by inserting a test plug in the 1Y position with
links already on it, as shown in Figure 9A.
iv) After the test has been completed ensure that K11 is on its correct setting. If any
other switches have been used to assist the test ie. K1, K2 or Ph make sure
they also are put back to their correct settings. Insert the normal 1Y and 1Z
bridging plugs.
Note: The directional characteristic may not be a perfect straight line and if a
near boundary operation occurs in the reverse direction, the normal
angular hysteresis will operate in the wrong direction until the memory has
run out. If Ph is lowered by 10 the effect should disappear and no
operation be obtained.
If a self-check is done with K11 in the position without the outgoing contacts
inhibited, the relay may indicate that it is not available. When K11 is returned
to its normal position and another self-check is done on the comparators, then
relay available indications will be restored.
QUADRAMHO Chapter 5
Page 24 of 24
Code selection
switch number Scheme Type of tripping
00 Basic 1Ph and 3Ph
01 Basic 3Ph only
02 Permissive underreach 1Ph and 3Ph
03 Permissive underreach 3Ph only
04 Permissive overreach 1Ph and 3Ph
05 Permissive overreach 3Ph only
06 Blocking 1Ph and 3Ph
07 Blocking 3Ph only
08 Zone 1 extension 1Ph and 3Ph
09 Zone 1 extension 3Ph only

SW9 Power swing detection Power swing detection
disabled enabled
SW8 Disable weak infeed option Enable weak infeed option
schemes 04 and 05 only
SW7 Disable weak infeed trip Enable weak infeed trip if
SW6 Normal A/R action Block A/R if CIS not
energised for schemes 02 to
07 inclusive
SW5 Disable comparator self- Enable comparator self-
checking checking
SW4 Normal A/R checking Block A/R for 3Ph Z1/AT
faults
SW3 VTS indication only VTS indication and block
SW1 SOTF for any comparator SOTF for current and no
operation volts on any phase
Figure 2: Scheme options available and option switches

QUADRAMHO Chapter 5
Appendix A
Page 1 of 18
(Top rack)
IZ
Memory check
VA 1 A11 Connect 1Z Terminals 1, 2 and 3
together, apply a close up CN fault
VB 2 A13
with adequate source impedance
The references
VC 3 A15 show which case
terminals are
connected to the
VN 4 A12 red side of the
test plug when
5
DC+ A17 inserted
6
DC A18
Any trip 7 B21
Any trip 8 B22

All secondary injections are made to
the relay side of the test plug.
9
10
Bridge to enable all
output contacts
Relay
side
(Bottom rack)
IY
VTS instantaneous indication and
IA 1 A19
blocking check
2 A20 Inject current into 1Y1 link 2 to 4 and
return to neutral from 1Y3. Apply AN
IB 3 A21
fault.
4 A22
IC 5 A23
6 A24
These connections
must be made before
7 A25 the test plug is inserted
Check on function of SW4
IN 8 A26
To obtain a 3 phase Zone 1
9 fault inject into 1Y1, link 1Y1 to
Internal
short 1Y3, 1Y2 to 1Y4, 1Y4 to 1Y6 and
10 return to the neutral from 1Y5, apply
AN fault
Figure 1: Injection test plug connections

QUADRAMHO Chapter 5
Appendix A
Page 2 of 18
Code selection
01 Basic 3Ph only

SW9 Power swing detection Power swing detection
disabled enabled
schemes 04 and 05 only
07 inclusive
SW5 Disable comparator self- Enable comparator self-
checking checking
SW4 Normal A/R checking Block A/R for 3Ph Z1/AT
faults
SW3 VTS indication only VTS indication and block
SW1 SOTF for any comparator SOTF for current and no
operation volts on any phase
Figure 2: Scheme options available and option switches

QUADRAMHO Chapter 5
Appendix A
Page 3 of 18
Test Test and method LED Comments

option indications
no.
40 Zone 1 comparators AN A Amplitude and angular

Gated with low set hysteresis operate on
current level detectors BN B any Zone 1 comparator.
CN C No tripping will occur
Zone 1 fault) BC Z3
CA AIDED
TRIP
(apply rated volts to A3A4) SOTF
Reset Zone 1 extension
miniature circuit breaker
opto input (apply rated volts V~FAIL
to A1A2)
41 Zone 2 comparators AN A Amplitude and angular

Gated with low set hysteresis operate on
current level detectors BN B any Zone 1 comparator.
CN C
Zone 2 fault) BC Z3
CA AIDED No tripping will occur
TRIP
Signal receive/reset Zone 1
extension opto input SOTF
(apply rated volts to A9A10)
Channel in service opto input V~FAIL
42 Zone 3 comparators AN A Amplitude hysteresis

Gated with low set operate on
current level detectors BN B any Zone 3
CN C comparator.
Zone 3 fault) BC Z3 No tripping will
CA AIDED occur
TRIP
Zero sequence voltage
Level detector SOTF
(secondary inject)
Inhibit PSB opto input V~FAIL
Figure 3: Sheet 1 Input test options Table 6

QUADRAMHO Chapter 5
Appendix A
Page 4 of 18

option indications
no.
detectors BN B
(secondary inject CN C
voltage
Pushbutton & push Z2
button override
(operate push-
button or apply 0V
to SK1 Pin 9)
Low set current A Z3

level detectors
B AIDED TRIP
(secondary inject C SOTF
current)
Inhibit PSB opto input N V~FAIL
45 Self check of AN A The LED lights

Zone 1 comparators BN B for the appropriate
CA AIDED TRIP 8 LEDs are on
self check has
not occurred
46 Self check of AN A As option 45

Zone 1 comparators BN B
CN C
AB Z2
BC Z3
CA AIDED TRIP
47 Self check of AN A As option 45

Zone 3 BN B
comparators CN C
AB Z2
BC Z3
CA AIDED TRIP

comparator
Figure 3: Sheet 2
QUADRAMHO Chapter 5
Appendix A
Page 5 of 18

option indications
no.

(secondary inject BN B
Zone 1 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Breaker open opto SOTF
input (apply rated
volts to A3A4)
Reset Zone 1 extension/ V~FAIL
miniature circuit breaker
opto input
(apply rated volts to
A1A2)

Zone 2 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Signal receive/reset SOTF

Zone 1 extension opto input
(apply rated volts to A9
A10)
Channel in service opto V~FAIL

input (apply rated volts
to A7A8)
Zone 3 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Zero sequence voltage

level detector (apply low SOTF
voltage and increase to pick up)

(apply rated volts to V~FAIL
A5A6)
Figure 3: Sheet 3
QUADRAMHO Chapter 5
Appendix A
Page 6 of 18

option indications
no.
53 Memory input volts VC B Option 53, LED B

(apply rated volts may be latched on or
to C Phase) off when rated volts
are not present. Monitor
Zone 6 comparators AB C memory on monitor
(secondary inject output socket pin 2 & 24,
Zone 6 fault) disregard LED B
indication LED on when
Option setting switch SW9 Z2 switch in right
High set current A Z3 hand position
level detectors B AIDED TRIP
(secondary inject C SOTF
current) N V~FAIL
54 Zone 2 timer 1280 A Indication lit

Switch setting 640 B when switches in
320 C right hand
160 Z2 position
80 Z3
40 AIDED TRIP
20 SOTF
10 V~FAIL
55 Zone 3 timer A As option 54

switch setting 2560 B
1280 C
640 Z2
320 Z3
160 AIDED TRIP
80 SOTF
40 V~FAIL
56 TP timer switch 48 A As option 54

setting 24 B
12 C
6 Z2
TD timer switch 48 Z3
setting 24 AIDED TRIP
12 SOTF
6 V~FAIL
Figure 3: Sheet 4
QUADRAMHO Chapter 5
Appendix A
Page 7 of 18
Test Test and Method LED Comments

Option Indications
No.
57 Option switch SW8 A As option 54

setting SW7 B
SW6 C
SW5 Z2
SW4 Z3
SW3 AIDED TRIP
SW2 SOTF
SW1 V~FAIL
58 Socket 1 inputs PIN8 A This option

PIN7 B will override
PIN6 C the normal
PIN5 Z2 function of the
PIN4 Z3 test socket
PIN3 AIDED TRIP except when
PIN2 SOTF option F0
PIN1 V~FAIL is selected.
99 EPROM identifier 8 A The EPROM

number 4 B identifier no.
(press push button) 2 C is indicated in
1 Z2 binary coded
8 Z3 decimal form.
4 AIDED TRIP Information
2 SOTF given is
1 V~FAIL intended for ALSTOM
T&D use.
F0 Code selection CSNX8 A The binary

number (enter F0 4 B coded decimal
to socket 1) 2 C form of each
1 Z2 code switch
CSNY8 Z3 number is
4 AIDED TRIP given.
2 SOTF
1 V~FAIL
Figure 3: Sheet 5
QUADRAMHO Chapter 5
Appendix A
Page 8 of 18
C B A1 85z-1 B1
A3 85z-2 B3
(See note 2) A4
A5 94A-1 B5
Direction of power flow Inhibit power swing blocking B6 Trip A (1)
94A-2 B7
A7 B8 Trip A (2)
P2 P1
A A Channel in service A8 94B-1 B9
S2 S1 A9
B B B10 Trip B (1)
C C
A11 IZ1 B12 Trip B (2)
Va 94C-1 B13
A13 IZ2
VT secondaries Va A15 IZ3
B14 Trip C (1)
Va 94C-2 B15 See note 7
Va A12 IZ4 B16 Trip C (2)
dc ve A17 IZ5 94T-1 B17
A18 IZ6 B18 Trip 3PH (1)
dc ve 94T-2 B19
A19 IV1 B20 Trip 3PH (2)
A20 IV2 94-1 IZ7 B21
IZ8 B22 Any trip (1)
A21 IV3 94-2 B23
A22 IV4 B24 Any trip (2)
A23 IV5 96-1 B25
A25 IV7 19A-1 C1
A26 IV8 C2 Fault locator A
19B-1 C3
C4 Fault locator B
Output 19C-1 C5
relays
common 19E-1 C7
Z2-1 C9
Z3-1 C11
98-1 C15
C16 SOFT trip alarm
97X-1 C17
C18 Fuse fail alarm
95-1 C19
97Y-1 C21
C22
(See note 3)
Notes:
c) Opens after operation of a) and b) when heavy 6. When busbar VTs and a single phase tripping scheme
duty connector is removed. incorporating P.S.B. are used this opto must be energised
during single pole dead times.
7. When 3 phase tripping scheme is used Trip A, Trip B, Trip C
and Any Trip respond as Trip 3 Phase.
Figure 4a: External connection diagram: Quadramho static distance protection relay 1 and 3 phase
tripping
QUADRAMHO Chapter 5
Appendix A
Page 9 of 18
C B A1 95z-1 B1
A3 95z-2 B3
(See note 2) A4
A5 94A-1 B5
Direction of power flow Inhibit power swing blocking B6
94A-2 B7
A7 B8
P2 P1
A A Channel in service A8 94B-1 B9
S2 S1 A9
B B B10
C C
A11 IZ1 B12
Va 94C-1 B13
Va A13 IZ2
VT secondaries B14
A15 IZ3 Trip 3PH
Va 94C-2 B15
Va A12 IZ4 B16
dc ve A17 IZ5 94T-1 B17
A18 IZ6 B18
dc ve 94T-2 B19
A19 IV1 B20
A20 IV2 94-1 IZ7 B21
IZ8 B22
A21 IV3 94-2 B23
A22 IV4 B24
A23 IV5 96-1 B25
A25 IV7 19A-1 C1
A26 IV8 C2 Fault locator A
19B-1 C3
C4 Fault locator B
Output 19C-1 C5
relays
common 19E-1 C7
Z2-1 C9
Z3-1 C11
98-1 C15
C16 SOFT trip alarm
97X-1 C17
C18 Fuse fail alarm
95-1 C19
97Y-1 C21
C22
(See note 3)
Notes:
c) Opens after operation of a) and b) when heavy
duty connector is removed.
Figure 4b: External connection diagram: Quadramho static distance protection relay 1 and 3 phase
tripping
QUADRAMHO Chapter 5
Appendix A
Page 10 of 18
Z3
Gr Gr
Z3
Z2
Z2
Z1
Z1
Z1
Z2
Z3
Ph PSB Ph PSB
Z3 Z3
Z2
Z2
Z1 Z1
Figure 5: Two Quadramho types both have 18 measuring elements and PSB
QUADRAMHO Chapter 5
Appendix A
Page 11 of 18
Auxiliary relay mode normal scheme option operations only

socket (active LED auxiliary relay
pin low)

SK220 SK AT IND AIDED TRIP Aided trip 94Y1
SK217 SK CTX Signal send output 85X1 85X2
SK216 SK +12V +12V supply rail
SK214 SK +5V 5V supply rail
SK213 SK BAR Block autoreclose output 961
SK212 SK TRIP 3Ph 3phase trip signal issued 94T1 94T2
SK211 SK ANY TRIP Trip signal issued by 941 942
distance relay
SK210 SK PSB ANN POWER SWING Output of power swing 51
blocking feature
SK29 SK CRX ANN Signal receive optical
isolator energised
SK27 SK TPS Output of power swing
50 ms timer
Z1Z2Z3 (except PSB)
SK25 SK SOTF EN Switchontofault
feature enabled
SK24 SK MCK/28 Master clock/28 (=3.6kHz
@ 50Hz, 4.32kHz @ 60Hz)
SK22 SK0V Zero volt common
SK21 SK INH MR Short to S~K22 to inhibit
relays
Figure 6: Table of test points

QUADRAMHO Chapter 5
Appendix A
Page 12 of 18
Test Output tested and switch to Output given on the rear terminals
option be set to the right and/or the monitor point box
60 A Indication SW8 Pressing the reset SK225

B Indication SW7 button causes the SK224
C Indication SW6 voltage on the monitor SK223
Z2 Indication SW5 point box terminals SK222
Z3 Indication SW4 (2 is 0V reference) to SK221
AIDED TRIP Indication SW3 fall from 24V to zero K220
Use high impedance SK219
"SOTF Indication SW2 voltmeter SK218
V~FAIL Indication SW1
61 Fault locator A SW8 19A1 C1C2

Fault locator B SW7 19B1 C3C4
Fault locator C SW6 19C1 C5C6
Fault locator N SW5 19E1 C7C8
62 Signal send SW8 85X1, 85X2, B1B2, B3B4 SK217

Aided trip alarm SW3 94Y1 C13C14
Switch on to fault SW2 981 C15C16
Trip alarm
63 POWER SWING indication SW6

Any Z1, Z2, Z3 SW5
Block A/R SW4 961 B25B26 SK26
Power swing alarm SW2 951 C19C20 SK213
64 SOTF Enabled SW3 As for 60 SW25
88 ANY TRIP SW5 941, 942 B21B22, B23B24 SK211

TRIP 3Ph SW4 94T1, 94T2 B17B18, B19B20 SK212
TRIP A SW3 94A1, 94A2 B5B6, B7B8
TRIP B SW2 94B1, 94B2 B9B10, B11B12
TRIP C SW1 94C1, 94C2 B13B14, B15B16
Note: No contact will close until the appropriate SW switch is to the right and the reset button is
pressed.
Figure 7: Output test options

QUADRAMHO Chapter 5
Appendix A
Page 13 of 18
Information required by the commissioning engineer

Station _________________ Circuit _________________ SHPM1
1 | RRZ07 2 | RRM08 3 | RRM09 4 | RCL10 5 | RFV04 6 | RVC53
K1 = K11 = K31 = Power swing
K2 = K12 = K32 = blocking Relay
available
ZPH = K1 + K2 K13 = K33 = Z1
In K14 = Z3 Z2
= Z1 = (K31 + K32)ZPH Z3
= (K11 + K12 + K13)K14ZPH = SW9
Vn = V
Z1 = tZ2 = msec f = Hz
a/ If fitted
b tZ3 = msec
K3 If fitted Z1X =
= = Z1 x K15 If used 7| REC15
tp = msec
RS = K3 K15 =
In Z1X = If used
= tD = msec Ph =
K21 = K35 = SW8 N =

K4 = SW7
K22 = K36 = SW6 QUADRAMHO
K5 =
K24 = K37 = SW5
K6 = SW4 In = Amps
Z2 = (K21+K22)K24ZPH Z3'
SW3
ZN = K4+K5+K6 = = (K35+K36) K33xK37ZPH SW2 fn = Hz
In
= SW1
=
fn = Hz fn = Hz X= Y=
Switch positions for the selected operating scheme

If Ph and N are different the basic ground fault loop impedance should be provided Z
(Ground fault) = ZPh + ZN = _________ _________ degrees.
Vx(2) given on module 4 is for the optical isolator inputs.
Vx(1) is the auxiliary dc supply used to derive the internal dc rails and is given on the back of the
relay where the power supply is housed.
Due to the lack of space above the tZ2, tZ3, tp and tD switch positions are shown below.
(test option 57 is used to check the SW1 8 switch positions).
Check with test Check with test Check with test

option 54 option 55 option 56
When using the test options If a switch is to be set to
1280 48 to check the switch positions the right indicate this by an
640 2560 tp 24 the indication LEDs will light arrow
320 1280 12 for any switch set to the
t2 160 t3 640 6 right the top LED If a switch is to be set to
80 320 48 corresponds to the top the left indicate this by an
40 160 td 24 switch in the block of 8 etc. arrow
20 80 12
10 40 6
Figure 8: Setting check list

QUADRAMHO Chapter 5
Appendix A
Page 14 of 18
1Y 1Z 1Z
Lower rack Upper rack Upper rack
1 1 1
2 2 2
3
3 3
4 4
4 All connections
5 must be made 5 5
before plug is
inserted
6 6
6
7 7 7
8 8 8
9 9 9
10 10 10
(a) (b) (c)
For current reversal For rotation of the voltages
Figure 9: Test plug connections for on load tests

QUADRAMHO Chapter 5
Appendix A
Page 15 of 18
+ MW
VA
IA IA

MVAR +MVAR
IA IA
MW
= Import + = Export
M.V.A.R.
=TAN1
M.W
Figure 10: Determination of load angle from load information

QUADRAMHO Chapter 5
Appendix A
Page 16 of 18
Lead Lag
VA
RCA
NOTE:
On load checks only involve
operation of phase -phase
compararors for simplicity these
diagrams are drawn on a single
phase basic
Measured at relay with

phase angle meter
I
PH IA
Operation
Power system information VB

VC
Load angle = Tan1 MVAR = 2
MW
1must show reasonable agreement with 2
Figure 11a: On load check exporting power with a lagging power faction
QUADRAMHO Chapter 5
Appendix A
Page 17 of 18
Lead Lag
VA
Voltage connections for

operation(see Fig. 9C)
Line Relay
VB VA
VC VB
VA VC
Also it is seen that

current reversal will give
operation for the normal
voltage connections
n
ratio
Ope
Measured at relay
with a phase 1
angle meter
PH
VB
VC
IA
Power system information RCA

MVAR
2 = TAN1
MW
1and 2 must show reasonable agreement

for the position of 1A
Figure 11b: On load check importing power with a leading power faction
QUADRAMHO Chapter 5
Appendix A
Page 18 of 18
LEAD LAG
VA
90 270
VC VB
180
Figure 11c
QUADRAMHO Chapter 5
Addendum 1
Page 1 of 3
STATIC DISTANCE PROTECTION TYPE SHPM
Calculation of reach settings (A worked example is given in the

application notes)
Station __________________________ Date ____________________________
Circuit __________________________ Engineer ________________________
Panel ___________________________ Contract _________________________
Scheme options __________________ Drawings ________________________
1 GENERAL DATA
1.1 CT RATIO ________________________ ________________________
VT RATIO ________________________ ________________________
1.2 LINE SECTION LENGTHS LINE 1 _______________ km
LINE 2 _______________ km
LINE 3 _______________ km
1.3 POSITIVE SEQUENCE LINE IMPEDANCE ___________________ ohms/km
ZERO SEQUENCE LINE IMPEDANCE ___________________ ohms/km
1.4 = Tan1 X/R 1 = 0 = ___________________ degrees
1.5 Z (PRIMARY) = (R2 + X2) Z1 = ___________ Z0 ___________ ohms/km
CT ratio
1.6 Z1 (SECONDARY) = Z1 (PRIMARY) x = ______________ ohms/km
VT ratio
VT RATIO
CT ratio
Z1 (PRIMARY) = Z1 (SECONDARY) x = ______________ ohms/km
VT ratio
QUADRAMHO Chapter 5
Addendum 1
Page 2 of 3
SETTINGS ON RELAY
2.1 Zone 1 ohmic reach = 80% of length of line 1 x Z1 (secondary)

= ___________ ohms
2.2 Select K1 + K2 = 4.8 unless the required reach is less than 4.8 ohms (0.96 ohm if
In = 5A) when a value equal to slightly less than the reach should be chosen.
K1 = ________________ K2 = ________________
ZPh = K1 + K2 = _______________ ohms

In
2.3 Divide the required Zone 1 reach by ZPh to obtain the Zone 1 multiplying factor
(K11 + K12 + K13) K14 = __________________
K11 = __________________
K12 = __________________
K13 = __________________
K14 = __________________
2.4 Zone 2 ohmic reach = 50% section 2 plus section 1
= _________________ ohms (secondary)
Divide the required Zone 2 reach by ZPh to obtain the Zone 2 multiplying factor
(K21 + K22) K24 = _____________________
K21 = ______________________
K22 = ______________________
K24 = ______________________
2.5 Zone 3 ohmic reach (forward) = __________ ohms (secondary)
Divide the required Zone 3 reach by ZPh to obtain the Zone 3 multiplying factor
(K31 + K32) K33 = _____________________
K31 = ______________________
K32 = ______________________
K33 = ______________________
QUADRAMHO Chapter 5
Addendum 1
Page 3 of 3
2.6 Zone 3 ohmic reach (reverse) = __________ ohms (secondary)
Divide the required Zone 3' reach by ZPh to obtain the Zone 3' multiplying factor
(K35 + K36) K33 x K37 = _______________________
K35 = ______________________
K36 = ______________________
K37 = ______________________
2.7 Neutral impedance setting ZN
K4 + K5 + K6 = [(Z0/Z1) 1] x (K1 + K2)/3 = _____________________
K4 = _______________________
K5 = _______________________
K6 = _______________________
2.8 Relay characteristic angles
If Ph and N differ by more than 10 the vector sum of ZPh and ZN should be
found to give the basic ground fault loop impedance and angle.
ph = ______________________
N = ______________________
2.9 Zone 1 extension ohmic reach (if used)
Divide the required Z1X reach by Z1 to obtain the Z1X multiplying factor
K15 = _______________________
2.10 Resistive reach (if quadrilateral characteristic is fitted)
Application engineers must advise the setting RS = ___________
RS = K3
In
K3 = _____________
Fill in the setting check list Figure 8 in the Commissioning Instructions

QUADRAMHO Chapter 5
Addendum 2
Page 1 of 13
STATIC DISTANCE PROTECTION TYPE SHPM
Station __________________________ Date ____________________________
Circuit __________________________ Engineer ________________________
Panel ___________________________ Contract _________________________
Scheme option ___________________ Drawings ________________________
TEST RESULTS
PRELIMINARY CHECKS (Tick boxes if correct)
Wiring check
Insulation test
Relay and module data check
DC supply check
Power up
Relay inoperative alarm contact check
Self-check
VOLTAGE LEVEL DETECTORS (Test Option 43)
Level Terminals LED Pick-up Drop-off Reset

detector injected indication volts volts ratio (%)
A phase 1Z 1 4 A
B phase 1Z 2 4 B
C phase 1Z 3 4 C
If actual measurements are not taken just tick to show that pick-up has occurred at
49 volts and not at 40 volts.
QUADRAMHO Chapter 5
Addendum 2
Page 2 of 13
PHASE CURRENT LEVEL DETECTOR CHECKS
Low-sets (test option 43)
5 4.8
Pick-up = x x In A (10%)
100 K1 + K2
K1 + K2 = ________ In = ________ A Nominal pick-up = _________

A phase 1Y 1 2 Z3
B phase 1Y 3 4 Aided trip
C phase 1Y 5 6 SOTF
High sets (test option 53)
12.1 4.8
Pick-up = x x In A (10%)
100 K1 + K2
= ________ A

A phase 1Y 1 2 Z3
B phase 1Y 3 4 Aided trip
C phase 1Y 5 6 SOTF
RESIDUAL CURRENT LEVEL DETECTOR CHECKS
Low-set (test option 43, LED indication V~FAIL)
2 4.8
Minimum operate level = x x In A (20%)
100 K1 + K2
= ________ A
Measured value injecting into A phase (1Y 1 2) = _____________ mA
Measured value injecting into B phase (1Y 3 4) = _____________ mA
Measured value injecting into C phase (1Y 5 6) = _____________ mA

QUADRAMHO Chapter 5
Addendum 2
Page 3 of 13
4.2 High-set (test option 53, LED indication V~FAIL)
16 4.8
Minimum operate level = x x In A (20%)
100 K1 + K2
= ________ A
Measured value injecting into A phase (1Y 1 2) = _____________ mA
Measured value injecting into B phase (1Y 3 4) = _____________ mA
Measured value injecting into C phase (1Y 5 6) = _____________ mA
DIRECTIONAL CHECK AND ZONE REACH MEASUREMENTS
Directional checks with a close up fault.
AN BN CN
AB BC CA
OPERATION TIMES
Source
impedance Phase Zone 1 (ms) Zone 2 (s) Zone 3 (s)
(Zs) ohms 50% of reach
AB
BC
CA
AG
BG
CG
QUADRAMHO Chapter 5
Addendum 2
Page 4 of 13
Relay Reqd Fault Relay Relay Equiv Actual %

angle reach type volts amps Z % Error
n/ph Zr
Zone AG
1 BG
CG
Zone AG
2 BG
CG
Zone AG
3 BG
CG
Zone 3 AG
Rev BG
CG
Quad AG
Res BG
if applicable CG
Zone AG
1 BG
CA
Zone AB
2 BC
CA
Zone AB
3 BC
CA
Zone 3 AB
Rev BC
CA
REACH TEST USING A COMPUTER BASED TEST SET

(Computer printout may be attached if available)
TERMINAL BLOCK LAYOUT
A B C
1. (+) Reset Z1 Ext 2. () 1. Signal Send 2. 1. Fault Loc A 2.

QUADRAMHO
3. (+) Breaker 4. () 3. Signal Send 4. 3. Fault Loc B 4.

SERVICE MANUAL
Open
5. Trip A 6. 5. Fault Loc C 6.
5. (+) Inhibit 6. ()
7. Trip A 8. 7. Fault Loc N 8.
P.S.B.
9. Trip B 10. 9. Zone 2 Trip 10.
7. (+) Channel 8. ()
in Service 11. Trip B 12. 11. Zone 3 Trip 12.
9. (+) Sig. rec 10. () 13. Trip C. 14. 13. Aided Trip. 14.
11. VA 12. VN 15. Trip C 16. 15. SOTF Trip 16.
13. VB 14. 17. Trip 3 phase 18. 17. VTS Alarm 18.
15. VC 16. 19. Trip 3 Phase 20. 19. PSB Alarm 20.
17. DC+ 18. DC 21. Any Trip 22. 21. Inoperative 22.
19. IA 20. IA 23. Any Trip 24. 23. 24.
21. IB 22. IB 25. Block A/R 26. 25. 26.
23. IC 24. IC 27. 28. 27. 28.
25. IN 26. IN
27. 28.
When a three phase tripping scheme is used Trip A, Trip B, Trip C and ANY Trip respond as Trip 3 phase
Put a tick in the box adjacent to the function checked
Chapter 5
Page 5 of 13
R5888B
Addendum 2
SHPM CONTACTS AND OPTICAL ISOLATOR INPUTS CHECKED

QUADRAMHO Chapter 5
Addendum 2
Page 6 of 13
POWER SWING BLOCKING FEATURE (IF USED)
Zone 6 Boundary (Inject A B)
Forward loop impedance required = 1.3 x forward Zone 3 loop impedance
= _________ ohms
Measured loop impedance = _________ ohms
Reverse loop impedance required
= Zone 3 reverse loop impedance + (0.3 x forward Zone 3 loop impedance)
= ________ ohms
Measured loop impedance = _________ ohms
An additional tolerance of 15% is allowed for the reverse reach
50ms Timer check
Measured time = _________ ms (5ms)
Blocking and contact check
Block works on Zone 1
Alarm contact operation
Opto isolator inhibit input
VOLTAGE TRANSFORMER SUPERVISION
Operation on zero sequence volts
Voltage on phases not reduced _________ V
_________ V
Voltage for operation on 3rd phase _________ V
Timing check
Nominal 5.5s (0.1s)
Actual time _________ s

QUADRAMHO Chapter 5
Addendum 2
Page 7 of 13
Prevention of operation with zero sequence current
Function correct
Relay inoperative obtained

when SW3 to the right
Instantaneous indication and

tripping obtained with SW3 to the left
Comparators blocked and time delayed

indication obtained with SW3 to the right
SWITCH-ON-TO-FAULT FEATURE (MODE CONTROLLED BY SW1 AND SW2)
SOTF indication
Trip time _________ ms
For busbar VT breaker open

opto isolator input checked
Alarm contact check
MEMORY FEATURE CHECK

(Close up C-N fault and C-N volts on all phases)
Measured dwell time of trip contacts _________ ms
FUNCTION OF SW4
(If to the right, auto reclose blocked for certain 3 phase faults)
Block auto reclose contact check
TRIP TEST FUNCTION CHECK (Test option 88)
Contacts checked __________________________
Contact operation inhibit checked

QUADRAMHO Chapter 5
Addendum 2
Page 8 of 13
SCHEME TESTS TO BE DONE FOR SELECTED SCHEME
ZONE 1 EXTENSION SCHEME (08 or 09)
Loop impedances required are K15 x the Zone 1 requirements in the main table.
Phase faults
Required Nominal Test Set Source Impedance =

reach ZR loop
impedance Fault Test set Actual loop Nominal
required impedance CT ratio impedance %
with 100% set
Zone 1
extension
Fault Actual Relay Relay Equivalent %

type % volts amps Z ohms Error
AB
BC
CA
Ground Faults
Required Nominal Test Set Source Impedance =

reach ZR loop
impedance Fault Test set Actual loop Nominal
required impedance CT ratio impedance %
with 100% set
Zone 1
extension
Fault Actual Relay Relay Equivalent %

type % volts amps Z ohms Error
AG
BG
CG
QUADRAMHO Chapter 5
Addendum 2
Page 9 of 13
PERMISSIVE UNDERREACH SCHEME (02 or 03)
Aided trip check
Instantaneous trip with aided trip
Indication obtained for Zone 2
Fault with signal receive opto isolator energised
Signal receive delay on drop-off (90 = 110ms)
Time measured = _________ ms
Signal send check
Contact operation for Zone 1 fault
Contact operation in test option 62
Signal receive check
In test option 41 check that the SOTF LED illuminates
Block auto reclose checks (SW6 function check)
SW6 to the right CIS not energised
Block auto reclose contact (B25-26) is closed
CIS energised contact open
SW6 to the left contact open if CIS energised or not
BLOCKING SCHEME (06 or 07)
Measurement of tD
Measured time for tD _________ ms

QUADRAMHO Chapter 5
Addendum 2
Page 10 of 13
Aided trip
Instantaneous aided trip obtained for Zone 2

fault and no signal received
Zone 2 time delayed trip obtained for

Zone 2 fault and signal received
Measurement of tp
Operation times with tp = 0
________ , _________ , ________ , ________ , _________ ,
Average time = ms (t1)
Opeation times with set tp
________ , _________ , ________ , ________ , _________ ,
Average time = ms (t2)
Set tp = t2 t1 + 6 ms
= ms (tolerance 5ms)
Signal Send Check
Contacts (B1-2, B3-4) close for reverse Zone 3 fault
Contacts operation in test option 62 with SW8 to the right

QUADRAMHO Chapter 5
Addendum 2
Page 11 of 13
PERMISSIVE OVERREACH SCHEME (04 or 05)
Aided trip
Instantaneous aided trip obtained for Zone 2

fault and signal received
Signal send check
Contacts (B1-2, B3-4) close immediately for a Zone 2 fault
Contacts operation in test option 62 with SW8 to the right
Measurement of tp
Time from signal receive to signal receive annunciate on monitor point box
Tolerance as in instructions .............. ms
Measurement of tD
Time from signal receive removal to signal receive

annunciate extinguishing on monitor point box
.............. ms
Tolerance 6ms

QUADRAMHO Chapter 5
Addendum 2
Page 12 of 13
Echo feature (if used)

Check that no echo is given until the breaker has been open for at least 60ms by
measuring time from breaker open (with signal receive energised) to signal send.
Expected time 65 75ms
_________ ms
Signal send echo time
Measured by dwell time of contacts _________ ms
Weak infeed feature (if used)
Week infeed echo
Breaker closed, SW8 to the right, SW7 to the left.
No ac volts. Delay on echo signal send from

signal receive energisation _________ ms
Signal send echo time _________ ms
No signal send if ac volts present
Weak infeed tripping (if used)
SW7 to the left. No ac volts.

Time from signal receive to any trip _________ ms
Aided trip indication
Three phase trips given
No trip with ac volts present
Delay in drop-off of carrier receive measured

by delay in drop-off of any trip after the
signal receive is removed _________ ms

QUADRAMHO Chapter 5
Addendum 2
Page 13 of 13
SIGNALLING CHANNEL CHECK (SCHEMES 02 to 07)
Signal receive at end A correct
Signal receive at end B correct
Test option 62 is used to send

Test option 41 is used to check the signal receive
TRIP TEST (Test option 88)
Select required SW switches to the right to

check breaker operation when reset is pressed.
Breaker(s) operation obtained
FINAL SETTING CHECKS
All switches agree with check list
ON LOAD CHECKS
Voltage correct
Phase rotation correct
CT/VT phasing check
Forward directional check
Reverse directional check
SWITCHES MOVED FOR LOAD CHECKS K11
Ph
K1
K2
Reset any switches moved and then insert normal bridging plugs.
QUADRAMHO Chapter 5
Addendum 3
Page 1 of 1
NEW RECOMMENDATIONS FOR TIMER SETTINGS

IN THE CURRENT REVERSAL GUARDS
Permissive Overreach Scheme 04 or 05

If the current reversal guard is not required, ie there is no parallel line or the
Zone 2 reach is not set to more than 150% of the line length, then set tD = 0 and
tp = 90ms.
If the guard is required, recommended tp = 30ms minimum signalling channel
operating time.
(The nearest available setting should be selected if the exact value is not
available).
To give satisfactory scheme operation the value selected for tp must also be
less than mimimum time from fault inception to current reversal minus
(30ms + maximum signalling channel operating time).
Recommended tD 25ms + maximum signalling channel reset time.
(The nearest available setting above should be selected if the exact value is not
available).
Blocking Scheme 06 or 07
Recommended setting for tp = maximum signalling channel operating time + X
available).
X = 30ms for quadrilateral/mho version of the relay.
= 35ms for mho/lenticular (a/b = 1).
= 40ms for mho/lenticular (a/b = 0.69).
= 45ms for mho/lenticular (a/b = 0/41).
Recommended setting for tD = 25ms minimum signalling channel reset time.
available).
Note: The new recommendation for tD is to bring it in line with the approval
panels results on SHNB (Micromho Protection) that where a single
frequency signalling channel is used, during current reversals the block
signal to the relay should be continuous until the external fault has been
cleared.
QUADRAMHO Chapter 5
Addendum 4
Page 1 of 2
USE OF DOBLE TEST TO COMMISSION QUADRAMHO
There are no problems with the Doble F3 test set; however, a problem occurs when
finding phase to phase reach using the teed configuration of voltage from the test
set.
In the teed configuration, two of the voltages are set 180 apart, these voltages
are then varied to find the phase to phase reach of that particular element. By
examining Figure 39, Chapter 2 and using an applied B-C fault as an example, it
can be seen that the VB and VC voltages will sum to zero at the ve input of IC1.
Since the voltage level detectors will have dropped off due to the low input voltage
from the Doble the VMA signal will be replaced by a small percentage of IZ. The
squaring action of IC1 will therefore produce a voltage VKA which is almost totally
all IZ. When summed with VA the resulting VQA will have the effect of restraining
the relay.
It can therefore be seen that if B and C are not totally opposite in magnitude and
phase, their relationship varies slightly, the relay may go from an operate to a
restrain condition resulting in chattering of the comparators.
This problem may be cured by using the more conventional wye type of voltage
connection and tolerating the extra calculations involved.
An example, of setting up the Doble for finding a BC reach is given below.
VA (reference)
VB-C
RCA
IB-C
VC VB
VB-C
QUADRAMHO Chapter 5
Addendum 4
Page 2 of 2
The 3 voltages are set up as follows:

Voltage Amp 1 A phase (reference)
Voltage Amp 2 B phase (120 lag)
Voltage Amp 3 C phase (120 lead)
Magnitude of A is full phase voltage.
Magnitude of B and C should be equal and of a convenient value for the reach to
be measured.
VBC is now 90 lag from the reference.
One current amplifier should now be connected so as to inject current through the
B and C current circuits as shown.
The current amplifier angle set on the Doble should be (90 + RCA) lag.
The current is now varied to find the reach point. The reach being given by:
3 VB
ZBC =
IBC
Live
A21 (1Y3)
Doble A22 (1Y4)

current
amplifier
A24 (1Y6)
A23 (1Y5)
Common
SHPM
terminals
Type SHPM 101
Service Manual
Chapter 6
Problem Analysis
QUADRAMHO Chapter 6
Contents
1 INTRODUCTION 1
2 INITIAL TESTS 1
2.1 Test equipment required 1
3 QUICK FAULT FINDING GUIDE 2
4 TEST PROCEDURE 2
4.1 Test equipment required 2
4.2 General notes 3
4.3 Initial checks, including self-check facilities 3
4.4 Trip test function check 4
4.5 On angle reach checks 4
4.5.1 Zone 1 reach tests 4
4.5.2 Zone 1 ext reach checks 5
4.5.3 Zone 2 reach tests 5
4.5.4 Zone 3 reach checks 5
4.6 Check Z3 lenticular polar plot (lenticular versions only). 6
4.7 Resistive reach check (if quadrilateral characteristic is fitted) 6
4.9 Memory feature check (synchronous polarising) 7
4.10.1 Voltage level detectors 7
4.10.2 Fixed current level detector checks 8
4.10.3 Auto ranging low set and high set residual current level detectors 8
4.11 Opto isolator check 9
4.12 Auxiliary contacts check 9
5 FURTHER TESTION 9
5.1 Introduction 9
5.2 Power supply check 9
5.3 Self checking 10
5.4 Voltage circuit checks 10
5.5 Current level detector checks 10
5.6 Current input module checks 10
5.7 Check on clock frequency 11
5.8 Check on Z1 extension 11
6 REPAIRS 12
ADDENDUM A
QUADRAMHO Chapter 6
Page 1 of 12
Section 1 INTRODUCTION
The following tests are designed to locate a faulty module which can then be
returned to ALSTOM T&D Protection & Control Ltd for repair. The tests may be used
in conjunction with the commissioning instructions Chapter 5 in the event of a fault
being detected. The Quadramho relay has several inbuilt test options and a 25
way monitor socket which are detailed in Figures 1, 2 and 3. These features are
used in the following tests.
Section 2 INITIAL TESTS
These initial tests are only applicable if the relay inoperative alarm contact has
closed with the relay in service. If this is not applicable move to the main tests in
Section 3.
2.1 Test equipment required
i) 1 Multimeter (20,000 ohms per volt on dc range).
ii) A Quadramho accessory kit 01.
Ensure that the following are correct:
i) The dc supply is correct.
ii) The ac wiring is correct and supplies are present.
iii) The relay settings are correct and a valid scheme selected.
iv) The two heavy current bridging plugs are in.
This test is applicable if the VTS is set to block (SW3 to right). If the V~FAIL LED is
illuminated then the voltage transformer supervision feature has detected a fault in
the voltage supply to the relay or internally. Check, and if necessary repair the
supply and reset the relay via the pushbutton. If the relay fails to reset (relay
available LED remains off) the more detailed tests described in Section 5.4 are
required.
The internal dc power rails can be checked via the 25 way monitor point box.
Connect the multimeter common to pin 2 (0V) and check each of the following
voltages are within 5% of nominal.
Pin 3 +24V
Pin 14 +5V
Pin 15 12V
Pin 16 +12V
If this test fails, the tests described in Section 5.2 should be carried out.
This test checks to see if the microprocessor is correctly executing the software.
Select option 57 and set switches SW1-8 to the left. Check all 8 LEDs are off.
Select switches SW1-8 to the right and check all 8 LEDs are on. Selection option
43 and check LED Z2 is off. Press and hold the pushbutton checking the LED is on.
If any of these tests fail, replace module 4 (RCL 10).
This test is only applicable if the self-checking feature is selected (SW5 to the right).
If the relay fails a self-check it results in the relay available LED being extinguished.
This can be checked by selecting option 45. This option displays the results of a
QUADRAMHO Chapter 6
Page 2 of 12
self-check on Zone 1 comparators via the top six LED. A failure is indicated by a
LED being off. Repeat for Zone 2 by selecting option 46 and Zone 3 by option 47.
In this option the LED SOTF represents the power swing blocking comparator. If a
failure is detected the detailed tests in Section 5.3 must be carried out.
Remove the dc supply and extract module 1 (RRZ 07), insert the double extender
card in the left hand position and connect edge connector AA33 to pin 16 of the
monitor point box which should be plugged in. Do not replace the module. Turn
the dc supply on and check the relay available LED. If the LED is illuminated,
replace module 1 (RRZ 07) otherwise replace module 2 (RRM 08).
Section 3 QUICK FAULT FINDING GUIDE
If a spare set of modules is available a method of substitution may be used to

locate a faulty module. This method is often quicker and requires no extra
equipment.
The following table may be used as a guide:
Fault symptom Module most likely to be faulty
Any element in Zone 1/2 inaccurate Module 2 RRM 08

but Zone 3 alright.
Any element in Zone 3 inaccurate Module 3 RRM 09
but Zone 1/2 alright.
Ground fault reach low Module 1 RRZ 07
in all zones.
Phase fault reach low Module 1 RRZ 07
in Zone 1/2.
No operation for elements Module 1 RRZ 07
involving a common phase.
Reach equally inaccurate Module 5 RFV 04
all zones.
No operation for three Module 2 RRM 08
phase close up faults.
Section 4 TEST PROCEDURE
4.1 Test equipment required

Quadramho accessory kit 01.
Test set.
1 interval timer (one that can work off contacts or 24V levels and has a dwell
facility).
2 multimeters (20,000 ohms per volt on dc range).
Single channel oscilloscope with X 10 probe or frequency meter.
2 single pole switches.
QUADRAMHO Chapter 6
Page 3 of 12
4.2 General notes

All the relay contacts can be prevented from operating while the rest of the relay
functions normally and gives indications, also signals for operation times can be
taken from the monitor point box. It is however necessary to check the operation of
contacts during testing, so alternative trip isolation must be obtained as necessary
by removing the circuit breaker trip isolation links.
The heavy current bridging plugs can now be replaced by the test plugs. The only
connections that must be made before insertion are the CT shorting links (see
Figure 4) on the red ringed terminals 1 to 2, 3 to 4, 5 to 6 and 7 to 8 of the test
plug, going in the 1Y position.
The notes in raised letters on the side of the test plugs should be observed.
The equipment is now effectively isolated from the system.
The various tests must be done in the order described in flow chart 1 and the
various paths through the other flow charts must be followed in order to identify a
faulty module. Select SW1-9 to the left hand positions. Connect the 25 way
monitor point box. See Figure 2 for details.
4.3 Initial checks, including self-check facilities
If the dc supplies are available on the panel they can be checked on test plug 1Z
red ringed terminals 5(+) and 6(). If the supply is within the required operative
range it can be linked through to the relay. If the panel supply is not available a
suitable supply could be connected to the relay side terminals 5 and 6 of the test
plug.
The bridge on terminals 10 of the 1Z test plug should be made and the relay
available green LED on module 6 should light. If the dc is removed and re-applied
it will be seen that all the red LEDs on module 4 light while the relay goes through
its power procedure and at the end of it, the relay available LED lights. (A scheme
option number must be selected, see Figure 5).
All of the following are monitored continuously by circuits within the relay:
i) Internal dc voltage rails for +5V, +12V, +24V and 12V.
ii) The internal clock.
iii) The reference voltages for the level detectors.
iv) The processor running through its program.
If a fault is detected in any of the above, the relay operative LED will extinguish
and the fault finding instructions in Section 1 should be consulted.
Note: It should be remembered later that the inoperative alarm is given if the
output relays are inhibited by any means or if the voltage transformer
supervision is set to block and zero sequence volts are detected.
Connect three phase to neutral voltages, each above 70% of 63.5V to the relay
side terminals 1, 2, 3 and 4 of test block 1Z, as shown in Figure 4, an additional
self-check on the comparators is made available if SW5 on module 4 is to the right
(see Figure 5). This feature can now be initiated by pressing the reset button, when
all the red LED, except power swing, will be seen to flash briefly If a failure is
detected the relay available LED will extinguish. In this case or if the LED do not
momentarily flash refer to Section 5.3.
QUADRAMHO Chapter 6
Page 4 of 12
4.4 Trip test function check

During this test the trip contacts will close so care is needed if the contacts are
connected to a system.
Select option 88 and using the information in Figure 3 select the appropriate
switch to the right and check the trip contacts close when the reset pushbutton is
pressed. Return SW1-5 to the left.
After this test, the contacts can be prevented from closing by removing the link
across 1Z-10. This will extinguish the relay available LED.
4.5 On angle reach checks
4.5.1 Zone 1 reach tests
i) The relay should now be connected to equipment able to supply three phase to
neutral volts and current in the correct phase relationship for a particular type of
fault on the selected relay characteristic angle. The facility for altering the loop
impedance (phase and ground fault compensation or phase and phase)
presented to the relay is essential. This may be a continuous adjustment or steps
of around 1% in the voltage or current.
The voltage supply to any test set working off 3 phase supplies should be
checked for correct phase rotation.
The test blocks should be connected as shown in Figure 4. Select option 00.
ii) Ground faults
Commence with connections for an A-G fault. To establish confidence in
operation a close-up fault with adequate source impedance to limit the current
should be applied. The LED marked A should light followed by Z2 and Z3 if the
fault is left on.
The current should then be reversed to check that operation does not occur,
except for Z3 if set with some reverse reach.
The appropriate loop impedance should now be presented to the relay.
K14 (K1 + K2 + K4 + K5 + K6) (K11 + K12 + K13)
ohms
In
or the nearest available above.
Make small step adjustments to the impedance, only presenting it for less than
Zone 2 time to the relay and determine the highest impedance which gives
instantaneous illumination of the A LED (if a low Zone 2 time is set it may help
to increase it temporarily).
The measured impedance should be within 10% of the calculated value
assuming the angle of the impedance presented is within 5 of Ph and N on
module 7 of the relay. (This applies for all later impedance checks).
Repeat the tests for BG and CG including the directional checks.
Note: The indications are automatically reset when a new trip output is
obtained, but it may be easier to understand what happens by using
the manual reset on module 4.
QUADRAMHO Chapter 6
Page 5 of 12
iii) Phase faults

The appropriate loop impedance is now:
2 x K14 (K1 + K2) (K11 + K12 + K13)
ohms
In
Carry out the tests as for the ground faults, starting with A-B and proceeding to
B-C and C-A faults.
Note: If using a ZFB, VTS indication will now be obtained.
4.5.2 Zone 1 ext reach checks
Select option 08 and check the RESET ZONE 1 EXT opto isolator is not energised.
The Zone 1 reach is now extended by K15. The reach should be checked as in
Section 4.5.1.
4.5.3 Zone 2 reach tests
Select option 00.
When checking Zone 2 reaches the effect of the expansion of the reach when any
trip occurs may be apparent.
If a fault is applied less than 5% outside the Zone 2 boundary and inside the Zone
3 boundary, then if Zone 3 times out, giving a trip output, Zone 2 indication will
also be seen if the fault is maintained for Zone 2 time after the Zone 3 trip occurs.
The ground fault loop impedance required is:
(K1 + K2 + K4 + K5 + K6) (K21 + K22) K24
In
and for phase faults the loop impedance required is:
2 x K14 (K1 + K2) (K21 + K22) K24
ohms
In
the reach for each type of phase-ground and phase-phase element of the relay
should be checked as in Section 4.5.1.
4.5.4 Zone 3 reach checks
If tZ3 has been set to , the switch must temporarily be moved to the left to enable
the reach checks to be done. Zone 3 has the facility for setting forward and
reverse reaches, on the line angle, independently. There are two different shapes
available as selected by the customer when ordering the relay. These are lenticular
or a quadrilateral for ground faults.
The presence of the lenticular shape is indicated on module 3 by a switch labelled
a/b which controls the aspect ratio as illustrated on the frontplate; when a/b is set
to 1 the characteristic is circular. For this test set a/b = 1 if fitted.
The presence of the quadrilateral shape is indicated on module 1 when switch (K3)
for the setting of the resistive forward and reverse reach of Zones 1, 2 and 3 is
fitted.
The ground fault loop impedance required for forward checks is:
(K1 + K2 + K4 + K5 + K6) (K31 + K32) K33
ohms
In
QUADRAMHO Chapter 6
Page 6 of 12
and for reverse reach ground faults is:

(K1 + K2 + K4 + K5 + K6) (K35 + K36) K33 x K37
ohms
In
The phase fault loop impedances required are for forward faults:
2 x (K1 + K2) (K31 + K32) K33
ohms
In
and for reverse phase faults:
2 x (K1 + K2) (K35 + K36) K33 x K37
ohms
In
The reach checks should be carried out for each element of the relay as in
Section 4.5.1.
Note: For the reverse reach an additional tolerance of 15% is allowed.
4.6 Check Z3 lenticular polar plot (lenticular versions only).
To check the lenticular shape, note the relay settings and return to them after
this test.
Set a/b = 0.41 and the forward and reverse reaches to the same, ie.
(K31 + K32) K33 = (K35 + K36) (K37 + K33)
Also set Ph = N = 80
Figure 6 shows the normalised theoretical shape for Zone 3 for these conditions.
From this diagram the theoretical reach ZT, for off angle faults can be determined
for both forward and reverse faults. Using this information the ground fault loop
impedance required is:
(K1 + K2 + K4 + K5 + K6) (K31 + K32) K33 x ZT
ohms
In
at the particular angle of ZT.
The phase fault loop impedance required is:
2 x (K1 + K2) (K31 + K32) K33 x ZT ohms
Check the reach as in Section 4.5 allowing the same tolerances.
4.7 Resistive reach check (if quadrilateral characteristic is fitted)
Checks are done using resistive faults, thus in the forward direction all zones will
be seen to operate at the same loop impedance.
The required loop fault resistance is:
K3
ohms
In
When the fault is reversed, only Zone 3 should operate due to the slope on the
bottom line of the characteristic for Zones 1 and 2.
The checks should be carried out for all phase to ground faults and results should
be within 10% of the selected setting.
QUADRAMHO Chapter 6
Page 7 of 12

Zone 1 operation times should be checked by applying a fault at 50%
(approximately) of the Zone 1 reach.
An interval timer should be started when the fault is applied and stopped from the
any trip output SK2-11 of the 25 way monitor point box. A timer treats a
connection across SK2-2 and SK2-11 as a normally open contact.
The following points should be noted:
i) To obtain fast operating times is is essential to use dynamic tests starting with
all phase-neutral voltages above the level detector setting.
If this is not done filters in the voltage circuits will already be switched in and
the operation times will be slower.
ii) If the polarising quantities are not correctly provided by the test set some slower
times may be measured.
iii) The times vary with the point-on-wave of fault application it is thus suggested
that 10 operations be done for each type of fault.
iv) Times vary with the type of characteristic being used and the SIR.
v) Typical times expected are:
a) Shaped mho characteristic 12 27ms
b) Quadrilateral characteristic 17 32ms
If the polarising quantities are not correct or if the voltage filters are in initially,
times may increase by 10 15ms. Times on 60Hz are approximately 10% faster.
The operation times should be checked for each phase-ground and each phase-
phase element.
4.9 Memory feature check (synchronous polarising)
The memory is mainly to deal with 3 phase close up faults, but is made to run out
when any voltage level detector resets or when any comparator operates. There is
nominally 8 cycles of memory polarising which is derived from C phase volts.
The memory is re-connected 140ms after all voltage level detectors pick up and all
comparators have reset.
To satisfy the above conditions and make the relay behave as though it is seeing a
3 phase close-up fault.
This is achieved by applying a close-up C-N fault after removing the A and B
voltage inputs and connecting test plug 1Z terminals 1, 2 and 3 together (see
Figure 4).
If the dwell time of the trip contacts is now measured, this will give a measure of
the memory time.
4.10.1 Voltage level detectors
Select test option 43 (X = 4, Y = 3) all the LED now have a different function from
that on the nameplate. Apply volts in turn to each voltage input and check that the
LED indicated lights when 49 volts is applied and does not when 40 volts is
QUADRAMHO Chapter 6
Page 8 of 12
applied. If preferred the precise pick-up can be determined and the drop-off should
be within 10% of that value.
A phase 1Z 1-4 A
B phase 1Z 2-4 B
C phase 1Z 3-4 C
Note: During test option checks only the LEDs mentions are of concern in a
particular test; others may be on and can be ignored. However, a full
table is given in Figure 1.
4.10.2 Fixed current level detector checks
i) Low set current level detectors
Each phase current is monitored and the setting is changed by the value of K1
and K2 selected on module1, the most sensitive setting is 5% In.
Current setting = 5 x 4.8 x In A (10%)

100 K1 + K2
In = relay rated current
Keep test option 43 selected and inject current into each pair of phase
terminals, on the left hand side of the 1Y test block, in turn. Determine the pick-
up as indicated below; the drop-off should be within 10% of actual pick-up.
A phase 1Y 1-2 Z3
B phase 1Y 3-4 Aided trip
C phase 1Y 5-6 SOTF
ii) High set current level detectors

12.1 x 4.8
Current setting = x In amps (10%)
100 K1 + K2
Select test option 53 and inject current as in the previous test. Determine the
pick-up, drop-off should be within 10% of the actual pick-up.
A phase 1Y 1-2 Z3
B phase 1Y 3-4 Aided trip
C phase 1Y 5-6 SOTF
4.10.3 Auto ranging low set and high set residual current level detectors
The auto-ranging only comes into action when a minimum setting is exceeded.
The residual signal is derived by summing the vectors of the voltages in the relay
which are proportional to the phase currents.
The operational level when auto ranging, varies directly with the highest phase
difference current until a limit is reached. The minimum operate level varies
inversely with K1 + K2.
QUADRAMHO Chapter 6
Page 9 of 12
i) Low set
2 x 4.8
Minimum operate level = x In amps (20%)
100 K1 + K2
Select test option 43, inject current into any phase and check the minimum
operate level as indicated by the LED marked V~FAIL. Drop-off should be
within 10% of the actual pick-up.
ii) High set
16 x 4.8
Minimum operate level = x In amps (20%)
100 K1 + K2
Select test option 53 and inject current as for the low set and check the
V~FAIL LED for operation. Drop-off should be within 10% of the actual pick-
up.
4.11 Opto isolator check
Energise each opto isolator in turn, selecting the appropriate test option. Check the
correct LED is on.
Opto isolator Test option LED marking
Breaker open (A3A4) 40 SOTF
Reset Z1 ext (A1A2) 40 V~Fail
Sitnal receive (A9A10) 41 SOTF
Channel in service (A7A8) 41 V~Fail
Inhibit PSB (A5A6) 42 V~Fail
4.12 Auxiliary contacts check
Reconnect the link 1Z 10 to enable all auxiliary relays. Care must be taken, as
output contacts will close during this test.
All the outputs may be checked as described in Figure 3.
Section 5 FURTHER TESTING
5.1 Introduction
These tests may be required to isolate a faulty module. They must only be done in
the order specified in the flow charts.
5.2 Power supply check
Turn off the dc supply and remove all the modules with the exception of modules 6
and 7. Reconnect the dc supply and check the internal dc rails via the 25 way
monitor point box as described in Section 2.5. If a fault persists, replace the power
supply module ZRE 01. Otherwise remove the dc supply and insert each module
individually. Again check the internal rails. If the fault reappears, replace the
module. Otherwise insert all the modules and recheck the rails. If the fault returns,
replace the power supply module ZRE 01.
QUADRAMHO Chapter 6
Page 10 of 12
5.3 Self checking

Remove the dc and ac supplies from the relay and select option 00 and SW5 to
the right. Reconnect the dc and check the relay available LED is on. Connect the
three phase-neutral voltages and ensure they are each above 50V. Press the reset
pushbutton. Select option 45. If all 8 LEDs are on, a self check has not been
performed. In this case check the voltage level detectors as in Section 5.4. If they
are correct replace module 4 (RCL 10). If all 8 LEDs in option 45 are not on, use
the information in Figure 1 to determine which if any of the 6 Zone 1 comparators
have failed. Select option 46 and 47 to check the Zone 2 and the Zone 3/6
comparators respectively. Replace module 2 (RRM 08) if any element in Zone 1 or
2 failed or module 3 (RRM 09) if any element in Zone 3/6 failed.
5.4 Voltage circuit checks
These tests are designed to locate a fault in the voltage circuits. They must be done
in the order shown in flow chart 5, Addendum A of this Chapter.
Remove all the ac voltages, select option 43 and check LED A, B and C are off.
Apply balanced rated voltage, select option 43 and check LED A, B and C are on.
Apply balanced rated voltage, select option 42 and check LED SOTF is off.
Apply balanced rated voltage, select option 42, remove each voltage one at a
time and check LED SOTF is on.
Apply balanced rated voltage, select option 53, connect a multimeter on an ac
voltage range greater than 24V to pins 24 and 2 (0V) of the 25 way monitor point
box. Check the multimeter reads approximately 12V. Remove C phase voltage and
check multimeter reads approximately 0V.
Select option 00, connect link 1Z 10 and check relay available LED is on.
Repeat test 2.7.
5.5 Current level detector checks
These tests are to be done in the order given. Flow chart 6 can be used to identify
a faulty module.
Select option 53 and check the bottom four LEDs are off. If LED Z3, Aided trip or
SOTF are on, replace module 4 (RCL 10). If LED V~Fail is on remove module 1.
If the LED remains on replace module 4 otherwise replace module 1 (RRZ 07).
Select option 43 and check the bottom four LEDs are off. If the V~Fail LED is on
remove module 3 (RRM 07) or if LED Z3, aided trip or SOTF are on remove
module 1 (RRZ 07). If the LED remains on replace module 4 (RCL 10) otherwise
replace the module that has been removed.
Check the six fixed current level detectors and the two auto-ranging level detectors
as in Section 4.10.
5.6 Current input module checks
The output from the current input module may be monitored by removing module 1
and inserting a double extender card in the right hand position. The right hand
board can be inserted leaving the left hand one unconnected. One multimeter is
used to measure the primary current, the other the transphasor and the transformer
(Quadrilateral version only) output voltages at the test points given in the table
below. Inject current into each phase in turn and check the output voltages
according to the following formulae.
QUADRAMHO Chapter 6
Page 11 of 12
i) Transphasor main winding

0.34
V (IY1 IY2) = IY 1%
In
where Y is either A, B, C or N and IY is the primary current.
ii) Transphasor additional winding
0.068
V (IN3 Incommon) = IN 1%
In
iii) Current transformer (Quadrilateral version only)
0.544
V (IRY IRcommon) = 10%
In
Phase Signal Test point Formula
A IA1 AA5 (I)
IA2 AB5
B IB1 AA19 (I)
IB2 AA1
C IC1 AB15 (I)
IC1 AA3
N IN1 BB31 (I)
IN3 BB19
N IN3 AB19 (ii)
INcommon AB35
A IAR BB21 (iii)
IARcommon AB17
B IBR AA21 (iii)
IBRcommon AA29
C ICR AA25 (iii)
ICRcommon AB25
5.7 Check on clock frequency

Using the oscilloscope or frequency meter, check the clock frequency which is
available at the 25 way monitor point box pin 4 (pin 2 0V). The frequency should
be 3.6kHz 1% for 50Hz relays or 4.32kHz 1% for 60Hz relays.
5.8 Check on Z1 extension
Remove module 2 and insert the double extender card into the right hand position.
Connect the positive terminal of the multimeter to edge connector BB27 and the
negative terminal to pin 2 (0V) of the 25 way monitor point box. Select option 63
and SW3 to the right. Check the multimeter reads 0V dc. Press and hold the
pushbutton and check the multimeter reads 12V dc. If this test fails replace (RCL
10).
QUADRAMHO Chapter 6
Page 12 of 12
Section 6 REPAIRS
Should the need arise for the equipment to be returned to ALSTOM T&D Protection
& Control Ltd for repair, then the form at the back of this manual should be
completed and sent with the equipment, together with a copy of any
commissioning test results.
QUADRAMHO Chapter 6
Addendum A
Page 1 of 15
Test option no. Test and method LED indications Comments

with low set current BN B angular hysteresis
Zone 1 comparator.
(Secondary Inject AB Z2 No tripping will
Zone 1 Fault) BC Z3 occur
CA AIDED TRIP
(apply rated volts to A3 A4) SOTF
Reset Zone 1 extension opto
input (Apply rated volts to
A1A2)
The Zone 1 extension opto is V~ FAIL
redesignated as miniature
circuit breaker open opto
when this version has been
supplied.

with low-set current BN B angular hysteresis
Z2 comparator
(Secondary inject AB Z2 No tripping will

Zone 2 fault) BC Z3 occur.
CA AIDED TRIP
Signal receive opto input
(apply rated volts to A9A10) SOTF
The signal receive opto also
can be used to reset Zone 1
extension for the appropriate
thumbwheel selection option.
42 Zone 3 comparators gated AN A Amplitude

with low-set current BN B hysteresis operates
level detectors CN C on any Zone 3
comparator.
(Secondary inject AB Z2 No tripping will
Zone 3 Fault) BC Z3 occur.
CA AIDED TRIP
Zero Sequence voltage level SOTF
detector (secondary inject)
(apply rated volts to A5A6) V~ FAIL
Figure 1: Sheet 1: Input test options Table 6

QUADRAMHO Chapter 6
Addendum A
Page 2 of 15
detectors BN B
(secondary inject voltage) CN C
Pushbutton & pushbutton Z2
override
(operate push-button or
apply 0V to SK1 Pin9)
Low set current level A Z3
(secondary inject current) C SOTF
N V~ FAIL
45 Self check of Zone 1 AN A The LED lights for

comparators BN B the appropriate
CA AIDED TRIP 8 LEDs are
illuminated, self
check has not
occurred.

comparators BN B
CN C
AB Z2
BC Z3
CA AIDED TRIP
Figure 1: Sheet 2
QUADRAMHO Chapter 6
Addendum A
Page 3 of 15

comparators BN B
CN C
AB AB Z2
BC Z3
CA AIDED TRIP
comparator
V~FAIL

Zone 1 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Breaker open opto input SOTF
Reset Zone 1 extension opto input V~ FAIL
(apply rated volts to A1 A2)
The Zone 1 extension opto
is redesignated miniature circuit
breaker open opto when this
version has been supplied.

Zone 2 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Signal receive opto input SOTF
(apply rated volts to A9 A10)
(apply rated volts to A7 A8).
The signal receive opto also can
be used to reset Zone 1 extension
for the appropriate thumbwheel
selection option.
Figure 1: Sheet 3
QUADRAMHO Chapter 6
Addendum A
Page 4 of 15

Zone 3 fault) CN C
AB Z2
BC Z3
CA AIDED TRIP
Zero sequence voltage level SOTF
detector (apply low voltage
and increase to pick up)
Inhibit PSB opto input V~ FAIL
53 Memory input volts VC B Provides a squared

(apply rated volts to C phases) monitor output on
socket 2 pin 24.
Zone 6 comparator AB C
(secondary inject AB
Zone 6 fault)
Option setting switch SW9 Z2 LED on when
High set current level A Z3 switches in right
detectors B AIDED TRIP hand position.
(secondary inject content) C SOTF
N V~ FAIL
54 Zone 2 timer switch 1280 A Indications lit

640 B when switches in
320 C right hand position.
160 Z2
80 Z3
40 AIDED TRIP
20 SOTF
10 V~FAIL
55 Zone 3 timer A As option 54.

switch settings 2560 B
1280 C
640 Z2
320 Z3
160 AIDED TRIP
80 SOTF
40 V~FAIL
Figure 1: Sheet 4
QUADRAMHO Chapter 6
Addendum A
Page 5 of 15
56 Tp timer switch setting 48 A As option 54.

24 B
12 C
6 Z2
TD timer switch setting 48 Z3
24 AIDED TRIP
12 SOTF
6 V~ FAIL
57 Option switch setting SW8 A As option 54.

SW7 B
SW6 C
SW5 Z2
SW4 Z3
SW3 AIDED TRIP
SW2 SOTF
SW1 V~FAIL
58 Socket 1 inputs PIN 8 A This option will

PIN 7 B override the normal
PIN 6 C function of the test
PIN 5 Z2 socket except when
PIN 4 Z3 option F0 is
selected.
PIN 3 AIDED TRIP
PIN 2 SOTF
PIN 1 V~FAIL
99 EPROM identifier number 8 A The EPROM

(press push button) 4 B identifier number is
2 C indicated
1 Z2 in binary coded
8 Z3 decimal form
4 AIDED TRIP Information given
2 SOTF is intended for
1 V~FAIL ALSTOM Protection
& Control Ltd use.
FO Code selection CSNX 8 A The binary coded

number (enter F0 4 B decimal form of
to socket) 2 C each code switch
1 Z2 number
CSNY 8 Z3 is given.
4 AIDED TRIP
2 SOTF
1 V~ FAIL
Figure 1: Sheet 5
QUADRAMHO Chapter 6
Addendum A
Page 6 of 15
Auxiliary relay module normal scheme option operations only

socket pin (active low) LED auxiliary

SK220 SK AT IND AIDED TRIP Aided trip 94Y1
SK217 SK CTX Signal send output 85X1 85X2

SK216 SK +12V +12V supply rail
SK214 SK +5V 5V supply rail
SK213 SK BAR Block autoreclose output 961
SK212 SK TRIP 3PH 3phase trip signal issued. 94T1 94T2
SK211 SK ANY TRIP Trip signal issued by 941 942
distance relay.
SK210 SK PSB ANN POWER SWING Output of power swing 951
blocking feature.
SK29 SK CRX ANN Signal receive optical

isolator energised.
SK27 SK TPS Output of power swing
50 ms timer.
Z1Z2Z3 (except PSB).
SK25 SK SOTF EN Switchon-to-fault
feature enabled.
SK24 SK MCK/28 Master clock/28 (=3.6kHz
@ 50Hz, 4.32kHz @ 60Hz)
SK22 SK0V Zero volt common.
SK21 SK INH MR Short to SK22 to inhibit
relays
Figure 2: Table of test points

QUADRAMHO Chapter 6
Addendum A
Page 7 of 15
Test Output tested and switch to Output given on the rear terminals
option no. be set to the right and/or the monitor point box
60 A Indication SW8 Pressing the reset SK225

B Indication SW7 button causes the SK224
C Indication SW6 voltage on the monitor SK223
Z2 Indication SW5 point box terminals SK222
Z3 Indication SW4 (2 is 0V reference) to SK221
AIDED TRIP Indication SW3 fall from 24V to zero SK220
Use high impedance SK219
:SOTF Indication SW2 voltmeter SK218
V~FAIL Indication SW1
61 Fault Locator A SW8 19A1 C1C2

Fault Locator B SW7 19B1 C3C4
Fault Locator C SW6 19C1 C5C6
Fault Locator N SW5 19E1 C7C8
62 Signal send SW8 85X1, 85X2, B1B2, B3B4 SK217

Aided Trip alarm SW3 94Y1 C13C14
Switch on to fault SW2 981 C15C16
Trip alarm
63 POWER SWING indication SW6

Any Z1, Z2, Z3 SW5 SK26
Block A/R SW4 961 B25B26 SK213
Power swing alarm SW2 951 C19C20
64 SOTF Enabled SW3 As for 60 SW25
88 ANY TRIP SW5 941, 942 B21B22, B23B24 SK211

TRIP 3PH SW4 94T1, 94T2 B17B18, B19B20 SK212
TRIP A SW3 94A1, 94A2 B5B6, B7B8
TRIP B SW2 94B1, 94B2 B9B10, B11B12
TRIP C SW1 94C1, 94C2 B13B14, B15B16
Note: No contact will close until the appropriate SW switch is to the right and the reset
button is pressed.
Figure 3: Output test options

QUADRAMHO Chapter 6
Addendum A
Page 8 of 15
Secondary injection
IZ (top rack)
Memory check
VA 1 A11 Connect 1Z Terminals 1, 2 and 3
together, apply a close up C-N fault
VB 2 A13
with adequate source impedance
The references
VC 3 A15 show which case
terminals are
connected to the
VN 4 A12 red side of the
test plug when
5
DC+ A17 inserted
6
DC A18
Any trip 7 B21
Any trip 8 B22

All secondary injections are made to
the relay side of the test plug.
9
10
Bridge to enable all
output contacts
VTS instantaneous indication and

IA 1 A19
blocking check
2 A20 Inject current into 1Y1 link 2 to 4 and
return to neutral from 1Y3. Apply A-N
IB 3 A21
fault.
4 A22
IC 5 A23
6 A24
These connections
must be made before
7 A25 the test plug is inserted
Check on function of SW4
IN 8 A26
To obtain a 3 phase Zone 1
9 fault inject into 1Y1, link 1Y1 to
Internal
short 1Y3, 1Y2 to 1Y4, 1Y4 to 1Y6 and
10 return to the neutral from 1Y5, apply
A-N fault
Normal test plug connections
Figure 4: Secondary injection test plug connections

QUADRAMHO Chapter 6
Addendum A
Page 9 of 15
Code selection

01 Basic 3Ph only
Option switches
SW9 Power swing blocking Power swing blocking

disabled enabled

(POR) only


07 inclusive
SW5 Disable selfchecking Enable self-checking
SW4 Normal A/R action Block a/r for 3Ph Z1/AT

faults
SW3 VTS indication only VTS Indication and block
SW2 SOTF dead time 110sec SOTF dead time 200msec

SW1 SOTF for any SOTF for current and no
comparator operation volts on any phase
Figure 5: Scheme options available

QUADRAMHO Chapter 6
Addendum A
Page 10 of 15
80
Figure 6: Lenticular characteristic

QUADRAMHO Chapter 6
Addendum A
Page 11 of 15
Fails
Initial check 4.3 Section 1
Fails Replace module 4
(RCL10)
Fails
Trip contacts 4.4 Section 2.6
Pass Replace module 6
(RVC53)
Reach checks 4.5 Fails
No operation of one Reach of one or more

or more elements elements inaccurate
flowchart 2 flowchart 3

Z3 lenticular 4.6 (RRM09)
Quad resistive Fails No No

reach 4.7 Only Z3 faulty Only Z1 faulty
Yes Yes
Replace module 3 Replace module 2 Replace module 1
(RRM09) (RRM08) (RRZ07)
Fails
Z1operating times 4.8

Check memory 4.9 Slow replace module 5 Fast check timer replace
(RRM08)
(RFV04) module 2 (RRM08)
Check level detectors Fails

Flowchart 4
4.10
Check optical isolators Fails Replace module 4

4.11 (RCL10)
Check auxilary contacts Fails Replace module 6

4.12 (RVC53)
Flowchart 1: Test procedure

QUADRAMHO Chapter 6
Addendum A
Page 12 of 15
Check current level

detectors
5.5
Correct
Classify faulty elements

using test 4.5
All elements in Quad only just G/F Justl elements in Just elements in
All G/F and P/F elements
Z1/Z2/Z3 involving a common Z1/Z2 Z3
involving a current
phase phase

(RCL10) (RRM08) (RRM09)
Flowchart 2: No operation of one or more elements

QUADRAMHO Chapter 6
Addendum A
Page 13 of 15
Yes Replace module 3

Only Z3
elements faulty (RRM09)
No
Only Z2 Yes
elements faulty
No
Only Z1/Z1X Yes Pass Replace module 2

elements faulty Check 21 ext 5.8 (RRM08)
No
(RRZ07)
All G/F Yes
Check current input
elements faulty module 5.6
Replace module 7
Fail (RFC15)
No
Relay chattering or all

elements involving a
common phase 5%
inaccurate
Yes Replace module 2

Only Z1/Z2 elements (RRM08)
No
Only Z3 Yes Replace module 3
elements (RRM09)
No
Replace module 5 Yes Common No

elements all zones Replace zone affected
(RFV04)
Flowchart 3: Reach inaccurate

QUADRAMHO Chapter 6
Addendum A
Page 14 of 15
Level detector No
operating cont or not
Yes
Low set
Check level detectors No current and voltage
5.4 and 5.5 level detectors equally
innacurate
Yes
Check clock frequency

5.7
Fail Pass
Replace module 2 Replace module 1

(RRM08) (RRM07)
Flowchart 4: Level detector

QUADRAMHO Chapter 6
Addendum A
Page 15 of 15
54.1
Fail Pass
Remove module 1
5.4.2
repeat 5.4.1
Fail Pass
All 3 level detectors
pick up 5.4.3
Replace module 4 Replace module 1
(RCL10) (RRZ07)
1 or 2 level detectors
pick up 5.4.3
No level detectors
are picked up 5.4.3 Fail Pass
Pass Fail
Voltage circuits all
right
Replace module 5
5.4.4 (RFV04) and module 1
(RRZ07)
Replace module 4
Pass (RCL10)
Fail
Fail
5.4.5 5.4.6
Pass
(RFV04)
Fail

(RCL10) and module 1 (RFV04) and module 1 (RRZ07)
(RRZ07) (RRZ07)
Fail
5.4.7
Flowchart 5: Voltage circuits

Type SHPM 101
Service Manual
Chapter 7
Relay Identification
QUADRAMHO Chapter 7
Contents
1. MODULES 1
2. CASES 1
3. SCHEMES 1
4. CASE IDENTIFICATION CODING 2
5. MODULE POSITIONS 2
QUADRAMHO Chapter 7
Page 1 of 2
Section 1. MODULES
Modules are identified by a 12 character coding. This is known as a 3 alpha

coding and is split up as follows:
XYZ 00 000 000 A
The first three characters are letters, which with the next five numbers, specify all
variations which will affect the circuit diagram of the module. The last three
numbers affect parameters such as ratings, time ranges etc. which do not affect the
circuit diagram but affect component values. The last letter is a design suffix.
The circuit diagram of a module is referenced L1 XYZ 00 000.
The external connection diagram of a module is referenced L10 XYZ 00.
The variations covered by the first group of three letters are all dealt with on the
one drawing. If the function of a module is not explicit, then it will be referred to on
the diagrams.
Section 2. CASES
The complete identification of a case or subrack (a subrack is a single tier housing)

is a nineteen character coding. The first four characters are letters and the next
three are numbers. These seven characters, together with the eighth indicate only
the type of mounting. The rest of the coding is either a sequential number with
design issue suffix, or a coding which relates to module parameters only and does
not affect case circuit diagrams.
The case terminals and their functions are shown on the external connection or
application diagrams. As with the module diagrams, these are specified by a
drawing number of the form L10 WXYZ 000, where 10 means external connection
diagram and WXYZ 000 is the coding of the equipment concerned.
For small equipment, the system or scheme diagram which indicates how the relay
is connected to other equipment, may carry a coding L12 WXYZ 000 or L14
WXYZ 000. Here again WXYZ 000 is the equipment identification.
The connections between modules and case terminals are shown on drawing S1
WXYZ 000. This cross refers the equipment connection diagram and module
circuit diagram.
Section 3. SCHEMES
Where an auxiliary subrack forms part of a more complex scheme, that is, in
conjunction with other ALSTOM T&D Protection & Control equipment, a coding
comprising five letters and six numbers is used. The related scheme or system
diagrams are coded L12 VWXYZ 000 000 or L41 VWXYZ 000 000 where the
numbers 12 or 14 indicate tender or contract, respectively. The numbers
following the coding are required for complete identification.
QUADRAMHO Chapter 7
Page 2 of 2
Section 4. CASE IDENTIFICATION CODING
The four letter code identifying an auxiliary subrack assembly are specified as
follows. The first letter is always Z, the second letter is D if the case height is one
subrack and K if it is two. The third letter denotes the number of modules, B for
one, C for two etc, vowels not being used. The fourth letter indicates application:
D for distance relay application
T for tripping application
X for general purpose.
Section 5. MODULE POSITIONS
The position of a module in a subrack is designated by a number. Module 1 in an

equipment is the module at the top left hand side of the case, viewing from the
front. If the protection is split into more than one complete unit, then each unit will
have an equipment number which will appear with the module number. Thus
module 1 in equipment 1, is module 1.1 and module 2 is module 2.1, etc.
Each module will connect with at least one edge connector and in a subrack
diagram the position of an edge connector has a designation, eg Z25M. This
signifies that the edge connector is on the upper subrack (Z), the lower ones being
Y, X etc, in turn, in a multi-tier equipment. The figure 25 indicates that the edge
connector is 25 modular pitches from the left hand side of the case, again looking
at it from the front. There are a total of 48 modular pitches in the full width case.
The letter M identifies the whole designation as an edge connector position in a
modular case.
A case or subrack circuit diagram will identify modules by:
The 3 alpha reference
The module number in the case
The edge connector positions in terms of modular pitches
It will show the interconnection between module edge connectors and the
connections between edge connectors and case terminals.
Type SHPM 101
Service Manual
Chapter 8
Special Variations
QUADRAMHO Chapter 8
Contents
1. SPECIAL VARIATIONS OF QUADRAMHO 1

1.1 PM001 1
1.2 PM001 1
1.3 PM003 2
1.4 PM003 3
1.5 PM005 3
1.6 PM006 3
1.7 PM007 4
1.7.1 Fault locator contacts 4
1.7.2 MCB blocking input opto-coupler 4
1.7.3 Channel in service opto-coupler 4
1.8 PM008 5
QUADRAMHO Chapter 8
Page 1 of 5
Section 1. SPECIAL VARIATIONS OF QUADRAMHO
Due to the nature of construction of Quadramho, all features are supplied as

standard and consequently few variations in hardware are possible. However, a
number of special schemes have been developed for various customers and these
are implemented by change in the EPROM in module 4 (RCL10).
To check which version of software is fitted, it is necessary to use the 3 alpha code
from module 5 (see Section 7 on module identification).
1.1 PM001
If module 4 is: RCL 10 001 000
RCL 10 001 001
RCL 10 001 002
The relay is fitted with a standard scheme and there are no special features.
Case connection diagrams:
Single and three phase tripping S10 SHPM101 sheet 1
Three phase tripping only S10 SHPM101 sheet 2
1.2 PM001
RCL 10 001 021
RCL 10 001 022
The relay is fitted with a special scheme initially developed for ECNSW (Australia).
It is based on the standard scheme with 3 differences:
The Zone 2 time delayed trip has a setting range 0 5.1s in 20ms steps.
The Zone 3 time delayed trip has a setting range 0 10.2s in 40ms steps.
Fault locator logic operates for all three zones, priority given to Zone 1 then
Zone 2.
QUADRAMHO Chapter8
Page 2 of 5
1.3 PM003
RCL 10 001 031
RCL 10 001 032
The relay is fitted with a special scheme initially developed for TVA/BC Hydro,
North America. this scheme contains three three-phase schemes only:
01 Basic
05 POR
07 Block
Due to the nature of the application, 2 of the opto-isolators and the fault locator
contacts have been assigned different functions.
Opto-isolators
A1-A2 Block operation of POR scheme and inhibit signal send
(block scheme)
A3-A4 Breaker open
A5-A6 Block Z2T and Z3T earth fault time delayed trips
A7-A8 Channel in service
A9-A10 Signal receive
Modified contacts:
C1-C2 Any Zone 1 fault
C3-C4 Any Zone phase-phase fault
C5-C6 Any Zone 2 earth fault
C7-C8 Any Zone 3 phase-phase fault
Modifications to schemes
Basic scheme:
Standard basic scheme with the addition that the signal send contact will close
for a reverse Zone 3 fault.
POR scheme:
Standard POR scheme, however, if opto-isolator A1-A3 is energised, carrier
send and accelerated trips are inhibited.
Block schemes:
Standard block scheme, however, if opto-isolator A1-A2 is energised, carrier
send is inhibited.
Case connection diagram:
Three phase tripping S10 SHPM101 sheet 901
QUADRAMHO Chapter 8
Page 3 of 5
1.4 PM004
RCL 10 001 041
RCL 10 001 042
The relay is fitted with a special scheme initially developed for WAPDA, Pakistan.
Apart from the format of the indications the scheme is standard. The Zone 1
extension scheme is not available on this version. Indications now give comparator
start information
A
B
C
N INST. TRIP
DEL. TRIP
Z2/Z3 START
V FAIL
A, B , C and N illuminate immediately a comparator operates. Inst. Trip operates
for Zone 1 fault, SOTF and a weak infeed trip. Del. Trip operates for Zone or Zone
3 time delayed trips. Z1/Z3 start illuminates of any Zone 2 or Zone 3 comparator
operates.
1.5 PM005
RCL 10 001 051
RCL 10 001 052
The relay is fitted with a revised program to allow the relay to work with miniature
circuit breakers instead of fuses in the VT supply. This has produced some far
reaching changes in the way the relay performs.
Note: Zone 1 extension schemes 08 and 09 are no longer available.
1.6 PM006
RCL 10 001 061
RCL 10 001 062
The relay is fitted with a special scheme to allow remote resetting of the relay
targeting (indications). The opto-isolator previously used to reset the Zone 1
extension feature on scheme option TSN = 8 and 9, now resets the indications.
The carrier receive opto-isolator is only required when a carrier aided scheme is
selected (TSN 2, 3, 4, 5, 6, 7). It is therefore possible to share this opto-isolator
QUADRAMHO Chapter8
Page 4 of 5
with reset Zone 1 extension. This approach ensures that other features are
retained.
1.7 PM007
RCL 10 001 071
RCL 10 001 072
The application requirement for this module call for extra output contacts.
To achieve this, a number of existing contacts have had their function changed.
Normally this change is contained in the software, but on this occasion, it has
been necessary to omit the power swing blocking software and hardware features.
The revived contact arrangement is available with all the standard scheme option
TSN 00 to 09.
1.7.1 Fault locator contacts
Zone 3 is included in the logic for driving FLA, FLB and FLC. This enables phase
information to be provided for faults on the busbars (reverse faults).
The FLN logic closes only for single phase faults. this allows it to be used for
energising the signal receive opto-coupler in scheme 04, when the signalling
channel is not in service. Accelerated trips can now be achieved over the whole
length of the line, for single phase faults.
1.7.2 MCB blocking input opto-coupler
To provide the Zone 1 extension feature and allow the relay to be used with
miniature circuit breakers (mcbs), a separate opto-coupler input is provided for
each function.
Only a normally open contact (n/o) is provided on the mcb, so the logic has been
inverted. This results in the opto-coupler being energised when the mcb is closed,
ie. continually energised under healthy conditions.
1.7.3 Channel in service opto-coupler
The logic for this opto-coupler has been inverted to become Channel out of
service. This is necessary to ensure the trip output logic can provide single phase
tripping, even if the opto-coupler is not wired up. Correct auto-reclose logic is also
retained
Single and three phase tripping S10 SHPM101.09
Three phase tripping only S10 SHPM101.10
QUADRAMHO Chapter 8
Page 5 of 5
1.8 PM008
RCL 10 001 081
RCL 10 001 082
The relay is suitable for 60Hz applications only. It is fitted with a revised program
to allow the relay to work with miniature circuit breakers instead of fuses in the VT
supply This has produced some far reaching changes in the way the relay
performs.
Note: Z1 extension scheme is not available.
REPAIR FORM
Please complete this form and return it to ALSTOM T&D Protection & Control Ltd with the
equipment to be repaired. This form may also be used in the case of application queries.
ALSTOM T&D Protection & Control Ltd

St. Leonards Works
Stafford
ST17 4LX,
England
For: After Sales Service Department
Customer Ref: ___________________________ Model No: ____________________

Contract Ref: ___________________________ Serial No: ____________________
Date: ___________________________
1. What parameters were in use at the time the fault occurred?
AC volts _____________ Main VT/Test set

DC volts _____________ Battery/Power supply
AC current _____________ Main CT/Test set
Frequency _____________
2. Which type of test was being used?
3. Were all the external components fitted where required? Yes/No

(Delete as appropriate.)
4. List the relay settings being used

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
5. What did you expect to happen?

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
continued overleaf
6. What did happen?

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
7. When did the fault occur?
Instant Yes/No Intermittent Yes/No

Time delayed Yes/No (Delete as appropriate).
By how long? ___________
8. What indications if any did the relay show?

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
9. Was there any visual damage?

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
10. Any other remarks which may be useful:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
______________________________________ _____________________________________
Signature Title
______________________________________ _____________________________________
Name (in capitals) Company name

A L S T O M T & D P r o t e c t i o n & C o n t r o l L t d St Leonards Works, Stafford, ST17 4LX England
Tel: 44 (0) 1785 223251 Fax: 44 (0) 1785 212232 Email: enquiries@pcs.alstom.co.uk Internet: www.alstomgpc.co.uk
1998 ALSTOM T&D Protection & Control Ltd

Our policy is one of continuous product development and the right is reserved to supply equipment which may vary from that described.
Publication R5888C Printed in England.

R5888C Quadramho A4RB

Încărcat de

Informații document

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

R5888C Quadramho A4RB

Încărcat de

Drepturi de autor:

Formate disponibile

Service Manual

The following publications form part of this manual:

HANDLING OF ELECTRONIC EQUIPMENT

CHAPTER 1 APPLICATION NOTES (R5580 included)

CHAPTER 2 DESCRIPTION, TECHNICAL DATA

CHAPTER 3 ELECTRONIC MODULE HOUSING (R5234 included)

CHAPTER 4 INSTALLATION AND HANDLING

CHAPTER 6 PROBLEM ANALYSIS

CHAPTER 7 MODULE IDENTIFICATION

CHAPTER 8 SPECIAL VARIATIONS

Caution: refer to product documentation Caution: risk of electric shock

Protective/safety *earth terminal

Functional *earth terminal.

Installing, Commissioning and Servicing

Equipment operating conditions

Decommissioning and Disposal

Insulation class: IEC 61010-1: 1990/A2: 1995 This equipment requires a

Installation IEC 61010-1: 1990/A2: 1995 Distribution level, fixed

Environment: IEC 61010-1: 1990/A2: 1995 Compliance is demonstrated

Product safety: 73/23/EEC Compliance with the

EN 61010-1: 1993/A2: 1995 Compliance is demonstrated

19.12 Circuit transformer requirements 19

Section 2. RELAY CHARACTERISTICS

Section 3. SCHEMES AVAILABLE ON RELAY

Section 4. CHOICE OF CHARACTERISTIC

Section 5. CHOICE OF ZONE 1 IMPEDANCE REACH

Although in most applications the reach accuracy of the relay distance

Section 6. CHOICE OF ZONE 2 IMPEDANCE REACH

Section 7. CHOICE OF ZONE 3 IMPEDANCE REACH

Section 8. POWER SWING BLOCKING FEATURE (PSB)

Section 9. CHOICE OF RESISTIVE REACH OF QUADRILATERAL CHARACTERISTIC

Section 10. AUTOMATIC COMPENSATION OF QUADRILATERAL REACH

Section 11. CHOICE OF ASPECT RATIO (LENTICULAR ZONE 3 CHARACTERISTIC)

Section 12. CHOICE OF RELAY CHARACTERISTIC ANGLES

Section 13. ZONE TIME DELAY SETTINGS

Section 14. SWITCH-ON-TO-FAULT TRIPPING FEATURE (SOTF)

For ground faults on multiple-earthed systems, it is possible, due to healthy phase

Section 15. SELECTION OF SCHEME LOGIC PROGRAMS

Section 16. SETTING OF SCHEME OPTION SWITCHES

SW1 (LEFT) SOTF tripping initiated by comparators

Section 17. DISCUSSION ON APPLICATION OF VARIOUS DISTANCE

17.1 Basic (see Figure 3)

Section 18. TIMER SETTINGS FOR DISTANCE SCHEME LOGIC OF QUADRAMHO

18.1 Permissive underreach scheme

a) Fault occurs busbar voltage b) End A relay clears fault and

SINGLE END FED DOUBLE CCT LINE, FAULT CLOSE UP

a) Fault occurs b) End A relay trips

CURRENT REVERSAL AFTER NEAREST CB OPENS

18.3 Blocking scheme

Strong Strong Weak

CURRENT REVERSAL AFTER NEAREST CB OPENS

Section 19. CURRENT TRANSFORMER REQUIREMENTS

Class X CT are required to meet the following specification:

Positive and zero sequence impedance of MAY transformers in parallel:

With K1 + K2 = 1.4 current level detector sensitivities:

Zone 1 multiplier = (K11 + K12 + K13) K14

= 1.0 x 1 x 0.25 x 1.4 = 0.07 /70 ohms

Ground loop impedance to Zone 1 reach point

Reach point = 7.99 x 63.5 = 10.91 volts

= (1.4 + 1.4) /70 x 4.6 = 2.58 /70 ohms secondary

Sensitivity = 4.8 x 5% = 17.1%

= 4637 x 5 = 116A secondary

b) Ground fault condition

= 2986 x 5 = 74.7A secondary