BAHEEHR UNIVERSITY

QUESTION SHEET (MIDTERM)

Name Surname : Date : 04/04/2016

Department :
Student ID :
Course Code : CMP2008 Computer Organization
In completing this examination I received no assistance from any other individual or used unauthorized materials.

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CLOSED NOTES / 90 MINUTES

1. (10) Write True or False for the statements. Also, fill the blanks
hit associativity penalty time Moore
back rate Amdahl miss through

(True/False) CPU time of a program is the same on different CPU

(True/False) High associativity in a cache reduces compulsory misses
(True/False) A virtual cache access time is always faster than that of a
physical cache
(True/False) Different computers have different instruction sets
(True/False) Sequential words are not at sequential addresses
Using a second-level cache improves ........... rate
Using a non-blocking cache improves miss ...........
Best metric to evaluate ISA is ...........
...........s Law is the observation that the number of transistors in a
dense integrated circuit doubles approximately every two years
Write-........... policy updates upper level only.

2. (8) Define the following terms:

a. Power wall c. Miss penalty
b. Write buffer d. Hit time

3. (12) Assume the following instruction mix for a MIPS-like RISC instruction set: 15%
stores, 25% loads, 10% branches and 50% integer arithmetic. Also, 10% of integer arithmetic
is integer multiply. Given that load and branch instructions require three cycles, store
instructions require two cycles and ALU instructions require one cycle, however, integer
multiplies require ten cycles. Compute the overall CPI.

4. (11) What are the design principles? List and explain them.

5. (11) What are the principles of locality for memory hierarchy? Explain advantages of
locality.
6. (13) Why is miss rate not a good metric for evaluating cache performance? What is the
appropriate metric? Give its definition. What is the reason for using a combination of first
and second- level caches rather than using the same chip area for a larger first-level cache?

7. (15) Assume that you are designing a computer with one CPU, which based CPI = 1 and
clock rate 5 Ghz, and one main memory. CPU has two-level cache hierarchy. Miss rate of L1
cache is %2. On the other hand, local miss rate of L2 cache is %1 and access time to L2
cache is 10 ns. Main memory access time of CPU is 160 ns. Calculate the effective CPI.

8. (20) A processor has a 32 byte memory and an 8 byte direct-mapped cache. Table 0 shows
the current state of the cache.
a. Write hit or miss under the each address in the memory reference sequence below.
Show the new state of the cache for each miss in a new table, label the table with the
address, and circle the change.
Address 10011 00001 00110 01010 01110 11001 00001 11100 10100
Hit/Miss

0. Initial State 1. (Write address of miss)

Index Valid Tag Data Index Valid Tag Data
000 N 000
001 Y 00 Mem(00001) 001
010 N 010
011 Y 11 Mem(11011) 011
100 Y 10 Mem(10100) 100
101 Y 01 Mem(01101) 101
110 Y 00 Mem(00110) 110
111 N 111

b. Do the same thing as in Part a, except for a 4-way set associative cache. Assume
00110 and 11011 were the last two addresses to be accessed. Use the Least Recently
Used replacement policy.
Address 10011 00001 00110 01010 01110 11001 00001 11100 10100
Hit/Miss

0. Initial State
Set Tag Data Tag Data Tag Data Tag Data
0 0011 Mem(00110) 1010 Mem(10100)
1 0000 Mem(00001) 1101 Mem(11011) 0110 Mem(01101)

1. (Write address of miss)

Set Tag Data Tag Data Tag Data Tag Data
0
1