RISC and CISC Architectures

(Used material from Patterson and Hennessey’s Computer Architecture Textbook to deduce the results)

The advent of microprocessor and strides in integrated circuit technology improved the performance of
computer system at roughly 35% per year. Mass production of lower cost microprocessors has increased
the share of microprocessor based computer in the market. This new architecture of microprocessor
based computers has become a true success after two major changes in computer marketplace. One is
elimination of programming at the assembly language level which eliminated the need for object-code
compatibility. So any architecture could reuse the source code written in higher level languages. The
second is the creation of standardized vendor-independent operating systems like UNIX and its clones like
Linux which lowered the cost and risk of bringing out a new architecture. The open standard of systems
eased the new computer architecture introduction.
The above improvements helped evolve computer architecture from a general microprocessor based
architecture to a new set of architectures called RISC architectures. RISC stands for Reduced Instruction
Set Computer. RISC architectures employ simpler instruction set as opposed to CISC which stands for
Complex Instruction Set Computer and employs rich and complex set of instructions.
The RISC-based machines focused attention of system designers on two critical performance techniques,
the exploitation of instruction level parallelism and usage of sophisticated caches. Instruction level
parallelism evolved through instruction pipelining and later into multiple instruction issue so is the case with
caches which evolved from simpler to sophisticated optimized organizations. RISC processors also paved
trends into multi-core processors and led into important parallel computing techniques like thread-level
parallelism and data-level parallelism.
These new improvements in computer architectures contributed by RISC architectures like have urged
others architectures to keep up. Intel, one of the contenders, rose up to the challenge to adopt the
new improvements of RISC by converting the complex instructions of CISC-based x86 into RISC-like
instructions internally first and then adopting the new innovations of RISC design from there on. Though
there is an overhead of translating the complex instructions to simpler instructions in Intel processors, the
transistor counts of their microprocessors in late 1990’s made overhead negligible.
Some key differences in terms of ISA’s of RISC and CISC are:
● Generally the instruction set of RISC architectures separate memory accesses from instructions
opposed to CISC architectures which are register-memory ISA’s. CISC (ex. 80x86) have
instructions which can access memory directly (due to their additional level translating the complex
instructions like these into simpler instructions) where as RISC and recent ISA‘s (ex. MIPS) access
memory using explicit load-store instructions.
● CISC ISA’s like that of 80x86 do not impose the necessity that objects in memory must be aligned
but accessing unaligned objects gets slower. But RISC ISA’s like that of MIPS require that objects
in memory be aligned and raise a special kind of exception when accessing unaligned objects in
memory.
● CISC ISA’s can support advanced addressing modes like variations of displacement. These
include absolute (no register) addressing mode, base indexed with displacement (two registers),
based with scaled index and displacement (two registers where one register is multiplied by the
size of the operands in bytes) in addition to Register, Immediate (for constants) and Displacement
 (where a constant offset is added to a register to form the memory address) addressing modes
of RISC ISA. 80x86 also has more variations of address modes without displacement: register
indirect, indexed, and based with scaled index. But all these types of addressing modes require
translation to simpler instructions although they ease programming in assembly.
● RISC instructions are simple and easy-to-pipeline where as CISC processors like 80x86 has a
much richer and larger set of operations.
● Most RISC microprocessors have are constant length (MIPS - 32 bits long) which simplifies and
speeds up decoding. CISC microprocessors like 80x86 have variable length instructions (80x86
- 1 to 18 bytes). Variable length instructions can take less space than fixed-length instructions,
so the program compiled for CISC are usually smaller than the same program compiled for RISC
machines.