Toshiba Mini NB205

A B C D E
1 1
Compal Confidential
2 2
Buffalo KAVAA
LA-5121P Schematics Document
Intel Diamondville Processor/ Calistoga(945GSE)/ ICH7M
3
2009-03-10 3
REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/17 Deciphered Date 2009/11/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAVAA LA-5121P M/B
D ate: Tuesday, March 10, 2009 Sheet 1 of 42
A B C D E
A B C D E
Compal Confidential
Model Name : KAVAA Fan Control Intel Diamondville SC Thermal Sensor Clock Generator
page 28
File Name : LA-5121P EMC1402 SLG8SP556VTR
FCBGA8-437 Pins page 4 page 12
1
(22x22mm) page 4,5
1
FSB
H_A#(3..31) 400/533MHz H_D#(0..63)
CRT Conn. Intel Calistoga GSE

page 14
Memory BUS(DDRII) 200pin DDRII-SO-DIMM
FCBGA998 page 11
LED Conn. LVDS

page 13 ONE CHANNEL (27x27mm) 1.8V DDRII 400/533
page 6,7,8,9,10
2
DMI x 2 USB Conn X3 Int. Camera 2
PCIeMini Card PCIeMini Card USB port 0,2,7 USB port 1

WiMax 3G page 20 page 21
USB port 4 USB port 5 USB USB
page 19 page 19
5V 480MHz 5V 480MHz BT conn Touch Screen conn
PCIeMini Card PCIeMini Card USB port 6 BTO USB port 4 ,5
PCIe 1x [2,4]
WLAN GPS 1.5V 2.5GHz(250MB/s)
Intel ICH7M page 21 page 20
PCIe port 2 USB port 5
page 19 page 19
BGA-652
PCIe 1x
(31x31mm)
RJ45 RTL8103EL 10/100M 1.5V 2.5GHz(250MB/s)
page 24
SATA port 0 SATA HDD&SSD
PCIe port 3 page 24 5V 1.5GHz(150MB/s)
page 21
USB page 15,16,17,18

3
Card Reader 3
RTS5159 2IN1 5V 480MHz
RTC CKT.
page 16 USB port 3 page 25 3.3V 24.576MHz/48Mhz
HD Audio
3.3V 33 MHz
LPC BUS
DC/DC Interface CKT. HDA Codec
page 30 ALC272-GR
page 22
Debug Port ENE KB926 D3

Power Circuit DC/DC page 28 page 26
AMP.
page 31~37 Int.
MIC CONN MIC CONN HP CONN TPA6017
page 23 page 23 page 23 page 23
Touch Pad Int.KBD SPI ROM GSENSOR
page 29 page 28 page 28 page 27
4 Power/B SPK CONN 4
page 29 page 23

Block Diagrams
1.0
KAVAA LA-5121P M/B
A B C D E
A B C D E
Voltage Rails
1 SIGNAL 1
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 G3
Full ON HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) ON ON ON OFF
B+ AC or battery power rail for power circuit. ON ON ON ON S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF OFF
+1.05VS VCCP switched power rail ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF OFF
+2.5VS 2.5V switched power rail ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3V_SB 3.3V power rail for LAN ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
BTO Option Table
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF
2 2
+3VS 3.3V switched power rail ON ON OFF OFF
+5VALW 5V always on power rail ON OFF ON OFF Function Mini PCI-E SLOT CAMERA & MIC BLUE TOOTH STAR G-SENSOR
+5V_SB 5V power rail for SB ON ON OFF OFF
+5VS 5V switched power rail ON OFF OFF ON
description
+VSB VSB always on power rail ON ON ON OFF explain Wi-Fi WiMax 3GGPS 3G CAMERA MIC BLUE TOOTH POWER SAVING HDD PROTECT
+RTCVCC RTC power ON ON ON OFF
BTO WLAN@ WIMAX@ 3GGPS@ 3G@ CAM@ MIC@ BT@ STAR@ GSENSOR@
Function
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
description
explain
BTO
3 3
EC SM Bus1 address EC SM Bus2 address

Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 010X b
ICH7M SM Bus address

Device Address
Clock Generator 1101 001Xb

(SLG8SP556VTR)
DDR DIMMA 1010 000Xb
4 4

Notes List
C ustom 1.0
KAVAA LA-5121P M/B
A B C D E
5 4 3 2 1
<6> H_A#[3..16]
U1A
+1.05VS +1.05VS <6> H_D#[0..15] H_D#[32..47] <6>
H_A#3 P21 V19 H_ADS# H_ADS# <6> U1B
H_A#4 A[3]# ADS# H_ BNR# H _D#0 H_D#32
H20 A[4]# BNR# Y19 H_BNR# <6> Y11 D[0]# D[32]# R3
H_A#5 N20 U21 H_B PRI# H_BPRI# <6> H _D#1 W10 R2 H_D#33
A[5]# BPRI# D[1]# D[33]#
1
H_A#6 R20 H _D#2 Y12 P1 H_D#34
A[6]# D[2]# D[34]#
0
GROUP
ADDR
H_A#7 J19 T21 H_D EFER# R1 R2 H _D#3 AA14 N1 H_D#35
A[7]# DEFER# H_DEFER# <6> D[3]# D[35]#
DATA GRP 0
H_A#8 N19 T19 H _ D R DY# H _ D R DY# <6> 56_0402_5% 330_0402_5% H _D#4 AA11 M2 H_D#36
H_A#9 A[8]# DRDY# H_DBSY# H _D#5 D[4]# D[36]# H_D#37
G20 A[9]# DBSY# Y18 H_DBSY# <6> W12 D[5]# D[37]# P2
H_A#10 M19 H _D#6 AA16 J3 H_D#38
2
H_A#11 A[10]# H_BR0# H _D#7 D[6]# D[38]# H_D#39
H21 T20 Y10 N3
DATA GRP 2
A[11]# BR0# H_BR0# <6> D[7]# D[39]#
H_A#12 L20 H _D#8 Y9 G3 H_D#40
A[12]# D[8]# D[40]#
CONTROL
D H_A#13 M20 F16 H_IER R# H _D#9 Y13 H2 H_D#41 D
H_A#14 A[13]# IERR# H_IN IT#_R R3 1 D[9]# D[41]#
K19 A[14]# INIT# V16 2 1K_0402_5% H_INIT# <16>
H_D#10 W15 D[10]# D[42]# N2 H_D#42
H_A#15 J20 H_D#11 AA13 L2 H_D#43
H_A#16 A[15]# H_LOCK# H_D#12 D[11]# D[43]# H_D#44
L21 A[16]# LOCK# W20 H_LOCK# <6> Close to CPU Y16 D[12]# D[44]# M3
H_ADSTB#0 K20 H_D#13 W13 J2 H_D#45
<6> H_ADSTB#0 ADSTB[0]# D[13]# D[45]#
T1 H_AP0 D17 D15 H_RESET# H_RS#[0..2] <6> H_D#14 AA9 H1 H_D#46
<6> H_REQ#[0..4] AP0 RESET# H_RESET# <6> D[14]# D[46]#
PAD H_REQ#0 N21 W18 H_RS#0 H_D#15 W9 J1 H_D#47
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_DSTBN#0 D[15]# D[47]# H_DSTBN#2
J21 REQ[1]# RS[1]# Y17 <6> H_DSTBN#0 Y14 DSTBN[0]# DSTBN[2]# K2 H_DSTBN#2 <6>
H_REQ#2 G19 U20 H_RS#2 <6> H_DSTBP#0 H_DSTBP#0 Y15 K3 H_DSTBP#2 H_DSTBP#2 <6>
H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2
P20 REQ[3]# TRDY# W19 H_TRDY# <6> <6> H_DINV#0 W16 DINV[0]# DINV[2]# L1 H_DINV#2 <6>
H_REQ#4 R19 H_DP#0 V9 M4 H_DP#2
REQ[4]# H _HIT# T2 PAD DP#0 DP#2 PAD T3
<6> H_A#[17..31] HIT# AA17 H_HIT# <6> <6> H_D#[16..31] H_D#[48..63] <6>
H_A#17 C19 V20 H_HITM# H_HITM# <6> H_D#16 AA5 C2 H_D#48
H_A#18 A[17]# HITM# H_D#17 D[16]# D[48]# H_D#49
F19 A[18]# Y8 D[17]# D[49]# G2
H_A#19 E21 K17 H_D#18 W3 F1 H_D#50
H_A#20 A[19]# BPM[0]# H_D#19 D[18]# D[50]# H_D#51
A16 A[20]# BPM[1]# J18 U1 D[19]# D[51]# D3
H_A#21 D19 H15 H_D#20 W7 B4 H_D#52
A[21]# BPM[2]# D[20]# D[52]#
DATA GRP 1
H_A#22 C14 J15 H_D#21 W6 E1 H_D#53
A[22]# BPM[3]# D[21]# D[53]#
ADDR GROUP 1
H_A#23 C18 K18 H_D#22 Y7 A5 H_D#54
H_A#24 A[23]# PRDY# PREQ# H_D#23 D[22]# D[54]# H_D#55
C20 A[24]# PREQ# J16 AA6 D[23]# D[55]# C3
XDP/ITP SIGNALS
H_A#25 E20 M17 ITP_TCK H_D#24 Y3 A6 H_D#56
DATA GRP 3
H_A#26 A[25]# TCK ITP_TDI H_D#25 D[24]# D[56]# H_D#57
D20 A[26]# TDI N16 W2 D[25]# D[57]# F2
H_A#27 B18 M16 ITP_TDO H_D#26 V3 C6 H_D#58
H_A#28 A[27]# TDO ITP_TMS H_D#27 D[26]# D[58]# H_D#59
C15 A[28]# TMS L17 U2 D[27]# D[59]# B6
H_A#29 B16 K16 ITP_TRST# H_D#28 T3 B3 H_D#60
H_A#30 A[29]# TRST# H_D#29 D[28]# D[60]# H_D#61
B17 A[30]# BR1# V15 AA8 D[29]# D[61]# C4
H_A#31 C16 H_D#30 V2 C7 H_D#62
H_A#32 A[31]# H_PROCHOT#_R H_D#31 D[30]# D[62]# H_D#63
A17 A[32]# PROCHOT# G17 1 2 H_PROCHOT# <37> W4 D[31]# D[63]# D2
H_A#33 B14 E4 H_THERMDA R4 22_0402_5% H_DSTBN#1 Y4 E2 H_DSTBN#3 H_DSTBN#3 <6>
<6> H_DSTBN#1
THERM
C H_A#34 A[33]# THRMDA H _THERMDC H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 C

B15 A[34]# THRMDC E5 Close to CPU <6> H_DSTBP#1 Y5 DSTBP[1]# DSTBP[3]# F3 H_DSTBP#3 <6>
H_A#35 A14 H_DINV#1 Y6 C5 H_DINV#3
A[35]# <6> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <6>
H_ADSTB#1 B19 H17 H_THERMTRIP# H_THERMTRIP# <6,16> H_DP#1 R4 D4 H_DP#3
<6> H_ADSTB#1 ADSTB[1]# THERMTRIP# DP#1 DP#3
H_AP1 M18 T4 PAD PAD T5
T6 PAD AP1 COMP0 R5 27.4_0402_1%
+CPU_GTLREF A7 GTLREF COMP[0] T1 1 2
H_A20M# U18 R6 1 @ 2 1K_0402_5% ACLKPH U5 T2 COMP1 1 R7 2 54.9_0402_1%
<16> H_A20M# A20M# ACLKPH COMP[1]
H_FE RR# T16 V11 CLK_CPU_BCLK CLK_CPU_BCLK <12> R8 1 @ 2 1K_0402_5% DCL KPH V5 F20 COMP2 2 R9 1 27.4_0402_1%
<16> H_FERR# FERR# BCLK[0] DCLKPH COMP[2]
H_IG NNE# J4 V12 CLK_CPU_BCLK# T17 F21 COMP3 2 R10 1 54.9_0402_1%
<16> H_IGNNE# IGNNE# BCLK[1] CLK_CPU_BCLK# <12> BINIT# COMP[3]
H_STPCLK# R16 R6 MISC
<16> H_STPCLK# H_IN TR STPCLK# EDM H_DPRSTP#
<16> H_INTR T15 +CPU_EXTBGREF M6 R18 H_DPRSTP# <16,37>
H CLK
H_N MI LINT0 EXTBGREF DPRSTP# H_DPSLP#

<16> H_NMI R15 LINT1 N15 FORCEPR# DPSLP# R17 H_DPSLP# <16>
H_SMI# U17 N6 U4 H _DPW R# H_DPW R# <6>
<16> H_SMI# SMI# HFPLL DPWR# H_PW RGOOD
P17 MCERR# PWRGOOD V17 H_PW RGOOD <16>
D6 C21 T6 N18 H_CPUSLP# H_CPUSLP# <6>
NC1 RSVD3 CPU_BSEL0 RSP# SLP#
G6 C1 J6 A13
NC
NC2 RSVD2 <6,12> CPU_BSEL0 BSEL[0] CORE_DET

H6 A3 CPU_BSEL1 H5 B7 +CPU_CMREF
NC3 RSVD1 <6,12> CPU_BSEL1 BSEL[1] CMREF[1]
K4 CPU_BSEL2 G5
NC4 <6,12> CPU_BSEL2 BSEL[2]
K5 NC5
M15 AU80586GE025512_FCBGA437 N7@
NC6
L16 NC7
+1.05VS
Layout note:
AU80586GE025512_FCBGA437 N7@
R11 1 2 1K_0402_5% H_A#32 .
COMP0,2 connect with Zo=27.4ohm +/-15%, make
R12 1 2 1K_0402_5% H_A#33 trace length shorter than 0.5" .
R16 1 2 1K_0402_5% H_A#34
R17 1K_0402_5% H_A#35
COMP1,3 connect with Zo=55ohm +/-15%, make
1 2
+1.05VS +1.05VS +1.05VS trace length shorter than0.5"
B +1.05VS B
mount R18,R19 for KIZ00 project
1
1
R18 1 2 @ 1K_0402_5% H_A20M#
R19 1 2 @ 1K_0402_5% H_IG NNE# R13 R14 R15 H_THERMDA, H_THERMDC routing together.
R23 1 2 @ 1K_0402_5% H_DPRSTP# +CPU_GTLREF 1K_0402_1% +CPU_EXTBGREF 1K_0402_1% +CPU_CMREF 1K_0402_1%
R24 1 2 @ 1K_0402_5% H _DPW R# Trace width / Spacing = 10 / 10 mil
2
2
R25 1 2 @ 1K_0402_5% H_DPSLP#
R26 1 2 @ 1K_0402_5% H_IN TR
R27 1 2 @ 1K_0402_5% H_N MI
1
1
R28 1 2 @ 1K_0402_5% H_SMI# +3VS
1 1 1
R29 1 2 @ 1K_0402_5% H_PW RGOOD
C1 R20 C2 R21 C3 R22
CPU THERMAL SENSOR
0.1U_0402_16V4Z 2K_0402_1% 1U_0402_6.3V4Z 2K_0402_1% 0.1U_0402_16V4Z 2K_0402_1%
2 2 2
0.1U_0402_16V4Z
CRB reserved 1
2
2
C4
U2
2
12/18 Reserve for debug close Close to CPU pin Close to CPU pin
to South Bridge Close to CPU pin
within 500mils. within 500mils. 1 VDD SMCLK 8 EC_SMB_CK2 EC_SMB_CK2 <26,27>
within 500mils.
H_FE RR# C484 1 2 220P_0402_50V7K Zo=55ohm Zo=55ohm H_THERMDA 2 DP SMDATA 7 EC_SMB_DA2
EC_SMB_DA2 <26,27>
Zo=55ohm C5
1 2 H _THERMDC 3 6 2 1 +3VS
2200P_0402_50V7K DN ALERT# @ R30 10K_0402_5%
2/25 PVT:Mount C484~C495 for EMI request
+1.05VS CPU_THERM# 4 5
H_STPCLK# C485 220P_0402_50V7K THERM# GND
1 2
H_IN IT#_R C486 1 2 220P_0402_50V7K +3VS 1 2
A
H_A20M# C487 1 2 220P_0402_50V7K R31 10K_0402_5% A
H_IG NNE# C488 1 2 220P_0402_50V7K EMC1402-1-ACZL-TR_MSOP8
H_DPRSTP# C489 1 2 220P_0402_50V7K R32 1 2 56_0402_5% ITP_TMS Address:0100_1100 EMC1402-1
H _DPW R# C490 1 2 220P_0402_50V7K R33 1 2 56_0402_5% ITP_TDI Address:0100_1101 EMC1402-2
H_DPSLP# C491 1 2 220P_0402_50V7K R34 1 2 56_0402_5% PREQ#
H_IN TR C492 1 2 220P_0402_50V7K R35 1 2 56_0402_5% ITP_TDO
H_N MI C493 1 2 220P_0402_50V7K
H_SMI# C494 1 2 220P_0402_50V7K R36 1 2 56_0402_5% ITP_TCK Security Classification Compal Secret Data Compal Electronics, Inc.
H_PW RGOOD C495 1 2 220P_0402_50V7K R37 1 2 56_0402_5% ITP_TRST# 2008/11/17 2009/11/17 Title
Issued Date Deciphered Date
12/18 Reserve for debug close This shall place near CPU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Diamondville(1/2)
to CPU AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
U 1D U 1C 2500mA +1.05VS
A2 VSS1 VSS162 N5
A4 N7 C9 0.1U_0402_16V7K 1U_0402_6.3V6K
VSS2 VSS161 VTT1
A8 VSS4 VSS160 N9 VTT2 D9 1
A15 N13 +1.05VS E9
VSS5 VSS159 VTT3 1 1 1 1
A18 N17 F8 C8 C9 C10 C11 + C7
VSS6 VSS158 VTT4
A19 VSS7 VSS157 P3 VTT5 F9
A20 P4 G8 220U_B2_2.5VM_R35
VSS8 VSS156 VTT6 2 2 2 2 2
B1 VSS9 VSS155 P5 V10 VCCF VTT7 G14
B2 VSS10 VSS154 P6 VTT8 H8
D B5 P7 A9 H14 0.1U_0402_16V7K 1U_0402_6.3V6K max 1700mA ESR:21~35m ohm D
VSS11 VSS153 VCCQ1 VTT9
B8 VSS12 VSS152 P9 B9 VCCQ2 VTT10 J8 PLACE IN CAVITY
B13 VSS13 VSS151 P13 VTT11 J14
B20 VSS14 VSS149 P15 VTT12 K8
B21 VSS15 VSS148 P16 VTT13 K14
C8 VSS16 VSS147 P18 VTT14 L8
C17 VSS17 VSS146 P19 VTT15 L14
D1 VSS18 VSS145 R1 VTT16 M8
D5 R5 +CPU_CORE M14
VSS19 VSS144 VTT17
D8 VSS20 VSS143 R7 VTT18 N8
D14 VSS21 VSS142 R9 VTT19 N14
D18 VSS22 VSS141 R13 VTT20 P8
D21 VSS23 VSS140 R21 A10 VCCP1 VTT21 P14
E3 VSS24 VSS139 T4 A11 VCCP2 VTT22 R8
E6 VSS25 VSS138 T5 A12 VCCP3 VTT23 R14
E7 VSS26 VSS137 T7 B10 VCCP4 VTT24 T8
E8 VSS27 VSS136 T9 B11 VCCP5 VTT25 T14
E15 VSS28 VSS135 T10 B12 VCCP6 VTT26 U8
E16 VSS29 VSS134 T11 C10 VCCP7 VTT27 U9
E19 VSS30 VSS133 T12 C11 VCCP8 VTT28 U10
F4 VSS31 VSS132 T13 C12 VCCP9 VTT29 U11
F5 VSS32 VSS131 T18 D10 VCCP10 VTT30 U12
F6 VSS33 VSS130 U3 D11 VCCP11 VTT31 U13
F7 VSS34 VSS129 U6 D12 VCCP12 VTT32 U14
F17 VSS35 VSS128 U7 E10 VCCP13
F18 VSS36 VSS127 U15 E11 VCCP14
G1 VSS37 VSS126 U16 E12 VCCP15
G4 VSS38 VSS125 U19 F10 VCCP16 VCCPC64 F14
G7 VSS39 VSS124 V1 F11 VCCP17 VCCPC63 F13
C G9 V4 F12 E14 C
VSS41 VSS123 VCCP18 VCCPC62
G13 VSS42 VSS122 V6 G10 VCCP19 VCCPC61 E13
G21 VSS45 VSS121 V7 G11 VCCP20
H3 VSS46 VSS120 V8 G12 VCCP21
H4 VSS48 VSS119 V13 H10 VCCP22
H13 VSS52 VSS116 V21 J10 VCCP25
H16 VSS53 VSS115 W1 J11 VCCP26
H18 VSS54 VSS114 W5 J12 VCCP27
H19 W8 K10 +1.5VS
VSS55 VSS113 VCCP28
J5 VSS56 VSS112 W11 K11 VCCP29
J7 VSS57 VSS111 W14 K12 VCCP30
130mA
J9 W17 L10 D7 +1.5VS
VSS58 VSS110 VCCP31 VCCA
J13 VSS59 VSS109 W21 L11 VCCP32 1
J17 Y1 L12 C12
VSS60 VSS108 VCCP33 CPU_ VID0 0.1U_0402_16V7K
K1 VSS61 VSS107 Y2 M10 VCCP34 VID[0] F15 CPU_VID0 <37>
K6 Y20 M11 D16 CPU_ VID1
VSS62 VSS106 VCCP35 VID[1] CPU_VID1 <37> 2
K7 Y21 M12 E18 CPU_ VID2 CPU_VID2 <37> +CPU_CORE
VSS63 VSS105 VCCP36 VID[2] CPU_ VID3
K9 VSS64 VSS104 AA2 N10 VCCP37 VID[3] G15 CPU_VID3 <37>
1
K13 AA3 N11 G16 CPU_ VID4 CPU_VID4 <37>
VSS65 VSS103 VCCP38 VID[4] CPU_ VID5 R38
K15 VSS66 VSS102 AA4 N12 VCCP39 VID[5] E17 CPU_VID5 <37>
K21 AA7 P10 G18 CPU_ VID6 CPU_VID6 <37>
VSS67 VSS101 VCCP40 VID[6] 100_0402_1%
L3 VSS68 VSS100 AA10 P11 VCCP41
L4 AA12 . P12 .
2
VSS69 VSS99 VCCP42 V CCSENSE
L5 VSS70 VSS98 AA15 R10 VCCP43 VCCSENSE C13 VCCSENSE <37> Length match within 25 mils
L6 VSS71 VSS97 AA18 R11 VCCP44
L7 VSS72 VSS96 AA19 R12 VCCP45 VSSSENSE
The trace space 7 mils,
L9 VSS73 VSS95 AA20 VSSSENSE D13 VSSSENSE <37>
B
L13 VSS74
Zo=27.4ohm B
1
L15 AU80586GE025512_FCBGA437
VSS75 N7@ R39
L18 VSS76
L19 VSS77
M1 100_0402_1%
VSS78
M5
2
VSS79
M7 VSS80
M9 VSS81
M13 +CPU_CORE +CPU_CORE
VSS82
M21 VSS83 PLACE IN CAVITY 2 x 330uF(9mohm/2)
N4 VSS84 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1
+ C13 + C14
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30
AU80586GE025512_FCBGA437 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
N7@ 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
1 1 1 1 1 1 1 1 1 1 1 1
C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42
2 2 2 2 2 2 2 2 2 2 2 2
A A
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
PLACE IN CORRIDOR AND CLOSE TO CPU

Diamondville(2/2)
C ustom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
<4> H_D#[0..63] H_A#[3..31] <4>

U3A U3B
H _D#0 C4 F8 H_A#3
H _D#1 H_D#_0 H_A#_3 H_A#4 DMI_TXN0 MCH_CLKSEL0 R403 1K_0402_5%
F6 H_D#_1 H_A#_4 D12 <17> DMI_TXN0 Y29 DMI_RXN_0 CFG_0 C18 1 2 CPU_BSEL0 <4,12>
H _D#2 H9 C13 H_A#5 DMI_TXN1 Y32 E18 MCH_CLKSEL1 R404 1 2 1K_0402_5%
H_D#_2 H_A#_5 <17> DMI_TXN1 DMI_RXN_1 CFG_1 CPU_BSEL1 <4,12>
H _D#3 H6 A8 H_A#6 DMI_TXP0 Y28 G20 MCH_CLKSEL2 R405 1 2 1K_0402_5%
H_D#_3 H_A#_6 <17> DMI_TXP0 DMI_RXP_0 CFG_2 CPU_BSEL2 <4,12>
D H _D#4 F7 E13 H_A#7 DMI_TXP1 Y31 G18 CF G3 R40 1 2 @ 2.2K_0402_5% D
H_D#_4 H_A#_7 <17> DMI_TXP1 DMI_RXP_1 CFG_3
H _D#5 E3 E12 H_A#8 J20 CF G5 R41 1 2 2.2K_0402_5%
H _D#6 H_D#_5 H_A#_8 H_A#9 DMI_RXN0 CFG_5 CF G6 R42 @ 2.2K_0402_5%
C2 H_D#_6 H_A#_9 J12 <17> DMI_RXN0 V28 DMI_TXN_0 CFG_6 J18 1 2
H _D#7 C3 B13 H_A#10 DMI_RXN1 V31
H_D#_7 H_A#_10 <17> DMI_RXN1 DMI_TXN_1
H _D#8 K9 A13 H_A#11 DMI_RXP0 V29
H_D#_8 H_A#_11 <17> DMI_RXP0 DMI_TXP_0
H _D#9 F5 G13 H_A#12 DMI_RXP1 V32
H_D#_9 H_A#_12 <17> DMI_RXP1 DMI_TXP_1
H_D#10 H_A#13
DMI
J7 H_D#_10 H_A#_13 A12
H_D#11 K7 D14 H_A#14
H_D#12 H_D#_11 H_A#_14 H_A#15
H8 H_D#_12 H_A#_15 F14
H_D#13 E5 J13 H_A#16 M_CLK_DDR0 AF33 K32
H_D#14
H_D#15
K8
H_D#_13
H_D#_14
H_A#_16
H_A#_17 E17 H_A#17
H_A#18
<11>
<11>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR1 AG1
SM_CK_0
SM_CK_1
RESERVED1
RESERVED2 K31 Strap Pin Table
J8 H_D#_15 H_A#_18 H15 RESERVED7 C17
H_D#16 J2 G15 H_A#19 AJ1 F18 000=FSB400
H_D#17 H_D#_16 H_A#_19 H_A#20 SM_CK_2 RESERVED8
J3 H_D#_17 H_A#_20 G14 AM30 SM_CK_3 RESERVED9 A3
CFG/RSVD
H_D#18 N1 A15 H_A#21 CFG[2:0] 001=FSB533
H_D#19 M5
H_D#_18 H_A#_21
B18 H_A#22 M_CLK_DDR#0 AG33
*
H_D#_19 H_A#_22 <11> M_CLK_DDR#0 SM_CK#_0
H_D#20 K5 B15 H_A#23 M_CLK_DDR#1 AF1 011=FSB667
H_D#_20 H_A#_23 <11> M_CLK_DDR#1 SM_CK#_1
H_D#21 J5 E14 H_A#24
H_D#22 H_D#_21 H_A#_24 H_A#25
H3 H_D#_22 H_A#_25 H13 AK1 SM_CK#_2
H_D#23 J4 C14 H_A#26 AN30 CFG3
H_D#24 H_D#_23 H_A#_26 H_A#27 SM_CK#_3
N3 A17 Reserved
DDR2 MUXING
H_D#25 H_D#_24 H_A#_27 H_A#28 DDR _CKE0
M4 H_D#_25 H_A#_28 E15 <11> DDR_CKE0 AN21 SM_CKE_0 CFG6
H_D#26 M3 H17 H_A#29 DDR _CKE1 AN22
H_D#_26 H_A#_29 <11> DDR_CKE1 SM_CKE_1
H_D#27 N8 D17 H_A#30 AF26
H_D#28 H_D#_27 H_A#_30 H_A#31 SM_CKE_2
N6 H_D#_28 H_A#_31 G17 AF25 SM_CKE_3 0=DMI X 2 *
H_D#29 K3 CFG5
H_D#30 H_D#_29 DDR _CS0#
N9 H_D#_30 <11> DDR_CS0# AG14 SM_CS#_0 1=DMI X4
H_D#31 M1 F10 H_ADS# DDR _CS1# AF12
H_D#_31 H_ADS# H_ADS# <4> <11> DDR_CS1# SM_CS#_1
H_D#32 V8 C12 H_ADSTB#0 AK14
H_D#_32 H_ADSTB#_0 H_ADSTB#0 <4> SM_CS#_2
C H_D#33 V9 H16 H_ADSTB#1 AH12 C
H_D#_33 H_ADSTB#_1 H_ADSTB#1 <4> SM_CS#_3
H_D#34 R6 E2 +H_VREF 2/25 PVT: Change Net Name to ICH_PWROK
H_D#35 H_D#_34 H_VREF0 H_ BNR#
T8 H_D#_35 H_BNR# B9 H_BNR# <4> AJ21 SM_OCDCOMP_0
H_D#36 R2 C7 H_B PRI# AF11 E31
HOST
H_D#_36 H_BPRI# H_BPRI# <4> SM_OCDCOMP_1 PM_ICHSYNC# MCH_ICH_SYNC# <15>

H_D#37 N5 G8 H_BR0# G21
H_D#_37 H_BREQ0# H_BR0# <4> PM_BMBUSY# PM_BMBUSY# <17>
PM
H_D#38 N2 B10 H_RESET# M_ODT0 AE12 F26 PM_EXTTS#0
H_D#_38 H_CPURST# H_RESET# <4> +1.8V <11> M_ODT0 SM_ODT_0 PM_EXTTS#_0 PM_EXTTS#0 <11>
H_D#39 R5 E1 +H_VREF M_ODT1 AF14 H26 PM_EXTTS#1 2 1
H_D#_39 H_VREF1 <11> M_ODT1 SM_ODT_1 PM_EXTTS#_1 PM_DPRSLPVR <17,37>
H_D#40 U7 AJ14 J15 R43 0_0402_5%
H_D#41 H_D#_40 CLK_MCH_BCLK# SM_ODT_2 THRMTRIP# H_THERMTRIP#
R8 H_D#_41 HCLKN AA6 CLK_MCH_BCLK# <12> AJ12 SM_ODT_3 PWROK AB29 H_THERMTRIP# <4,16>
H_D#42 T4 AA5 CLK_MCH_BCLK W27 ICH _PW ROK
H_D#_42 HCLKP CLK_MCH_BCLK <12> RSTIN# ICH_PW ROK <17>
H_D#43 T7 C10 H_DBSY# R44 1 2 80.6_0402_1% SMRCOMPN AN12 PLTRST_R# 1 2
H_D#_43 H_DBSY# H_DBSY# <4> SM_RCOMPN PLTRST# <15,17,19,24,28>
H_D#44 R3 C6 H_D EFER# 1 2 SMRCOMPP AN14 R45 100_0402_5%
H_D#_44 H_DEFER# H_DEFER# <4> SM_RCOMPP
H_D#45 T5 H5 H_DINV#0 R46 80.6_0402_1% AA33
H_D#_45 H_DINV#_0 H_DINV#0 <4> SM_VREF_0
CLK
H_D#46 V6 J6 H_DINV#1 +DIMM_VREF AE1 A27
H_D#_46 H_DINV#_1 H_DINV#1 <4> SM_VREF_1 D_REFCLKN CLK_MCH_DREFCLK# <12>
H_D#47 V3 T9 H_DINV#2 10uA A26
H_D#_47 H_DINV#_2 H_DINV#2 <4> D_REFCLKP CLK_MCH_DREFCLK <12>
0.1U_0402_16V4Z
H_D#48 W2 U6 H_DINV#3 1 J33
H_D#_48 H_DINV#_3 H_DINV#3 <4> D_REFSSCLKN MCH_SSCDREFCLK# <12>
C 43
H_D#49 W1 G7 H _DPW R# H33
H_D#_49 H_DPWR# H_DPW R# <4> D_REFSSCLKP MCH_SSCDREFCLK <12>
H_D#50 V2 E6 H _ D R DY# J22 2 1
H_D#_50 H_DRDY# H _ D R DY# <4> CLKREQ# MCH_CLKREQ# <12>
H_D#51 W4 F3 H_DSTBN#0 R416 0_0402_5%
H_D#52 H_D#_51 H_DSTBN#_0 H_DSTBN#1 2 C511
W7 H_D#_52 H_DSTBN#_1 M8 Layout Note:
H_D#53 W5 T1 H_DSTBN#2 QG82945GSE SLB2R A3_FCBGA998 @
H_D#54 H_D#_53 H_DSTBN#_2 H_DSTBN#3
+DIMM_VREF trace 22P_0402_50V8J
V5 H_D#_54 H_DSTBN#_3 AA3
+1.05VS H_D#55 AB4 F4 H_DSTBP#0 width and spacing
H_D#_55 H_DSTBP#_0 H_DSTBN#[0..3] <4>
H_D#56 AB8 M7 H_DSTBP#1 is 20/20.
H_D#57 H_D#_56 H_DSTBP#_1 H_DSTBP#2
W8 H_D#_57 H_DSTBP#_2 T2
H_D#58 AA9 AB3 H_DSTBP#3 2/5 DVT: For WWLAN request
H_D#59 H_D#_58 H_DSTBP#_3
AA8 H_D#_59 H_DSTBP#[0..3] <4>
54.9_0402_1%
H_D#60 AB1 H_D#_60

1
1
54.9_0402_1%
H_D#61 AB7
B H_D#62 H_D#_61 H _HIT# B
AA2 H_D#_62 H_HIT# C8 H_HIT# <4> Layout Note:
R 47
R 48
H_D#63 AB5 B4 H_HITM#

H_D#_63 H_HITM#
C5 H_LOCK#
H_HITM# <4> H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_LOCK# H_LOCK# <4>
G9 H_REQ#0 H_SWNG1 trace width and spacing is 10/20.
2
H_REQ#_0 H_REQ#1
H_REQ#_1 E9
H_XRCOMP A10 G12 H_REQ#2
H_XSCOMP H_XRCOMP H_REQ#_2 H_REQ#3
A6 H_XSCOMP H_REQ#_3 B8
+H_SW NG0 C15 F12 H_REQ#4
H_YRCO MP H_XSWING H_REQ#_4 H_RS#0 +1.05VS +1.05VS
J1 H_YRCOMP H_RS#_0 A5 H_REQ#[0..4] <4>
H_YSCOMP K1 B6 H_RS#1
+H_SW NG1 H_YSCOMP H_RS#_1 H_RS#2 +1.05VS
H1 H_YSWING H_RS#_2 G10
221_0402_1%
221_0402_1%
E8 H_CPUSLP#
H_SLPCPU# H_RS#[0..2] <4>
1
100_0402_1%
E10 H_TRDY#
H_TRDY#
1
H_CPUSLP# <4>
R 51
R 49
R 50
24.9_0402_1%
24.9_0402_1%
H_TRDY# <4>
1
QG82945GSE SLB2R A3_FCBGA998

R 52
R 53
2
+H_SW NG0 +H_SW NG1
2
+H_VREF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
100_0402_1%
100_0402_1%
1 1
1
R 54
C 44
R 55
C 45
200_0402_1%
1
R 56
C 46
+3VS
C44 ,C45,C46 be placed 2 2
PM_EXTTS#0 1 2 <100mils from GMCH pin
2
R57 10K_0402_5% 2
2
PM_EXTTS#1 1 @ 2
R58 10K_0402_5%
A A

Calistoga(1/5)-GTL/DMI/DDR
C ustom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
D U 3C DDR_A_D[0..63] <11> D
DDR_A_BS0 AK12 AC31 DDR _A_D0
<11> DDR_A_BS0 SA_BS_0 SA_DQ_0
DDR_A_BS1 AH11 AB28 DDR _A_D1
DDR_A_BS2 AG17 AE33 DDR _A_D2
AF32 DDR _A_D3
<11> DDR_A_DM[0..7] SA_DQ_3
DDR_A_DM0 AB30 AC33 DDR _A_D4
DDR_A_DM1 SA_DM_0 SA_DQ_4 DDR _A_D5
AL31 SA_DM_1 SA_DQ_5 AB32
DDR_A_DM2 AF30 AB31 DDR _A_D6
AK26 SA_DM_3 SA_DQ_7 AE31
DDR_A_DM4 AL9 AH31 DDR _A_D8
AG7 SA_DM_5 SA_DQ_9 AK31
DDR_A_DM6 AK5 AL28 DD R_A_D10
DDR_A_DM7 SA_DM_6 SA_DQ_10 DD R_A_D11
AH3 SA_DM_7 SA_DQ_11 AK27
<11> DDR_A_DQS[0..7] AH30 DD R_A_D12
D DR_A_DQS0 SA_DQ_12 DD R_A_D13
AC28 SA_DQS_0 SA_DQ_13 AL32
D DR_A_DQS1 AJ30 AJ28 DD R_A_D14
D DR_A_DQS2 SA_DQS_1 SA_DQ_14 DD R_A_D15
AK33 SA_DQS_2 SA_DQ_15 AJ27
D DR_A_DQS3 AL25 AH32 DD R_A_D16
AN9 SA_DQS_4 SA_DQ_17 AF31
D DR_A_DQS5 AH8 AH27 DD R_A_D18
AM2 SA_DQS_6 SA_DQ_19 AF28
D DR_A_DQS7 AE3 AJ32 DD R_A_D20
SA_DQS_7 SA_DQ_20 DD R_A_D21
<11> DDR_A_DQS#[0..7] SA_DQ_21 AG31
DDR_A_DQS#0 AC29 AG28 DD R_A_D22
DDR_A_DQS#1 AK30 SA_DQS#_0 SA_DQ_22 DD R_A_D23
SA_DQS#_1 SA_DQ_23 AG27
DDR_A_DQS#2 AJ33 AN27 DD R_A_D24
DDR_A_DQS#3 AM25 SA_DQS#_2 SA_DQ_24 DD R_A_D25
AM26
DDR2 SYSTEM MEMORY

DDR_A_DQS#4 AN8 SA_DQS#_3 SA_DQ_25 DD R_A_D26
SA_DQS#_4 SA_DQ_26 AJ26
DDR_A_DQS#5 AJ8 AJ25 DD R_A_D27
C DDR_A_DQS#6 AM3 SA_DQS#_5 SA_DQ_27 DD R_A_D28 C
SA_DQS#_6 SA_DQ_28 AL27
DDR_A_DQS#7 AE2 AN26 DD R_A_D29
SA_DQS#_7 SA_DQ_29 DD R_A_D30
<11> DDR_A_MA[0..13] SA_DQ_30 AH25
DDR_A_MA0 AJ15 AG26 DD R_A_D31
DDR_A_MA1 SA_MA_0 SA_DQ_31 DD R_A_D32
AM17 SA_MA_1 SA_DQ_32 AM12
DDR_A_MA2 AM15 AL11 DD R_A_D33
AH15 SA_MA_3 SA_DQ_34 AH9
DDR_A_MA4 AK15 AK9 DD R_A_D35
AN15 SA_MA_5 SA_DQ_36 AM11
DDR_A_MA6 AJ18 AK11 DD R_A_D37
AF19 SA_MA_7 SA_DQ_38 AM8
DDR_A_MA8 AN17 AK8 DD R_A_D39
AL17 SA_MA_9 SA_DQ_40 AG9
DDR_A_MA10 AG16 AF9 DD R_A_D41
AL18 SA_MA_11 SA_DQ_42 AF8
DDR_A_MA12 AG18 AK6 DD R_A_D43
AL14 SA_MA_13 SA_DQ_44 AF7
AG11 DD R_A_D45
D DR_A_CAS# SA_DQ_45 DD R_A_D46
<11> DDR_A_CAS# AJ17 SA_CAS# SA_DQ_46 AJ6
D DR_A_RAS# AK18 AH6 DD R_A_D47
<11> DDR_A_RAS# SA_RAS# SA_DQ_47
SA_R CVENIN# AN28 AN6 DD R_A_D48
T7 PAD SA_RCVENOUT# SA_RCVENIN# SA_DQ_48 DD R_A_D49
AM28 SA_RCVENOUT# SA_DQ_49 AM6
T8 PAD DDR_A_W E# AH17 AK3 DD R_A_D50
<11> DDR_A_W E# SA_WE# SA_DQ_50
AL2 DD R_A_D51
SA_DQ_51 DD R_A_D52
AH21 SB_BS_0 SA_DQ_52 AM5
AJ20 AL5 DD R_A_D53
SB_BS_1 SA_DQ_53 DD R_A_D54
AE27 SB_BS_2 SA_DQ_54 AJ3
AJ2 DD R_A_D55
SA_DQ_55 DD R_A_D56
AN20 SB_MA_0 SA_DQ_56 AG2
B DD R_A_D57 B
AL21 SB_MA_1 SA_DQ_57 AF3
AK21 AE7 DD R_A_D58
SB_MA_2 SA_DQ_58 DD R_A_D59
AK22 SB_MA_3 SA_DQ_59 AF6
AL22 AH5 DD R_A_D60
AH22 SB_MA_5 SA_DQ_61 AG3
AG22 AG5 DD R_A_D62
AF21 SB_MA_7 SA_DQ_63 AF5
AM21 SB_MA_8
AE21 SB_MA_9
AL20 SB_MA_10 SB_CAS# AG19
AE22 SB_MA_11 SB_RAS# AG21
AE26 SB_MA_12 SB_WE# AG20
AE20 SB_MA_13
A A

Calistoga(2/5)-DDR2
C ustom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
D D
U 3F R59 +1.5VS_PCIE
24.9_0402_1%
H27 R28 PEGCOMP 1 2
GMCH_CRT_R SDVO_CTRLDATA EXP_A_COMPI
2 1 J27 SDVO_CTRLCLK EXP_A_ICOMPO M28
R60 150_0402_1% Y26
<12> CLK_MCH_3GPLL# G_CLKN
2 1 GMCH_CRT_G AA26 N30
<12> CLK_MCH_3GPLL G_CLKP SDVO_TVCLKIN#
MISC
R61 150_0402_1% R30
GMCH_CRT_B SDVO_INT#
2 1 SDVO_FLDSTALL# T29
R62 150_0402_1%
<14> GMCH_CRT_CLK H20 CRT_DDC_CLK SDVO_TVCLKIN M30

<14> GMCH_CRT_DATA H22 CRT_DDC_DATA SDVO_INT P30
GMCH_CRT_B A24 T30
<14> GMCH_CRT_B CRT_BLUE SDVO_FLDSTALL
A23 CRT_BLUE#
GMCH_CRT_G E25
<14> GMCH_CRT_G CRT_GREEN
F25 CRT_GREEN#
SDVO
GMCH_CRT_R C25
<14> GMCH_CRT_R CRT_RED
VGA
Close to U3.H25 D25 CRT_RED#
<14> GMCH_CRT_VSYNC F27 CRT_VSYNC
<14> GMCH_CRT_HSYNC D27 CRT_HSYNC
2 1 CRT_ IREF H25 P28
R63 255_0402_1% CRT_IREF SDVO_RED#
SDVO_GREEN# N32
<13> GMCH_INVT_PW M H30 L_BKLTCTL SDVO_BLUE# P32
<26> ENBKL G29 L_BKLTEN SDVO_CLKN T32
C LCTLA_CLK F28 C
LCTLB_DATA L_CLKCTLA
3/4 PVT:Add support DPST function E28 L_CTLBDATA
<13> LVDS_SCL LVDS_SCL G28 N28
LVDS_SDA L_DDC_CLK SDVO_RED
<13> LVDS_SDA H28 L_DDC_DATA SDVO_GREEN M32
GM CH_ENVDD K30 P33
<13> GMCH_ENVDD L_VDDEN SDVO_BLUE
2 1 L_IBG K27 R32
R65 1.5K_0402_1% L_IBG SDVO_CLKP
J29 L_VBG +1.5VS
J30 L_VREFH
K29 L_VREFL
LVDS_ACLK# D30 A21
<13> LVDS_ACLK# LA_CLKN TV_DACA
LVDS_ACLK C30 C20
<13> LVDS_ACLK LA_CLKP TV_DACB
A30 LB_CLKN TV_DACC E20
LVDS
A29 LB_CLKP TV_IREF G23
TV
R64 2 1 100K_0402_5% ENBKL LVDS_A0# G31
TV_IRTNA B21
C21
Disable TV
<13> LVDS_A0# LA_DATAN_0 TV_IRTNB
<13> LVDS_A1# LVDS_A1# F32 D21
LVDS_A2# LA_DATAN_1 TV_IRTNC
<13> LVDS_A2# D31 LA_DATAN_2
<13> LVDS_A0 LVDS_A0 H31
LVDS_A1 LA_DATAP_0
<13> LVDS_A1 G32 LA_DATAP_1 TV_DCONSEL0 G26
<13> LVDS_A2 LVDS_A2 C31 J26
LA_DATAP_2 TV_DCONSEL1
F33 LB_DATAN_0
+3VS D33 LB_DATAN_1
F30 LB_DATAN_2
1 2 LCTLA_CLK E33
R66 10K_0402_5% LB_DATAP_0
D32 LB_DATAP_1
B LCTLB_DATA B
1 2 F29 LB_DATAP_2
R67 10K_0402_5%
A A

Calistoga(3/5)-VGA/LVDS/TV
C ustom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
+1.05VS +1.5VS
U3E U3G
U3H AH33 VSS_1
T25 VCC_NCTF1 AD25 Y33 J16 W33 W30
VCCAUX_NCTF1 VSS_2 VSS_111 NC1 NC61
R25 VCC_NCTF2 AC25 V33 AL15 AM33 Y6
P25 VCC_NCTF3 AB25 R33 AG15 AL33 AL1
N25 VCC_NCTF4 AD24 G33 W15 C33 Y5
M25 VCC_NCTF5 AC24 AK32 R15 B33 Y10
P24 VCC_NCTF6 AD22 AG32 F15 AN32 W10
N24 VCC_NCTF7 AD21 AE32 D15 A32 W25
M24 VCC_NCTF8 AD20 AC32 AM14 AN31 V24
Y22 AD19 AA32 AH14 W28 U24
VCC_NCTF9 VCCAUX_NCTF9 VSS_10 VSS_119 NC9 NC69
W22 AD18 U32 AE14 V27 V10
V22 AD17 H32 H14 W29 U10
D VCC_NCTF11 VCCAUX_NCTF11 VSS_12 VSS_121 NC11 NC71 D
U22 AD16 E32 B14 J24 K18
T22 AD15 C32 F13 H24
VCC_NCTF13 VCCAUX_NCTF13 VSS_14 VSS_123 NC13
R22 AD14 AM31 D13 W32
P22 K14 AJ31 AL12 G24
N22 AD13 AA31 AG12 F24
M22 Y13 U31 H12 E24
Y21 W13 T31 B12 D24
W21 V13 R31 AN11 K33
V21 U13 P31 AJ11 A31
U21 T13 N31 AE11 E21
T21 VCC_NCTF22 R13 M31 AM9 C23
VCCAUX_NCTF22 VSS_23 VSS_132 NC22
R21 VCC_NCTF23 VCCAUX_NCTF23 P13 J31 VSS_24 VSS_133 AJ9 AN19 NC23
P21 VCC_NCTF24 VCCAUX_NCTF24 N13 F31 VSS_25 VSS_134 AB9 AM19 NC24
N21 VCC_NCTF25 VCCAUX_NCTF25 M13 AL30 VSS_26 VSS_135 W9 AL19 NC25
M21 VCC_NCTF26 VCCAUX_NCTF26 AD12 AG30 VSS_27 VSS_136 R9 AK19 NC26
Y20 VCC_NCTF27 VCCAUX_NCTF27 Y12 AE30 VSS_28 VSS_137 M9 AJ19 NC27
W20 VCC_NCTF28 VCCAUX_NCTF28 W12 AC30 VSS_29 VSS_138 J9 AH19 NC28
V20 VCC_NCTF29 VCCAUX_NCTF29 V12 AA30 VSS_30 VSS_139 F9 AN3 NC29
NC
U20 VCC_NCTF30 VCCAUX_NCTF30 U12 Y30 VSS_31 VSS_140 C9 Y9 NC30
T20 VCC_NCTF31 VCCAUX_NCTF31 T12 V30 VSS_32 VSS_141 A9 J19 NC31
R20 VCC_NCTF32 VCCAUX_NCTF32 R12 U30 VSS_33 VSS_142 AL8 H19 NC32
P20 VCC_NCTF33 VCCAUX_NCTF33 P12 G30 VSS_34 VSS_143 AG8 G19 NC33
N20 VCC_NCTF34 VCCAUX_NCTF34 N12 E30 VSS_35 VSS_144 AE8 F19 NC34
M20 VCC_NCTF35 VCCAUX_NCTF35 M12 B30 VSS_36 VSS_145 U8 E19 NC35
Y19 VCC_NCTF36 VCCAUX_NCTF36 AD11 AA29 VSS_37 VSS_146 AA7 D19 NC36
P19 VCC_NCTF37 VCCAUX_NCTF37 AD10 U29 VSS_38 VSS_147 V7 C19 NC37
N19 VCC_NCTF38 VCCAUX_NCTF38 K10 R29 VSS_39 VSS_148 R7 B19 NC38
M19 VCC_NCTF39 VSS_NCTF1 AN33 P29 VSS_40 VSS_149 N7 A19 NC39 RESERVED26 Y25
Y18 VCC_NCTF40 VSS_NCTF2 AA25 N29 VSS_41 VSS_150 H7 Y8 NC40 RESERVED27 Y24
P18 V25 M29 E7 G16 AB22
C
N18
M18
Y17
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
NCTF VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
U25
AA22
AA21
H29
E29
B29
VSS_42
VSS_43
VSS_44
VSS_151
VSS_152
VSS_153
B7
AL6
AG6
F16
E16
D16
NC41
NC42
NC43
RESERVED28
RESERVED29
RESERVED30
AB21
AB19
AB16 C
VCC_NCTF44 VSS_NCTF6 VSS_45 VSS_154 NC44 RESERVED31
P17 VCC_NCTF45 VSS_NCTF7 AA20 AK28 VSS_46 VSS_155 AE6 C16 NC45 RESERVED32 AB14
N17 VCC_NCTF46 VSS_NCTF8 AA19 AH28 VSS_47 VSS_156 AB6 B16 NC46 RESERVED33 AA12
M17 VCC_NCTF47 VSS_NCTF9 AA18 AE28 VSS_48 VSS_157 W6 AN2 NC47 RESERVED34 W24
Y16 VCC_NCTF48 VSS_NCTF10 AA17 AA28 VSS_49 VSS_158 T6 A16 NC48 RESERVED35 AA24
P16 VCC_NCTF49 VSS_NCTF11 AA16 U28 VSS_50 VSS_159 M6 Y7 NC49 RESERVED36 AB24
N16 VCC_NCTF50 VSS_NCTF12 AA15 T28 VSS_51 VSS_160 K6 AM4 NC50 RESERVED37 AB20
VSS
M16 AA14 J28 AN5 AF4 AB18
Y15 AA13 D28 AJ5 AD4 AB15
P15 A4 AM27 B5 AL4 AB13
N15 A33 AF27 AA4 AK4 AB12
M15 B2 AB27 V4 W31 AB17
Y14 AN1 AA27 R4 AJ4
VCC_NCTF56 VSS_NCTF18 VSS_57 VSS_166 NC56
W14 C1 Y27 N4 AH4
VCC_NCTF57 VSS_NCTF19 VSS_58 VSS_167 NC57
V14 U27 K4 AG4
VCC_NCTF58 VSS_59 VSS_168 NC58
U14 K28 T27 H4 AE4
VCC_NCTF59 CFG_19 VSS_60 VSS_169 NC59
T14 R27 E4 AM1
VCC_NCTF60 VSS_61 VSS_170 NC60
R14 K25 P27 AL3
VCC_NCTF61 RESERVED10 VSS_62 VSS_171
P14 K26 N27 AD3
N14 R24 M27 W3
+1.05VS VCC_NCTF63 RESERVED12 VSS_64 VSS_173 QG82945GSE SLB2R A3_FCBGA998
M14 T24 G27 T3
K21 E27 B3
RESERVED14 VSS_66 VSS_175
T10 K19 C27 AK2
VTT_NCTF1 RESERVED15 VSS_67 VSS_176
R10 K20 B27 AH2
P10 K24 AL26 AF2
N10 K22 AH26 AB2
L10 J17 W26 M2
D1 K23 U26 K2
K17 AN25 H2
RESERVED21 VSS_73 VSS_182
M10 K12 AK25 F2
RSVD_3 RESERVED22 VSS_74 VSS_183
A18 K13 AG25 V1
RSVD_4 RESERVED23 VSS_75 VSS_184
AB10 K16 AE25 R1
B RSVD_5 RESERVED24 VSS_76 VSS_185 B
AA10 K15 J25
RSVD_6 RESERVED25 VSS_77
G25
QG82945GSE SLB2R A3_FCBGA998 VSS_78
A25
VSS_79
H23
VSS_80
F23
VSS_81
B23
VSS_82
AM22
VSS_83
AJ22
VSS_84
AF22
VSS_85
G22
VSS_86
E22
VSS_87
J21
VSS_88
H21
VSS_89
F21
VSS_90
AM20
VSS_91
AK20
VSS_92
AH20
VSS_93
AF20
VSS_94
D20
VSS_95
W19
VSS_96
R19
VSS_97
AM18
VSS_98
AH18
VSS_99
AF18
VSS_100
U18
VSS_101
H18
VSS_102
D18
VSS_103
AK17
VSS_104
V17
VSS_105
T17
VSS_106
F17
VSS_107
B17 VSS_108
A A
AH16 VSS_109
U16 VSS_110

Calistoga(4/5)-PWR/GND
Custom 1.0
KAVAA LA-5121P M/B
Date: Tuesday, March 10, 2009 Sheet 9 of 42
5 4 3 2 1
5 4 3 2 1
+1.05VS +1.5VS
2940mA U3D 144mA

T26 B20
R26
P26
VCC0
VCC1
VCCATVDACA0
VCCATVDACA1 A20
B22
PCI-E/MEM/PSB PLL decoupling
VCC2 VCCATVDACB0
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
N26 VCC3 VCCATVDACB1 A22 Disable TV
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
M26 VCC4 VCCATVDACC0 D22
V19 C22 +1.5VS_3GPLL +1.5VS
1 1 VCC5 VCCATVDACC1
1 1 1 1 1 U19 D23 R68
VCC6 VCCATVBG
C47
C48
C49
C50
C51
C52
C53
+ + T19 E23 +1.5VS_3GPLL 2 1 +1.5VS
VCC7 VSSATVBG
0.1U_0402_16V4Z
10U_0805_10V4Z
W18 VCC8 VCCDTVDAC F20
@ V18 F22 0_0603_5%
2 2 2 2 2 2 2 VCC9 VCCDQTVDAC
0.1U_0402_16V4Z
T18
VCC10 VCCDLVDS0
C28 20mA +1.5VS 1 1 1
R18 B28
VCC11 VCCDLVDS1
C54
C55
C56
D D
W17 A28
VCC12 VCCDLVDS2
0.1U_0402_16V4Z
10U_0805_10V4Z
U17
VCC13 VCCHV0
E26 40mA +3VS 2 2
@
2
R17 D26 1 1
VCC14 VCCHV1
0.1U_0402_16V4Z
10U_0805_10V4Z
W16 C26
VCC15 VCCHV2
C57
C58
V16 AB33 U4_AB33 10mil 1 1
VCC16 VCCSM0 U4_AM32
T16 AM32
VCC17 VCCSM1 2 2
C59
C60
R16
VCC18 VCCSM2
AN29 10mil
V15
VCC19 VCCSM3
AM29
2 2
PLACEIN CAVIY
1U_0402_6.3V6K
1U_0402_6.3V6K
U15 AL29 1 1
VCC20 VCCSM4
T15 AK29
VCC21 VCCSM5
C61
C62
VCCSM6
AJ29
+1.5VS_MPLL
45mA Max. +1.5VS_HPLL
45mA Max.
AD33 AH29 R69 R70
+1.05VS VCCAUX1 VCCSM7 2 2 0_0603_5% 0_0603_5%
AD32 VCCAUX2 VCCSM8 AG29
AD31 VCCAUX3 VCCSM9 AF29 2 1 +1.5VS 2 1 +1.5VS
AD30 AE29 +1.8V
VCCAUX4 VCCSM10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
AD29 VCCAUX5 VCCSM11 AN24
2
+1.5VS AD28 AM24

D1 VCCAUX6 VCCSM12
AD27 VCCAUX7 VCCSM13 AL24 1 1 1 1
CH751H-40PT_SOD323-2 1250mA AC27 VCCAUX8 VCCSM14 AK24
220U_B2_2.5VM_R25M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C63
C64
C65
C66
1U_0402_6.3V6K
AD26 VCCAUX9 VCCSM15 AJ24
0.1U_0402_16V4Z
AC26 AH24 1
1 1
VCCAUX10 VCCSM16 2 2 2 2
AB26 VCCAUX11 VCCSM17 AG24 1
AE19 AF24 +
1 VCCAUX12 VCCSM18
+2.5VS
C71
C68
C69
C70
C67
R71 AE18 AE24 @
VCCAUX13 VCCSM19
AF17 VCCAUX14 VCCSM20 AN18 10mil 2 2
10_0402_5% AE17 AN16
2 VCCAUX15 VCCSM21
AF16 AM16
2
VCCAUX16 VCCSM22
AE16 VCCAUX17 VCCSM23 AL16 Place as close as possible to the edge(<200mils)
AF15 VCCAUX18 VCCSM24 AK16 1 533 MTS=1720mA
1/13 DVT:Change D1 P/N to SC1H751H010 AE15 VCCAUX19 VCCSM25 AJ16 PLACEIN CAVIY
J14 AN13 C72 2/6 DVT:Reserve C67 with 220uf
VCCAUX20 VCCSM26 1U_0402_6.3V6K
J10 VCCAUX21 VCCSM27 AM13
C
H10 AL13 2 C
VCCAUX22 VCCSM28
AE9 VCCAUX23 VCCSM29 AK13
AD9 VCCAUX24 VCCSM30 AJ13
+1.5VS_DPLLB
50mA Max. +1.5VS_DPLLA
50mA Max.
+1.05VS U9 AH13
VCCAUX25 VCCSM31 L1
AD8 AG13 L2
VCCAUX26 VCCSM32
780mA AD7 VCCAUX27 VCCSM33 AF13 1 2 +1.5VS 1 2 +1.5VS
C73 AD6 VCCAUX28 VCCSM34 AE13
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
VCCSM35
AN4 10mil 1 FBMA-L10-160808-301LMT_2P FBMA-L10-160808-301LMT_2P
1 2 10mil U4_A14 A14 AM10 1 1
VTT0 VCCSM36 +
D10 AL10 1 1
VTT1 VCCSM37
C76
C74
C514
C77
C75
P9 AK10 +
VTT2 VCCSM38
1U_0402_6.3V6K
0.47U_0603_10V7K L9
VTT3 VCCSM39
AH1 10mil 1 2 2
D9 AH10
VTT4 VCCSM40 2 2 2
C78
P8 AG10
VTT5 VCCSM41
L8 AF10
VTT6 VCCSM42 2
1U_0402_6.3V6K
D8 AE10 1
VTT7 VCCSM43
P7 AN7
VTT8 VCCSM44
C79
C80 L7 AM7
VTT9 VCCSM45
D7 AL7
U4_A7 VTT10 VCCSM46 2
1 2 10mil A7
VTT11 VCCSM47
AK7
P6 AJ7
VTT12 VCCSM48 2/6 DVT:For ESD team request
L6 AH7
0.47U_0603_10V7K VTT13 VCCSM49
G6 AN10
VTT14 VCCSM50
POWER
D6 AJ10
VTT15 VCCSM51 +2.5VS
0.1U_0402_16V4Z
220U_B2_2.5VM_R35
U5
VTT16 VCCAMPLL
AD1 +1.5VS_MPLL 45mA
P5
VTT17 VCCAHPLL
AD2 +1.5VS_HPLL 45mA
1 L5
VTT18 VCCADPLLA
B26 +1.5VS_DPLLA 50mA 1
G5
VTT19 VCCADPLLB
J32 +1.5VS_DPLLB 50mA
C81
+ D5
VTT20 VCCDHMPLL1
AE5 +1.5VS150mA C82
Y4
VTT21 VCCDHMPLL2
AD5 Route +2.5VS from GMCH pinN33 to
2 +1.5VS_PCIE
2
U4
VTT22 VCCTXLVDS0
D29 +2.5VS60mA decoupling cap <250mil to the edge.
P4 C29 R72
B VTT23 VCCTXLVDS1 B
L4
VTT24 VCC3G0
U33 400mA 2 1 +1.5VS
G4 T33 0_0805_5%
VTT25 VCC3G1
220U_B2_2.5VM_R35
D4
VTT26 VCCA3GPLL
V26 +1.5VS_3GPLL 400mA 10/23 EVT check water wave +2.5VS
1
10U_0805_10V4Z
10U_0805_10V4Z
Y3
VTT27 VCCA3GBG
N33 +2.5VS 2mA 1 1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
U3 M33 +
VTT28 VSSA3GBG
C84
C85
C83
P3
VTT29 VCCSYNC
J23 70mA
L3 C24 +2.5VS_CRTDAC 70mA 2 R73 1 +2.5VS
VTT30 VCCACRTDAC0 2 2 2
0.1U_0402_16V4Z
10U_0805_10V4Z
G3 B24 0_0402_5%
VTT31 VCCACRTDAC1
0.1U_0402_16V4Z
C86
C87
10U_0805_10V4Z
0.022U_0402_16V7K
D3 B25 1 1
VTT32 VSSACRTDAC
Y2 B31 10mA +2.5VS 1 1 1
VTT33 VCCALVDS
C88
C89
U2 B32 +1.05VS
VTT34 VSSALVDS
C91
C92
P2
VTT36 2 2
C90
L2 P1
VTT35 VTT41 2 2 2
G2 L1 CRTDAC: Route FB
VTT37 VTT42 +2.5VS +2.5VS
D2 G1 within 3" of Calistoga
U4_AA1 VTT38 VTT43
10mil AA1
VTT39 VTT44
U1
U4_F1 F1 Y1
VTT40 VTT45
10mil
1 1 QG82945GSE SLB2R A3_FCBGA998
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
C93 C94
0.1U_0402_16V4Z
0.01U_0402_25V7K
1 1 1 1
0.47U_0603_10V7K 0.47U_0603_10V7K
2 2
C95
C96
C97
C98
Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then 2 2 2 2
connect to the gnd plane.
close pin C29/D29 close pin B31

A A

Calistoga(5/5)-PWR/GND
http://hobi-elektronika.net
Custom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
JDDR1
<7> DDR_A_DQS#[0..7] +DIMM_VREF 1 VREF 2
VSS DDR_A_D4
3 VSS 4
+1.8V DDR_A_D0 DQ4 DDR_A_D5
<7> DDR_A_D[0..63] 5 DQ0 6
DDR_A_D1 DQ5
7 DQ1 8
VSS DDR_A_DM0
<7> DDR_A_DM[0..7] 9 VSS 10
DM0
1
DDR_A_DQS#0 11 12
R74 DDR_A_DQS0 DQS0# VSS DDR_A_D6
<7> DDR_A_DQS[0..7] Layout Note: 13 DQS0 DQ6 14
15 16 DDR_A_D7
Place near JDDR1 1K_0402_1% DDR_A_D2 17
VSS DQ7
18
<7> DDR_A_MA[0..13] DQ2 VSS
DDR_A_D3 19 20 DDR_A_D20
2
DQ3 DQ12 DDR_A_D21
+DIMM_VREF 21 22
DDR_A_D16 VSS DQ13
23 24
DQ8 VSS
1
D DDR_A_D17 DDR_A_DM2 D
25 26
R75 DQ9 DM1
Share +DIMM_VREF for 27
VSS VSS
28
DDR_A_DQS#2 29 30 M_CLK_DDR0
1.DDRII VREF DQS1# CK0 M_CLK_DDR0 <6>
1K_0402_1% DDR_A_DQS2 31 32 M_CLK_DDR#0
M_CLK_DDR#0 <6>
DQS1 CK0#
2.GMCH SM_VREF_0 33 34
2
+1.8V DDR_A_D18 VSS VSS DDR_A_D22
SM_VREF_1 35 36
DDR_A_D19 DQ10 DQ14 DDR_A_D23
37 38
DQ11 DQ15
39 40
VSS VSS
+DIMM_VREF
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2 2 2 2 2 20mils DDR_A_D9
41
VSS VSS
42
DDR_A_D12
43 DQ16 44
DQ20
C99
C100
C101
C102
C103
DDR_A_D8 45 46 DDR_A_D13
DQ17 DQ21
1 1 47 VSS 48
1 1 1 1 1 C104 C105 DDR_A_DQS#1 VSS R76
49 DQS2# 50 1 2 PM_EXTTS#0 <6>
DDR_A_DQS1 NC DDR_A_DM1 0_0402_5%
51 DQS2 52
0.1U_0402_16V4Z 2.2U_0603_6.3V6K DM2
53 VSS 54
2 2 DDR_A_D10 VSS DDR_A_D14
55 DQ18 56
DDR_A_D11 DQ22 DDR_A_D15
57 DQ19 58
DQ23
59 VSS 60
DDR_A_D24 VSS DDR_A_D28
61 DQ24 62
DQ28
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
220U_B2_2.5VM_R35
1 DDR_A_D25 63 64 DDR_A_D29
DQ25 DQ29
1 1 1 1 65 VSS 66
+ DDR_A_DM3 VSS DDR_A_DQS#3
67 DM3 68
DQS3#
C106
C107
C108
C109
C110
@ 69 70 DDR_A_DQS3
NC DQS3
71 VSS 72
2 2 2 2 2 DDR_A_D26 VSS DDR_A_D30
73 DQ26 74
DDR_A_D27 DQ30 DDR_A_D31
75 DQ27 76
DQ31
77 VSS 78
DDR_CKE0 VSS DDR_CKE1
<6> DDR_CKE0 79 CKE0 80 DDR_CKE1 <6>
NC/CKE1
81 VDD 82
VDD
83 NC 84
C DDR_A_BS2 NC/A15 C
<7> DDR_A_BS2 85 BA2 86
NC/A14
87 VDD 88
DDR_A_MA12 VDD DDR_A_MA11
89 A12 90
DDR_A_MA9 A11 DDR_A_MA7
91 A9 92
DDR_A_MA8 A7 DDR_A_MA6
93 A8 94
A6
95 VDD 96
DDR_A_MA5 VDD DDR_A_MA4
97 98
DDR_A_MA3 A5 A4 DDR_A_MA2
Layout Note: 99
A3 A2
100
DDR_A_MA1 101 102 DDR_A_MA0
Place one cap close to every 2 pullup 103
A1 A0
104
DDR_A_MA10 VDD VDD DDR_A_BS1
resistors terminated to +0.9VS 105
A10/AP BA1
106 DDR_A_BS1 <7>
DDR_A_BS0 107 108 DDR_A_RAS#
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
DDR_A_WE# 109 110 DDR_CS0#
<7> DDR_A_WE# WE# S0# DDR_CS0# <6>
111 112
DDR_A_CAS# VDD VDD M_ODT0
<7> DDR_A_CAS# 113 114 M_ODT0 <6>
DDR_CS1# CAS# ODT0 DDR_A_MA13
<6> DDR_CS1# 115 116
NC/S1# NC/A13
117 118
M_ODT1 VDD VDD
<6> M_ODT1 119 120
NC/ODT1 NC
121 122
+0.9VS DDR_A_D32 VSS VSS DDR_A_D36
123 124
125 126
DQ33 DQ37
127 128
DDR_A_DQS#4 VSS VSS DDR_A_DM4
129 130
DDR_A_DQS4 DQS4# DM4
131 132
DQS4 VSS DDR_A_D38
133 134
DDR_A_D34 VSS DQ38 DDR_A_D39
135 136
DQ34 DQ39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_D35 137 138

DQ35 VSS DDR_A_D44
1 1 1 1 1 1 1 1 1 1 1 1 1 139 140
DDR_A_D40 VSS DQ44 DDR_A_D45
141 142
DQ40 DQ45
C111
C112
C113
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
DDR_A_D41 143 144

DQ41 VSS DDR_A_DQS#5
145 146
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 148
B DM5 DQS5 B
149 150
DDR_A_D42 VSS VSS DDR_A_D46
151 152
153 154
DQ43 DQ47
155 156
DDR_A_D48 VSS VSS DDR_A_D52
157 158
159 160
DQ49 DQ53
161 162
VSS VSS M_CLK_DDR1
163 164 M_CLK_DDR1 <6>
NC,TEST CK1 M_CLK_DDR#1
165 166 M_CLK_DDR#1 <6>
DDR_A_DQS#6 VSS CK1#
167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 170
DQS6 DM6
171 172
+0.9VS DDR_A_D50 VSS VSS DDR_A_D54
173 174
RP1 RP2 DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 176
DDR_A_MA0 DDR_A_RAS# DQ51 DQ55
1 8 8 1 177 178
DDR_A_MA13 DDR_A_MA4 DDR_A_D56 VSS VSS DDR_A_D60
2 7 7 2 179 180
DDR_CS0# DDR_A_MA2 DDR_A_D57 DQ56 DQ60 DDR_A_D61
3 6 6 3 181 182
M_ODT0 DDR_A_BS1 DQ57 DQ61
4 5 5 4 183 184
DDR_A_DM7 VSS VSS DDR_A_DQS#7
Layout Note: 185
DM7 DQS7#
186
56_0804_8P4R_5% 56_0804_8P4R_5% Place these resistor 187 188 DDR_A_DQS7
RP3 RP4 DDR_A_D58 VSS DQS7
closely DIMMA,all 189 190
DDR_A_MA1 DDR_CKE1 DDR_A_D59 DQ58 VSS DDR_A_D62
1 8 8 1 191 192
DDR_A_MA3 DDR_A_MA7 trace length<750 mil DQ59 DQ62 DDR_A_D63
2 7 7 2 193 194
DDR_A_MA5 DDR_A_MA6 CLK_SMBDATA VSS DQ63
3 6 6 3 <12,19> CLK_SMBDATA 195 196
DDR_A_CAS# DDR_A_MA11 CLK_SMBCLK SDA VSS R77
4 5 5 4 <12,19> CLK_SMBCLK 197 198 1 2 10K_0402_5%
SCL SA0 R78
+3VS 199
VDDSPD SA1
200 1 2 10K_0402_5%
56_0804_8P4R_5% 56_0804_8P4R_5%
RP5 RP6 201 202
DDR_A_WE# 1 G1 G2
8 8 1 DDR_A_MA12 1
DDR_A_BS0 2 7 7 2 DDR_A_MA9 C125
M_ODT1 3 6 6 3 DDR_A_MA8 FOX_AS0A426-N4RN-7F
DDR_CS1# 4 5 5 4 DDR_A_MA10 0.1U_0402_16V4Z @
A
56_0804_8P4R_5% 56_0804_8P4R_5%
2
DIMMA A
DDR_A_BS2 1 R79 2
Layout Note:
Place these resistor
56_0402_5% Issued Date 2008/11/17 Deciphered Date 2009/11/17 Title
closely DIMMA,all
DDR_CKE0 1 R80 2
56_0402_5% trace length THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMMA
Max=1.3" Size Document Number R ev
Custom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
+3VM_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB R81
250 mA
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1 2
FBMH1608HM601-T_0603 1 1 1 1 1 1 1
C126 C127 C128 C129 C130 C131 C132 C133
0 0 0 266 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
For WWAN request 2 2 2 2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
+1.05VM_CK505
R82
0 1 0 200 100 33.3 14.318 96.0 48.0 80 mA For WWAN request +3VS
+1.05VS 1 2
FBMH1608HM601-T_0603 1 1 1 1 1 1 1
0 1 1 166 100 33.3 14.318 96.0 48.0 C134 C135 C136 C137 C138 C139 C140 C141
D R83 R84 D
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
2 2 2 2 2 2 2 2.2K_0402_5% 2.2K_0402_5%
1 0 0 333 100 33.3 14.318 96.0 48.0
2/25 PVT:Change R81,R82 form 0 ohm to FBMH1608HM601 Q1A
2N7002DW-T/R7_SOT363-6
1 0 1 100 100 33.3 14.318 96.0 48.0
<17> ICH_SMBDATA 6 1 CLK_SMBDATA
1 1 0 400 100 33.3 14.318 96.0 48.0 2/25 PVT:Mount C133,C141 with 47P
+3VS
2
1 1 1 Reserved SA000020K00 (Silego : SLG8SP556VTR )
5
SA000020H10 (ICS : ICS9LPRS387AKLFT) <17> ICH_SMBCLK 3 4 CLK_SMBCLK
Q1B 2N7002DW-T/R7_SOT363-6
+3VM_CK505
2/5 DVT: Reserve C509,C510 with 10P
U4
9 CLK_SMBDATA
SDA CLK_SMBDATA <11,19>
55 VDD_SRC
10 CLK_SMBCLK
SCL CLK_SMBCLK <11,19>
6 VDD_REF
CLK_CPU_BCLK
12 VDD_PCI CPU_0 71
CLK_CPU_BCLK#
CLK_CPU_BCLK <4>
SRC PORT LIST
72 VDD_CPU CPU_0# 70 CLK_CPU_BCLK# <4>
19 68 CLK_MCH_BCLK
VDD_48 CPU_1 CLK_MCH_BCLK <6>
27 67 CLK_MCH_BCLK#
PORT DEVICE
VDD_PLL3 CPU_1# CLK_MCH_BCLK# <6>
C509@1 210P_0402_50V8J
66 24 CLK_MCH_DREFCLK
SRC0 MCH_DREFCLK
C +1.05VM_CK505 VDD_CPU_IO SRC_0/DOT_96 CLK_MCH_DREFCLK <6> C
31 25 CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK# <6>
SRC2 PCIE_3GPLL
VDD_PLL3_IO SRC_0#/DOT_96# C510@1 210P_0402_50V8J
2/25 PVT:Mount C142,C143,C868 with 22P 62
SRC3 PCIE_SATA
VDD_SRC_IO MCH_SSCDREFCLK
CLK_48M_CR and CLK_ICH_48M 52
LCDCLK/27M 28 MCH_SSCDREFCLK <6> SRC4 PCIE_WWAN
VDD_SRC_IO MCH_SSCDREFCLK#
need to same lengh 23
LCDCLK#/27M_SS 29 MCH_SSCDREFCLK# <6> SRC6 PCIE_WLAN
VDD_IO
For WWAN request C142 1 2 22P_0402_50V8J 38 32 CLK_MCH_3GPLL
CLK_MCH_3GPLL <8>
SRC7
VDD_SRC_IO SRC_2
22_0402_5% 1 2 R 90 33 CLK_MCH_3GPLL#
CLK_MCH_3GPLL# <8>
SRC8
<25> CLK_48M_CR SRC_2#
22_0402_5% 1 2 R 91 FSA 20
SRC9 PCIE_LAN
<17> CLK_ICH_48M USB_0/FS_A CLK_PCIE_SATA
<4,6> CPU_BSEL0 2 1 FSA C143 1 2 22P_0402_50V8J F SB CPU_BSEL1 2
SRC_3
35 CLK_PCIE_SATA <16> SRC10 PCIE_ICH
R86 2.2K_0402_5% FS_B/TEST_MODE CLK_PCIE_SATA#
33_0402_5% 1 2 R 93 F SC 7
SRC_3#
36 CLK_PCIE_SATA# <16> SRC11
CPU_BSEL1 <17> CLK_ICH_14M REF_0/FS_C/TEST_
<4,6> CPU_BSEL1
For WWAN request C868 1 2 22P_0402_50V8J 8 39 CLK_PCIE_WWAN
REF_1 SRC_4 CLK_PCIE_WWAN <19> +3VS
2 1 F SC 40 CLK_PCIE_WWAN#
<4,6> CPU_BSEL2 SRC_4# CLK_PCIE_WWAN# <19>
R104 10K_0402_5% VGATE 1 MCH_CLKREQ# R97 2 1 10K_0402_5%
<17,26,37> VGATE CKPWRGD/PD# SATA_CLKREQ# R98 2 10K_0402_5%
1
11 57 CLK_PCIE_WLAN W LAN_CLKREQ# R99 2 1 10K_0402_5%
NC SRC_6 CLK_PCIE_WLAN <19>
W WAN_CLKREQ# R100 2 1 10K_0402_5%
56 CLK_PCIE_WLAN# LAN_CLKREQ# R101 2 1 10K_0402_5%
SRC_6# CLK_PCIE_WLAN# <19>
H_STP_CPU# 53
<17> H_STP_CPU# CPU_STOP#
61
R428 1 SRC_7
+3VS 2 H_STP_PCI#_R R427 1 2 @ 0_0402_5% H_STP_PCI#_R 54
10K_0402_5% <17> H_STP_PCI# PCI_STOP#
60
SRC_7#
For WWAN request CLK_XTAL_IN 5
XTAL_IN
B 3/5 PVT:Reserve R427 with 0 ohm SRC_8/CPU_ITP
64 B
3/5 PVT:Add R428 with 10Kohm to +3VS CLK_XTAL_OUT 4
C144 XTAL_OUT
1 2 22P_0402_50V8J SRC_8#/CPU_ITP#
63
33_0402_5% 1 2 R103 CLK_PCI_DDR_R 13 CLK_PCIE_LAN

<28> CLK_PCI_DDR PCI_1 SRC_9
44 CLK_PCIE_LAN <24>
REQ PORT LIST
PCI2_TME 14 45 CLK_PCIE_LAN#
PCI_2 SRC_9# CLK_PCIE_LAN# <24>
2/25 PVT:Mount C144,C145,C146 with 22P C145 1 2 22P_0402_50V8J
15
PCI_3
50 CLK_PCIE_ICH
CLK_PCIE_ICH <17>
PORT DEVICE
33_0402_5% 1 SRC_10
<26> CLK_PCI_LPC 2 R107 PCI4_SEL 16
PCI_4/SEL_LCDCL
33_0402_5% 1 2 R108 ITP_EN 17
SRC_10#
51 CLK_PCIE_ICH#
CLK_PCIE_ICH# <17> REQ_3# PCIE_SATA
<15> CLK_PCI_ICH PCIF_5/ITP_EN
C146 1 2 22P_0402_50V8J 48
REQ_4# PEIC_WWAN
SRC_11
18 47
REQ_6# PEIC_WLAN
VSS_PCI SRC_11#
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# REQ_7#
3
VSS_REF
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# REQ_9# PCIE_LAN
22 37 SATA_CLKREQ#
Pin28/29 : LCDCLK / LCDCLK# VSS_48 CLKREQ_3# SATA_CLKREQ# <17>
1 = Pin24/25 : SRC_0 / SRC_0# 26 41 W WAN_CLKREQ#

W WAN_CLKREQ# <19>
REQ_10#
VSS_IO CLKREQ_4#
Pin28/29 : 27M/27M_SS 69 58 W LAN_CLKREQ#
W LAN_CLKREQ# <19>
REQ_11#
VSS_CPU CLKREQ_6#
For PCI2_TME:0=Overclocking of CPU and SRC allowed REQ_A# MCH_3GPLL
30 65
(ICS only) 1=Overclocking of CPU and SRC NOT allowed VSS_PLL3 CLKREQ_7#
34 43 LAN_CLKREQ#
VSS_SRC CLKREQ_9# LAN_CLKREQ# <24>
+3VS 59 49
VSS_SRC SLKREQ_10#
42 VSS_SRC CLKREQ_11# 46
2
A A
R112 73 21 MCH_CLKREQ#
VSS USB_1/CLKREQ_A# MCH_CLKREQ# <6>
CLK_XTAL_IN
C147 22P_0402_50V8J 10K_0402_5%
1
SLG8SP556VTR_QFN72_10X10
1
Y1
14.31818MHZ_16PF_DSX840GA ITP_EN PCI4_SEL PCI2_TME
2
CLK_XTAL_OUT
2
C148 22P_0402_50V8J @
R113 R114 R115 Security Classification Compal Secret Data Compal Electronics, Inc.
Routing the trace at least 10mil Issued Date 2008/11/17 Deciphered Date 2009/11/17 Title
10K_0402_5% 10K_0402_5% 10K_0402_5%
Clock Generator CK505
http://hobi-elektronika.net
1
Size Document Number Rev
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT
D D
+LCDVDD
1/22 DVT:Change R117 from 47K to 100K
+3VS W=40mils
1
R116 +3VS
150_0603_5%
1
1
C149
2
1 @
R117 C183 4.7U_0805_10V4Z
3
100K_0402_5% 2
Q2B 0.1U_0402_16V7K 2A
3
2 S
G
2N7002DW -T/R7_SOT363-6 5 2 1 2
R141 47K_0402_5% 1/22 DVT:Change Q11 from SI2301BDS to A03413
D Q11
1
1 AO3413_SOT23
C498
+LCDVDD
6
0.01U_0402_25V7K W=40mils
2
Q2A
<8> GMCH_ENVDD 2 1 1
1
2N7002DW -T/R7_SOT363-6 C186 C187 +3VS
@
1
R142 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2
10K_0402_5%
10K_0402_5%
C 100K_0402_5% C
2
R143
R144
1/22 DVT:Add C498 with 0.01uF
1
LVDS_SCL LVDS_SCL <8>
LVDS_SDA
LED/PANEL BD. Conn. LVDS_SDA <8>
680P_0402_50V7K 2 1 C188
68P_0402_50V8J 2 1 C189
3/4 PVT:Del JLVDS pin2
JLVDS
250mA B+ R376 1 2 0_0805_5% + LEDVDD 1 21
1 GND
2 2
450mA +LCDVDD R377 1 2 0_0805_5% (20 MIL) + LCDVDD_L 3 R419 1 2 0_0402_5% LCD_PW M
3 <26> INVT_PW M
+3VS 4 R420 1 2 @ 0_0402_5%
B 4 <8> GMCH_INVT_PW M B
LCD_PW M 5
BKOFF# 5
1 1 <26> BKOFF# 6 6
C468 C469 LVDS_SDA 7 3/4 PVT:Add support DPST function
@ @ LVDS_SCL 7
8 8
680P_0402_50V7K 680P_0402_50V7K 9
2 2 LVDS_A0 9
<8> LVDS_A0 10 10
<8> LVDS_A0# LVDS_A0# 11 11
12 12
<8> LVDS_A1 LVDS_A1 13
LVDS_A1# 13
<8> LVDS_A1# 14 14
15 15
For EMI request <8> LVDS_A2 LVDS_A2 16
LVDS_A2# 16
<8> LVDS_A2# 17 17
18 18
LVDS_ACLK 19
<8> LVDS_ACLK 19
LVDS_ACLK# 20 22
<8> LVDS_ACLK# 20 GND
ACES_87213-2000G
@
A
LVDS_ACLK C871 1 2 10P_0402_50V8J LVDS_ACLK# A
2/25 PVT:Mount C871 with 10pF

LVDS /INVERTER
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
A B C D E
Place closed to conn.

CRT CONNECTOR
1
D2 D3 D4
DAN217_SC59
DAN217_SC59
DAN217_SC59
2/16 DVT: Mount C504 for EMI request
+3VS
3
@ @ @
1 1 1
C504
Place closed to conn. 0.1U_0402_16V4Z

2
L6
GMCH_CRT_R 1 2 CRT_R_L
<8> GMCH_CRT_R
BLM15AG121SN1D_0402
L7
GMCH_CRT_G 1 2 CRT_G_L
<8> GMCH_CRT_G
BLM15AG121SN1D_0402
L8
GMCH_CRT_B 1 2 CRT_B_L
<8> GMCH_CRT_B
BLM15AG121SN1D_0402
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
1
1
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1
R145 R146 R147 C190 C191 C192 C193 C194 C195
2 2 2 2 2 2
2
2 2
+CRT_VCC
1 2 1 2
C196 0.1U_0402_16V4Z R148 10K_0402_5%
5
1
U13
OE#
P
2 4 CRT_HSYNC_1 R149 1 2 39_0402_5% H S YN C

<8> GMCH_CRT_HSYNC A Y
G
SN74AHCT1G125DCKR_SC70-5 CRT_ VSYNC_1 R150 1 2 39_0402_5% V S YN C

3
33P_0402_50V8K
33P_0402_50V8K
+CRT_VCC
1 1
1 2
C197 0.1U_0402_16V4Z C198 C199
5
U14
2 2
OE#
P
<8> GMCH_CRT_VSYNC 2 A Y 4
G
SN74AHCT1G125DCKR_SC70-5 3/02 PVT:Change D5 from SC1B491D000 to SCS00002000.

3
If=1A
+5VS
D5 +CRT_VCC_R +CRT_VCC
2 F1 30mil
1 1 2
3 RB491D_SOT23-3 1.1A_6V_MINISMDC110F-2 1
3 3
C200
+3VS +CRT_VCC @ 0.1U_0402_16V4Z
2
+3VS
1
+CRT_VCC
1
R151 R152 JCRT

R153 R154 6
4.7K_0402_5% 4.7K_0402_5% RGND
11 ID0
4.7K_0402_5% 4.7K_0402_5% CRT_R_L 1
2
Red
7
2
GGND
5
C RT_DDC_DAT 12
Q3B CRT_G_L SDA
2 Green
4 3 C RT_DDC_DAT 8
<8> GMCH_CRT_DATA H S YN C BGND
13 Hsync
2N7002DW -T/R7_SOT363-6 CRT_B_L 3 Blue
2
9 +5V
V S YN C 14
CRT _DDC_CLK Vsync
<8> GMCH_CRT_CLK 1 6 4 res
Q3A 10
2N7002DW -T/R7_SOT363-6 CRT _DDC_CLK SGND
1 1 15 SCL
5 GND
C201 C202
470P_0402_50V8J 470P_0402_50V8J 16
@ 2 2 @ GND
17 GND
4
SUYIN_070546FR015S263ZR 4
@

CRT PORT
1.0
KAVAA LA-5121P M/B
A B C D E
5 4 3 2 1
D D
U15B
E18 D7 P CI_REQ#0
AD0 REQ0#
C18 AD1 GNT0# E7
A16 C16 P CI_REQ#1 2/25 PVT:Mount C203,C204 for WWAN request
F18
AD2 PCI REQ1#
D16
AD3 GNT1# P CI_REQ#2
E16 AD4 REQ2# C17
+3VS A18 AD5 GNT2# D17
P CI_REQ#3
For EMI, close to ICH7
E17 AD6 REQ3# E13
A17 AD7 GNT3# F13
A15 A13 P CI_REQ#4
AD8 REQ4# / GPIO22 PCI_RST#
C14 AD9 GNT4# / GPIO48 A14
R157 1 2 8.2K_0402_5% P CI_FRAME# E14 C8 P CI_REQ#5
AD10 GPIO1 / REQ5#
D14 AD11 GPIO17 / GNT5# D8
R166 1 2 8.2K_0402_5% PCI_PIRQC# B12 PLTRST#
AD12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C13 AD13 C/BE0# B15
R168 1 2 8.2K_0402_5% PCI_ PIRQE# G15 C12 1 1
AD14 C/BE1#
G13 AD15 C/BE2# D12
C203
C204
R169 1 2 8.2K_0402_5% PCI_PIRQF# E12 C15
AD16 C/BE3#
C11 AD17
R170 1 2 2
C 2 8.2K_0402_5% PCI_ PIRQG# D11 AD18 IRDY# A7 P C I_ I RDY# C
A11 AD19 PAR E10
R171 1 2 8.2K_0402_5% PCI_PIRQH# A10 B18 PCI_RST#
AD20 PCIRST# PCI_RST# <26>
F11 A12 PCI_DEVSEL#
R172 1 AD21 DEVSEL#
2 8.2K_0402_5% P CI_REQ#0 F10 AD22 PERR# C9 PCI_PERR#
E9 E11 PCI_PLOCK# 1 R165 2
R174 1 AD23 PLOCK#
2 8.2K_0402_5% P CI_REQ#1 D9 AD24 SERR# B10 PCI_SERR#
B9 F15 PCI_STOP# 100K_0402_5%
R175 1 AD25 STOP#
2 8.2K_0402_5% P CI_REQ#2 A8 AD26 TRDY# F14 PCI_TRD Y# For EC request.
A6 F16 P CI_FRAME#
R178 1 AD27 FRAME#
2 8.2K_0402_5% P CI_REQ#5 C7 AD28 1 2 100K_0402_5%
B6 C26 PLTRST# R179
AD29 PLTRST# PLTRST# <6,17,19,24,28>
E6 A9 CLK_PCI_ICH Place closely pin A9
AD30 PCICLK CLK_PCI_ICH <12>
D6 AD31 PME# B19
+3VS CLK_PCI_ICH
RP10 Interrupt I/F
2
1 8 PCI_STOP# PCI_ PIRQA# A3 G8 PCI_ PIRQE#
PCI_TRD Y# PCI_ PIRQB# PIRQA# GPIO2 / PIRQE# PCI_PIRQF# @
2 7 B4 PIRQB# GPIO3 / PIRQF# F7
3 6 P CI_REQ#3 PCI_PIRQC# C5 F8 PCI_ PIRQG# R173
P CI_REQ#4 PCI_PIRQD# PIRQC# GPIO4 / PIRQG# PCI_PIRQH# 10_0402_5%
4 5 B5 PIRQD# GPIO5 / PIRQH# G7
1
8.2K_0804_8P4R_5% MISC
AE5 RSVD[1] RSVD[6] AE9 1
+3VS AD5 AG8 @
RP11 RSVD[2] RSVD[7] C205
AG4 RSVD[3] RSVD[8] AH8
1 8 PCI_DEVSEL# AH4 F21 8.2P_0402_50V8D
PCI_PLOCK# RSVD[4] RSVD[9] 2
2 7 AD9 RSVD[5] MCH_SYNC# AH20 MCH_ICH_SYNC# <6>
3 6 PCI_SERR#
B PCI_PERR# B
4 5
ICH7_BGA652
8.2K_0804_8P4R_5%
+3VS
RP12
1 8 P C I_ I RDY#
2 7 PCI_PIRQD#
3 6 PCI_ PIRQB#
4 5 PCI_ PIRQA#
8.2K_0804_8P4R_5%
12/18 Change package to 8P4R with 8.2K
A A

ICH7M(1/4)HUB,PCI,HOST
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
+RTCBATT
1
C207
18P_0402_50V8J
D D32 ICH_RTCX1 D
2 1
BAS40-04_SOT23-3
10M_0402_5%
+RTCVCC Y2
1
32.768K_1TJS125BJ4A421P
3
R181
2 NC
+CHGRTC IN 1
1
3 4
C454 NC OUT U15A
2
LPC_AD[0..3] <26,28>
0.1U_0402_16V4Z C208
2
RTC
18P_0402_50V8J AB1 AA6 LPC_AD0
ICH_RTCX2 RTXC1 LAD0 LPC_AD1
2 1 AB2
RTCX2 LAD1
AB5
AC4 LPC_AD2
R182 1 ICH_RTCRST# LAD2 LPC_AD3
+RTCVCC 2 AA3 RTCRST# LAD3 Y6
LPC
20K_0402_5%
ICH_INTVRMEN W4 AC3
@ J1 SM_INTRUDER# INTVRMEN LDRQ0#
Y5 INTRUDER# AA5
LDRQ1# / GPIO23
1 2
3MM AB3 LPC_FRAME#
LFRAME# LPC_FRAME# <26,28>
W1 EE_CS
Y1 EE_SHCLK 2 1 R183 10K_0402_5% +3VS
C209 Y2 AE22 GATEA20
EE_DOUT A20GATE GATEA20 <26>
LAN
1U_0402_6.3V4Z W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# <4>
CPU
1 2
V3 LAN_CLK AG27
CPUSLP#
U3 AF24 H_DPRSTP#
LAN_RSTSYNC TP1 / DPRSTP# H_DPSLP# H_DPRSTP# <4,37>
TP2 / DPSLP# AH25 H_DPSLP# <4>
U5 LAN_RXD0 2 1 56_0402_5% +1.05VS
V4 AG26 H_FERR# R184
+RTCVCC LAN_RXD1 FERR# H_FERR# <4>
T5 LAN_RXD2
AG24 H_PWRGOOD
GPIO49 / CPUPWRGD H_PWRGOOD <4>
U7 LAN_TXD0
C H_IGNNE# C
V6 LAN_TXD1 AG22 H_IGNNE# <4>
IGNNE#
1 2 ICH_INTVRMEN V7 LAN_TXD2 INIT3_3V# AG21
R185 332K_0402_1% AF22 H_INIT#
INIT# H_INIT# <4>
AF25 H_INTR
INTR H_INTR <4> +1.05VS
1 2 SM_INTRUDER#
AC-97/AZALIA
R186 1M_0402_5% BITCLK_ICH U1
SYNC_ICH ACZ_BCLK EC_KBRST#
R6 AG23 EC_KBRST# <26>
ACZ_SYNC RCIN#
1
RST#_ICH R5 AF23 H_SMI#
ACZ_RST# SMI# H_NMI H_SMI# <4>
AH24 R187
NMI H_NMI <4>
<22> HDA_SDIN0 T2 56_0402_5%
ACZ_SDIN0 H_STPCLK#
T3 AH22 H_STPCLK# <4>
ACZ_SDIN1 STPCLK#
T1
2
ACZ_SDIN2 THRMTRIP_ICH#
AF26 1 R188 2 H_THERMTRIP# <4,6>
SDOUT_ICH THERMTRIP# 24.9_0402_1%
T4
ACZ_SDOUT
DA0
AH17 Layout note: R187 needs to placed
SATALED# AF18 AE17
<29> SATALED# SATALED# DA1 within 2" of ICH7, R193 must be placed
AF17
DA2 within 2" of R187 w/o stub.
SATA_IRX_C_DTX_N0 AF3 AE16
<21> SATA_IRX_C_DTX_N0 SATA0RXN DCS1#
<21> SATA_IRX_C_DTX_P0 SATA_IRX_C_DTX_P0 AE3 AD16
SATA_ITX_DRX_N0 SATA0RXP DCS3#
12/21 Del R190 with 8.2Kohm <21> SATA_ITX_DRX_N0 AG2
SATA0TXN
SATA
Change R189 from 4.7K to 10Kohm for customer SATA_ITX_DRX_P0 AH2
<21> SATA_ITX_DRX_P0 SATA0TXP
AB15
+3VS 12/23 The unused port RX DD0
AF7 AE14
SATA2RXN DD1
signals must be properly AE7 AG13
SATA2RXP DD2
1 2 IDE_DIORDY_IRQ tied to ground AG6 AF13
R189 10K_0402_5% SATA2TXN DD3
AH6 AD14
SATA2TXP DD4
AC13
DD5
1 2 SATALED# <12> CLK_PCIE_SATA#
CLK_PCIE_SATA# AF1 AD12
R191 10K_0402_5% CLK_PCIE_SATA SATA_CLKN DD6
<12> CLK_PCIE_SATA AE1 AC12
B SATA_CLKP DD7 B
AE12
DD8
2 1 SATARBIAS AH10 AF12
R192 24.9_0402_1% SATARBIASN DD9
AG10 AB13
SATARBIASP DD10
10mils width less DD11
AC14
AF14
than 500mils DD12
AH13
DD13
R193 1 2 39_0402_5% SYNC_ICH IDE_DIORDY_IRQ AG16
IDE DD14
AH14
AC15
<22> HDA_SYNC IORDY DD15
AH16
R194 1 BITCLK_ICH IDEIRQ
<22> HDA_BITCLK 2 39_0402_5% AF16
DDACK#
AH15 AE15
R195 1 RST#_ICH DIOW# DDREQ
<22> HDA_RST# 2 39_0402_5% AF15
DIOR#
R196 1 2 39_0402_5% SDOUT_ICH
<22> HDA_SDOUT
ICH7_BGA652
A A

ICH7M(2/4)LAN,ATA,LPC,RTC
Custom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
+3VS +3V_SB +3V_SB
10K_0402_5% +3VS
R197 1 2 SERIRQ Place closely pin B2 Place closely pin AC1
2
2
2
8.2K_0402_5% R201 R202 R204
R198 1 2 PM_CLKRUN# R199 R200 8.2K_0402_5% CLK_ICH_48M CLK_ICH_14M
2.2K_0402_5% 2.2K_0402_5% U15C 12/4 SW recommend
D 8.2K_0402_5% 10K_0402_5% 10K_0402_5% D
1
R220 2 1 BT_DET# ICH_SMBCLK C22 AF19
<12> ICH_SMBCLK
1
ICH_SMBDATA SMBCLK GPIO21 / SATA0GP BT_RST# <21>
<12> ICH_SMBDATA B22 AH18 BIOS need to R205 R206
SMBDATA GPIO19 / SATA1GP
SMB
SATA
GPIO
LINKALERT# A26 AH19 set GPIO
LINKALERT# GPIO36 / SATA2GP BT_OFF <21>
ICH_SMLINK0 B25 AE19 @ 10_0402_5% @ 10_0402_5%
ICH_SMLINK1 SMLINK0 GPIO37 / SATA3GP
A25
2
SMLINK1
+3V_SB +3V_SB
1 1
R203 AC1 CLK_ICH_14M C211 C212
CLK14 CLK_ICH_14M <12>
Clocks
10K_0402_5% 1 2 ICH _RI# A28 B2 CLK_ICH_48M
RI# CLK48 CLK_ICH_48M <12>
R207 1 2 LINKALERT# 8.2K_0402_5% @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
SB_SPKR A19 2 2
<22> SB_SPKR SUS_STAT# SPKR ICH_SUSCLK
10K_0402_5% PAD T9 A27 C20 T10 PAD
R208 1 ITP_DBRESET# ITP_DBRESET# SUS_STAT# SUSCLK
2 A22 SYS_RST#
SYS
B24 PM_SLP_S3#
SLP_S3# PM_SLP_S3# <26>
10K_0402_5% PM_BMBUSY# AB18 D23 PM_SLP_S4# PM_SLP_S4# <26>
R209 1 OCP# <6> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# PM_SLP_S5#
2 SLP_S5# F22 PM_SLP_S5# <26>
OCP# B23
@ 10K_0402_5% GPIO11 / SMBALERT# ICH_PWROK
PWROK AA4
POWER MGT
R210 1 2 SPI_MISO H_STP_PCI# AC20
<12> H_STP_PCI# GPIO18 / STPPCI#
GPIO
H_STP_CPU# AF21 AC22 PM_DPRSLPVR 2/25 PVT:Change Net Name to ICH_PWROK
<12> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR <6,37>
@ 10K_0402_5%
R212 1 2 SB_SPI_CS# A21 C21 ICH_LOW_BAT#
GPIO26 TP0 / BATLOW#
1K_0402_5% B21 C23 PBTN_OUT#
GPIO27 PWRBTN# PBTN_OUT# <26>
R213 1 2 EC_SWI# E23 2/25 PVT:for correcting power down sequence
GPIO28 PLTRST#
LAN_RST# C19 PLTRST# <6,15,19,24,28>
8.2K_0402_5% PM_CLKRUN# AG18
R214 2 ICH_LOW_BAT# GPIO32 / CLKRUN# SB_RSMRST# ICH_PWROK
1 Y4 1 2
RSMRST# R211 10K_0402_5%
2/25 PVT:Change net name from ICH_PCIE_WAKE# to EC_SWI# AC19 GPIO33 / AZ_DOCK_EN#
@ 10K_0402_5% U2
R217 1 SPI_MOSI GPIO34 / AZ_DOCK_RST# EC_PWROK
2 1 2
C EC_SWI# EC_SCI# R418 10K_0402_5% C
<26> EC_SWI# F20 WAKE# E20 EC_SCI# <26>
@ 8.2K_0402_5% SERIRQ GPIO9 ICH _ACIN
<26> SERIRQ AH21 SERIRQ A20
R218 2 EC_SMI# EC_THERM# GPIO10 @
1 <26> EC_THERM# AF20 THRM# GPIO12 F19 1 2
E19 EC_LID_OUT# R417 0_0402_5%
VGATE GPIO13 SLP_CHG# EC_LID_OUT# <26> +3VS
@ 10K_0402_5% AD22 R4
EC_SCI# VRMPWRGD GPIO14 SLP_CHG# <20>
R219 1 2 E22
GPIO15
GPIO24 R3
5
BT_DET# U37
<21> BT_DET# AC21
AC18
GPIO6 GPIO GPIO25
D20
AD21 SATA_CLKREQ# 1
P
EC_SMI# GPIO7 GPIO35 / SATAREQ# SATA_CLKREQ# <12> <26> EC_PWROK B
<26> EC_SMI# E21 AD20 4 ICH_PWROK <6>
GPIO8 GPIO38 Y
AE20 <12,26,37> VGATE 2
GPIO39 A
G
ICH7_BGA652 TC7SH08FUF_SSOP5
3
U15D
F26 V26 DMI_RXN0
PERn1 DMI0RXN DMI_RXP0 DMI_RXN0 <6>
F25
PERp1 DMI0RXP
V25 DMI_RXP0 <6> 12/18 Add RSMRST# Circuit for leakage current
DIRECT MEDIA INTERFACE

E28 U28 DMI_TXN0
PETn1 DMI0TXN DMI_TXN0 <6>
E27 U27 DMI_TXP0 DMI_TXP0 <6> R406 2 1 @ 0_0402_5%
+3V_SB PETp1 DMI0TXP
RP7 PCIE_PTX_C_IRX_N2 H26 Y26 DMI_RXN1 SB_RSMRST# 1 Q31 3
C
USB_OC#0_2_D <19> PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2 PERn2 DMI1RXN DMI_RXP1 DMI_RXN1 <6> EC_RSMRST# <26>
5 4 WLAN H25 Y25 1 2
E
<19> PCIE_PTX_C_IRX_P2 PCIE_ITX_PRX_N2 PERp2 DMI1RXP DMI_TXN1 DMI_RXP1 <6>
6 3 <19> PCIE_ITX_C_PRX_N2 C213 2 1 0.1U_0402_16V7K G28 W28 DMI_TXN1 <6> R215 MMBT3906_SOT23-3
USB_OC#1 C214 2 PCIE_ITX_PRX_P2 PETn2 DMI1TXN DMI_TXP1
7 2 1 0.1U_0402_16V7K G27 W27 10K_0402_5%
B
<19> PCIE_ITX_C_PRX_P2 DMI_TXP1 <6>
2
USB_OC#3 PETp2 DMI1TXP
8 1 1 2 +3V_SB
PCI-EXPRESS
10K_0804_8P4R_5% PCIE_PTX_C_IRX_N3 K26 AB26 R408
<24> PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN
1
LAN PCIE_PTX_C_IRX_P3 K25 AB25 4.7K_0402_5%
<24> PCIE_PTX_C_IRX_P3 PCIE_ITX_PRX_N3 PERp3 DMI2RXP
RP8 <24> PCIE_ITX_C_PRX_N3 C215 2 10.1U_0402_16V7K J28 AA28 D43B D43A
USB_OC#4 C216 2 PCIE_ITX_PRX_P3 PETn3 DMI2TXN
5 4 <24> PCIE_ITX_C_PRX_P3 10.1U_0402_16V7K J27 AA27 BAV99DW-7_SOT363 BAV99DW-7_SOT363
B SLP_CHG_M3 PETp3 DMI2TXP B
6 3
7 2 SLP_CHG_M4 PCIE_PTX_C_IRX_N4 M26 AD25
USB_OC#7_D <19> PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PERn4 DMI3RXN
8 1 M25 AD24
6
<19> PCIE_PTX_C_IRX_P4 PCIE_ITX_PRX_N4 PERp4 DMI3RXP
10K_0804_8P4R_5% WWLAN C217 2 1 @ 0.1U_0402_16V7K L28 AC28 2 1
<19> PCIE_ITX_C_PRX_N4
<19> PCIE_ITX_C_PRX_P4 C218 2 1 @ 0.1U_0402_16V7K PCIE_ITX_PRX_P4 L27
PETn4
PETp4
DMI3TXN
DMI3TXP
AC27 R409 RSMRST# circuit
2.2K_0402_5%
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# <12>
2/25 PVT:Reserve WWLAN PCIE Interface P25
PERp5 DMI_CLKP
AE27 CLK_PCIE_ICH <12>
N28
PETn5 R221 24.9_0402_1%
+3VALW
N27
PETp5 DMI_ZCOMP
C25
DMI_IRCOMP
Within 500 mils
D25 1 2 +1.5VS
DMI_IRCOMP
T25
PERn6 USB20_N0 +3V_SB
T24 F1 USB20_N0 <20>
PERp6 USBP0N
2
R28 F2 USB20_P0
R410 R27
PETn6 USBP0P
G4 USB20_N1
USB20_P0 <20> USB1(Right)
PETp6 USBP1N USB20_N1 <21>
2
330K_0402_5% G3 USB20_P1
@ R2
USBP1P
H1 USB20_N2
USB20_P1 <21> CMOS R216
SB_SPI_CS# SPI_CLK USBP2N USB20_P2 USB20_N2 <20>
P6 H2
USB2(Right) 330K_0402_5%
1
SPI_CS# USBP2P USB20_P2 <20>

SPI
D44 P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 <25>
USB_OC#7_D 2 1 J3 USB20_P3
Card Reader
1
USB_OC#7 <20,26> USBP3P USB20_P3 <25>
SPI_MOSI P5 K1 USB20_N4 D6
SPI_MISO SPI_MOSI USBP4N USB20_P4 USB20_N4 <19> ICH _ACIN
@ CH751H-40PT_SOD323-2 3/4 PVT:For USB over current protect P2 K2 2 1
SPI_MISO USBP4P
L4 USB20_N5 USB20_P4 <19> WiMAX ACIN <26,29,31>
USBP5N USB20_P5 USB20_N5 <19>
1 2 L5
R423 0_0402_5% USB_OC#0_2_D D3
USBP5P
M1 USB20_N6 USB20_P5 <19> WWAN CH751H-40PT_SOD323-2
USB_OC#1 OC0# USBP6N USB20_P6 USB20_N6 <21>
USB_OC#0_2
C4
D5
OC1# USB USBP6P
M2
N4 USB20_N7 USB20_P6 <21> BT
USB_OC#3 OC2# USBP7N USB20_P7 USB20_N7 <20>
3/5 PVT:Add R423,R424,Reserve R410,R421,D44,D45 D4 N3
USB_OC#4 E5
OC3# USBP7P USB20_P7 <20> USB3(Left)
+3VALW SLP_CHG_M3 OC4# R222 22.6_0402_1%
<20> SLP_CHG_M3 C3
SLP_CHG_M4 OC5# / GPIO29 USBRBIAS
<20> SLP_CHG_M4 A2 D2 1 2
USB_OC#7_D OC6# / GPIO30 USBRBIAS#
B3 OC7# / GPIO31 USBRBIAS D1
2
A A
R421
Within 500 mils
330K_0402_5% ICH7_BGA652
@
1
D45
USB_OC#0_2_D 2 1 USB_OC#0_2 <20,26>
@ CH751H-40PT_SOD323-2
1 2
R424 0_0402_5%
ICH7M(3/4)USB,GPIO,PCIE
Custom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1
+5VS +3VS
1/13 DVT:Change D7 P/N to SC1H751H010 U15F +1.05VS U15E
2
0.94A A4
VSS[0] VSS[98]
P28
R223 D7 6mA +ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
CH751H-40PT_SOD323-2 Vcc1_05[2] L12 B1 R11
100_0402_5% VSS[2] VSS[100]
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 R12
+1.5VS VSS[3] VSS[101]
2 L16 1 1 B11 R13
1
+ICH_V5REF_RUN Vcc1_05[4] + C221 VSS[4] VSS[102]
10mA+ICH_V5REF_SUS F6 V5REF_Sus Vcc1_05[5] L17 C219 C220 B14 VSS[5] VSS[103] R14
0.77A Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
1 0.1U_0402_16V4Z AA22 M11 220U_B2_2.5VM_R35 B20 R16
C222 Vcc1_5_B[1] Vcc1_05[7] 2 2 2 VSS[7] VSS[105]
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 R17
VSS[8] VSS[106]
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B28 R18
1U_0402_6.3V4Z C223 + C227 C224 C225 VSS[9] VSS[107]
AB23 Vcc1_5_B[4] Vcc1_05[10] P18 C2 T6
D 2 220U_B2_2.5VM_R35 1U_0402_6.3V4Z VSS[10] VSS[108] D
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 T12
+5V_SB +3V_SB VSS[11] VSS[109]
AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 T13
2 2 2 2 VSS[12] VSS[110]
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 T14
VSS[13] VSS[111]
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 T15
VSS[14] VSS[112]
1
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
R224 D8 Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 Vcc1_5_B[10] Vcc1_05[16] V12 D21 T17
VSS[16] VSS[114]
CH751H-40PT_SOD323-2 AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 U4
10_0402_5% VSS[17] VSS[115]
Place closely pin D26 Vcc1_5_B[12] Vcc1_05[18] V16 E1 VSS[18] VSS[116] U12
D27 V17 E2 U13
2
+ICH_V5REF_SUS D28,T28,AD28. Vcc1_5_B[13] Vcc1_05[19] VSS[19] VSS[117]

D28 Vcc1_5_B[14] Vcc1_05[20] V18 E4 U14
VSS[21] VSS[118]
1 E24 Vcc1_5_B[15] E8 U15
C226 VSS[22] VSS[119]
E25 Vcc1_5_B[16] Vcc3_3 / VccHDA U6 +3VS56mA E15 VSS[23] VSS[120] U16
1/13 DVT:Change D8 P/N to SC1H751H010 E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
0.1U_0402_16V4Z F23 R7 +3V_SB 10mA C228 F4 U24
2 Vcc1_5_B[18] VccSus3_3/VccSusHDA +1.05VS VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 U25
0.1U_0402_16V4Z VSS[26] VSS[123]
G22 Vcc1_5_B[20] V_CPU_IO[1] AE23 F12 U26
2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 14mA F27 VSS[28] VSS[125] V2
1 2 H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
R385 0_0603_5% H23 0.27A G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 1 1 G2 V24
VSS[31] VSS[128]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2N7002DW-T/R7_SOT363-6 J23 AB12 G5 V27
Vcc1_5_B[25] Vcc3_3[4] VSS[32] VSS[129]
C229
C230
C231
+5V_SB 1 6 +5VALW K22 AB20 1 1 1 1 G6 V28
Q4A Vcc1_5_B[26] Vcc3_3[5] VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 W6
2 2 2 VSS[34] VSS[131]
C232
C233
C234
C235
<26,30> SBPWR_EN# SBPWR_EN# STAR@ L22 AD13 G14 W24
Q4B Vcc1_5_B[28] Vcc3_3[7] VSS[35] VSS[132]
L23 AD18 G18 W25
2
Vcc1_5_B[29] Vcc3_3[8] VSS[36] VSS[133]

5
STAR@ 2 2 2 2
M22 Vcc1_5_B[30] Vcc3_3[9] AG12 G21 W26
2N7002DW-T/R7_SOT363-6 VSS[37] VSS[134]
M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 Y3
VSS[38] VSS[135]
4 3 1 R225 2 +VSB N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
47K_0402_5% N23 G26 Y27
Vcc1_5_B[33] VSS[40] VSS[137]
1 R226 2 STAR@ P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C @ 330K_0402_5% P23 B13 H4 AA1 C
Vcc1_5_B[35] Vcc3_3[13] VSS[42] VSS[139]
1 2 R22 B16 1 1 1 H5 AA24
C496 STAR@ Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 AA25
VSS[44] VSS[141]
C236
C237
C238
0.1U_0402_25V6 R24 C10 H27 AA26
Vcc1_5_B[38] Vcc3_3[16] VSS[45] VSS[142]
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 AB4
SBPWR_EN# 1 2 2 2 VSS[46] VSS[143]
2 +5VALW R26 F9 J1 AB6
R369 100K_0402_5% +3VS Vcc1_5_B[40] Vcc3_3[18] VSS[47] VSS[144]
T22 Vcc1_5_B[41] Vcc3_3[19] G11 J2 AB11
VSS[48] VSS[145]
STAR@ T23 G12 J5 AB14
Vcc1_5_B[42] Vcc3_3[20] VSS[49] VSS[146]
T26 G16 J24 AB16
Vcc1_5_B[43] Vcc3_3[21] VSS[50] VSS[147]
T27 J25 AB19
Vcc1_5_B[44] VSS[51] VSS[148]
1 T28 W5 +RTCVCC J26 AB21
C240 Vcc1_5_B[45] VccRTC VSS[52] VSS[149]
U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3V_SB45mA
U23 P7 K27 AB27
0.1U_0402_16V4Z Vcc1_5_B[47] VccSus3_3[1] VSS[54] VSS[151]
V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]
C243
C244
V23 A24 C241 C242 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 C24 L15 AC5
Vcc1_5_B[50] VccSus3_3[3] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[57] VSS[154]
W23 D19 L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 D22 L25 AC11
Vcc1_5_B[52] VccSus3_3[5] VSS[59] VSS[156]
Place closely pin AG28 within 100mlis. Y23
Vcc1_5_B[53] VccSus3_3[6]
G19 L26
VSS[60] VSS[157]
AD1
M3 AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL VSS[61] VSS[158]
B27 K3 M4 AD4
R227 R228 Vcc3_3[1] VccSus3_3[7] +3V_SB VSS[62] VSS[159]
50mA VccSus3_3[8]
K4 1 1 M5
VSS[63] VSS[160]
AD7
1 2 1 2 +1.5VS_DMIPLL AG28 K5 C245 C246 M12 AD8
VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z
0.01U_0402_25V7K
K6 M13 AD11
0.5_0805_1% 0_0805_5% VccSus3_3[10] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[65] VSS[162]
1 1 +1.5VS AB7 L1 M14 AD15
Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
0.64A AC6
Vcc1_5_A[2] VccSus3_3[12]
L2 M15
VSS[67] VSS[164]
AD19
C247
C248
AC7 L3 M16 AD23

Vcc1_5_A[3] VccSus3_3[13] VSS[68] VSS[165]
1 AD6 L6 M17 AE2
2 2 C249 Vcc1_5_A[4] VccSus3_3[14] VSS[69] VSS[166]
AE6 L7 M24 AE4
AF5 M6 M27 AE8
B 0.1U_0402_16V4Z Vcc1_5_A[6] VccSus3_3[16] VSS[71] VSS[168] B
AF6 M7 M28 AE11
2 Vcc1_5_A[7] VccSus3_3[17] VSS[72] VSS[169]
AG5 N7 N1 AE13
AH5 N2 AE18
Vcc1_5_A[9] VSS[74] VSS[171]
AB17 +1.5VS N5 AE21
L9 1 +1.5VS_SATAPLL Vcc1_5_A[19] VSS[75] VSS[172]
+1.5VS 2
MBK1608121YZF_0603
Place closely pin AG5. AD2
VccSATAPLL Vcc1_5_A[20]
AC17 N6
VSS[76] VSS[173]
AE24
N11 AE25
VSS[77] VSS[174]
1 +3VS AH11 T7 N12 AF2
Vcc3_3[2] Vcc1_5_A[21] VSS[78] VSS[175]
0.1U_0402_16V4Z
C250 F17 N13 AF4

Vcc1_5_A[22] VSS[79] VSS[176]
1 AB10 G17 N14 AF8
0.1U_0402_16V4Z +1.5VS Vcc1_5_A[10] Vcc1_5_A[23] VSS[80] VSS[177]
AB9 N15 AF11
2 Vcc1_5_A[11] VSS[81] VSS[178]
C251
1 AC10 AB8 1 2 N16 AF27

C253 Vcc1_5_A[12] Vcc1_5_A[24] VSS[82] VSS[179]
AD10 AC8 N17 AF28
2 Vcc1_5_A[13] Vcc1_5_A[25] C252 0.1U_0402_16V4Z VSS[83] VSS[180]
AE10 N18 AG1
1U_0402_6.3V4Z Vcc1_5_A[14] ICH_K7 VSS[84] VSS[181]
2
AF10
Vcc1_5_A[15] VccSus1_05[1]
K7 PAD T1117mA N24
VSS[85] VSS[182]
AG3
AF9 N25 AG7
Vcc1_5_A[16] ICH_C28 VSS[86] VSS[183]
AG9 C28 PAD T12 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
12/18 Add L15 for ripple AH9
Vcc1_5_A[18] VccSus1_05[3]
G20 PAD T13 P3
VSS[88] VSS[185]
AG14
P4 AG17
VSS[89] VSS[186]
+3V_SB Place closely pin AG9. E3
VccSus3_3[19] Vcc1_5_A[26]
A1 +1.5VS P12
VSS[90] VSS[187]
AG20
1 H6 P13 AG25
C254 L15 1 Vcc1_5_A[27] VSS[91] VSS[188]
+1.5VS 2 10mA C1
VccUSBPLL Vcc1_5_A[28]
H7 1 P14
VSS[92] VSS[189]
AH1
MBK1608121YZF_0603 J6 C256 P15 AH3
0.1U_0402_16V4Z ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
1 T14 PAD AA2 J7 P16 AH7
2 C255 ICH _Y7 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] 0.1U_0402_16V4Z VSS[94] VSS[191]
T15 PAD Y7 P17 AH12
VccSus1_05/VccLAN1_05[2] 2 VSS[95] VSS[192]
P24 AH23
0.1U_0402_16V4Z VSS[96] VSS[193]
V5 P27 AH27
2 VccSus3_3/VccLAN3_3[1] VSS[97] VSS[194]
V1
VccSus3_3/VccLAN3_3[2] ICH7_BGA652
W2
VccSus3_3/VccLAN3_3[3]
+3V_SB W7
VccSus3_3/VccLAN3_3[4]
A ICH7_BGA652 A
1
C257
0.1U_0402_16V4Z
2

ICH7M(4/4)POWER/GND
Custom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN/WiMax

2/25 PVT:Mount C479,C480 with 47pf
+3V_WLAN +1.5VS
120 mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z Please place neer to MINI card conn.
1 1 1 1 1 1
C258 C259 C260 C479 C261 C262 C263 C480 USB20_N4 R378 1 2 TSP4@ 0_0402_5% USB20_TS-
USB20_TS- <21>
WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ USB20_P4 R379 1 2 TSP4@ 0_0402_5% USB20_TS+ USB20_TS+ <21>
2 2 2 47P_0402_50V8J 2 2 2 47P_0402_50V8J USB20_N5 R380 TSP5@ 0_0402_5% USB20_TS-
1 2
1 0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z USB20_P5 R381 TSP5@ 0_0402_5% USB20_TS+ 1
1 2
For WWAN request For WWAN request
12/1 reserve touch screen function
+3V_WLAN +3VS
+1.5VS PJ20
JWLAN
2 1
2 1
1
WLAN_BT_DATA 1 @ JUMP_43X79
<21> WLAN_BT_DATA 3 2
WLAN_BT_CLK 3 2 +3V_SB
<21> WLAN_BT_CLK 5 4
WLAN_CLKREQ# 5 4 PJ21
<12> WLAN_CLKREQ# 7 7 6 6
9 9 8 8 2 2 1 1
<12> CLK_PCIE_WLAN# 11 11 10 10
13 12 @ JUMP_43X79
<12> CLK_PCIE_WLAN 13 12
15 15 14 14
16
16
2/4 DVT: Add PJ20,PJ21 for Echo Peak Issue
Kill SWITCH
17 17
2/3 DVT: Add R411 with 0 ohm
19 19 18 18 Reserve SW1,RM1,U17,C264 for del kill switch function
21 20 XMIT_OFF#
21 20 PLTRST# +3VS
<17> PCIE_PTX_C_IRX_N2 23 23 22 PLTRST# <6,15,17,24,28> 1 2
22 R411 0_0402_5%
<17> PCIE_PTX_C_IRX_P2 25 25 24
24
27 27 26
26
2
29 29 28
28 SW1 DM1 +3VS
<17> PCIE_ITX_C_PRX_N2 31 31 30 CLK_SMBCLK <11,12>
30 DAN217_SC59 C264 0.1U_0402_16V4Z
33 33 32 CLK_SMBDATA <11,12> 5
<17> PCIE_ITX_C_PRX_P2 32 G2 @
35 35 34 4 1 2
34 G1 RM1 @ U17
37 37 36 USB20_N4 <17>
36
5
WLAN/ WiFi +3V_WLAN 39 38 1 2 +3VS @
1
39 38 USB20_P4 <17>
41 40 3 100K_0402_5% 2
P
2 41 40 LED_WIMAX# 3 <26> WL_OFF# B XMIT_OFF# 2
43 43 42 42 LED_WIMAX# <29> Wi Ma x 2 2 KILL_SW# <26> KILL_SW# 1 Y 4
45 45 44 1
44 1 A
G
47 46 R229
R425 1 0_0402_5% 47 46 100K_0402_5% 1BS003-1210L_3P @
2 49 48
3
<26> EC_TX_P80_DATA 49 48
R426 1 2 0_0402_5% 51 50 1 2 +3VS @ NC7SZ08P5X_NL_SC70-5
<26> EC_RX_P80_CLK 51 50
52 52
Debug card using 53
GND
54
GND
3/5 PVT: Add R425,R426 with 0 ohm
P-TWO_A54402-A0G16-N
@
Mini-Express Card for 3G/GPS

3G current need to 2750mA 12/1 Change BOM Config from GPS@ to 3GGPS@
+3VS +1.5VS
120 mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1
C265 C266 C267 C482 C268 C269 C270 C481
3GGPS@ 3GGPS@ 3GGPS@ 3GGPS@ 3GGPS@ 3GGPS@
2 2 2 47P_0402_50V8J 2 2 2 47P_0402_50V8J +UIM_PWR
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z
For WWAN request For WWAN request
1
3 2/25 PVT:Mount C482,C481 with 47pf R230 3
4.7K_0402_5%
@
+3VS
J3GSIM
120 mil
2
+1.5VS +UIM_PWR 1 4
JGPS +UIM_PWR VCC GND
UIM_RST 2 5 UIM_VPP
RST VPP
1
1 1 UIM_CLK 3 6 UIM_DATA
1 D9 CLK I/O
Reserve 3
3 2
2
5 4 C271 GLZ20A LL-34 7 8 1
5 4 NC NC
1
<12> WWAN_CLKREQ# WWAN_CLKREQ# 7 6 +1.5VS 0.1U_0402_16V4Z 3G@ 1 1
7 6 +UIM_PWR 3G@ 2 MOLEX_47273-0001 C274
9 8 +UIM_PWR
2
9 8 UIM_DATA C272 C273 @ 22P_0402_50V8J

<12> CLK_PCIE_WWAN# 11 10
11 10 UIM_CLK 10P_0402_50V8J 10P_0402_50V8J D10 D11 D12 2 @
<12> CLK_PCIE_WWAN 13 12
13 12 UIM_RST 3G@ 2 2 3G@ DAN217_SC59 DAN217_SC59 DAN217_SC59
15 14
15 14 UIM_VPP @ @ @
16
2
16
+UIM_PWR
17
17
19 18
19 18 UWB_OFF#
21 20 UWB_OFF# <26>
21 20 PLTRST#
<17> PCIE_PTX_C_IRX_N4 23 22
23 22
<17> PCIE_PTX_C_IRX_P4 25 24
25 24
27 26
27 26
29 28
29 28 CLK_SMBCLK
<17> PCIE_ITX_C_PRX_N4 31 30
31 30 CLK_SMBDATA
<17> PCIE_ITX_C_PRX_P4 33 32
33 32
35 34
35 34
37 36 USB20_N5 <17>
37 36
+3VS 39 38 USB20_P5 <17>
39 38
41 40
41 40 LED_WIMAX#
43 43 42
4 42 4
45 45 44
44
47 47 46
46
49 49 48 48
51 51 50
50
52 52
53 GND
54 GND
P-TWO_A54402-A0G16-N
@ 2008/11/17 2009/11/17 Title
Issued Date Deciphered Date
WLAN/WiMAX Express Slot
1.0
KAVAA LA-5121P M/B
A B C D E
5 4 3 2 1
+USB_VCCA +USB_VCCA
W=60mils W=60mils
USB CONN--Right 1
+USB_VCCA 0.1U_0402_16V4Z
1
+USB_VCCA 0.1U_0402_16V4Z
1 1 1 1 1
C455 + C464 C465 C458 + C515 C466 C467
@
150U_B_6.3VM_R40M 150U_B_6.3VM_R40M
2 2 2 2 2 2 2
1000P_0402_50V7K JUSBA 470P_0402_50V8J 1000P_0402_50V7K JUSBB

1 1
D
+5VALW 1.4A +USB_VCCA USB20_N0_R
USB20_P0_R
2
VCC
D-
USB20_N2_R
USB20_P2_R
2
VCC
D-
D
U18
W=60mils 3 D+ 3 D+
4 GND 4 GND
1 GND OUT 8
2 IN OUT 7 5 GND1 5 GND1
3 IN OUT 6 1 6 GND2
2/9 DVT:Change C455,C458 from 220uf to 150uf 6 GND2
<26> USB_EN# USB_EN# 4 5 C283 7 2/6 DVT:Modify JUSBA,JUSBB Symbol for GND pad 7
EN# FLG @ GND3 GND3
8 GND4
3/4 PVT:Add C515 for EMI request 8 GND4
G528_SO8 4.7U_0805_10V4Z
2 SUYIN_020173MR004S512ZL SUYIN_020173MR004S512ZL
@ @
D37 D38
1 I/O1 I/O4 6 1 I/O1 I/O4 6
2 REF1 REF2 5 +5VALW 2 REF1 REF2 5 +5VALW

USB_OC#0_2 <17,26>
USB20_P0_R 3 4 USB20_N0_R USB20_P2_R 3 4 USB20_N2_R
I/O2 I/O3 I/O2 I/O3
CM1293A-04SO_SOT23-6 CM1293A-04SO_SOT23-6
@ @
2/3 DVT: Change D38,D37 from PRTR5V0U2X_SOT143-4 to CM1293A-04SO_SOT23-6

1 2 1 2
R386 0_0402_5% R387 0_0402_5%
L10 L11
<17> USB20_N0 USB20_N0 1 2 USB20_N0_R <17> USB20_N2 USB20_N2 1 2 USB20_N2_R
1 2 1 2
C C
<17> USB20_P0 USB20_P0 4 3 USB20_P0_R <17> USB20_P2 USB20_P2 4 3 USB20_P2_R
4 3 4 3
W CM-2012-900T_0805 @ W CM-2012-900T_0805 @
1 2 1 2
R388 0_0402_5% R389 0_0402_5%
For EMI request For EMI request
USB Board--Left +USB_VCCB

W=30mils
+3VALW
please close to SB under 30mm +USB_VCCB 0.1U_0402_16V4Z
1
+USB_VCCB +USB_VCCB U19 0.1U_0402_16V4Z
C291 1 1 1
C288 + C516 C289 C290
1
USB20_P7_S 1 10 1 2
R232 R233 1D+ VCC 150U_B_6.3VM_R40M
75K_0402_1% 43K_0402_1% USB20_N7_S 2 2 2 2
2 1D- S 9 SLP_CHG# <17>
USB20_P7 3 8 USB20_P7_R 470P_0402_50V8J 1000P_0402_50V7K JUSBC
<17> USB20_P7
2
2D+ D+
1 VCC
USB20_P7_S_O USB20_N7 4 7 USB20_N7_R USB20_N7_R_S 2
<17> USB20_N7 2D- D- D-
USB20_N7_S_O USB20_P7_R_S 3 D+
5 GND OE# 6 4 GND
1
B R234 R235 B
3/4 PVT:Add C516 for EMI request 5 GND1
51K_0402_1% 51K_0402_1% TS3USB221RSER_QFN10_2X1P5 2/9 DVT:Change C288 from 220uf to 150uf 6 GND2
7 GND3
8
2
D15 GND4
1 6 SUYIN_020173MR004S512ZL
I/O1 I/O4 @
SLP_CHG FUNCTION 2 REF1 REF2 5 +5VALW
U20 USB20_P7_R_S 3 4 USB20_N7_R_S
I/O2 I/O3
<17> SLP_CHG_M3 1 1OE# LOW D=1D
4 CM1293A-04SO_SOT23-6 2/6 DVT:Modify JUSBC Symbol for GND pad
2OE# @
<17> SLP_CHG_M4 10 3OE#
13 4OE# HIGH D=2D 2/3 DVT: Change D15 from PRTR5V0U2X_SOT143-4 to CM1293A-04SO_SOT23-6
USB20_P7_S 2 3 USB20_P7_S_O
USB20_N7_S 1A 1B USB20_N7_S_O
5 2A 2B 6
9 3A 3B 8 R236 1 2 100_0402_5% W=30mils 1 2
12 11 R390 0_0402_5%
4A 4B +5VALW 1.4A
U21
+USB_VCCB
USB20_N7_R
L12
USB20_N7_R_S
+USB_VCCB 14 VCC GND 7 1 1 2 2
1 GND OUT 8
2 SN74CBT3125PW RG4_TSSOP14 2 7
IN OUT USB20_P7_R USB20_P7_R_S
3 IN OUT 6 4 4 3 3
C293 <26> USB_CHG_EN# 4 5 USB_OC#7 <17,26>
EN# FLG W CM-2012-900T_0805 @
0.1U_0402_16V4Z 1
1 G528_SO8 1 2
C292 R391 0_0402_5%
A
4.7U_0805_10V4Z For EMI request A
2 @
SLP_CHG_M3 SLP_CHG_M4
Mode 3 HIGH LOW Issued Date 2008/11/17 Deciphered Date 2009/11/17 Title
USB Conn
Mode 4 Size Document Number R ev
LOW HIGH AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
A B C D E F G H
SATA Conn. Lid SW

For 1.8" SSD
+5VS +3VS SSD HDD need 400mA for 3V(PHISON) +3VALW
Place closely JHDD SATA CONN.
1.2A
1 1 1 1 1 1 1 1 U22
1 C275 C276 C277 C278 C279 C280 C281 C282 APX9132ATI-TRL_SOT23-3 1
@ @ @ @
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
2 3
GND
VDD VOUT LID_SW # <26>
1 1
1
JSATA C300 C301
1 0.1U_0402_16V4Z 10P_0402_50V8J
GND SATA_ITX_C_DRX_P0 C284 1 0.01U_0402_25V7K 2 2
RX+ 2 2 SATA_ITX_DRX_P0 <16>
3 SATA_ITX_C_DRX_N0 C285 1 2 0.01U_0402_25V7K
RX- SATA_ITX_DRX_N0 <16>
GND 4
5 SATA_IRX_DTX_N0 C286 1 2 0.01U_0402_25V7K
TX- SATA_IRX_C_DTX_N0 <16>
6 SATA_IRX_DTX_P0 C287 1 2 0.01U_0402_25V7K
TX+ SATA_IRX_C_DTX_P0 <16>
GND 7
3.3V 8 +3VS
26 boss 3.3V 9
25 boss 3.3V 10
GND 11
24 GND GND 12
23 GND GND 13
5V 14 +5VS
15
5V
5V
GND
16
17
Camera Conn.
Rsv 18
2 19 2
GND
12V 20
21
12V
12V 22 Int. Camera
ALLTO_C16674-12204-L_NR W=20mils
@
+5VS +CAM_VDD 1 2
C299
0.1U_0402_16V4Z
CAM@ 1 CAM@ 2
R392 0_0402_5%
JCAM L13
BlueTooth Interface 1
2
1
2 USB20_N1_R
USB20_P1_R
1 1 2 2
USB20_N1 <17>
3 3 USB20_P1 <17>
4 4 4 4 3 3
5 5
+3VS 6 @ W CM2012F2S-900T04_0805
+3VS GND1
GND2 7 1 2
R393 0_0402_5%
ACES_88266-05001 CAM@
1
@
R237 0.1U_0402_16V7K
100K_0402_5%
C294
1 2
BT@
For EMI request
BT@
3
S
47K_0402_5%
2
G
<17> BT_OFF 1 2 2
3 R238 BT@ 3
1
C499 D Q16 BT@
1
BT@ AO3413_SOT23
0.01U_0402_25V7K
1/22 DVT:Change R238 from 10K to 47K 2
Add C499 with 0.01uF +BT_VCC
Bluetooth Connector
JBT
Touch Screen Conn.
1 +3VS
USB20_P6 1 C470@
<17> USB20_P6 2 2
USB20_N6 3 1 2
<17> USB20_N6 3
<19> W LAN_BT_CLK 4 4 1 2
<17> BT_DET# 1 BT@ 2 5 R394 0_0402_5% 680P_0402_50V7K
5
<17> BT_RST# 1 BT@ 2 BT_RESET# R239 0_0402_5% 6 6
L14 JTS
R240 100K_0402_5% 7 <19> USB20_TS- 1 2 1
<19> W LAN_BT_DATA 7 1 2 1
8 USB20_TS-_R 2
8 USB20_TS+_R 2
+3VS 1 2 9 9 3 3
R241 @ 10 <19> USB20_TS+ 4 3 <26> TS_STOP 4
4.7K_0402_5% 10 4 3 4
+BT_VCC <26> TS_RST 5 5 G1 7
C296 @ W CM2012F2S-900T04_0805 6 8
6 G2
2
0.1U_0402_16V4Z 1 (MAX=200mA) 1 2
BT@ R242 11 R395 0_0402_5% ACES_87213-0600G
C297 C298 BT@ GND1 @
12 GND2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5%
BT@ 2 BT@ ACES_87213-1000G
1
4
@ For EMI request 4
12/22 Add C872 and close to JBT for EMI request
W LAN_BT_CLK C872@ 1 2 10P_0402_50V8J

SATA /BT/CMOS/TS/ Lid SW
C ustom 1.0
KAVAA LA-5121P M/B
A B C D E F G H
A B C D E
HD Audio Codec +3VS_DVDD

30mil R A1 Audio regulator
10U_0805_10V4Z 2 1 +3VS
1 1 0_0603_1%
CA1 CA2
+AVDD
40mil 2 2
R A3 0.1U_0402_16V4Z
+VDDA 2 1 10U_0805_10V4Z 0.1U_0402_16V4Z
0_0603_1% 1 1 1 1 1 2 +5VS
CA3 CA4 CA5 CA6 10U_0805_10V4Z 1 2
1 1 1 @ PJ19 1
(output= 300mA) JUMP_43X79
2 2 2 2 CA7 CA8
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 +5VS +VDDA
0.1U_0402_16V4Z U A1
25
38
30mil
9
U A2 4.75V
1 5 2
DVDD_IO
AVDD1
AVDD2
DVDD
VIN VOUT CA10
2
CA9 2 @
@ GND CA11 @ 1U_0402_6.3V4Z
14 35 1U_0402_6.3V4Z 3 4 2 1 1
LINE2-L LOUT1_L 1 SHDN# BP
15 36 0.22U_0402_10V4Z
LINE2-R LOUT1_R @
16 39 APL5151-475BC-TRL_SOT23-5
<23> MIC2_L MIC2_L LOUT2_L
Int. Mic 17 41 2/5 DVT:Reserver UA1,CA9,CA11
<23> MIC2_R MIC2_R LOUT2_R
23 LINE1_L SPDIFO1 48
24 LINE1_R SPDIFO2 45
<23> MIC1_C_L 21 MIC1_L HPOUT_L 33 1 2 HP_L <23>

RA5 63.4_0402_1%
HP out
Ext. Mic <23> MIC1_C_R 22 MIC1_R HPOUT_R 32 1
RA6
2
63.4_0402_1%
HP_R <23>
2/4 DVT:Change CA14 from 100pf to 0.1uf
1 2 MONO_IN 12 37
2 CA14 0.1U_0402_16V4Z BEEP_IN MONO_OUT AMP_SPK <23> SPK out Beep sound 2
<16> HDA_BITCLK 6 BITCLK DMIC_CLK1/2 46 1/22 DVT:Link UA2.37 to UA3.17 for mono speaker
<16> HDA_SDOUT 5 SDATA_OUT DMIC_CLK3/4 44
<16> HDA_SDIN0 2 1 HDA_SDIN0_R 8 SDATA_IN LINE2_VREFO 20

RA7 33_0402_5%
11 18 2/11 DVT:mount RA13 with 0 ohm
<16> HDA_RST# RESET# LINE1_VREFO EC Beep
<16> HDA_ SYNC 10 SYNC MIC1_VREFO 28 10mil +MIC1_VREFO Layout need to open channel <26> BEEP# 1
RA8
2
19
10mil 47K_0402_5%
MIC2_VREFO +MIC2_VREFO
2 GPIO0/DMIC_DATA1/2 1 2
31 1 2 RA12 @ 0_0603_5%
3 GPIO1/DMIC_DATA3/4
CPVEE CA16 2.2U_0603_6.3V6K PCI Beep RA9
CA15
27 AC_VREF CA18 CA19 1 2 1 2 MONO_IN
VREF <17> SB_SPKR
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SENSE_A 13 1 2 47K_0402_5%
SENSE A A C_JDREF 1 RA10 RA13 0_0603_5% 0.1U_0402_16V4Z
JDREF 40 2 1 1
SENSE_B 34 20K_0402_1%
SENSE B
CBN 30 1 2
1 2 EAPD_R 47 CA17 2.2U_0603_6.3V6K 1 2
<26> EAPD EAPD 2 2
R A4 0_0402_5% 29 RA14 @ 0_0603_5%
CBP
43 NC
1
IF test OK, link direct 1
4 DVSS AVSS1 26
7 42 RA11 CA20
CA34 10P_0402_50V8J DVSS AVSS2 10K_0402_5%
HDA_BITCLK
DGND AGND 2
0.1U_0402_16V4Z
1 2 1 2
2
3 RA31 22_0402_5% ALC272-GR_LQFP48_7X7 3
DGND need to re-link ALC272 AGND

CA42 100P_0402_25V8K 3/10 PVT:Change CA18 from 10uF to 0.1uf
1 2 HDA_RST# 2 1 +3VS
RA37 4.7K_0402_5%
2/25 PVT:Mount RA31 with 22 ohm,CA34 with 10pf
For EMI request
Sense Pin Impedance Codec Signals Function place close to chip

39.2K PORT-A (PIN 39, 41) SENSE_A
<23> MIC_SENSE 1 2
RA18 20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A
10K PORT-C (PIN 23, 24) <23> NBA_PLUG 1 2 SENSE_B
RA16 5.1K_0402_1%
5.1K PORT-D (PIN 35, 36) SPK out 1

RA17
2
20K_0402_1%
MIC@
4 39.2K PORT-E (PIN 14, 15) 4
20K PORT-F (PIN 16, 17) Int. MIC

SENSE B
10K PORT-H (PIN 37) Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-I (PIN 32, 33) Headphone out ALC272-GR Codec
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
KAVAA LA-5121P M/B
A B C D E
A B C D E
Ext. Mic CH751H-40PT_SOD323-2

RA21 2 RA20 1 1 2
TPA6017 Medium Range Amplifier <22> MIC1_C_L
4.7U_0805_10V4Z 2
CA21
1
1K_0402_5%
2 1
4.7K_0402_5% DA1
MIC1_L
+MIC1_VREFO
+5VS 4.7U_0805_10V4Z 2 1 2 1 MIC1_R

<22> MIC1_C_R
1K_0402_5%
0.1U_0402_16V4Z CA22 RA22 2 RA23 1 1 2 +MIC1_VREFO
4.7K_0402_5% DA2
1 Rin =70Kohm 1 1 1 CH751H-40PT_SOD323-2 1
CA23 CA24 CA25

10U_0805_10V4Z 10 dB
2 2 2
2/6 DVT: Change RA38,RA40 with 2K ohm +5VS
Change RA39,RA41 with 8.2K ohm 0.1U_0402_16V4Z
Int. Mic
CA29 CA43 2 MIC@ 1 +MIC2_VREFO
1
4.7K_0402_5% RA24
16
15
1 2 1 2 1 2
6
RA38 2K_0402_5% UA3 RA28 RA27 MIC@ RA25 MIC@
0.033U_0402_16V7K 1U_0402_6.3V6K 100K_0402_5% 100K_0402_5% CA26 1K_0402_5% JMIC
PVDD1
PVDD2
VDD
1 2 @ 1U_0402_6.3V4Z 2 1 2 1 IN T_MIC 1
<22> MIC2_L 1
RA39 8.2K_0402_5% 1 2 2
2
1U_0402_6.3V4Z 2 CA27 2
<22> MIC2_R 1 2 1
7 2 1K_0402_5% 220P_0402_50V7K 3
CA30 CA44 RIN+ GAIN0 CA28 RA26 MIC@ GND
MIC@ 4 GND
<22> AMP_SPK 1 2 1 2 1 2LINE_C_OUTR GAIN1 3 MIC@
RA40 2K_0402_5% ACES_88231-02001
PACDN042Y3R_SOT23-3
0.033U_0402_16V7K 1U_0402_6.3V6K 17 @
RIN-
2
1 2 18 SPKR+ RA30 RA29
RA41 8.2K_0402_5% ROUT+ 100K_0402_5% 100K_0402_5%
@
14 SPKR-
2
CA31 1 ROUT-
Use mono SPK 2 0.033U_0402_16V7K 9 LIN+ DA3
1
setting 68Hz LOUT+ 4
2 F=1/2 kRC --> -3db 5 2
LIN-
LOUT- 8
C=0.033U,R=70K,F=68Hz 2/3 DVT:Change DA3 from PJDLC05 to PACDN042Y3R
2/16 DVT:Mount DA3 with EMI request
NC 12 Keep 10 mil width

10 AMP_BYPASS
BYPASS
<26> EC_MUTE# 19 SHUTDOWN
1/13 DVT:Change net name from JLINE to JEXMIC
2
Ex.MIC JACK
GND5
GND1
GND2
GND3
GND4
CA33
0.47U_0603_10V7K JEXMIC
1 2/3 DVT:Change DA7 from PJDLC05 to PACDN042Y3R 5
TPA6017A2_TSSOP20
21
20
13
11
1
<22> MIC_SENSE 4
MIC1_R 1 2 MIC1_L_R 3
GAIN0 GAIN1 Av(db)Rin(ohm) LA7 0_0603_5% 6
MIC1_L 1 2 MIC1_L_L 2
0 0 6 90K LA8 0_0603_5% 1
DA6
0 1 10 70K FOX_JA6033L-B3T4-7F_6P-T
3 1 1
1 0 15.6 45K 1
2 CA40 CA41
1 1 21.6 25K 100P_0402_25V8K 100P_0402_25V8K
@ PACDN042Y3R_SOT23-3 @ 2 2 @
3 3
2/3 DVT:Change DA6 from PJDLC05 to PACDN042Y3R

2/16 DVT:Mount DA6 with EMI request
3/4 PVT:Reserve DA6 with PACDN042Y3R
2/25 PVT:Change JEXMIC,JLINE PCB footprint

Head Phone JACK
Right Speaker Connector
JLINE
1/13 DVT:Change net name from JEXMIC to JLINE 5
AG ND
DA5 PJDLC05_SOT23-3 4
<22> NBA_PLUG
3
1 <22> HP_R 1 2 HP _R_R 3
2 LA9 0_0603_5% 6
JSPKR 1 2 HP_L_R 2
<22> HP_L
SPKR+ LA5 1 2 0_0603_5% SPK_R1 1 3 LA10 0_0603_5% 1
SPKR- LA6 1 1 NC1
2 0_0603_5% SPK_R2 2 2 NC2 4 DA7
FOX_JA6033L-B3T4-7F_6P-T
3/4 PVT:Mount DA5 with EMI request ACES_85204-0200N 3
@ 1
4 2 4
PACDN042Y3R_SOT23-3
@
2/3 DVT:Change DA7 from PJDLC05 to PACDN042Y3R

AMP/VR/Audio Jack/MIC
C ustom 1.0
KAVAA LA-5121P M/B
A B C D E
A B C D E
Close to Pin10,13,30,36 +LAN_VDD12
4 2 2 2 2 4
CL15 CL2 CL3 CL4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

Place Close to Chip UL2 1 1 1 1
<17> PCIE_PTX_C_IRX_P3 CL9 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 20 33 LAN_DO PAD

HSOP LED3/EEDO T16
34 LAN_ DI 1 2 +3V_LAN
CL8 LED2/EEDI/AUX
<17> PCIE_PTX_C_IRX_N3 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 21 HSON LED1/EESK 35 LAN_SK_LAN_LINK# RL1 3.6K_0402_5%
32 LAN_CS 1 2
EECS RL2 1K_0402_5%
<17> PCIE_ITX_C_PRX_P3 15 HSIP
38 LAN _ACTIVITY#
LED0
<17> PCIE_ITX_C_PRX_N3 16 HSIN Close to Pin48 Close to Pin1,37,29
RTL8103EL-GR 2 LAN_MDI0+
MDIP0 LAN_MDI0- +3V_LAN
<12> CLK_PCIE_LAN 17 REFCLK_P MDIN0 3 12/18 Del CL6 with 10U
<12> CLK_PCIE_LAN# 18 5 LAN_MDI1+
REFCLK_M MDIP1 LAN_MDI1- VCTRL12
MDIN1 6
<12> LAN_CLKREQ# 25 CLKREQB NC 8
NC 9 2 2 2 2
27 11 CL7 CL10 CL11 CL12
<6,15,17,19,28> PLTRST# PERSTB NC
NC 12
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RL3 1 1 1 1
1 2 2.49K_0402_1% 46 RSET NC 4
<26> LOM_W AKE# 26 48 VCTRL12

ISOLATEB LANWAKEB VCTRL12A
28 ISOLATEB
+3V_LAN 2 1 VDDTX 19 +EVDD12
RL4 100K_0402_5% LAN_X1 41 30 +LAN_VDD12
LAN_X2 CKXTAL1 DVDD12
42 CKXTAL2 DVDD12 36
3 13 3
DVDD12
DVDD12 10 Close to Pin 45 Close to Pin19
39 +LAN_VDD12 +EVDD12
+3VS NC
23 NC NC 44
24 NC VCTRL12D 45 +LAN_VDD12
1
RL5 7 29 +3V_LAN 1 2 2 2
1K_0402_5% GND VDD33 CL28 CL5 CL13 CL14
14 GND VDD33 37
31 GND
47 1 10U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2
ISOLATEB GND AVDD33 2 1 1 1

NC 40
22 GNDTX NC 43
RL6 RTL8103EL-GR_LQFP48_7X7
15K_0402_5%
YL 1
LAN Conn.
LAN_X1 2 1 LAN_X2 JLAN
LAN _ACTIVITY# 2 1 12
RL7 150_0402_1% Amber LED-
25MHz_20pF_6X25000017 1
1 1 +3V_LAN 2 1 11 Amber LED+ SHLD4 16
CL17 CL18 CL19 RL11 150_0402_1%
68P_0402_50V8J 8 15
27P_0402_50V8J 27P_0402_50V8J 2 PR4- SHLD3
2 2 2 2
7 PR4+
RJ4 5_MIDI1- 6 PR2-
5 PR3-
4 PR3+
R J45_MIDI1+ 3 PR2+
RJ4 5_MIDI0- 2
UL3 PR1-
Place CL20,CL21 closed to UL3 SHLD2 14
R J45_MIDI0+ 1
LAN_MDI0+ R J45_MIDI0+ PR1+
1 TD+ TX+ 16
LAN_MDI0- 2 15 RJ4 5_MIDI0- LAN_SK_LAN_LINK# 2 1 10 13
TD- TX- RL8 RL10 150_0402_1% Green LED- SHLD1
1 2 3 CT CT 14 1
CL20 0.01U_0402_25V7K 4 13 CL26 1 2 1000P_0402_50V8-J 1 2 75_0402_1% 2 1 9
NC NC RJ4 5_GND CL22 +3V_LAN RL12 150_0402_1% Green LED+
5 NC NC 12 1 2 1 2
1 2 6 11 CL27 1000P_0402_50V8-J 75_0402_1% 68P_0402_50V8J FOX_JM36113-P2221-7F
CL21 0.01U_0402_25V7K LAN_MDI1+ CT CT R J45_MIDI1+ RL9 2 @
7 RD+ RX+ 10
LAN_MDI1- 8 9 RJ4 5_MIDI1-
RD- RX-
8456E RJ4 5_GND 1 2 1000P_1808_3KV7K LAN GND

CL23 1 1
2/6 DVT: Change UL3 from NS681680(SP050003N00) to 8456E(SP050005V00) CL24 CL25
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
1 1

RTL8103EL 10/100 LAN
C ustom 1.0
KAVAA LA-5121P M/B
A B C D E
5 4 3 2 1
+3VS_CR
RC2 0_0603_5%
+3VS 1 2
+3VALW 1 2
@ RC4 0_0603_5% 1
CC1
0.1U_0402_16V4Z
confirm that whether can be removed 2 RC7 0_0402_5%
2 1
D CC6 0.1U_0402_16V4Z D
1 2
UC2
+3VS_CR
CC4 0.1U_0402_16V4Z 1
AV_PLL
2 1 3
NC
2
7
RC8 NC
+VCC_3IN1 9
100K_0402_5% CARD_3V3
11
D3V3
+3VS_CR 33 D3V3 VREG 10
22 1
1
MS_D4 CC7
NC 30
RC10 0_0402_5% +3VS_CR 8 1U_0402_6.3V4Z
RST# RST#_R CC5 RST#_R 3V3_IN
2 1 44 RST#
MODE SEL 45 2
4.7U_0603_6.3V6K XTLO MODE_SEL
1 47 XTLO XD_CLE_SP19 43
CC8 XTLI 48 42
1U_0402_6.3V4Z XTLI XD_CE#_SP18
XD_ALE_SP17 41
4 40 SD_DATA2
2 <17> USB20_N3 DM SD_DAT2/XD_RE#_SP16 SD_DATA3
<17> USB20_P3 5 DP SD_DAT3/XD_WE#_SP15 39
CR_LED# 14 38
GPIO0 XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13 37
SD_DAT5/XD_D0/MS_D6_SP12 35
2/25 PVT:Mount RC21,CC16 and close to UC2.48 34 SD_MS_CLK RC11 1 2 33_0402_5% SDCLK
SD_CLK/XD_D1/MS_CLK_SP11
MODE SEL 10_0402_5% 10P_0402_50V8J 29
XTLI MS_INS#_SP9
1 2 28
SD_DAT7/XD_D2/MS_D2_SP8 SD_MS_DATA0
RC21 CC16 26
SD_DAT1/XD_D3/MS_D1_SP6
XD_D5_SP5 25
1
C SD_DATA1 C
1 XD_D4/SD_DAT1_SP4 23
CC13 RC16 21 SDCD#
0.1U_0402_16V4Z SD_CD#_SP3 SDWP#
0_0402_5% SD_WP_SP2 20
@ 19
2 +3VS XD_CD#_SP1
18
2
EEDI
2 13 XTAL_CTR 1 2 +3VS_CR
RREF XTAL_CTR RC20 0_0402_5%
24
MS_D5
1
12
RC13 DGND
32 15
220_0402_5% DGND EEDO
EECS
16 XTAL_CTR Description
6 17
AGND EESK SDCMD
46 36 0 Use 12MHz Crystal
2
AGND SD_CMD
1 Use 48MHz CLK Gen

2
2
RTS5159-GR_LQFP48_7X7
DC1 RC14 RC15
HT-110UYG-CT_YEL/GRN 6.19K_0402_1% 0_0402_5%
1
1
1
2 in 1 Card Reader
CR_LED#
JCARD
SD_DATA3 1
SDCMD D3
2
B CMD B
3
VSS1
+VCC_3IN1 4
SDCLK VDD
5
CLK
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1 1 6
VSS2
SD_MS_DATA0 7
CC10 CC11 SD_DATA1 D0
8
2 2 SD_DATA2 D1
9
SDWP# D2
10
SDCD# WP
11
CD
R C USB AUTO DE-LINK MS FORMATTER Description

12
GND1
13
0 NC GND2
YES Recommended
48Mhz TAITW_PSDBTC09GLBS1N14N0
NC 47P YES YES @
<12> CLK_48M_CR 1 2 XTLI NC NC Compatible with RTS5158E

RC19 0_0402_5%
NC 680P YES LED ON

12Mhz 10_0402_5% 10P_0402_50V8J
SDCLK 1 2
10K 180P LED ON
XTLI @ RC18 @ CC15
A CC9 @ 6P_0402_50V8D A
10K 680P YES
1
YC 1
@
12MHZ_16P_6X12000012
2
XTLO
CC12 @ 6P_0402_50V8D
RTS5159 Card Reader
Custom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
+3VALW
+3VALW
1 1 1 1 1 1 C384
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
1000P_0402_50V7K
C378
C379
C380
C381
C382
C383
1 2
0.1U_0402_16V4Z
2 2 2 2 2 2
111
125
22
33
96
67
9
U29
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
GATEA20 1 21 INVT_PW M
<16> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PW M <13>
EC_KBRST# 2 23 BEEP#
<16> EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <22>
SERIRQ 3 26
<17> SERIRQ SERIRQ# FANPWM1/GPIO12
LPC_FRAME# 4 27 ACO FF
<16,28> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <33>
LPC_AD3 5
<16,28> LPC_AD3 LAD3
LPC_AD2 7 PWM Output
<16,28> LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMPA
<16,28> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA <32>
LPC_AD0
<16,28> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
AD P_I
ADP_I/AD2/GPIO3A 65 ADP_I <33>
C LK_PCI_LPC 12 AD Input 66 ADP_V
<12> CLK_PCI_LPC PCICLK AD3/GPIO3B ADP_V <33>
PCI_RST# 13 75 KILL_SW #
<15> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42 KILL_SW # <19>
ECRST# 37 76 H DPACT
ECRST# SELIO2#/AD5/GPIO43 HDPACT <27>
EC_ SCI# 20 C LK_PCI_LPC
<17> EC_SCI# SCI#/GPIO0E
W L_BT_LED# 38
<29> W L_BT_LED# CLKRUN#/GPIO1D
1
+3VALW R303 68 U SB_CHG_EN#
DAC_BRIG/DA0/GPIO3C USB_CHG_EN# <20>
47K_0402_5% 70 EN_ DFAN1 R302
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <28>
2 1 ECRST# DA Output 71 IR EF @ 10_0402_5%
IREF/DA2/GPIO3E IR E F <33>
K SI0 55 72 CHGV ADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <33>
2 1 K SI1 56
2
C387 0.1U_0402_16V4Z K SI2 KSI1/GPIO31
57 KSI2/GPIO32 1
K SI3 58 83 EC_MUTE#
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <23>
K SI4 59 84 USB_EN# C385
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <20>
K SI5 60 85 TS_STOP @ 22P_0402_50V8J
KSI5/GPIO35 PSCLK2/GPIO4C TS_STOP <21> 2
K SI6 61 PS2 Interface 86 TS_RST
KSI6/GPIO36 PSDAT2/GPIO4D TS_RST <21>
K SI7 62 87 TP_CLK
KS O[0..15] KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <29>
KSO0 39 88 TP_DATA
<28> KSO[0..15] KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <29>
KSO1 40
KSI[0..7] KSO1/GPIO21 R243
KSO2 41
<28> KSI[0..7] KSO3 KSO2/GPIO22 VGATE LID_SW #
42 KSO3/GPIO23 SDICS#/GPXOA00 97 VGATE <12,17,37> +3VALW 1 2
KSO4 43 98 W OL_EN#
KSO4/GPIO24 SDICLK/GPXOA01 W OL_EN# <30>
confirm battery team change +5VALW to +3VALW KSO5 SBPW R_EN#
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
SBPW R_EN# <18,30> 47K_0402_5%
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # <21>
KSO7 46 SPI Device Interface
RP9 KSO8 KSO7/GPIO27
47 KSO8/GPIO28
+3VALW 1 8 EC_SMB_CK1 KSO9 48 119 EC_SI_SPI_SO
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <28>
2 7 EC_SMB_DA1 KSO10 49 120 EC_SO_SPI_SI
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <28> +3VALW
+5VS 3 6 TP_CLK KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 E C_SPICLK
KSO11/GPIO2B EC_SPICLK <28>
4 5 TP_DATA KSO12 51 128 S PI_CS#
KSO12/GPIO2C SPICS# SPI_CS# <28>
KSO13 52 1 2
4.7K_0804_8P4R_5% KSO14 KSO13/GPIO2D 330K_0402_5% R307
53 KSO14/GPIO2E
KSO15 54 73 USB_OC#0_2 D21
KSO15/GPIO2F CIR_RX/GPIO40 USB_OC#0_2 <17,20>
81 74 USB_OC#7 A CIN_D 2 1
KSO16/GPIO48 CIR_RLC_TX/GPIO41 USB_OC#7 <17,20> A C IN <17,29,31>
82 89 F STCHG
+3VS KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <33>
90 BATT_FULL_LED# CH751H-40PT_SOD323-2
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <29>
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <28>
EC_SMB_CK2 EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BATT_CHG_LOW _LED# Add D21 for AC-IN leakage issue
<32> EC_SMB_CK1 SCL1/GPIO44 BATT_CHG_LOW _LED# <29>
R308 2.2K_0402_5% EC_SMB_DA1 78 93 PW R_ON_LED#
<32> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_ON_LED# <29>
EC_SMB_DA2 EC_SMB_CK2 79 SM Bus 95 S Y SON
<4,27> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 S YSON <30,35>
R309 2.2K_0402_5% EC_SMB_DA2 80 121 V R_ON
<4,27> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <37>
127 A CIN_D
AC_IN/GPIO59
3/4 PVT:Add net name to USB_OC#0_2
For EC recommend 10/17
PM_SLP_S3# 6 100 EC_RSMRST#
<17> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <17>
PM_SLP_S5# 14 101 EC_LID_OUT#
<17> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <17>
EC_SMI# 15 102 E C_ON 3/10 PVT:Add EC_SWI# for USB sleep&charge function
<17> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <29>
16 103 EC_SW I#
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# <29>
17 104 EC_PW ROK
SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PW ROK <17>
BATT_TEMPA 1 2 18 G PO 105 BKOFF# BKOFF# <13>
C388 100P_0402_25V8K HDPINT PBTN_OUT#/GPIO0C BKOFF#/GPXO08 W L_OFF#
<27> HDPINT 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 W L_OFF# <19> 2/25 PVT:Change net name from ICH_POK to EC_PWROK
25 107 UW B_OFF# UW B_OFF# <19>
A CIN_D FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 ARROW _LED#
1 2 <28> FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 ARROW _LED# <29>
C390 100P_0402_25V8K 29
EC_TX_P80_DATA FANFB2/GPIO15
<19> EC_TX_P80_DATA 30 EC_TX/GPIO16
EC_RX_P80_CLK 31 110 PM_SLP_S4#
<19> EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# <17>
ON /OFFBTN# 32 112 ENBKL
<29> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <8>
PW R_SUSP_LED# 34 114 EAPD
<29> PW R_SUSP_LED# PWR_LED#/GPIO19 GPXID3 EAPD <22>
NUM_LED# 36 GPI 115 EC_THERM#
<29> NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <17>
116 SUSP#
GPXID5 SUSP# <30,33,35,36>
117 PBTN_OUT#
GPXID6 PBTN_OUT# <17>
118 LOM_W AKE#
C R Y1 GPXID7 LOM_W AKE# <24>
122 XCLK1
+3VALW C R Y2 +EC_V18R
123 XCLK0 V18R 124
20mil
AGND
KSO1 1 2
GND
GND
GND
GND
GND
R314
R312 47K_0402_5% C391
KSO2 1 2 C R Y1 1 2C R Y2 4.7U_0603_6.3V6K
R313 47K_0402_5% KB926QFC0_LQFP128
11
24
35
94
113
69
@ 20M_0402_5%
to avoid EC entry ENE test mode

1 1
C392 C393
1
4
15P_0402_50V8J
15P_0402_50V8J
X1
IN
OUT
2 2
NC
NC

2
KB926 D3
32.768KHZ_12.5PF_1TJS125BJ4A421P Size Document Number R ev
C ustom 1.0
KAVAA LA-5121P M/B
5 4 3 2 1
G-Sensor
DVT phase:use SA000035U00 (TIS355AL3TR LGA)
PVT phase:use SA000039900(TSH35TR LGA)
U31 GSENSOR@
+3VS_HDP 2 3 VOUTX C 394 1 2 0.033U_0402_16V7K GSENSOR@
Vdd1 Voutx V OUTY C 395 1
12 Vdd2 Vouty 5 2 0.033U_0402_16V7K GSENSOR@
D 7 VOUTZ C 396 1 2 0.033U_0402_16V7K GSENSOR@ D
Voutz
SELF_TEST 4 10
ST NC1
6 PD NC2 11
8 FS NC3 14
NC4 15
NC5 16
+3VS_HDP 9 Rev GND1 1

GND2 13
TSH35TR LGA
12/18 Change P/N from SA000030500 to SA000035U00

2/11 DVT:Change P/N from SA000035U00 to SA000039900
CH751H-40PT_SOD323-2
+5VS D23 +3VS_HDP +3VS_HDP
U32
1 2 GSENSOR@
@ C3 98 0.1U_0402_16V4Z 2 1VOUTX 2 6
XOUT VDD
2 U33
C4 97 @ C3 99 0.1U_0402_16V4Z 2 1V OUTY 3
1U_0402_6.3V4Z YOUT
1 IN OUT 5 2 NC 1
GSENSOR@ @ @ C3 97 0.1U_0402_16V4Z 2 1 VOUTZ 4 ZOUT NC 8
C 1 C4 00 C
2 GND NC 11
@ C 867 1U_0402_6.3V4Z 9 12
1 0G-DET NC
3 SHDN# BYP 4 2 1 NC 14
+3VS_HDP 7 SLEEP#
G9191-330T1U_SOT23-5 0.22U_0402_10V4Z 10
SELF_TEST G-SELECT
13 ST VSS 5
MMA7360LR2_LGA14
2/6 Reserve C867 with 0.22 for U33.4 NC pin @
2/6 Change U33 from APL5151-33BC to G9191-330T1U
12/24 Change U32.7 link to +3VS_HDP
Change U32.9 no connect
12/25 Del R398 with 0 ohm and U32.10 link to GND
U34
EC_SM B_CK2 1 11 H DPACT <26>

<4,26> EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01
1
SELF_TEST 2 12
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# R3 18
GSENSOR@ 47K_0402_5%
+3VS_HDP R3 19 2 1 4.7K_0402_5% 3 13 GSENSOR@
RESET# P1_4/TXD0
2
GSENSOR@
R3 20 2 1 4.7K_0402_5% XOUT 4 14
XOUT/P4_7 P1_3/KI3#/AN11/TZOUT
B 5 15 VOUTZ B
VSS/AVSS P1_2/KI2#/AN10/CMP0_2
GSENSOR@
R3 21 2 1 4.7K_0402_5% X IN 6 16 +3VS_HDP
XIN/P4_6 P4_2/VREF
1
7 17 VOUTX C4 01
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z
GSENSOR@ GSENSOR@
R3 22 2 2
1 4.7K_0402_5% 8 MODE P1_0/KI0#/AN8/CMP0_0 18 V OUTY
GSENSOR@
HDP INT R3 23 2 1 1K_0402_5% 9 19
<26> HDP INT P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
10 20 EC_SM B_DA2
P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 EC_SMB_DA2 <4,26>
R5F211B4D31SP LSSOP GSENSOR@

1 1
C 402 C 403
GSENSOR@ GSENSOR@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2/16 DVT phase:Use SA000037Y60
2 2
A A

G-Sensor
Size D ocument Number Rev
Cus tom KAVAA LA-5121P M/B 1.0
Dat e: Tuesday, March 10, 2009 Sheet 27 of 42
5 4 3 2 1
SPI Flash (8Mb*1)
FAN Control Circuit 2/3 DVT: Add C501,C502,C503,R412 for EMI request
+5VS +3VALW
330P_0402_50V7K
U36 1 1 1
1 1 8 C503 C502 C411
<26> SPI_CS# CE# VDD
1
10U_0805_10V4Z
C407 D28 0.1U_0402_16V4Z
1A @ 1SS355_SOD323-2 2 2 2
<26> EC_SI_SPI_SO 2 SO HOLD# 7
U35 2 J FAN 470P_0402_50V8J
1 8 +FAN1 1
12
EN GND 1 E C_SPICLK
2 VIN GND 7 2 2 +3VALW 3 WP# SCK 6 EC_SPICLK <26>
+FAN1 3 6 2 3
VOUT GND @ D29 C408 3
<26> EN_DFAN1 4 VSET GND 5 1
@ 4 C501 4 5 EC_SO_SPI_SI
GND VSS SI EC_SO_SPI_SI <26>
1 APL5607KI-TRG_SO8 1000P_0402_25V8J 5
2
1 GND 330P_0402_50V7K
C409 BAS16_SOT23-3 @ ACES_85204-0300N 2 MX25L8005M2C-15G_SO8
10U_0805_10V4Z
2 R332 10K_0402_5% 3/2 PVT:Change U36 to MX25L8005M2C(SA00000XT00)
2 1 +3VS
FAN_SPEED1 <26> C508 R412

2 1 2 1 2 E C_SPICLK
33_0402_5%
C410 33P_0402_50V8K
@
1 0.01U_0402_16V7K
2/25 PVT:Change R412 with 33ohm,C508 with 33pF
LPC Debug Port

K SI0 C414 1 2 100P_0402_50V8J
K SI1 C419 1 2 100P_0402_50V8J
K SI2 C416 1 2 100P_0402_50V8J
K SI3 C418 1 2 100P_0402_50V8J
KEYBOARD K SI4 C422 1 2 100P_0402_50V8J
Please place the connector neer to DDR door K SI5 C424 1 2 100P_0402_50V8J
CONN. K SI6 C426 1 2 100P_0402_50V8J
JP4
1 KSI[0..7] K SI7 C428 1 2 100P_0402_50V8J
+3VS 1 KSI[0..7] <26>
CLK_PC I_DDR 2
<12> CLK_PCI_DDR 2 KS O[0..15]
3 KSO0 C430 1 2 100P_0402_50V8J
3 KSO[0..15] <26>
LPC_AD0 4
<16,26> LPC_AD0 4
LPC_AD1 5 KSO1 C432 1 2 100P_0402_50V8J
<16,26> LPC_AD1 5
LPC_AD2 6
<16,26> LPC_AD2 6
LPC_AD3 7 JKB KSO2 C434 1 2 100P_0402_50V8J
<16,26> LPC_AD3 7
LPC_FRAME# 8
<16,26> LPC_FRAME# 8 1
9 KSO3 C436 1 2 100P_0402_50V8J
PLTRST# 9 2
<6,15,17,19,24> PLTRST# 10 10 3 CAPS_LED# <26>
11 R382 1 2 300_0402_5% +3VS
GND 4 K SI1
12 GND 5 K SI6
ACES_85201-1005N 6 K SI5
@ 7 K SI0 KSO4 C415 1 100P_0402_50V8J
8 2
K SI4
9 K SI3 KSO5 C420 1 100P_0402_50V8J
10 2
K SI2
11 K SI7 KSO6 C417 1 100P_0402_50V8J
12 2
CLK_PC I_DDR KSO15
13 KSO12 KSO7 C421 1 100P_0402_50V8J
14 2
KSO11
15
2
KSO10 KSO8 C423 1 2 100P_0402_50V8J

R341 16 KSO9
22_0402_5% 17 KSO8 KSO9 C425 1 100P_0402_50V8J
18 2
@ KSO13
19 KSO7 KSO10 C427 1 100P_0402_50V8J
2
1
20 KSO6
2 21 KSO14 KSO11 C429 1 2 100P_0402_50V8J
C438 22 KSO5
22P_0402_50V8J 23 KSO3 KSO12 C431 1 100P_0402_50V8J
24 2
1 KSO4
@ 25 KSO0 KSO13 C433 1 2 100P_0402_50V8J
26 KSO1
27 KSO2 KSO14 C435 1 100P_0402_50V8J
28 2
29 KSO15 C437 1 100P_0402_50V8J
30 2
31 CAPS_LED# C461 1 100P_0402_50V8J
32 2
33
34
@ ACES_88170-3400
3/4 PVT:Mount C414~C437,C461 for EMI request
12/18 Follow KB Matrix the same to KSKAA
Security Classification Compal Secret Data

SPI ROM//KB//FAN/Debug Poart
1.0
KAVAA LA-5121P M/B
A B C D E
Power Button +3VALW
Right Switch Touch/B Connector
2
R324
SW2 1/22 DVT:JTOUCH pin define reversal
100K_0402_5% SMT1-05_4P
D24 1 3
1
SW3 2 JTOUCH
ON/OFFBTN#_R 1 ON/OFFBTN# <26> TP_SWR
1 3 2 4 8 GND
TOP side 3 51_ON# <31> 7
GND
2 4 1 6
6
5
CHN202UPT SC-70 +5VS 6
<26> TP_CLK 5
1 SMT1-05_4P C404 5 1
2 4
6
5
<26> TP_DATA TP_SWL 4

180P_0402_50V8J 3
2 C405 TP_SWR 3
2
SW4 1U_0402_6.3V4Z 2
D26 1
1
1
D 1
1 3
2 Q15 3 @ ACES_85201-06051
<26> EC_ON
BTM side 2 4 G
D27 1
2
S 2N7002_SOT23 2/3 DVT:For EMI request 2
3
SMT1-05_4P R327 3
6
5
10K_0402_5% 1
PJDLC05_SOT23-3
2 Left switch @
1
debug phase using PACDN042Y3R_SOT23-3 SW5
@ SMT1-05_4P
3/4 PVT:Change R413,R414,R415 from 0 ohm to FBMA-10-100505-151T 1 3
JPOWER TP_SWL 2 4
ISPD
PWR_ON_LED# R413 1 2 FBMA-10-100505-151T 1
PWR_ON_LED R414 1 1
2 FBMA-10-100505-151T 2 1 Z ZZ PJP1
6
5
ON/OFFBTN#_R R415 1 2
2 FBMA-10-100505-151T 3 3 C406
4 4
1/13 DVT:Change ON/OFFBTN# to ON/OFFBTN#_R 180P_0402_50V8J
180P_0402_50V8J
2 PCB DC-IN
180P_0402_50V8J
180P_0402_50V8J
E&T_6905-E04N-00R
1 C505 1 1 @ PCB LA-5121P DAZ BOM PJP1
C506
C507
45@
@ @ @ U1
2 2 2
2 CPU 2
CPU N280
N8@
LED Conn
DC-IN LED
AC IN
ACIN <17,26,31>
Vf=2.0V(typ),2.4V(max)
If=30mA(max)
2
G
D33
1 2 2 1 1 3 SATALED#
+3VALW
R370 220_0402_5% HDD LED SATALED# <16>
D
2
HT-110UYG-CT_YEL/GRN
Q27 2N7002_SOT23 2N7002DW-T/R7_SOT363-6
+3VS 2 R373 1 6 1
10K_0402_5%
BATT CHARGE/FULL LED
5
Q10A
D36
Vf=1.9V(typ),2.4V(max) for amber +3VS 1 2 2 1 3 4
Vf=2.0V(typ),2.4V(max) for green R374 220_0402_5%
HT-110UYG-CT_YEL/GRN Q10B 2N7002DW-T/R7_SOT363-6
If=30mA(max)
D34
2 BATT_CHG_LOW_LED# <26> WiMAX&3G LED
+3VALW 1 2 1
R371 220_0402_5% WIMAX_LED_GND 1 R334 2
3 LED_WIMAX# <19> 3
3 0_0402_5%
BATT_FULL_LED# <26>
2
@
Q5A 2N7002DW-T/R7_SOT363-6
HT-210UD/UYG_AMB/GRN Vf=2.8V(typ),3.15V(max) +5VS 2 R335 1 6 1
If=20mA(max) 10K_0402_5%
5
WIMAX@ WIMAX@
D31
POWER/SUSPEND LED +5VS 1 2 2 1 WIMAX_LED_GND 3 4
R336 300_0402_5%
WIMAX@ HT-110NB5 1204 BLUE Q5B 2N7002DW-T/R7_SOT363-6
D35 WIMAX@ WIMAX@
2 PWR_SUSP_LED# <26>
1 2 1
+3VALW
R372 220_0402_5% WL&BT LED
3 PWR_ON_LED# <26>
HT-210UD/UYG_AMB/GRN
1 2 PWR_ON_LED Vf=1.9V(typ),2.4V(max)
+5VALW
R375 300_0402_5% If=20mA(max)
2/3 DVT:Change R375.1 Net name from +3VALW to +5VALW
2/3 DVT:Change R375 from 220 to 300 ohm D30
+3VS 1 2 2 1 WL_BT_LED# <26>
R333 220_0402_5%
ARROW MODE LED WLAN@ HT-110UD_1204_AMBER
WLAN@
D40
+3VS 1 2 2 1 ARROW_LED# <26>
R383 220_0402_5%
4 HT-110UYG-CT_YEL/GRN 4
NUMERIC MODE LED

D41
+3VS 1 2 2 1 NUM_LED# <26>
R384 220_0402_5% Issued Date 2008/11/17 2009/11/17 Title
HT-110UYG-CT_YEL/GRN Deciphered Date
ON/OFF /TP Conn/LEDS
Custom 1.0
KAVAA LA-5121P M/B
A B C D E
A B C D E
+3VALW TO +3VS +5VALW TO +5VS +3VALW TO +3V_SB Vgs=10V,Id=6A,Rds=35mohm

+3VALW +3V_SB
+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS PJ18
2 2 1 1
1 1 1 1 Q20 @ JUMP_43X79
Q18 Q19 4.7U_0603_6.3V6K
D
470_0805_5%
470_0805_5%
1 8 1 C439 C440 8 1 C441 C442 6 1
S
D S D S
2
7 2 1U_0402_6.3V4Z 4.7U_0805_10V4Z 7 2 1U_0402_6.3V4Z 4.7U_0805_10V4Z 1 5 4
D S 2 2 D S 2 2 R343
6 D S 3 6 D S 3 2 1 1
2
5 4 R342 5 4 C444 1 4.7U_0603_6.3V6K C445
D G D G C443 STAR@ R345
STAR@
G
SI4800BDY_SO8 2
1 R344 2 +VSB SI4800BDY_SO8 1 R346 2 +VSB @ 1U_0402_6.3V4Z STAR@
3 1
3 1
3
2 2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.01U_0402_25V7K
1 1 47K_0402_5% 1 1 47K_0402_5% STAR@ 470_0805_5%
6
0.022U_0402_16V7K
C447 +VSB 2 1 SI3456BDV-T1-E3_TSOP6
6 1
1
C446 C448 C449 R349 Q7A R347 47K_0402_5%
3
R348 Q6A Q6B 200K_0402_5% Q7B STAR@ 1
2 2 SUSP 2 2 @ SUSP STAR@ R350 C450
2 5 2 5
330K_0402_5% 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 120K_0402_5% 0.1U_0402_25V6
2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 SBPW R_EN# 5 STAR@ Q8A 2 SBPW R_EN#
<18,26> SBPW R_EN#
2
4
Q8B 2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6
1
STAR@ STAR@
2/25 PVT:Change C447 with 0.022uF
+3VALW TO +3V_LAN 2/25 PVT:Reserve R349 with 200Kohm

Change R346 with 47Kohm
+5VALW
+3VALW +3VALW
+5VALW
Vgs=-4.5V,Id=3A,Rds<97mohm
2
2
R353 R361
2 100K_0402_5% 1 100K_0402_5% R362 2
STAR@ C451 100K_0402_5%
2
STAR@
1
1
3
S
STAR@ 0.1U_0402_16V7K PJ17 SUSP
2
<36> SUSP
1
2 G
SYSON#
<26> W OL_EN# 1 2 2 JUMP_43X79
R355 47K_0402_5% Q21 @
1
AO3413_SOT23 D
1
STAR@
1
+3V_LAN D
1/22 DVT: Change R355 from 3.3K to 47K
1
D
Add C500 with 0.01uf 1 2 <26,33,35,36> SUSP# 2
C500 0.01U_0402_25V7K G S Y SON 2
<26,35> S YSON
2
STAR@ Q28 S 2N7002_SOT23 G
3
1 1 Q29 S 2N7002_SOT23
3
R401 R402
C452 C453 1U_0402_6.3V4Z 10K_0402_5% 10K_0402_5%
4.7U_0805_10V4Z STAR@
1
@ 2 2
Screw Hole MINI Card

Half card
Full card
+1.5VS +2.5VS +1.05VS H20 H21
M/B H11 H12 H13 H14
2
H1 H2 H3 H4 H5 @ @
R363 R364 R365 @ @ @ @
1
3 470_0603_5% 470_0603_5% 470_0603_5% H_3P3 H_3P3 3
1
@ @ @ @ @ @ @ H_3P3 H_3P3 H_3P3 H_3P3
1
1
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
KB 1/13 DVT:Add H20,H21 for half card
1
D D D H16
2 SUSP 2 SUSP 2 SUSP H15
G G G GNDA @
S Q30 S Q23 S Q24 @ +3VS +3VS +3VS +3VS
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 H_3P0
1
@ @ H6 H7 H8 H_3P0N
2 2 2 2
1
@ @ @
C517
C518
C519
C520
PJ22 R422
1
1
H_3P0 H_3P0 H_3P0 JUMP_43X79 0_0402_5%

2/6 DVT: Reserve +1.5VS,+1.05VS,+0.9VS,+1.8VS discharge circuit @ @ 1 1 1 1
22
2
+0.9VS +1.8V FAN 3/4 PVT:For ESD team request
H9 H10 H17 3/5 PVT:For EMI request FIDUCIAL_C40M80
2
R366 R367 H18 H19

470_0603_5% 470_0603_5% @ @ @ FM1 FM2 FM3 FM4
@ @
1
H_1P2 H_1P2 H_1P2 @ @ @ @ @ @

1
1
4 4
H_2P6N H_6P0X2P6N
1
D D
2 SUSP 2 SYSON# 3/2 PVT:Change H18 from H_3P0N to H_2P6N
G G 3/2 PVT:Change H19 from H_6P0X3P0N to H_6P0X2P6N
S Q25 S Q26
3
2N7002_SOT23 2N7002_SOT23
@ @ Security Classification Compal Secret Data Compal Electronics, Inc.
DC INTERFACE
C ustom 1.0
KAVAA LA-5121P M/B
A B C D E
A B C D
VS
V IN PR1
PL1 V IN 1M_0402_1%
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2
1
1
PJP1 VS PR3
5A_24VDC_429007.W RML PR2 5.6K_0402_5% PR4
1 84.5K_0402_1% 10K_0402_1%
+
1
1 2 AC IN <17,26,29>
2
PC1 PC2 PC3 PC4 PR5
8
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 22K_0402_1% PU1A
2
2 1 2 3
P
1
- + PACIN
1
O 1 PACIN <33>
2 -
G
1
@ SINGA_2DW -0005-B03
1
PR6 LM393DG_SO8
4
PC5 20K_0402_1% PC6 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%
2
2
2
2 1 RTCVREF
PR8
V IN 10K_0402_1%
3.3V
Vin Detector
2
PD2
RLS4148_LL34-2 High 18.384 17.901 17.430
1
Low 17.728 17.257 16.976
BATT+ 2 1
1
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11
2
200_0603_5%
CHGRTCP 1 2 N1 3 1 VS
1
1
2
PC8 2
PR13 PC7 0.1U_0603_25V7K
8
100K_0402_1% 0.22U_1206_25V7K PU1B
2
2
5
P
2
+
O 7
<29> 51_ON# 1 2 6 -
G
PR15
22K_0402_1% LM393DG_SO8
RTC Battery
4
RTCVREF
1
PR17
200_0603_5%
- PBJ1 +
PR21 PR22 PU2 G920AT24U_SOT89-3 2 1 +RTCBATT
560_0603_5% 560_0603_5% 3.3V +RTCBATT
2
1 2 1 2 3 2 N2
+CHGRTC OUT IN
@ MAXEL_ML1220T10
1
GND
PC9 PC10
10U_0805_10V4Z 1
2
1U_0805_25V4Z
SP093MX0000
3 3
PJ1 PJ2
+3VALW P 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V
@ JUMP_43X118 @ JUMP_43X118
(5A,200mils ,Via NO.= 10) (5A,200mils ,Via NO.= 10)
(OCP min=6.44A) (OCP min=6.07A)
PJ3 PJ4
+5VALW P 2 2 1 1 +5VALW +1.05VSP 2 2 1 1 +1.05VS
@ JUMP_43X118 @ JUMP_43X118
(5A,200mils ,Via NO.= 10) (6A,240mils ,Via NO.=12)
(OCP min=7.55A)
(OCP min=6.53A)
PJ5
PJ6
+VSBP 2 1 +VSB +1.5VSP 2 1 +1.5VS
2 1 2 1
@ JUMP_43X39 @ JUMP_43X79
(3A,120mils ,Via NO.=6)
(120mA,40mils ,Via NO.= 1)
PJ8
PJ7
+0.9VSP 2 2 1 1 +0.9VS +2.5VSP 2 2 1 1 +2.5VS
4 4
@ JUMP_43X79 @ JUMP_43X39
(2A,80mils ,Via NO.= 4) (100mA,40mils ,Via NO.= 2)

DCIN&DECTOR
1.0
KAVAA LA-5121P M/B
A B C D
A B C D
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
VMB VL
PF2 PL2 VL
PJP2 7A_24VDC_429007.W RML SMB3025500YA_2P VL
1 BATT_S1 1 2 1 2
1 BATT+
2
2 BATT_P3 1 2 1 2 PR30
2 +3VALW P
1
3 BATT_P4 PR28 PR29 47K_0402_1%
1
3 BATT_P5 1K_0402_1% 47K_0402_1% PC14 PC15 PH1 PC16
1
4 4 MAINPW ON <34>
9 5 EC_SMDA <BOM Structure> 1000P_0402_50V7K 0.01U_0402_25V7K 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR31
1
9 5 EC_SMCA 47K_0402_1%
6 6
1
8 7 1 2
2
8 7 PR33 PR32
8
@ SUYIN_250005MR007G163ZR 1K_0402_1% 13.7K_0402_1% PU3A
1 2 3
P
+
1 2 1 2
2
O
2
2
TM_REF1 2 PQ4
-
G
PR34 PR35 PD6 DTC115EUA_SC70-3
100_0402_1% 100_0402_1% LM393DG_SO8 RLS4148_LL34-2
3
0.22U_0805_16V7K
1
15.4K_0402_1%
1
1
PC17
PR36
PR37
1000P_0402_50V7K
6.49K_0402_1%
2 1 +3VALW P 2 1
2
VL
PC18
PR38
2
100K_0402_1%
2
1
1
PR39
1K_0402_1%
PR40
100K_0402_1%
2
2
BATT_TEMPA <26>
2 2
EC_SMB_DA1 <26>
EC_SMB_CK1 <26>
PH2 near main Battery CONN :
BAT. thermal protection at 90 degree C
Recovery at 53 degree C
VL VL
PQ5
2
TP0610K-T1-E3_SOT23-3
1
PR41
47K_0402_1%
B+ 3 1 +VSBP PH2 PR42
100K_0603_1%_TH11-4H104FT 47K_0402_1%
1
100K_0402_1%
@ 0.22U_1206_25V7K
@ 0.1U_0603_25V7K
1 2
2
1
1
PR43
PC19
PC20
PR44
8
13.7K_0402_1% PU3B
1 2 5
P
2
+
7 2 1
2
TM_REF1 O
6 -
G
1
VL PR45 PD7
1
3 3
22K_0402_1% LM393DG_SO8 RLS4148_LL34-2
4
1 2 PC21 PR46
2
0.22U_0805_16V7K 16.9K_0402_1%
2
PR47
2
100K_0402_1%
PR48
1
0_0402_5% D
1 2 2 PQ6
<34> POK
G SSM3K7002FU_SC70-3
@.1U_0402_16V7K
S
3
1
PC22
2
4 4

BATTERY CONN/OTP
1.0
KAVAA LA-5121P M/B
A B C D
A B C D
B+
PQ7
P2
P2003EVG_SO8
P3 PR49 0.05_1206_1%
B+ CHG_B+
PD9 1 8 PJ9
VIN 2 1 2 7 1 4 2 2 1 1
3 6 PQ8
B340A_SMA2 5 2 3 @ JUMP_43X118 CS IN P2003EVG_SO8
1 1
0.1U_0402_25V6
1 8
4.7U_1206_25V6K
2200P_0402_50V7K
CSIP 2 7
4.7U_1206_25V6K
3 6
1
PC131
PQ10 TP0610K-T1-E3_SOT23-3 5
PC24
PC124
PQ9 PR50
PC23
DTA144EUA_SC70-3 200K_0402_1% 3 1 D CIN
4
PC26 P3
2
1
1
2 5600P_0402_25V7K
1
PC27 PR52 PQ11 PR53
1
PR51 0.1U_0603_25V7K 100K_0402_1% DTC115EUA_SC70-3 1 2
2
47K_0402_1% VIN
2
PR54 PD10 47K_0402_1%
2
2
100K_0402_1% 2 FSTCHG PR55 PD11
1
2
1
PD12 2 1 2 1 10K_0402_1% 1 2 ACOFF

1SS355_SOD323-2 3
1 2 6251VDD SUSP# <26,30,35,36> 1SS355_SOD323-2
1
2.2U_0603_6.3V6K
RB715F_SOT323-3 PR57
PC28
2 PR56 200K_0402_1%
3
1
1
PQ12 10K_0402_1% 1 2 V IN
DTC115EUA_SC70-3 2 1 PU5 PC31
<26> FSTCHG 0.1U_0603_25V7K
2
1
100K_0402_1%
1 2 1 24 D CIN 2 1 PQ15 PD13
3
VDD DCIN
1
1
2 DTC115EUA_SC70-3 2 1 2
PR59
G PQ13 PC29
S PR58 .1U_0402_16V7K 2 23 1SS355_SOD323-2
3
SSM3K7002FU_SC70-3 150K_0402_1% ACSET ACPRN PR60

20_0603_5%
2
1
6251_EN CSON D
3 EN CSON 22 1 2
1
@ PC30 PC32 PC33 2 PACIN
5
6
7
8
680P_0402_50V7K 0.047U_0603_16V7K 0.1U_0603_25V7K G
CSON 1 2 4 21 1 2 CSOP S PQ14
3
2 CELLS CSOP PR61 PQ16 SSM3K7002FU_SC70-3 2
PC34 6800P_0402_25V7K 20_0603_5% AO4466_SO8

1 2 5 ICOMP CSIN 20 2 1
1
2
D PR62 4
2 PQ17 PC35 PR63 6.81K_0402_1% PC36 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2
1
VCOMP CSIP PL3 PR66
S
3
0.01U_0402_25V7K 1 2 PR65 100_0402_1% PR64 10UH_MPL73-100_3A_20% 0.02_2512_1% BATT+
3
2
1
PR67 1 2 7 18 LX_CHG 2.2_0603_5% 1 2 C HG 1 4
22K_0402_1% @ PC37 100P_0402_50V8J ICM PHASE
5
6
7
8
4.7_1206_5%
PACIN 1 2 1 2 2 3
<31> PACIN
10U_1206_25V6M
10U_1206_25V6M
PC38 6251VREF 8 17 DH_CHG
VREF UGATE
PR19
PR68<26> ADP_I .1U_0402_16V7K PR69 PC39
309K_0402_1% 2.2_0603_5% 0.1U_0603_25V7K PQ18
1
PC40
PC41
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 AO4466_SO8
<26> IREF CHLIM BOOT
1
1
PQ19 PR70 4
2
0.01U_0402_25V7K
DTC115EUA_SC70-3 24.9K_0402_1% PD14
2
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1
680P_0603_50V8J
1
1
PC42
PC13
ACOFF 2 PR71 1 26251VDD
<26> ACOFF
3
2
1
100K_0402_1% PR72 11 14 DL_CHG
2
VADJ LGATE
2
20K_0402_1% PR73
2
4.7_0603_5%
2
12 13 PC43
3
1
GND PGND 4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
PR74
15.4K_0402_1%
1 2
<26> CHGVADJ
1
3 3
PR75
Iada=0~1.579A(30W) CP= 92%*Iada; CP=1.4526A 31.6K_0402_1%
2
CP mode
Vaclim=2.39*(20K//152K/(24.9K//152K+20K//152K))=1.0817V
V IN
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)
where Vaclm=1.0817V, Iinput=1.4526A
1
PR76
CC=0.25A~2A CHGVADJ=(Vcell-4)/0.10627 309K_0402_1%
IREF=1.636*Icharge Vcell CHGVADJ PR12
2
10K_0402_1%
IREF=0.409V~3.272V 4V 0V 1 2 ADP_V <26>
VCHLIM need over 95mV 4.2V 1.2V

1
1
4.35V 3.3V @ PD15 PR77
GLZ4.3B_LL34-2 47K_0402_1% PC44
.1U_0402_16V7K
2
2
CELLS VDD GND Float 2

4 4
CELL number 4 3 2

CHARGER
1.0
KAVAA LA-5121P M/B
A B C D
5 4 3 2 1
TPS51427_B+
TPS51427_B+
PR78
PJ10 0_0805_5%
2 1 1 2
B+ 2 1
2200P_0402_50V7K
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
0.1U_0402_25V6
0.1U_0402_25V6
1
5
6
7
8
VL
8
7
6
5
P C45
P C46
P C47
P C48
P C49
P C50
D D
1
PC129
PC130
2
2
2
2
2
2
1U_0603_10V6K
PC51 4
4.7U_0805_6.3V6K
4 0.1U_0603_25V7K
1
P C52
PQ21
P C53
PQ20
1
AO4466_SO8 +5VALWP
3
2
1
AO4466_SO8
1
2
3
PL5
PL4 4.7UH_PCMC063T-4R7MN_5.5A_20%
7
4.7UH_PCMC063T-4R7MN_5.5A_20% PU6 PC54 2 1
1 2 1U_0603_10V6K
LDO
VIN
V5FILT
+3VALWP
5
6
7
8
33 TP V5DRV 19 1 2
8
7
6
5
1
PQ22
1
PQ23 PR79 D H3 26 15 D H5 PR83 AO4712_SO8 PR82
PR81 AO4712_SO8 2.2_0603_5% DRVH2 DRVH1 2.2_0603_5% 4.7_1206_5%
4.7_1206_5% 1 2 BST3A 24 17 BST5A 1 2
VBST2 VBST1
1
@ 61.9K_0402_1%
4
2
2
2
@.1U_0402_16V7K
1 PR80 4 PC57
P R84
0_0402_5% PC56 0.1U_0603_25V7K
@ .1U_0402_16V7K
PC55 + 0.1U_0603_25V7K
1
1
1
P C99
LX3 25 16 LX5 PC59 1

2
3
2
1
150U_B2_6.3VM_R35M PC58 LL2 LL1 680P_0603_50V8J
1
2
3
1
2
PC120
680P_0603_50V8J + PC60
2
2
DL3 23 18 DL5 150U_B2_6.3VM_R45M
1
DRVL2 DRVL1
2
2
2
0_0402_5%
C 22 C
PGND
2
FB3 30 VOUT2
P R86
@ PR85
10K_0402_1% 10
VOUT1
32
VL
1
REFIN2
1
11 FB5
2VREF_TPS51427 FB1
1 2 1 VREF2
PC61 0.22U_0603_10V7K
VSW 9
8 LDOREFIN @ PR87 0_0402_5%
SKIPSEL 29 2 1 VL
PR88 0_0402_5%
1 2
20 NC PGOOD2 28
PD16 PR89
GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 POK <32>
VS EN_LDO PGOOD1 PR91
2
200K_0402_1%
200K_0402_1%
2
P R90
14 12 ILM1 2 1
PC62 EN1 TRIP1
0.22U_0603_10V7K
TONSE
VREF3
1
27 31 IL IM2 2 1
GND
1
EN2 TRIP2
1
B 1SS355_SOD323-2 B
2
PR92
VL
0_0402_5%
PD17 @ PR93 SN0806081RHBR_QFN32_5X5 200K_0402_1%
21
P R94
0_0402_5%
2
2
PR95
1
1
1U_0603_10V6K
806K_0603_1% 2VREF_TPS514271
PR97 @ PR98 PR96 +5VALWP Ipeak=5.84A ; Imax=4.088A

1
2
P C63
0_0402_5% 47K_0402_5% 0_0402_5%
+3.3VALWP Ipeak=6A ; Imax=4.2A 2 1 1 2
Choke DCRmax=65.6m ohm
2VREF_TPS514272
<32> MAINPWON Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Choke DCRmax=65.6m ohm
1
0.047U_0603_16V7K
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 200K)/10=100mV

1
Ilimit=100mV/15m ~ 100mV/18m
P C64
Vlimit=(5E-06 * 200K)/10=100mV
Ilimit=100mV/15m ~100mV/18m =5.55A ~ 6.66A
2
=5.55A ~6.66A Iocp=Ilimit+1/2*Delta IL

1
Iocp=Ilimit+1/2*Delta IL =6.53A ~ 7.64A

@ PC65
1/2*Delta IL=0.98A (Freq=400KHz)
3
=6.44A ~ 7.55A 0.047U_0402_16V7K

2
1/2*Delta IL=0.89A (Freq=300KHz)

2 PQ24
TP0610K-T1-E3_SOT23-3
A A
1

+5VALWP/+3VALWP
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
A B C D
PJ11 B+
1.05V_B+ 2 1
2 1
0.1U_0402_25V6
4.7U_1206_25V6K
4.7U_1206_25V6K
2200P_0402_50V7K
@ JUMP_43X118
1
PC127
1
1
PC66
PC67
PC125
2
5
6
7
8
1 1
2
PQ25
AO4466_SO8
PR99 4
1 2
PR100 255K_0402_1% PR101
0_0402_5% 2.2_0603_5%
1 2 BST_1.05V1 2
<26,30,33,36> SUSP#
3
2
1
1
PL6
15
14
PC69
1
@PC68 PU7 2.2UH_PCMC063T-2R2MN_8A_20%
.1U_0402_16V7K BST_1.05V-1 1 2 1 2
EN_PSV
TP
VBST
+1.05VSP
4.7_1206_5%
2 13 DH_1.05V 0.1U_0603_25V7K
TON DRVH
PR102
PR103 3 12 LX_1.05V
VOUT LL
5
6
7
8
422_0603_1% 1 220U_B2_2.5VM
@ .1U_0402_16V7K
+5VALW 1 2 4 11 1 2 +5VALW PQ26
V5FILT TRIP PR104 AO4712_SO8 + PC70
2
5 10 13.7K_0402_1%
VFB V5DRV
1
PC121
1
1
2
680P_0603_50V8J
6 9 DL_1.05V 4
PGOOD DRVL
PGND
PC72
PC71
GND
2
1U_0603_10V6K @ PC73
2
1
47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC74
3
2
1
4.7U_0805_10V6K
2
2 2
PR105
8.25K_0402_1%
1 2
1
PR106
20.5K_0402_1%
2
PJ12
51117_B+ 2 1 B+
2 1
0.1U_0402_25V6
4.7U_1206_25V6K
4.7U_1206_25V6K
2200P_0402_50V7K
@ JUMP_43X118
1
PC128
1
1
PC75
PC76
PC126
2
5
6
7
8
PQ27
2
AO4466_SO8
PR107
255K_0402_1% 4
1 2
PR108 PR109
0_0402_5% 2.2_0603_5%
1 2 BST_1.8V 1 2
<26,30> SYSON
3
2
1
3 3
1
PL7
15
14
PC78
1
@PC77 PU8 2.2UH_PCMC063T-2R2MN_8A_20%

.1U_0402_16V7K BST_1.8V-1 1 2 1 2
EN_PSV
TP
VBST
+1.8VP
2
4.7_1206_5%
2 13 DH_1.8V 0.1U_0603_25V7K
TON DRVH
PR110
PR111 3 12 LX_1.8V
VOUT LL
5
6
7
8
@ .1U_0402_16V7K
422_0603_1%
+5VALW 1 2 4 11 1 2 +5VALW PQ28 1
V5FILT TRIP PR112 AO4712_SO8
1
PC122
5 10 15.4K_0402_1% + PC79
VFB V5DRV 220U_B2_2.5VM_R25M
1
680P_0603_50V8J
6 9 DL_1.8V 4
2
PGOOD DRVL
PGND
PC81
PC80
GND
1U_0603_10V6K PC82
2
2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC83
7
3
2
1
4.7U_0805_10V6K
2
PR113
28.7K_0402_1%
1 2
1
PR114
20.5K_0402_1%
2
4 4

1.05VSP/1.8VP
1.0
KAVAA LA-5121P M/B
A B C D
5 4 3 2 1
D D
+1.8V
1
1
PJ13
@ JUMP_43X79
2
PJ14
PU9 @ JUMP_43X79 PU10
2
1 6
VIN VCNTL
+3VALW +3VS 1 2 2 3
1 2 IN OUT
+2.5VSP
.1U_0402_16V7K
2 2 GND NC 5
1
PC85
1
GND
PC123
PC84 3 7 1U_0603_10V6K
VREF NC
1
4.7U_0805_6.3V6K PR115 PC86 APL5508-25DC-TRL_SOT89-3
1
2
1K_0402_1% 1 PC87 @ PR116
4 VOUT NC 8
1U_0603_10V6K 4.7U_0805_6.3V6K 150_1206_5%
2
9
2
TP
C APL5331KAC-TRL_SO8 C
.1U_0402_16V7K
PR117
+0.9VSP
1
1
0_0402_5% D
PC88
<30> SUSP 1 2 2 PR118
1
G 1K_0402_1%
2
1
S PQ29 PC90
3
PC89 SSM3K7002FU_SC70-3 10U_0805_6.3V6M

2
2
@ 0.1U_0402_16V7K
2
+5VALW +1.8V
1
PJ15
@ JUMP_43X39
1
2
2
1
1
1U_0603_10V6K
PC91
PC92
B 10U_0805_6.3V6M B
2
6
PU11
5
VCNTL
VIN
7 POK
VOUT 4 +1.5VSP
0.01U_0402_25V7K
PR119 3
VOUT
PC93
0_0402_5%
22U_0805_6.3V6M
1 2 8 2 PR120
<26,30,33,35> SUSP# EN FB
1
2.7K_0402_1%
GND
PC94
9
2
VIN
1
2
PC95
1
1
@ 0.47U_0402_6.3V6K
2
APL5912-KAC-TRL_SO8
PR121
3K_0402_1%
A A

+0.9VSP/+1.5VP/+2.5VSP
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
A B C D E F G H
1 1
PR122
499_0402_1%
<6,17> PM_DPRSLPVR 1 2 +5VS
C PU_VID6
C PU_VID5
C PU_VID4
C PU_VID3
C PU_VID2
C PU_VID1
C PU_VID0
<5>
<5>
<5>
<5>
<5>
<5>
<5>
+CPU_B+ PL8
PR123 FBMA-L11-201209-121LMA50T_0805
V R_ON
<26>
0_0402_5%
2
<4,16> H_DPRSTP# 1 2 1 2 B+
4700P_0402_25V7K
4.7U_0805_25V6M
4.7U_0805_25V6M
PR125 0_0402_5% PR124
1 2 1_0603_5%
CLK_ENABLE#
1
PR126
P C96
P C97
P C98
0_0402_5%
+3VS 1 2
2
1U_0603_10V6K
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0.01U_0402_25V7K
1
1
1U_0402_6.3V6K
1
1
PC100
PC101
PC102
PR127
5
6
7
8
10K_0402_1%
2
2
PQ30
2
PR128
PR129
PR130
PR131
PR132
PR133
PR134
PR135
AO4466_SO8
+1.05VS <12,17,26> VGATE 4
@ 0.1U_0402_16V7K
+CPU_COREP
41
40
39
38
37
36
35
34
33
32
31
2
P U12
3
2
1
PR136
3V3
DPRSTP#
VID6
VID5
VID4
VID3
GND PAD
PGOOD
CLK_EN
DPRSLPVR
VR_ON
1
PC103
68_0402_5% PR138 PC104 PL9

PJ16
2.2_0603_5% 0.22U_0603_25V7K 1.5UH_PCMC063T-1R5MN_9A_20%
1 30 1 2 1 2 1 2 1 2
+CPU_CORE
1
FDE VID2 1 2
PR139
1 2 2 29 @
PMON VID1 JUMP_43X118
5
6
7
8
1
PW ON
PR137 40.2K_0402_1%
1
1 2 @ 3 28
RBIAS VID0 @ PR140
147K_0402_1%
1
H_PROCHOT# 4 27 PQ31 4.7_1206_5% PR141
P H3 VR_TT# VCCP AO4712_SO8 11.8K_0402_1%
2
2 1 2 1 2 5 26 LGATE_CPU 4 2
2
<4> H_PROCHOT# NTC LGATE
VSUM
@ 100K_0603_1%_TH11-4H104FT P D18
PR142 1 2 6 25 B340A_SMA2
1
@ 4.22K_0402_1% PC105 SOFT VSSP
0.015U_0402_16V7K 7 24 PHASE_CPU
3
2
1
OCSET PHASE @ PC106
2
PR143 8 23 UGATE_CPU 680P_0603_50V8J
VW UGATE
1 2
4.12K_0402_1% 9 22 BOOT_CPU
COMP BOOT
DROOP
10 21
2
FB NC
VSUM
VDIFF
VSEN
VDD
RTN
VSS
DFB
2
VIN
VO
PR144
PC107 ISL6261ACRZ-T_QFN40_6X6
6.81K_0402_1% 1000P_0402_50V7K
1
11
12
13
14
15
16
17
18
19
20
1
PC108
2 1 PR145
120P_0402_50V8 332K_0402_1%
1 2 +5VS
PC109 PR146
1
82P_0402_50V8J 10_0603_5%
PC110
1U_0402_6.3V6K
2
PC111
PR148 1200P_0402_50V7K PR147
1 2 1 2 10_0603_5%
1.54K_0402_1% 1 2 +CPU_B+
1
PR149
1K_0402_1% PC112
1 2 0.22U_0603_25V7K
2
PC113 1000P_0402_50V7K
3 3
<5> V CCSENSE 1 2 1 2 VSUM
PR150
1
0_0402_5%
PC114 PR151
1
@ 0.068U_0402_10V6K
1.82K_0402_1%
1000P_0402_50V7K @ 3.57K_0402_1%
2
PR153
1 2
2 2
2
1
.1U_0402_16V7K
<5> VSSSENSE PR152

PC118
PC115
0_0402_5% PC116 330P_0402_50V7K

2
1
1 2
1
PC117 P H4
330P_0402_50V7K 1 2 1 2 @ 10KB_0603_5%_ERTJ1VR103J
2
PR154 PR155
1K_0402_1% 1.62K_0402_1%
+CPU_COREP
1
PC119
0.22U_0603_25V7K
2
4 4

+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
KAVAA LA-5121P M/B
A B C D E F G H
OP!EBUF!!!!!QBHF!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
.............................................................................................................
EVT P34-3VALW/5VALW Change PD17 SC1SS355010 TO SC100001K00 Choice the same rating
EVT P35-1.05VSP/1.8VP Change PR101&109 0_0603_1% to0_0603_5% Choice the same rating
EVT P33-CHARGER Change PR67 22K_0402_5% to 22K_0402_1% Choice the same rating
EVT P36-+0.9VSP/+1.5VP/+2.5VSP Change PC85 1U_0603_6.3V6M TO 1U_0603_10V6M Choice the same rating
EVT P36-+0.9VSP/+1.5VP/+2.5VSP Change PC88 SE076104KM8 to SE076104K80

Choice the same vender
EVT P37-+CPU_CORE Change PC115 SE076104KM8 to SE076104K80

Choice the same vender
EVT P33-CHARGER Change PR76 SD03430938L to SD034309380 Choice the A51 component
EVT P34-3VALW/5VALW Change PC55 & PC60 SGA00001E00 TO SGA00002900 Choice the small size
DVT P31-DCIN/DECTOR Change PF1 SP04107P303 TO SP040000P00 Decrease the rating(Memo)
DVT P37-+CPU_CORE Change PC116 & PC117 SE074331K00 TO SE074331K80 Choice the pb free material
DVT P34-3VALW/5VALW Change PC60 Sga00002900 TO Sga00001e00 Change main source
DVT P31-DCIN/DECTOR Change PJP1 4pin to 2pin change dimation
DVT P34-3VALW/5VALW Change PC55 Change the ESR
DVT P35-1.05VSP/1.8VP Change PC79 TO SGA00004800 Change the ESR
DVT P36-+0.9VSP/+1.5VP/+2.5VSP Add PC123 0.1u ESD recommend
DVT P33-CHARGER Change PR68 154K_0402_1% to 309K_0402_1% Design change
DVT All Sunber All RF recommend
PVT P33-CHARGER add PR12 10K Design change
PVT P33-CHARGER add pc131 & pc124 RF tema require
PVT P34-3VALW/5VALW PR83 & PR79 change to 2.2ohm EMI tema require
PVT P34-3VALW/5VALW ADD PC129 & PC130 RF tema require
PVT P35-1.05VSP/1.8VP PR101 & PR109 chnage to 2.20hm EMI team require
PVT P37-+CPU_CORE PR138 change to 2.2 ohm EMI tema require
PVT P35-1.05VSP/1.8VP ADD PC128 & PC127& PC125 & PC126 RF team require
PVT P33-CHARGER add PQ9 &PR51&PQ12&PQ13 Design change
PVT P33-CHARGER Change PR74 & Delete PD15 Design change
PVT P37-+CPU_CORE PR140 & PC106 reserved EMI tema require

Power PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KAVAA LA-5121P M/B 1.0
5 4 3 2 1
PIR (Product Improve Record)

KAVAA LA-5121P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------
08/12/15
(1) P15 Del C7 with 220U For layout placement limit
D
(2) P16 Change Net name R182.1 from +RTCBATT to +RTCVCC D
Change Net name R185.1 from +RTCBATT to +RTCVCC
Del C210 with 0.1uf
(3) P18 Change Net name C244 from +RTCBATT to +RTCVCC
(4) P28 Reversal KB Pin define For KB pin define difference from PCB Foorprint
08/12/11
(1) P25 Change Card Reader Function "3IN1" to "2IN1" For Cost down
(2) P26 Link Net name TS_STOP from U29.85 to JTS.4 For Touch Screen
Link Net name TS_RES from U29.86 to JTS.5 For Touch Screen
08/12/10
(1) P25 Change Card Reader Footprint T-SOL_143-1400303600_21P_NR-T
(2) P28 Change KB Matrix from 30 pin to 34 pin
(3) P29 Add D40,D41 for Key board F10/F11 function
08/12/09
(1) P12 Reserve C472~C478 with 47P for WWLAN request
(2) P19 Reserve C479~C481 with 47P for WWLAN request
(3) P28 Reserve R399,Q32 for test for cost down plan
08/12/05
C
(1) P13 Reserve R468,R469 with 680pF for EMI request C
(2) P20 Reserve L10,L11,L12 Commom choke for EMI request for EMI request
(3) P21 Reserve L13,L14 Commom choke for EMI request for EMI request
(4) P22 Add PJ19 and link to +5VS for Cost Down Plan
(5) P22 Reserve RA31,RA37,CA34,CA42 for EMI request for EMI request
(6) P22 Reserve RA4 with 0 ohm for EMI request for EMI request
(7) P28 Reserve R396,Q31,C471,D39 for test for cost down plan
08/12/04
(1) P17 Change BT_RST# from GPIO37/SATA3GP to GPIO21/SATA0GP for SW recommend
(2) P17 Link R204.1 to GPIO37/SATA3GP for SW recommend
(3) P26 Change package R749 from 0603 to 0402 for layout placement limit
(4) P13 Change LVDS footprint to "ACES_87213-2000G_20P" for ME request
(5) P21 Change TOUCH SCREEN CONN. footprint to "ACES_87213-0600G_6P" for ME request
08/12/01
(1) 13 Change L4,L5 from Bead to 0ohm
(2) 14 Change R151,R152 from 2.2K to 4.7K
(3) 14 Change R153,R154 form 2.2k to 4.7K
(4) 17 Change power sourse +3VALW to +3V_SB
(5) 18 Add R385 with 0ohm
(6) 18 Change R226 from STAR@ to @
B
(6) 19 Change R229 from WINMAX@ to ALWAY B
(7) 19 Change C265~C270 form GPS@ to 3GGPS@
(8) 19 Add R378~R381 with Oohm for touch screen select
(9) 20 Add D37,D38 ESD diode to USB D+/- port0,2
(10) 21 Add Touch screen conn.
(11) 23 Del RA31,RA32 with 0ohm
(12) 25 Del RC21 with 0ohm
(13) 25 Del QC1 with 2N7002
(14) 25 Change net name CR_LED to CR_LED#
(15) 26 Del ROM Circuit of reserve
(16) 28 Del R368 with 300ohm
(17) 28 Add R382~384 with 300ohm
(18) 29 Change Q14A form SOT363 to SOT23
(19) 30 Change R355 from 1k to 3.3k
(20) 30 Change C451 with 0.1uf and link to +3VALW
(21) 30 Change R353.2 link from +5VALW to +3VALW
(22) 30 Change Q14B,Q9 form SOT363 to SOT23
A A

ISPD
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1

REVISION CHANGE: 0.1

---------------------------------------------------------------------------------------------------------------------
08/12/30
(1) P30 Mount R361 with 100K ohm For SUSP pull high
08/12/26
D
N0 PAGE MODIFICATION LIST PURPOSE D
(1) P29 Add U1(SA000036K00)forN280 CPU
08/12/25
(1) P27 Del R398 with 0 ohm and U32.10 link to GND For customer recommend
(2) P31 Change H3 link to GNDA For EMI request
08/12/24
N0 PAGE MODIFICATION LIST PURPOSE
(1) P27 Change U32.7 link to +3VS_HDP
Change U32.9 no connect
08/12/23
(1) P16 Add U15A.AF7 and U15A.AE7 link to GND The unused STAT port RX signals must be properly tied to ground
08/12/22
(1) P15 Change C203.1 Net name from PLTRST#_R to PLTRST#
(2) P12 Reserve C868 with 10P For Custome request
(3) P13 Reserve C871 with 10P For Custome request
(4) P25 Reserve RC21 with 10 ohm and CC16 with 10P For Custome request
08/12/21
(1) P16 Change C209 Package from 0603 to 0402 For layout pacement limit
(2) P18 Change C222 Package from 0603 to 0402 For layout pacement limit
Change C219 Package from 0603 to 0402 For layout pacement limit
(3) P25 Mount RC20 with 0 ohm For CLK 48Mhz
C C
08/12/18
(1) P4 Reserve C484~C495 with 180p For debug
(2) P6 Add R403~R405 with 1K ohm For CPU CLK link to NB
(3) P10 Change package C61,C62,C68,C78,C79 from 0603 to 0402 For layout pacement limit
Change package C74,C75 from D2 to B2 For layout pacement limit
(4) p11 Del C124 with 2.2U
(5) P12 Del R85,R87,R88,R89,R92,R94,R95,R96,R102,R105,R106,R109 For CPU BSELE0~2 link to CLK Gen
Change R90,R91 from 33 ohm to 22 ohm For damping resistor when loading is two device
Chagne net name FSB to CPU_BSEL1 For CPU link to CLK Gen
Del R110,R111 with 10K ohm For UMA platform not need to reserve
(6) P13 Change Net name R117.1 from +3V_SB to +3VS For layout pacement
Change C183 link from GND to +3VS For layout pacement
Change JLVDS pin2 from +LEDVDD to +LCDVDD_L For LCD power consumption
(7) P14 Change C190~195 to 2.2P For EMI request
(8) P15 Change package to 8P4R with 8.2K For layout pacement limit
Dell U16,R180,C206
(9) P16 Del R190 with 8.2Kohm For customer request
Change R189 from 4.7K to 10K ohm
Change Net name from IDE_DIORDY to IDE_DIORDY_IRQ
(10) P17 Change R216 from 100K to 330K ohm For ACIN issue
Add R215,R406,Q31,R408,D43,R409 For leakage current of RSMRST# Circuit
Add R410,D44 For EC leakage current to SB
(11) P18 Add R496 with 0.1U For soft start
B
(12) P18 Add L15 with MBK1608121YZF_0603 For Ripple B
(13) P20 Change C455,C458,C222 from D2 to B2 with 220U For layout placeemnt limit
Change U21.4 from USB_EN# to USB_CHG_EN# For customer request
Add U21.5 link to U29.74
(14) P21 Dell Q17 with 2N7002 For cost down
Change R237.1 from +5VS to +3VS
Chagne C294.2 from GND to +3VS
(15) P22 Reserve PJ19
(16) P24 Dell CL6 with 10U
Change UL3 from HD-024A to NS681680 For cost down
(17) P25 Reserve CC9,CC12,YC1
Mount RC19 for 48Mhz
Mount RC20 For 48Mhz
(18) P26 Del R304 with 10K ohm
Change R307 from 100K to 330K ohm
R243 please close to EC
Add Net Name USB_CHG_EN#
Del D22,R310,R311
(19) P27 Change U31 P/N from SA000030500 to SA000035U00
(20) P28 Chagne U36 ROM Size from 16M*1 to 8M*1
JBK KB Matrix the same to KSKAA
Del JP2
(21) P29 Change R370,R371,R372,R375,R383,R384,R374,R333 from 120 ohm to 220 ohm
Del R325,R326
A A
(22) p30 Add R401,R402 with 10K ohm

ISPD
Size Document Number Rev
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1

REVISION CHANGE: 0.1-->0.2

---------------------------------------------------------------------------------------------------------------------
1) 1/13 10 Change D1 to CH751H-40PT_SOD323-2 For BOM simplify
2) 1/13 18 Change D7,D8 to CH751H-40PT_SOD323-2 For BOM simplify
D
3) 1/13 23 Change net name from JLINE to JEXMIC For EXMIC JACK D
4) 1/13 23 Change net name from JEXMIC to JLINE For JLINE JACK
5) 1/13 29 Chagne JPOWER.3 net name from ON/OFFBTN# to ON/OFFBTN#_R For PWR/B can't power on with battery mode
1/13 30 Add H20,H21 For half card
6) 1/22 13 Change R117 from 47k to 100K ohm For LCD Soft start reduse inrush current
Change Q11 from SI2301BDS to A03413 For LCD Soft start reduse inrush current
Add C498 with 0.01uF For LCD Soft start reduse inrush current
7) 1/22 19 Change SW1.3 to dummy pin For Kill switch issue
Change SW1.1 to GND For Kill switch issue
8) 1/22 21 Change R238 from 10K to 47K For BT Soft start reduse inrush current
Add C499 with 0.01uF For BT Soft start reduse inrush current
9) 1/22 22 Del Net name AMP_SPK_R and AMP_SPK_L For Mono SPK
Add Net name AMP_SPK from UA2.37 to UA3.17 For Mono SPK
23 Del CA32 with 0.033UF For Codec output less than 0.9V
Add RA38,RA40 with 1K ohm For Codec output less than 0.9V
Add RA39,RA41 with 9.09k ohm For Codec output less than 0.9V
Add CA43 with 1uf For Codec output less than 0.9V
1/22 27 Change U34 P/N from SA00000XZ50 to SA000037Y60 For G-sensor controller chip change
29 JTOUCH pin define reversal For ME request assembly easy
30 Change R355 from 3.3K to 47K For LAN Soft start reduse inrush current
Add C500 with 0.01uf For LAN Soft start reduse inrush current
10) 2/3 14 Reserve C504 with 0.1uf For EMI request
C
2/3 19 Add R411 with 0 ohm Del Kill switch function C
2/3 Reserve SW1,RM1,U17,C264 for del kill switch function Del kill switch function
2/3 20 Change D15,D38,D37 from PRTR5V0U2X to CM1293A-04SO For EMI request
2/3 23 Change DA3,DA6,DA7 from PJDLC05 to PACDN042Y3R For EMI request
2/3 28 Add C501,C502 with 330pf For EMI request
Add C503 with 470pf For EMI request
Add R412 with 10 ohm For EMI request
Add C508 with 6pf For EMI request
2/3 29 Add R413,R414,R415 with 0 ohm For EMI request
Reserve C505,C506,C507 with 0.1uf For EMI request
Change D27 from PJDLC05 to PACDN042Y3R For EMI request
Del D25 with PJDLC05 For EMI request
Change R375 from 220 to 300 ohm For White LED of PWR/B
Change R375.1 Net name from +3VALW to +5VALW For White LED of PWR/B
11) 2/4 22 Change CA14 from 100pf to 0.1uf For SPK noise issue
Add PJ20,PJ21 For customer request(Echo Peak Issue)
24 Change UL3 from 16pin(SP050003N00) to 24pin(SP050003P00) For EMI issue
12) 2/5 06 Add R416 with 0 ohm For WWLAN request
Reserve C511 with 22pf For WWLAN request
12 Reserve C509,C510 with 10p For WWLAN request
22 Reserve UA1,CA9,CA11 For cost down plan
2/6 Modify JUSBA,JUSBB,JUSBC Symbol for GND pad For GND pin
B
10 Reserve C67 with 220uF For Cost down plan B
Add C514 with 0.1uF For ESD team request
23 Change RA38,RA40 with 2K ohm For Codec output less than 0.9V
Change RA39,RA41 with 8.2K ohm For Codec output less than 0.9V
24 Change UL3 from NS681680(SP050003N00)to 8456E(SP050005V00)For ESD fail issue
30 Reserve +1.5VS,+1.05VS,+0.9VS,+1.8VS discharge circuit For Cost down plan
27 Reserve C867 with 0.22uf For U33.4 NC pin
Change U33 from APL5151-33BC to G9191-330T1U For power sequence issues on HPC
2/9 20 Change C455,C288 from 220uf to 150uf
Reserve C458 with 150uf For Cost down plan
2/11 22 Mount RA13 with 0 ohm For EMI requet open channel
27 Change U31 from SA000035U00 to SA000039900 For Customer request version change
2/16 14 Mount C504 with 0.1uF For EMI request
23 Mount DA3/DA6 with PACDN042Y3R For EMI request
17 Reserve C217,C218 with 0.1uF For Reserve WWAN PCIE interface
A A

ISPD
1.0
KAVAA LA-5121P M/B
5 4 3 2 1
5 4 3 2 1

REVISION CHANGE: 0.2-->1.0

---------------------------------------------------------------------------------------------------------------------
1) 2/25 4 Mount C484~C495 with 220pF For EMI request
2) 2/25 6 Change Net name from ICH_POK to ICH_PWROK For correcting power down sequence
D
3) 2/25 12 Change R81,R82 from 0 ohm to FBMH1608HM601-T_0603 For WWAN request D
Mount C133,C141 with 47pF For WWAN request
Mount C142,C143,C144,C145,C146,C868 with 22pF For WWAN request
4) 2/25 13 Mount C871 with 10pF For WWAN request
5) 2/25 15 Mount C203,C204 with 0.1uF For WWAN request
6) 2/25 17 Change Net name from ICH_POK to ICH_PWROK For correcting power down sequence
Add R418 with 10K ohm For correcting power down sequence
Add U37 with TC7SHO8FUF_SSOP5(SA007080100) For correcting power down sequence
Reserve R417 with 0 ohm For correcting power down sequence
7) 2/25 19 Mount C479,C480,C481,C482 with 47pF For WWAN request
8) 2/25 22 Mount RA31 with 22 ohm,CA34 with 10pF For WWAN request
9) 2/25 23 Change JEXMIC,JLINE PCB footprint to JA6033L-B3T4-7F_6P-TFor ME request
10) 2/25 25 Mount CC16 with 10pf,RC21 with 10 ohm For WWAN request
11) 2/25 26 Change U29.104 net name from ICH_POK to EC_PWROK For correcting power down sequence
12) 2/25 28 Mount C508 with 33pF,R412 with 33 ohm For WWAN request
13) 2/25 30 Reserve R349 with 200K ohm For design change
Change C447 from 0.01uf to 0.022uF For design change
Change R346 from 20K to 47K ohm For design change
14) 3/2 14 Change D5 from SC1B491D000 to SCS00002000 For buyer recommend
28 Change Change U36 to MX25L8005M2C(SA00000XT00) For CLK frequency 75MHz
3/2 30 Change H18 from H_3P0N to H_2P6N For ME request
H19 from H_6P0X3P0N to H_6P0X2P6N For ME reqeust
C
3/4 08 Add GMCH_INVT_PWM on U3.H30 For support DPST function C
13 Add R419 with 0 ohm For support DPST function
Reserve R420 with 0 ohm For support DPST function
Del JLVDS pin 2 for dummy pin For prevent short B+
23 Mount DA5 with PJDLC05 For EMI request
23 Reserve DA6 with PJDLC05 For EMI reqeust
20 Add C515,C516 with 470pF For EMI request
28 Mount C414~C437,C461 with 100pF For EMI request
17 Add R421 with 330K ohm to +3VALW For USB over current protect
17 Add D45 with CH751H-40PT to USB_OC#0_2 For USB over current protect
17 Change RP7.4 from USB_OC#0_2 to USB_OC#0_2_D For USB over current protect
17 Change U15.D3 from USB_OC#0_2 to USB_OC#0_2_D For USB over current protect
26 Add Net name to USB_OC#0_2 For USB over current protect
29 Change R413,R414,R415 from 0 ohm to FBMA-10-100505-151T For EMI request
30 Add C517~C520 with 0.1uF For ESD request
3/5 12 Reserve R427 with 0 ohm For Silego source chip
Add R428 with 10K ohm to +3VS For Silego source chip
Change U4.54 from H_STP_PCI# to H_STP_PCI#_R For Silego source chip
3/5 17 Add R423,R424 with 0 ohm For design change
Reserve R410,R421 with 330 K ohm For design change
Reserve D44,D45 with CH751H-40PT For design change
19 Add R425,R426 with 0 ohm For debug
B
30 Reserve R422 with 0 ohm and PJ22 with JUMP_43X79 For EMI request B
30 Change H15 to Non-PTH hole For design change
3/10 17 Change R214.2,U15.F20 from ICH_PCIE_WAKE# to EC_SWI# For wakeup LAN function
30 Add EC_SWI# and link to both U29.103 to U15.F20 For wakeup LAN function
3/10 22 Change CA18 from 10uF to 0.1uF For Audio noise
A A

ISPD
1.0
KAVAA LA-5121P M/B
5 4 3 2 1

Toshiba Mini NB205

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

CRT Conn. Intel Calistoga GSE

LED Conn. LVDS

PCIeMini Card PCIeMini Card USB port 0,2,7 USB port 1

USB page 15,16,17,18

Debug Port ENE KB926 D3

Security Classification Compal Secret Data Compal Electronics, Inc.

EC SM Bus1 address EC SM Bus2 address

ICH7M SM Bus address

Clock Generator 1101 001Xb

Security Classification Compal Secret Data Compal Electronics, Inc.

C H_A#34 A[33]# THRMDA H _THERMDC H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 C

H_N MI LINT0 EXTBGREF DPRSTP# H_DPSLP#

NC2 RSVD2 <6,12> CPU_BSEL0 BSEL[0] CORE_DET

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z

PLACE IN CORRIDOR AND CLOSE TO CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

<4> H_D#[0..63] H_A#[3..31] <4>

H_D#_36 H_BPRI# H_BPRI# <4> SM_OCDCOMP_1 PM_ICHSYNC# MCH_ICH_SYNC# <15>

H_D#60 AB1 H_D#_60

H_D#63 AB5 B4 H_HITM#

QG82945GSE SLB2R A3_FCBGA998

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR2 SYSTEM MEMORY

QG82945GSE SLB2R A3_FCBGA998

Security Classification Compal Secret Data Compal Electronics, Inc.

<14> GMCH_CRT_CLK H20 CRT_DDC_CLK SDVO_TVCLKIN M30

QG82945GSE SLB2R A3_FCBGA998

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

2940mA U3D 144mA

+1.5VS AD28 AM24

close pin C29/D29 close pin B31

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_A_D35 137 138

DDR_A_D41 143 144

33_0402_5% 1 2 R103 CLK_PCI_DDR_R 13 CLK_PCIE_LAN

1 = Pin24/25 : SRC_0 / SRC_0# 26 41 W WAN_CLKREQ#

LCD POWER CIRCUIT

2/25 PVT:Mount C871 with 10pF

Security Classification Compal Secret Data Compal Electronics, Inc.

Place closed to conn.

Place closed to conn. 0.1U_0402_16V4Z

2 4 CRT_HSYNC_1 R149 1 2 39_0402_5% H S YN C

SN74AHCT1G125DCKR_SC70-5 CRT_ VSYNC_1 R150 1 2 39_0402_5% V S YN C

SN74AHCT1G125DCKR_SC70-5 3/02 PVT:Change D5 from SC1B491D000 to SCS00002000.

R151 R152 JCRT

Security Classification Compal Secret Data Compal Electronics, Inc.

12/18 Change package to 8P4R with 8.2K

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

+3VS +3V_SB +3V_SB

DIRECT MEDIA INTERFACE

SPI_CS# USBP2P USB20_P2 <20>

1/13 DVT:Change D7 P/N to SC1H751H010 U15F +1.05VS U15E

+ICH_V5REF_SUS D28,T28,AD28. Vcc1_5_B[13] Vcc1_05[19] VSS[19] VSS[117]

Vcc1_5_B[29] Vcc3_3[8] VSS[36] VSS[133]

AC7 L3 M16 AD23

C250 F17 N13 AF4

1 AC10 AB8 1 2 N16 AF27

Security Classification Compal Secret Data Compal Electronics, Inc.

Mini-Express Card for WLAN/WiMax