|| Volume 2 || Issue 5 || 2017 || ISSN (Online) 2456-3293

MULTILEVEL INVERTER WITH POWER QUALITY ANALYZER

Malik Muhammad Zaid1, Muhammad Umair Aslam2, Sajjad Ahmed3, Muhammad Usama Malik4
Graduate Student, Electrical Engineering, University of Engineering and Technology, Lahore, Pakistan. 1
P.G. Student, Electrical Engineering, University of Engineering and Technology, Lahore, Pakistan. 2
P.G. Student, Electrical Engineering, University of Engineering and Technology, Taxila, Pakistan. 3
Instructor Electrical, Electrical Engineering, Technical Education & Vocational Training Authority (TEVTA),Jhelum, Pakistan.4
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Abstract: This paper is based on grid tied multilevel inverter with power quality monitoring and analysis. In this, a switch
ladder multilevel inverter (SLMLI) topology is used to develop a 17-level inverter. This inverter produces a low distortion
output voltage and attenuates the dv/dt stresses. It resolves the electromagnetic compatibility (EMC) contentions [1]. The
SLMLI topology abates the distortion to such a low level as requisite by the WAPDA for grid connectivity. The overall grid
connectivity of the inverter is restrained automatically by the NI myRIO-1900 FPGA and microcontroller.
The PQ analyzer can measure the voltage (RMS), current (RMS), real power (P), reactive power (Q), apparent power (S),
power factor, crest factor (CF), voltage dips-swells and total harmonic distortion (THD) of current and voltage using national
instruments (NI) LABVIEW GUI.
Keywords: multilevel inverter; LabVIEW; power quality monitoring system; graphical user interface.
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I INTRODUCTION sources cascaded multilevel inverters were developed. In
which clamping diode and flying capacitors were not used [4-
The technology of multilevel inverter is an appropriate 6]. The main advantage of cascaded multilevel inverter is the
replacement for the areas which demand high power voltage absence of voltage imbalance. In cascaded multilevel
control. In practical of power inverters, the output voltage is a inverter, imperceptible numbers of components are used as
mixture of rectangular waveforms but ideally, it is a pure compared to other two topologies. Instead of most of the
sinusoidal. The main problems which power inverters have to research work is done in the configuration of the multilevel
face are to develop such modulation methods to normalize inverter, new trends are still introduced in the transformation
the output rectangular waveforms. The term multilevel of multilevel inverters. A 7-level inverter was made by
inverter was introduced many years ago. Applications where making modification in multilevel inverter structure using 9
medium to high voltage is required, the multilevel inverter switches by removing 3 switches from the structure of
are used. For example, in blowers, renewable sources, cascaded multilevel inverters [7]. It gives desired 7-level
industrial drives, and conveyors such as gears and shafts. In output with low total harmonic distortion (THD). From the
multilevel inverter using small voltage step helps inverters to cascaded multilevel inverters topology having 9 switches, by
withstand better voltage, less switching losses and switch reducing 2 more switches a 7-level inverter having 7 switches
ratings, fewer harmonics with good power quality and high was generated which was a good renovation in the switch
electromagnetic compatibility [3]. In the beginning cascaded reduction [8]. Later, to gain a 7-level output another topology
multilevel inverters were introduced. After which diode- was designed which consists of 4 dc sources and 6 switches
clamped multilevel inverters were invented and then flying [9]. In the following topology, the greater success is that the
capacitor multilevel inverters. To achieve the required output THD factor is low, and fewer gate circuits are used.
following topologies using different techniques and II PROPOSED TOPOLOY OF INVERTER
mechanisms. In cascaded multilevel inverters to achieve a
The 17-level switch ladder multilevel inverter
required output, H-bridge is used which are connecting in
(SLMLI) is implemented to get an approximate sinusoidal
series whereas in diode clamped multilevel inverter series
output voltage waveform [10]. The single-phase topology of
capacitor banks are used instead of H-bridge. In the third
this inverter is shown in Figure 1. It uses at least 10 switches
topology for clamping of the output voltage, floating
and 6 power supplies for single phase implementation.
capacitors are used [3]. As H-bridge inverters possess
Supplies V1 and V2 are of same value whereas V3 and V4
isolation transformers so for the separation of DC input

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also have the same value. The output voltage cycle contains
all the possible combinations of supplies which gives a very
high value of output voltage as compared to applied dc
voltage of supplies.
Figure 1 17-Level inverter topology.
The gate driver circuit for single phase inverter has
been made that includes 6 independent power supplies with
an output voltage of 15V and 8 optoisolators to drive the
MOSFETs. Opto-isolators are used to isolate the
microcontroller from the gate terminals of high power
MOSFETs. Figure 2 shows the PCB circuit of gate driver
circuit.
Figure 2 Gate driver circuit
The single-phase topology uses two bi-directional
and six unidirectional switches. Although every bi-directional
switch contains two MOSFETs but only one power supply is
needed to drive the gate of a bidirectional switch. All the
other switches which have their source terminals common
also need a single supply for their gate. All the MOSFETs
contain a diode in an antiparallel direction which provides a
freewheeling path in case of a highly inductive load. A delay
between the switching pulses is also considered. A switching
pattern in which all the MOSFETS are off cannot be applied
to the inverter because there will no path of current and a
severe voltage may be established across the load which can
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ISSN (Online) 2456-3293
be dangerous for the switches as well as load. The switching
scheme of pulses is developed using a state machine in the
microcontroller. A switching pattern for a complete
sinusoidal supply cycle is shown in Table 1.
The topology given in Figure 1 is simulated on
MATLAB Simulink using constant PWM technique. Figure 3
shows the results obtained from simulation of the 17-level
topology of Figure 1. V1 = V2 = 25 V and V3 = V4 = 75 V is
applied to the inverter which gives a maximum peak value of
200 V at the output. A three phase 17-level inverter can be
developed by repeating the topology of Figure 1 three times.
The three-phase inverter uses a total of 30 switches. There are
only 18 power supplies required for the gate driver circuit.
Table 1 Switching Pattern of Developed topology
Figure 3 Simulated result of 17-level inverter
III LOW COST POWER QUALITY ANALYZER
To fulfil customers requirements power quality is
one of the dominant factor which is considered by utilities.
With the passage of time consumers needs become more
critical and at the same time, this power quality problem
shifts into a serious issue. So, it becomes important to
develop such monitoring system for power quality which is
used to check power quality disturbance [2]. NI LabVIEW
and NI myRIO is used as a simulating tool and for
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programming of FPGA. In this graphical block diagrams are electrical device under test. In the second implementation
used by the programmer to connect different function nodes method, a running average is computed for all the power
by drawing wires between the blocks. A user-friendly quality parameters. That running average updates every 1.5
graphical user interface (GUI) is implemented which helps to seconds on the GUI. Values computed by both methods of a
analyse certain power parameters. The analyser can measure particular parameter have been placed on two different tabs
voltage (RMS), current (RMS), real power (P), reactive by using a tab control on the GUI. A user can switch between
power (Q), apparent power (S), power factor (cos ), crest the two tabs to observe the various power quality parameters
factor (CF), voltage dips-swells and total harmonic distortion values. The right side of Figure 5 shows the instantaneous
(THD) of current and voltage using national instruments (NI) values of all the power quality parameters whereas the
LABVIEW. Figure 4 shows the PCB circuit of data average values GUI tab is shown in Figure 6.
acquisition card that includes voltage and current sensors
used for the data acquisition of a given electrical device. Hall
Effect current sensors Tamura L18P***D15 series are used
along with the current transformers (CTs) to measures the
current of a particular load for its quality monitoring. For a
high current measurement, CTs are used to measure the
current whereas small current measurement can be taken
using only current sensors without CTs. Potential
transformers (PTs) are used to acquire the voltage data of the
system to calculate the power quality parameters.

Figure 6 Average measurements of power quality

parameters
LabVIEW platform contains two panels: a front
panel and block diagram. The front panel contains the GUI
which displays all the power quality parameters. The block
diagram comprises of all the back end programming in the
form of blocks which is called G-code (graphical
programming). Figure 7 shows a portion of the block diagram
Figure 4 Data acquisition card
G-code.
The results are compared with FLUKE-435 which is
an industrial grade analyser. The error is as low as 1% but the
cost is almost ten times less as compared to the FLUKE-435.
Figure 5 shows a comparison between FLUKE-435 and
developed analyser for a CFL and a fluorescent lamp.

Figure 5 Comparisons of Results Figure 7 G-code portion of block diagram

Two methods are used to calculate the power quality REFERENCES
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of all the power quality parameters are calculated from the
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real time data that is acquired from a given electrical device.
eprints.uthm.edu.my/1729/1/farrah_salwani.pdf
Those values show the manipulation of live data from an

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