Lecture 23: Oxidation

Contents
1 Introduction 1

2 Oxidation types 2

3 Oxide growth model and parameters 4

4 Oxide furnaces 12

5 Thermal nitridation 17

1 Introduction
Oxidation refers to the conversion of the silicon wafer to silicon oxide (SiO2
or more generally SiOx ). The ability of Si to form an oxide layer is very
important since this is one of the reasons for choosing Si over Ge. The Horni
transistor design, which was used in the first integrated circuit by Robert
Noyce, was made of Si and the formation of SiOx helped in fabricating a
planar device.
Si exposed to ambient conditions has a native oxide on its surface. The
native oxide is approximately 3 nm thick at room temperature. But this is
too thin for most applications and hence a thicker oxide needs to be grown.
This is done by consuming the underlying Si to form SiOx . This is a grown
layer. It is also possible to grow SiOx by a chemical vapor deposition process
using Si and O precursor molecules. In this case, the underlying Si in the
wafer is not consumed. This is called a deposited layer.
SiOx helps in protecting the wafer from contamination, both physical and
chemical. Thus, it acts as a passivating layer. The oxide layer protects
the wafer surface from scratches and it also prevents dust from interacting
with the wafer surface, and thus minimizes contamination. The oxide layer
also protects the wafer from chemical impurities, mainly electrically active

1
 MM5017: Electronic materials, devices, and fabrication

Table 1: Silicon oxide thickness chart

Thickness, in A Application
60-100 Tunneling gates
150-500 Gate oxides, capacitor dielectrics
200-500 LOCOS pad oxide
2000-5000 Hard masks, surface passivation
3000-10000 Field oxides

contaminants. SiOx acts as a hard mask for doping and as an etch stop during
patterning. The original gate oxide in MOSFET was made of SiOx . SiOx
was also used as the inter-layer dielectric separating different metallization
layers, though this is usually a deposited layer. SiO2 is also used to prevent
induced charge due to the metal layers, this is called a field oxide. In all of
these forms, different thickness of the oxide layer are required. These are
summarized in table 1.

2 Oxidation types
In the case of grown oxide layers, there are two main growth mechanisms

1. Dry oxidation Si reacts with O2 to form SiO2 .

Si (s) + O2 (g) SiO2 (s) (1)

2. Wet oxidation Si reacts with water (steam) to form SiO2 .

Si (s) + 2H2 O (g) SiO2 (s) + 2H2 (g) (2)

In both cases, Si is supplied by the underlying wafer. Dry and wet oxidation
need high temperature (900 - 1200 C) for growth, though the kinetics are
different, which is why this process is called thermal oxidation. Since the
underlying Si is consumed, the Si/SiO2 interface moves deeper into the wafer.
The movement of the interface is shown in figure 1.
There is also a volume expansion since the densities of the oxide layer and
silicon are different. Thus, the final thickness is higher than the initial Si
thickness. Consider the oxide layer silicon interface as shown in figure 2.
Here, d is the thickness of the original Si layer that has been consumed in
forming the oxide layer of thickness d0 . Si has a density of 2.33 gcm3 (Si )
and an atomic weight of 28.08 gmol1 (ZSi ) while SiO2 has a density of 2.65
gcm3 (SiO2 ) and a molecular weight of 60.08 gmol1 (ZSiO2 ). Given that

2
 MM5017: Electronic materials, devices, and fabrication

Figure 1: Movement of the silicon-oxide interface as oxide thickness grows.

The original thickness of the wafer is marked by dotted lines. The oxide
has a higher density, which is why the overall thickness is higher. Adapted
from Fundamentals of semiconductor manufacturing and process control -
May and Spanos.

Figure 2: Schematic cross section of the Si oxide interface showing the oxide
thickness, d0 , and the thickness of Si consumed, d, to form the oxide. The
ratio of the thicknesses is inversely proportional to the densities and directly
proportional to the atomic/molecular weights.

3
 MM5017: Electronic materials, devices, and fabrication

Figure 3: A one dimensional growth model for oxide formation with the
fluxes and concentrations marked. There is a certain concentration of the
diffusing species, oxygen or steam, in the gas phase, and it is in equilibrium
with the concentration in the oxide layer and the oxide-silicon interface.

the cross section area, A, is the same it is possible to use the law of molar
conservancy to derive the relation between d and d0 . This is given by

dASi d0 ASiO2
= (3)
ZSi ZSiO2

Substituting the values in equation 3 gives the relation

d0 = 1.88 d (4)

Hence, the thickness of the oxide layer is larger than the thickness of the Si
that is consumed to form that oxide. To grow 100 nm of oxide, per equation
3, 53.2 nm of Si needs to be consumed.

3 Oxide growth model and parameters

Consider the oxide growth model shown in figure 3, which depicts an inter-
mediate stage in the growth process. There is an oxide layer of a certain
thickness, d0 , already formed on the semiconductor. There are also oxidizing
species present in the gas phase, which can cause further growth of the oxide
layer. There are three fluxes present in the system.

4
 MM5017: Electronic materials, devices, and fabrication

1. Flux, F1 , corresponds to the transport of oxidizing species from the

bulk of the gas phase to the surface of the oxide layer, i.e. oxide-gas
interface.

2. Flux, F2 , corresponds to the transport of the oxidizing species through

the oxide layer to the oxide-Si interface. For simplicity it can be as-
sumed that there is no dissociation of the oxidizing species within the
oxide layer.

3. Flux, F3 , corresponds to the reaction of the oxidizing species with Si,

to form a new oxide layer.

When the system is in steady state, all fluxes must balance

F1 = F2 = F3 (5)

Consider transport through the gas phase. This flux, F1 , can be written in
terms of concentration as

F1 = hG (CG CS ) (6)

where hG is the mass transfer coefficient in the gas phase and CG and CS are
concentrations in the bulk of the gas phase and at the oxide/gas interface,
see figure 3. This can also be rewritten in terms of the concentration of the
oxidizing species within the oxide layer as

F1 = h (C C0 ) (7)

where h is related to hc by
hG
h = (8)
HkB T
where H is the Henrys law constant and T is the temperature. C is the
equilibrium bulk concentration of the oxidizing species within the oxide (no
dissociation) and C0 is the concentration of the oxidizing species at the sur-
face.
The flux of the oxidizing species within the oxide layer, F2 , is given by

D (C0 Ci )
F2 = (9)
d0
where D is the diffusion coefficient and C0 and Ci are the concentrations of
the oxide species at the oxide surface and oxide-Si interface, respectively. d0

5
 MM5017: Electronic materials, devices, and fabrication

is the thickness of the oxide layer at a particular time, see figure 3. The
diffusion coefficient is given by an Arrhenius type expression
Ea
D = D0 exp( ) (10)
kB T
where Ea is the activation energy and D0 is the pre-exponent factor. These
values depend on the oxidizing species and the Si planes through which dif-
fusion is happening, typically i.e. (100) or (111).
The last flux term, F3 , refers to the reaction of the oxidizing species with Si
to form the oxide. This can be written as

F3 = ks Ci (11)

where ks is the rate constant for the conversion of Si to SiO2 and Ci , defined
above, is the interface concentration. In steady state, all three fluxes are
equal, see equation 5, and this can be used to calculate expressions for Ci
and C0 .
It is possible to write a general equation for the growth of an oxide layer
(with a starting oxide layer)

d20 + Ad0 = B (t + ) (12)

where d0 is the thickness of the oxide layer at time t. A, B, and are

constants that are given by
1 1
A = 2D [ + ]
ks h
2DC
B = (13)
N1
d2i + Adi
=
B
where di is the initial oxide thickness (at t = 0). The values of A and B and
hence depend on the type of oxidation (wet or dry) and also the Si surface
plane i.e. (100) or (111). This data is summarized in figure 4. Equation 12
is a second order quadratic equation and the general solution can be written
as
d0 t + 1/2
= [1 + 2 ] 1 (14)
A/2 A /4B
While the general equation can be solved it is more instructive to consider
two limiting cases.

6
 MM5017: Electronic materials, devices, and fabrication

Figure 4: Linear rate constants, A and B, for different types of oxide, as a

function of temperature. The activation energies for wet and dry oxidation
are similar but the oxidation rate for wet ox is higher than dry ox. Adapted
from VLSI fabrication principles - S.K. Ghandhi

7
 MM5017: Electronic materials, devices, and fabrication

Figure 5: Rate constant, B, for thick oxide growth. The activation energy
for steam is lower than dry oxygen. This is related due to the difference
in diffusing species for the two systems. Adapted from VLSI fabrication
principles - S.K. Ghandhi

1. In the diffusion limited case, the supply of the oxidizing species to

the Si-SiO2 interface is the rate limiting step. This determines the
growth rate of the oxide layer. The diffusion limiting case occurs when
there is a thick oxide layer, or at long oxidation time i.e. t  .
When t  and t  A2 /4B, equation 14 reduces to

d20 = Bt (15)

This is a parabolic rate law, which predicts that as the oxide thickness
increases, the time increases as the square of the thickness. The rate
constant, B, as a function of temperature is shown in figure 5.

2. When D is large or when the oxide thickness is small, growth is con-

trolled by the formation of the oxide layer, reaction controlled case.
For short oxidation times (or thin oxides) (t + )  A2 /4B. This

8
 MM5017: Electronic materials, devices, and fabrication

Figure 6: Thin oxide growth rate for Si (100) at different temperatures,

showing a near linear dependence of oxide thickness on growth time. Adapted
from VLSI fabrication principles - S.K. Ghandhi.

means that equation 12 can be simplified to (ignoring the term d20 )

B
d0 = (t + ) (16)
A
This is a linear rate law, so that for thin oxides, the thickness increases
linearly with time. This is shown in figure 6.
To better understand the different growth regimes, consider dry oxidation
(using O2 gas) at a temperature of 1000 C. For Si(100), the value of B is
0.017 m2 /hr. To grow an oxide layer of thickness (d0 ) 100 nm (thick oxide),
using the parabolic rate law, equation 15, gives a growth time of 51 min. To
grow 200 nm, the corresponding time is 3 hr and 25 min, since the time
increases as the square of the thickness. Thus, to grow thick oxides using dry
oxidation, temperature should be increased, to have a higher D and hence
B. The oxide thickness as a function of time for dry ox is shown in figure 7.
Instead of dry oxidation, consider wet oxidation under the same tempera-
ture, 1000 C. The value of B for wet ox is 0.287 m2 /hr. Using the same
parabolic rate law, equation 15, the time to grow 100 nm is only 2 min while
for 200 nm time is 8 min. These times are much smaller than dry ox, but
2 min is too short a growth time to obtain uniformity across the wafer, i.e.
process control will be difficult. Also, electrical properties of the silicon oxide
grown by wet oxide are different from that grown by dry oxide. The oxide
thickness vs. time for wet ox is shown in figure 8.
Oxide growth rate is also affected by the dopant concentration. Heavily
doped Si oxidizes at a faster rate than lightly doped Si. Since the oxide

9
 MM5017: Electronic materials, devices, and fabrication

Figure 7: Oxide thickness for (a) Si (100) and (b) Si (111) at different tem-
peratures for dry oxidation. The scale is logarithmic in both axes. Typically,
for thick oxides dry oxidation is not preferred since the rate constant B is
small compared to wet oxidation, see figure 4. Adapted from VLSI fabrica-
tion principles - S.K. Ghandhi.

10
 MM5017: Electronic materials, devices, and fabrication

Figure 8: Oxide thickness for (a) Si (100) and (b) Si (111) at different tem-
peratures for wet oxidation. The scale is logarithmic for both axes. Wet
oxidation is carried out at lower temperature than dry oxidation to get uni-
form thickness. Adapted from VLSI fabrication principles - S.K. Ghandhi.

11
 MM5017: Electronic materials, devices, and fabrication

forms by consuming the underlying Si the dopant concentration in the Si

layer adjacent to the oxide layer is altered. For n-Si (P, As, Sb), as the oxide
grows, the dopants get ejected into the underlying Si. This leads to pile-up
of dopants at the interface, which will affect the electrical properties. On
the other hand, for p-Si (B), the oxide layer draws in the dopants, so that
the concentration is lowered near the interface. This has implications for
performance of devices. A pn junction fabricated in Si can have its junction
potential altered during oxide formation on its surface (for example when
patterning to make contacts or when forming inter layer dielectrics). Also,
the transport properties through the junction could be altered leading to
change in device performance. These become important considerations dur-
ing circuit design.
Thermal oxides are formed at temperatures in the range 900 - 1200 C (de-
pending on thickness and type of oxide). Most oxides grown on Si have thick-
nesses greater than 30 nm (gate oxides are replaced by high-k dielectrics).
But with scaling, thin oxides, 5 - 20 nm (or 50-200 A) are required for cer-
tain applications. Also, for oxide growth during later stages of fabrication it
might not be feasible to heat to high temperatures, since this could damage
the rest of the device (e.g. doping concentrations would get affected at high
temperatures due to diffusion). Some applications also require thin films of
oxide and nitride growth together (oxynitrides). In such cases, the growth
rate must be slow to get uniformity. This requires new growth techniques
and chemicals. Ultra thin oxides (20 nm or less) can be grown on Si by
using nitric acid at 100 C. Because of low temperature, the process can be
integrated with conventional lithography as well.

4 Oxide furnaces
Thermal oxides are grown in tube furnaces by a batch process, i.e. multiple
wafers are processed at the same time. This becomes important in the con-
text of process control, since any deviation from required conditions would
affect multiple wafers and hence lead to overall cost increase.
For small wafer sizes, typically 3 and 4 wafers, horizontal tube furnaces
are used for oxidation. A schematic of this furnace is shown in figure 9. The
furnace is typically divided into 3 zones - source zone, center zone, and load
zone. The source zone is used for introducing the gases required for oxida-
tion. Typically, this is oxygen (dry ox) or steam (wet ox) at the appropriate
partial pressure (concentration). Sometimes, chlorinated oxide layers are also
grown. The chlorine incorporated in the oxygen reduces mobile ions in the
oxide layer and also reduces charge concentration at the oxide-Si interface.

12
 MM5017: Electronic materials, devices, and fabrication

Figure 9: Schematic of (a) horizontal diffusion furnace. (b) The furnace is

typically divided into 3 zones, with the product wafers loaded in the center
zone. The zones have their individual heaters and temperature controllers,
to ensure uniform temperature. Adapted from Microchip fabrication - Peter
van Zant.

13
 MM5017: Electronic materials, devices, and fabrication

Figure 10: Schematic of a commercial horizontal diffusion furnace. The

wafers are loaded in plastic boxes called FOUPs (Front opening universal
pod). The wafers are cleaned first before loading in the furnace. In this
setup, there is no provision for storing the wafers but newer designs based on
vertical furnaces also have provision for storing multiple FOUPs. Adapted
from Microchip fabrication - Peter van Zant.

This improves cleanliness and device performance. Chlorine is introduced

in the form of Cl2 , hydrogen chloride gas (HCl), trichloroethylene (lq), or
trichloroethane (lq). Vapor from gaseous sources is mixed with the oxygen,
while for liquid sources, the gas is bubbled through the liquid. There are a
few purge and pump steps, to reduce contamination in the furnace before
oxygen is introduced. Commercial tube furnaces also have loading zones (for
loading wafers) and cleaning stations, and stations for storing wafers. A
schematic of a commercial horizontal furnace is shown in figure 10.
The process wafers (wafers that are used to fabricate the integrated cir-
cuits) are loaded in the center zone. Usually, baffle plates are loaded at the
ends (these are made of quartz). Bare wafers, called fillers, are also loaded
along with the process wafers. These help in regulating gas flow through the
furnace so that oxide growth is uniform in the process wafers. Thus, not all
wafers in the furnace are process wafers. Higher the ratio of process wafers to
blank wafers that can be loaded in the furnace, higher is the process through-
put (number of process wafers processed per hour). Temperatures are also
constantly maintained and regulated within the furnace during oxidation,
using a PID (proportional-integral-derivative) mechanism. Typical temper-
ature profile during oxidation is shown in figure 11. The idle temperature is

14
 MM5017: Electronic materials, devices, and fabrication

Figure 11: Temperature profile in a tube furnace during oxidation. The

furnace is usually maintained at elevated temperature (idle) and wafers are
loaded in this, starting at room temperature. Then temperature is increased,
held for oxidation, and cooled until the wafers can be unloaded. Adapted
from Microchip fabrication - Peter van Zant.

typically 300-400 C, to minimize heating and cooling time during the oxida-
tion process. The elevated temperature also prevents gases from condensing
on the tube inner walls.
For larger wafers (typical process wafers are now 12 or 300 mm wafers), hor-
izontal furnaces are not practical and also occupy a lot of space. Diffusion
furnaces designs are now vertical, called vertical diffusion furnaces (VDF). A
schematic of a VDF is shown in figure 12. The furnace consists of a loading
station and space for storing wafers (before and after processing). The boat
(where wafers are loaded for processing) moves vertically into the furnace, see
figure 12. VDF are more compact than horizontal furnaces. Gas flow is also
more uniform, with less turbulence. The boat is rotated during operation to
ensure uniformity of the oxide layer. This is especially true for mixed gases
since the gases move parallel to gravity and hence do not get separated. The
operation of the VDF is similar to the horizontal tube furnace. There are
also baffles and blanks, loaded along with the process wafers. Typically, a
125 wafer boat holds a maximum of 75 product wafers, the rest are fillers,
baffles, and monitor wafers (for measuring oxide thickness and uniformity for
process control).

15
 MM5017: Electronic materials, devices, and fabrication

Figure 12: Schematic of a vertical diffusion furnace. These types of furnaces

are now common due to the space constraint in a commercial fab that pro-
cesses large wafers (300 mm). They also come with storage for processing
multiple FOUPs, depending on furnace capacity. Furnaces for processing
smaller diameter wafers are still of the horizontal type. Adapted from Mi-
crochip fabrication - Peter van Zant.

16
 MM5017: Electronic materials, devices, and fabrication

Figure 13: Nitride thickness vs time for different temperatures. The rate is
smaller than oxidation since the gas has to diffuse through the nitride layer,
and that forms the rate limiting step. Adapted from Microchip fabrication -
Peter van Zant.

5 Thermal nitridation
Nitridation is the growth of silicon nitride (Si3 N4 or more generally SiNx )
by consuming the underlying Si. This is carried out by exposing Si to am-
monia gas at temperatures of around 950-1200 C (similar to temperatures
used for oxidation). Nitrogen gas is not used (unlike dry ox, which used oxy-
gen gas) since the activation energy to break the N-N bond is much higher
than energy required to break the O-O bond. Nitridation kinetics is sim-
ilar to oxidation. Figure 13 shows nitride thickness vs. time for different
temperatures. Nitride thickness is smaller than oxide (for same time and
temperature). This is because the nitride layer is denser, and diffusion of the
reaction species through the nitride layer is usually the rate limiting step,
the parabolic rate law, equation 15, can be used. Thus, growing thick nitride
layers is an issue. Nitride layers also have larger stresses than oxide and can
delaminate at higher thickness. Special low pressure processes are required to
minimize the stress. Sometimes, oxynitrides or ONO (oxide/nitride/oxide)

17
 MM5017: Electronic materials, devices, and fabrication

layers are also grown. These were originally used as gate oxides, replacing
pure silicon oxide, since they have a higher dielectric constant. These have
now been replaced by high k-dielectric materials.

18