Computer Organization Assignment-2

Shyam Shankar H R
EE15B127
August 21, 2017

Question
Aim: To implement delay subroutine with help of stack. Here, nested subroutine method is used to provide the required
delay of 5.5s. The clock frequency specified is 1Mhz. Since 2 plain nested subroutines can provide only upto a maximum
delay of about 0.9s, here a 3-level nested subroutine system has been used.

Specifications
Clock Frequency: 1MHz.
Delay: 5.5 s

Method used: Nested Subroutine

Code
jmp start

delay3: push H ;push H register to stack 12

push PSW ;push acc and flag reg to stack 12
mvi H,0FFh ;[H] = 0FFh = 255 7
loop3: dcr H ;decrement count 4
jnz loop3 ;until count is zero, repeat 10/7
pop PSW ;pop stack contents to acc & flag reg 10
pop H ;pop stack contents to H reg 10
ret ;return to delay subroutine2 10

delay2: push D ;push D register to stack 12

push PSW ;push acc and flag reg to stack 12
mvi D,0FAh ;[D] = 0FAh = 250 7
loop2: call delay3 ;calls second order nested subroutine 18
dcr D ;decrement count 4
jnz loop2 ;until count reaches 0, repeat 10/7
pop PSW ;pop stack contents to acc & flag reg 10
pop D ;pop stack contents to D reg 10
ret ;return to delay subroutine1 10

delay1: push B ;push B register to stack 12

push PSW ;push acc and flag reg to stack 12
mvi B,06h ;[B] = 06h = 6 7
loop1: call delay2 ;calls nested subroutine 18
dcr B ;decrement count 4
jnz loop1 ;until count reaches 0, repeat 10/7
pop PSW ;pop stack contents to acc & flag reg 10
pop B ;pop stack contents to B register 10
ret ;return to main program 10

;Main program
start: lxi sp,1000h ;initializing stack
mvi A,01h ;[A] = 01h = 1
mvi B,0FEh ;[B] = 0FEh= 254
add B ;[A] = [A]+[B] ;The Parity(P) and Sign(S) bits

1
 ;are set to 1, all others are 0. ;Accumulator content is 0FFh.
call delay1 ;delay subroutine call
hlt ;halts the program

Calculating delay:
The number of T-states for each instruction of the delay subroutines is marked to the right end of each line. The total
number of T-states is obtained as:

N o. of T states = 12 + 12 + 7 + [18 + 12 + 12 + 7 + {18 + 12 + 12 + 7 + ((10 + 4) 255 3)

+10 + 10 + 10 + 4 + 10} 250 3 + 10 + 10 + 10 + 4 + 10] 6 3 + 10 + 10 + 10

= 5490598

Given, the clock frequency = 1MHz.

Time period (= time for one T-State) = 1s

T otal delay = 5490598 106 = 5.49s 5.5s

Program verification
The accumulator and flag register values are compared before and after calling the delay routines. Before the delay
routine call, accumulator holds the value 0xFF, and Flag registers are 1 for sign, and partity bits and zero for others.
It is observed to remain unchanged after the program counter returns from the delay subroutines. This verifies that the
stack operations are done properly and the delay subroutines dont corrupt the main program.