design

March 2015 | Volume 5, Issue 3

www.electronicspecifier.com

Shaping the future of Solar

Graphene has the potential to
change the photovoltaic
industry

Enabling Development Tools Power Wireless

Technologies Better software features Semiconductor Can the IoT really be united
A look at the latest highly in driving up Addressing the need for by a single wireless
approaches to new productivity and reliability more efficiency in energy technology?
challenges harvesting circuits
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design
Contents
06 News
FinFETs forge ahead, plus all the latest news

16
08 Market & Trends
Embedded Databases for Embedded Systems

10 In the mix
The demand for smaller and cheaper mixed signal technology

14 Aceeding to Energy
Why the microWatt/MHz MCU is the low-energy king

16 Interfaces that touch you back

Haptic effects for tomorrows touch screens and buttons
24
20 A Hot Topic
Does Silicon Carbide hold the key to high power semiconductor technology?

24 Shaping the future of solar

Why graphene has the potential to change the photovolatic industry

26 Power conversion for energy harvesting

Practical solutions for harnissing ambient energy

Beyond co-design
28 Taking advantage of pre-layout simulation and simultaneous process design
36
A new IDEa
32 The increasing need for better design tools in MCU based devices

Getting to Market
36 Fast Time to Market - confidence inspiring or virtually meaningless? 46
Software as a Process
40 Safety, security and performance processes for software development

Enabling world wide mobility for the IoT

43 Long range, low power spread spectrum technology

Editor: Ad sales: Head Office: Copyright Electronic Specifier. Contents of Elec-

tronic Specifier, its publication, websites and
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Designer: Publishing Director Kent. ME18 6DA publication. In particular, no liability can be ac-
cepted in result of any claim based on or in rela-
Stuart Pritchard Steve Regnier Tel: 01622 871944 tion to material provided for inclusion. Electronic
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electronicspecifier.com 3
Editors Comment
Its a race to the bottom
Benchmarks are good; they provide a simple way
to compare two or more products or services
based on a standard set of parameters, giving a
quick and easy way to select one that best meets
a particular set of requirements. Benchmarks are
bad; they only provide part of the picture,
invariably obfuscating the really important stuff
from view, only revealed after valuable time is
spent digging deeper.
In reality, benchmarks cant provide the level of
detail necessary for all possible applications and, as
such, they are both good and bad depending on
your needs, particularly in a world where the
products/services being measured are subject to an
almost endless array of variation. This is evident
with the latest benchmark from EEMBC; ULPBench,
which focuses on ultra low-power MCUs.
design
Despite being released in April 2014 to date only four
manufacturers have published figures, but more are
expected in the near future.
As its supposed to indicate energy frugality, it may be
surprising that a higher figure for the benchmark is
better. The most recent score published came from
STMicroelectronics, but how long it will reign is up for
debate. EEMBC is also working on phase 2 of the
ULPBench, which will allow manufacturers to make
more optimisations and, as such, will undoubtedly
generate an entirely new wave of results. Any effort to
create a benchmark that will be adopted by even half
of any given industry should be commended, but its
important to remember that milage may vary. !
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News design

In full flow
Reportedly, TSMC now has in the
region of 60 customers with products
targeting its 16nm FinFET+ process,
among them Xilinx; its only FPGA
customer and perhaps the most
ambitious. Its using the process for its
latest generation of FPGAs and SoCs;
UltraScale+, which follows in the
footsteps of UltraScale. However,
thanks to the adoption of the cutting-
edge process, it could be argued that it
bears little resemblance to its
predecessor.
Three families are getting the +
treatment; Virtex, Kintex and Zynq
of the three perhaps Zynq is the most
interesting, as it introduces what Xilinx
is calling MPSoC; a heterogeneous
multi-processing platform that adds, for
the first time in the
companys history,
dual real-time ARM
Cortex-R5 cores and
a Mali-400MP Graphics Processor,
along side quad 64-bit Cortex-A53
cores. It pushes Performance/W up by
as much as 500% over the 28nm
family, according to Xilinx.
One of the target markets for the
UltraScale+ Zynq family will be the
Industrial Internet of Things, which
should be aided by the presence of the
dual Cortex-R5 processors. This is
essentially a new market for FPGAs
when measured against the
established markets of network
infrastructure, wireless, cloud and data
centre, and video/vision all which will
clearly benefit from the performance
boosts in the new family. Whether
those benefits will open doors in the
IIoT remains to be seen.
The Virtex family benefits from the
FinFET treatment with what Xilinx is
calling 3D-on-3D; referring to FinFET
(3D transistors) in a multi chip (or 3D)
package using interposers. The Kintex
family gains from an entirely
redesigned block RAM, called
UltraRAM, as well as enhanced
interfaces including PCIe. First tape-
out is scheduled for Q2 with first
shipments in Q4 this year.

Extended Java support

Building on established support for
the RX MCUs, IS2T will now
provide the same level of support
for Renesas RZ/A group of MPUs.
The intention is to offer Java and
C/C++ developers an embedded
Software tools company, Vector Informatik, has introduced a solution for multi- software platform that allows for a
sensor application development, targeting ADAS. Specifically, vADASdeveloper consistent user experience across
provides the infrastructure to develop algorithms for driver assistance systems, several devices, while accelerating
supporting the development, debugging and testing of multi-sensor applications. the development of HMI
The tool is able to acquire and present data captured from common ADAS applications based on the RZ
sensors such as cameras and laser scanners, and supports the integration of family.
Visual Studio.
The scaleability of the MicroEJ
Mobile FinFET advanced logic process software platform means the same
The industrys first mobile technology in the industry, it application could run on a range of
Application Processor based on a expects the AP to positively devices from MCUs to MPUs, on
14nm FinFET process has gone in impact the growth of the mobile various operating systems.
to mass production, according to industry by enabling further Support will also extend to the RZ-
Samsung Electronics. Described performance improvements for A1 Renesas Starter Kit, which
as undoubtedly the most cutting-edge smart phones. features a graphic display.

6 electronicspecifier.com
design
Closing the floodgates
In a bid to create a secure
platform for industrial automation
and the Internet of Secure
Things, Mentor Graphics has
chosen Icon Labs Floodgate
security products to integrate into
its Nucleus RTOS and
embedded Linux operating
systems. It is intended to ensure
security is intrinsic to the
architecture of a device.
Natively securing the device
simplifies protection and
compliance, according to the
partners. The integration will
provide benefits which include an
integrated embedded firewall,
anti-tamper support and audit
log reporting.
Benchmark bravado
With the highest posted score on
the EEMBC ULPBench website,
STMicro has claimed the crown for
lowest power MCU, for its STM32L4
series based on the Cortex-M4 core.
Scoring 123 (where higher is better)
the first two devices in the family
outperform the other scores on the
site. However, to date, only three
other scores have been posted. With
a swath of ultra low-power MCUs
about to enter the market, the tide
may be rising in the near future.
Until then and, quite justifiably, ST will
remain champion. Michel Buffa,
General Manager, Microcontroller
Division, STMicroelectronics, said:
The STM32L4s ULPBench score of
123 is the best in the industry today
and demonstrates that designers
can now get higher performance and
larger memory without trading power
consumption.
News
A place to call work
The idea of using collaborative
workspace isnt new; some have
made a business out of it. The
availability of a hardware design lab in
such a space, however, is less
common. But residents of Berlin who
need a place to explore an idea using
high-end test and measurement of test and measurement equipment,
equipment, without the expense of work benches and other hardware
purchase, can now do just that tools, to create a hub for startups
thanks to betahaus Berlin, with highly innovative ideas for the
Hardware.co and Conrad Electronic. future of technology, according to
The Hardware.co lab provides a range Conrads CEO, Jn Werner.
Power Integrations has moved its power supply design tool, PI Expert
Suite, to the cloud. Previously only available as a downloaded application,
users can now access the design tool from any internet browser and be
sure its always the most up-to-date version.
Roll PC! sizes up to 85 inches and able to
A rollable and flexible projected detect as many as 40 simultaneous
capacitive film that supports multiple touches though glass as thick as
touch detection has been announced 10mm means it could be popular in
by Zytronic, which could be used in DooH (Digital out of Home)
large interactive displays. Available in applications.
The film gives customers the option of
creating a bespoke touch screen
display, by laminating the film on the
rear of a transparent substrate, such
as a shop window, and combining it
with a projector or LCD. The polyester
touch foils can even be reused, as it
supports semi-permanent installation.
electronicspecifier.com 7
Market & trends
Embedded Databases
for Embedded Systems
The increase in the power, complexity and
prevalence of embedded systems means they
are handling more data and, consequently,
increasingly using databases. The traditional
solution has been to run this on a separate PC
or mainframe in the loop; today, the database
can run within the system. By Chris Hills, CTO,
Phaedrus Systems
While there are still embedded systems that
need only a look-up table or a linked list, for
many applications the data demands are such
that only a database will work. Many people think
they can write their own database system or use
a database not designed from the ground up for
embedded systems. Neither route is a good
solution. Writing your own, whether for an RTOS,
for graphics, communications stacks or
databases, is never a good idea unless you really
are an expert. Learning all the techniques and
methods takes a lot of time and effort that could
be better spent elsewhere on your project.
Developers often think they need to write their
own as their problem is unique. When examined,
it usually turns out that
Image courtesy of Renjith Krishnan at FreeDigitalPhotos.net
their problem is not
unusual and
resolving it is
well-
understood.
Neither is it
difficult to
come up
with a
complex
8 electronicspecifier.com
design
solution; the skill is designing a simple and
elegant solution that handles the what-ifs. These
two points illustrate that rolling your own is
unlikely to be cost effective, once you have
factored in the time to design, build and debug
an embedded database. Frequently McObject,
the supplier of the eXtremeDB in-memory
database frequently finds that when examining
the database schema and code of a new user,
there is a simpler solution.
Once you have decided to buy in a database,
you will find that not all databases are the
same. Many are designed to run in an
environment with disk drives, virtual memory
and lots of ever expanding resources (lets call
it a computer). There are also databases
designed from the ground up to work in
embedded systems. The most successful
route is to use an In-Memory Database
System (IMDBS). This is not the same as a
cached system, as IMDBSs require a
completely different way of working internally
to a conventional DBS.
You should not start designing your database
until you fully understand how an IMDBS
works. For example you need to have a
strategy for persistent and non-persistent data
(And need to know what they are!) Another
choice is of course how to talk to the
database; the first thought is often SQL, a
1970s system that brings it own baggage.
Like much in system development, adding a
database is not easy, but with careful choice
of database the overall system will be more
powerful, secure and stable. !
For further reading on choosing an embedded database, visit
www.phaedsys.com/principals/mcobject/mcobjectdata/
Insight rresides
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oftware.
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Enabling Technologies
In the mix
The demand for smaller and cheaper mixed-
signal technology is growing. Steve
Rogerson looks at how the industry is rising
to the challenge
The quest for smaller and smaller devices,
particularly in the mobile and Internet of
Things world, is driving a demand for
integrated circuits that combine multiple
processes in one device, be it analogue,
power, digital or a combination thereof. This
is posing technical problems for the chip
makers but, almost surprisingly these days,
in some companies cultural problems
remain; the divide between analogue and
digital engineers still exists.
Bringing it all The result has been an increased demand for
together: How ST analogue engineers who are willing to work
Microelectronics across both domains, especially given the
combines multiple richness in functionality that can be provided
processes by combining processes on a single die.
10 electronicspecifier.com
design
Among the biggest drivers of this are, of course,
smart phones, as well as the emerging IoT and
wearables market(s). For many IoT and wearable
applications, there is not a lot of computing
power needed but they do require sensors that
are bringing in analogue signals: The key
advantage is that it reduces the area on the final
board, said Giuseppe Croce, Technical Line
Manager at ST Microelectronics. You have one
device that embeds all the functions. There is
also a gain in terms of reliability because the
connections are etched in, rather than on a PCB.
If the technology can combine most of the
elements, you can reduce two or three ICs to
one, said Manuel Alves, Product Line Manager
at Freescale. You have space savings and you
can save costs on manufacturing and testing.
The technical difficulties potentially impeding
include the fact that as geometries become
smaller, analogue just does not scale as
well: The physics doesnt shrink the same
way for analogue, said John Weil, Vice
President of Marketing at
Cypress, So you end up with a
situation where it can be more
cost effective to have an
analogue die and a digital die to
get the performance you need.
Steve Carlson, Group Director at
Cadence, added: Analogue has
more sensitivity to problems
when you go down to the real
small geometries. This means
we are seeing digitally corrected
and compensated analogue. In
other words, dont worry about
the analogue, just let the digital
fix it.
design
The other result of this is that mixed signal chips
are often a couple of geometries behind pure
digital ICs. In IoT and wearables, the noise has
to be kept down as the signals tend to be small
and again digital compensation plays a role.
There are also multiple power domains at work,
with memory working at different voltages to the
sensors, and these require new disciplines.
You cant just put the same old cells on the
lower voltage, said Carlson. You have to
redesign the cells.
There can be crosstalk issues between the
high voltages and the more sensitive memory,
which means isolation techniques have to be
used between the different parts of the IC. So
the main challenge is ensuring that the features
of one process do not adversely affect the
other processes. This, said Croce, often
involved a compromise, usually because of
cost reasons: Theoretically, it should be
possible to do everything, he said. You
should be able to merge the processes but the
cost can explode. You need to simplify the
process complexity, so compromises are
needed, and that is the main challenge.
Alves agreed: It is not straightforward to
combine technologies, he said. There is R&D
effort to do this. With people and money, you
can always solve the problem. You need to find
the right balance.
Weil believes the way to handle it is to start
with the most advanced of the processes and
then look to integrate the other processes into
that: You anchor on the most advanced
technology, he said. Then you think about
the other technologies. The processor guys
think gate count per square millimetre, the
processor guy looks at layers and added
flash, the radio guy wants good RF that also
has integrated flash. These dont always go
hand in hand. This is why earlier radio models
used different dies in the same package,
though progress has now been made on
integrating flash and RF and it can be done
cost effectively.
Enabling Technologies
Things like Bluetooth and Zigbee can be Integration on a
integrated on the same die as flash, but if you Cypress M series
move to high performance RF such as high- chip
speed Wifi and cellular, you are still better putting
that on a separate die, said Weil. This is just one
area where using multiple chips is still the
sensible way to go. It is a matter of what level of
performance you are looking for, said Croce. In
applications where PCB area is a key factor, a
single chip is probably the best. This includes
mobile, where size cant explode. But there are
plenty of areas where reliability is a key factor,
such as in automotive.
Also, it depends on the balance between
analogue and digital. If the IC is going to be 90
per cent logic, then it is not really worth the
design effort to combine analogue; they might as
well be put on a separate die. It would not be
worth trying, said Alves. You need a balanced
mix of features. Integration is not great for all
products. That is why Weil believes a lot of the
problems can be solved with packaging
technology with more than one die put together
at a chip-scale level. Rather than try to integrate
the technologies on chips, use chip-scale
packaging to find creative ways to put them
together, he said.
Culture
The real difficulty is bringing together the
separate cultures that there are between
analogue and digital designers, said Carlson.
They have to work closely together. The
wearables market has cracked this divide
electronicspecifier.com 11
Enabling Technologies
open again, believes Weil: Analogue had
become a forgotten art, he said. There
wasnt an end demand for more complex
mixed signal technology. The wearables
market is changing that. It is pushing the
boundaries of low-power analogue.
There are varying styles of multi-discipline
approach, but Carlson found that in most
cases the disciplines work separately: They
partition the problem, he said. Analogue is
here and digital is there. But as you push down
the process nodes, you need to move them
together and be able to handle the resultant
complexity. This, he said, meant there were
digital tasks that the analogue guys had to
learn, many of which were new concepts for
them. The divide still exists but we are seeing
more job advertisements for mixed signal
engineers, he said. You have to change the
divide and conquer concept; you introduce
the digital to the analogue world and have to
manage the culture.
Weil added: The culture barrier is still there. You
go in one day and you talk to the analogue guys
and then you talk to the digital guys and they
dont really care. The analogue guys are into the
nitty-gritty of the design. Every time that is
There has to be a
good balance for
mixed-signals
chips to be cost
effective
12 electronicspecifier.com
design
integrated, they have to give up a little bit of turf.
A classic case of this, he said, was what
happened with glucose meters; what was once
very complex for measuring the chemical
reaction is now relatively trivial.
Croce believed the way to go is to recruit good
engineers and train them internally: There are a
lot of good engineers, he said. We recruit smart
engineers and we have a strong internal training
process. But he said there was nothing wrong
with having engineers within the team who were
strong in just one area provided they worked as
part of the team: We do have some who
specialise in digital or analogue, he said, but
they have to think about what they are doing
when this is put together with other parts.
Test and verification
Design is not the only problem when it comes to
mixed signals. The test and verification phases
also have to work across both domains. You
need people to understand both sides of the
fence, said Carlson. By and large, the analogue
and digital designers can do what they do
without learning too much of each other. But
when the design comes up for verification, that is
where they really need to learn about the other
side. Here, he said, it was important to find
design Enabling Technologies

someone with a multiple domain background

who could oversee the process. Some
companies do simply dictate that the analogue
team design must work with digital in mind, but
that does not always come out well.

The most successful, he said, is when you

have the mixed signal experience. The analogue
guys are not used to thinking about breaking up
the test sequence. They just have one Spice
model and add as they go along. They are not
very good at partitioning things up. The
advantage of combining everything on one chip
when it comes to testing is that there are fewer
test points and you also reduce the number of
test instruments needed. For us internally, it
creates some challenges for testing the IC technologies to achieve both the size and the How Freescale
functions, said Alves, but the end user will have cost needed for what is shaping up to be a mass puts it all
less to test. market. But some R&D departments are still together
suffering from old divisions and these need to be
The IoT and particularly the wearables market is resolved if the companies are to capitalise on the
driving new research into mixed-signal latest wave. !

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Enabling Technologies
Acceding to Energy
In the world of the low-energy
application, the microWatt/MHz MCU is
king. By Philip Ling
Generally speaking, embedded solutions are
defined by one of two overriding parameters;
high performance, or low energy. Ideally they
wouldnt be mutually exclusive and for some
applications they arent. Its all relative, after all.
But for the billions of IoT nodes in development,
expected to operate for many years from a single
battery, low energy takes priority. Fortunately,
performance in these applications isnt expected
to be demanding; a core running in the low MHz
should provide more than enough processing
power to meet the majority of requirements, such
as periodically servicing sensors and sporadically
communicating with a local hub. As a result,
many manufacturers are now laser-focused on
developing MCUs with the lowest active and
static power credentials.
The architecture of choice, for many, is ARMs
Cortex-M family; in particular, the diminutive
Figure 1: The reality of power curves
14 electronicspecifier.com
design
Cortex-M0+ has found favour with many
manufacturers, as it offers the best
power/performance trade-off. It may seem odd,
therefore, for a manufacturer to choose the
comparatively thirsty Cortex-M4F when
launching a new MCU targeting ultra-low energy
applications, but thats exactly what Ambiq Micro
has done with Apollo; the companys first MCU
family based on its proprietary Sub-Threshold
Power Optimised Technology (SPOT) platform.
Initial claims are bold; compared to other Cortex-
M4 based MCUs from Atmel and STMicro it
promises between three and ten times lower
active power respectively, and as much as 28
times better sleep mode power than the
STM32F401. The differences in these figures for
competitor devices based on the Cortex-M0+
are smaller but still better, and no less impressive
for it, so how does it do it?
SPOT on
The key to the power savings is the theory
behind SPOT; by keeping transistor switching
excursions below the thresholds normally used
for switching, the power represented by the area
under the curve is significantly reduced (Figure 1).
Its a technique thats been around for many
decades but more recently Ambiqs founders
were part of an academic team working on its
revival at the University of Michigan, before
spinning it out in to a commercial company.
According to Mike Salas, VP of Marketing at
Ambiq Micro and ex-VP & GM of Silicon Labs
Microcontroller division, almost all of the Apollo
uses the SPOT platform (the only parts not built
on SPOT are the Flash and RAM), which is
manufactured on a standard CMOS process but
did require new transistor models and cell
libraries to implement. Salas commented:
Theres nothing exotic about the technology
itself, it was clearly important that we do this on
design
standard CMOS. This makes it a little less
transferable, but not impossible.
The circuitry required to detect the lower
thresholds and combat the bad things that
can happen at lower voltages is Ambiqs
patented technology and, although it does
introduce an overhead in terms of silicon
area, Salas claimed its modest; around 5%.
Some of those bad things relate to the
impact process and environmental
variations can have at the transistors level;
the voltage threshold can vary with
temperature and the on current depends
exponentially on this (Figure 2), which is why
the platforms finer details are patent
protected. Salas explained: Really the
Crown Jewels of the company is not so much in
our ability to dial the voltage down, but in our
ability to create a set of dynamic adaptive
circuitry that accounts for and overcomes the
bad issues; thats where all the patents and
innovation really exists.
All this can still be used alongside other
established techniques used by most if not all
MCU manufacturers, such as voltage/frequency
scaling, power/clock gating and autonomous
peripherals, leading to the impressive results.
Salas explained: We do most of those things,
but even though we benefit from the same
architectural tricks, its because our floor is so
much lower than everybody elses that allows us
to develop these incredibly low power numbers.
Salas added that the company plans to release
ULPBench results in the near future to
substantiate these claims.
Whats the catch?
Ultimately, there is a price to pay for lower energy
consumption; V/F scaling illustrates this in
conventional MCUs and in Apollo it comes in
the form of the maximum operating frequency.
Salas explained that the SPOT platform is limited
by speed, it couldnt offer a device operating at
1GHz, for example, but he is confident that it
could reach 100MHz and beyond. However, the
Apollo family has been specified at 24MHz
Enabling Technologies
Figure 2: Process
because this is the sweet spot for its target variations can
applications, such as wearables and the IoT. impact energy
efficiency
Another benefit that Salas was keen to point out
was that SPOT allows for optimisation of both
active and sleep mode power at the same time;
something others need to choose between: If
they want to optimise sleep power they tend to
work in an older process node that has very
good leakage currents but at the expense of
higher dynamic power, or vice versa. Salas
maintains that Ambiq doesnt have that problem.
It also means it doesnt have to make the
decision between a Cortex-M0+ core or M4:
The penalty for us between using an M0 or an
M4 is negligible. It makes a lot more sense for us
to use an M4 core in these applications. He was
referring to the amount of computation IoT
nodes are expected to do now and in the future.
It also means that Salas sees no problem with
implementing the Cortex-M7 in a future family.
That may happen in the future, the Apollo family
is sampling now and scheduled to go in to
volume production in the Spring, priced at $1.50
in 10k+ volumes. And even though the title of
lowest power MCU will be hotly contested even
when the Apollo becomes available, developers
will still need to weight their demands against the
manufacturers claims when it comes to selecting
the right part for their application. !
electronicspecifier.com 15
Enabling Technologies
Interfaces that touch you back
The industry is working on a multitude
of different haptic effects for
tomorrows touch screens and buttons,
writes Sally Ward-Foxton
User interfaces for electronic devices have come
to be dominated by touch screens and
capacitive and resistive touch buttons. Although
there are many benefits to replacing mechanical
buttons and keypads, some say that useability is
decreasing, as the user doesnt get any physical
or audible feedback to let them know their touch
was registered. Many still miss a physical keypad
for smartphones and tablets, and for kitchen
appliances, the old-fashioned buttons and knobs
could be operated quicker and without looking.
Several different technologies, all with
entirely different mechanisms, have been
developed to solve this problem by
implementing haptic feedback.
Although haptic feedback has been around in
gaming controllers for quite some time, creating
vibration using a motor attached to a weight
inside the controller, much more sophisticated
Figure 1: The
Reactive Grip
controller features
sliding contactor bars
(the grey bars in the
grip). They can be
moved up and down
separately to create
different sensations.
16 electronicspecifier.com
design
implementations of electromechanical haptics
are emerging. Tactical Haptics, formed out of the
Haptics and Embedded Mechatronics Lab at the
University of Utah, has developed a haptic
feedback controller for gaming that it calls
Reactive Grip (Figure 1).
Reactive Grip can create richer haptic feedback
than vibration feedback and can emulate the
feeling of inertia, elasticity, and damped motion,
whereas vibration feedback is mostly limited to
representing transient events and textures, says
Dr Will Provancher, CEO of Tactical Haptics. The
Reactive Grip controller features sliding contactor
bars built into the handle to convey motion and
force. Translational motions and forces are made
when all the contactor bars move in the same
direction. Moving the bars in opposing directions
creates the feeling of the handle wrenching in the
users grasp, perhaps emulating the kick of firing
a gun. More complex movements can be
conveyed by combinations of these motions
imagine holding a fishing rod with a fish
struggling on the line, for example.
We use linear actuators to move the contactor
bars along with standard methods for controlling
their motions, Provancher says. Game
developers simply specify a force vector to our API
between the values of -10 and +10 for each bar.
The initial market being targeted for Tactical
Haptics technology is gaming, but Provancher
says that potential future markets are much
broader: Other applications include training and
therapy, for surgical, stroke rehabilitation,
maintenance and military applications, as well as
teleoperating things like robots in space,
hazardous material handling robots or surgical
robots, he adds.
Sense and Feedback
Piezo haptics uses a type of polymer material
that has piezoelectric properties; the material
design
Figure 2: Aitos Software Enhanced Piezo technology uses an
industry-standard piezo element controlled by one of the
companys touch controller chips.
experiences a mechanical deformation when an
electric current is applied. They can also
generate electric current when a mechanical
force is applied. Applying the right electrical
signal to the piezo element can make it
effectively vibrate, making it suitable for haptics
in electronic buttons.
Over and above basic vibrations, a number of
companies are working on doing more complex
things with piezo, such as Netherlands-based
Aito. Our local, high definition haptic feedback is
able to generate a wide range of sensations. We
can simulate very precisely the feeling and sound
of a mechanical key press, including press and
release clicks, explains Peter Kurstjens, CEO of
Aito. However, the Aito solution actually
combines haptic actuation with touch sensing
using one single piezo element.
Using the same piezo element for both touch
sensing and haptic feedback is not
straightforward; Aitos solution uses an industry-
standard piezo element, but adds functionality
using proprietary software on their haptic control
Enabling Technologies
chip (Figure 2). The software handles the signal
processing, reading the input from touch and
directly controls the generation of feedback. By
coupling the sensing and actuation signals, using
a closed control loop, Aito is able to generate a
superior haptic experience compared to any
existing solution in the market, Kurstjens says.
In terms of applications, Aitos solution is very thin
and features very low power consumption,
making it suitable for user interface control for
smartphones and wearables (Figure 3). In the
future, Kurstjens expects that haptics will be a
bigger part of user interfaces: We see a trend
towards interactive surfaces, in which buttons
and controls are invisible to the user until they are
needed, he says. The controls are seamlessly
integrated within the surface material and can be
seen and felt by lighting up and giving a local
tactile vibration. For instance, in the automotive
industry, OEMs are searching for solutions that
replace clunky buttons and still provide easy and
fast access to most used functions. With Aitos
Smart Piezo, the climate controls or window
buttons could be seamlessly integrated within
the metal or wooded interior parts.
Coulombs force, the principle of attraction Figure 3: An
between positive and negative electrical charges, example of an
is the basis for a new type of haptic technology application for
being commercialised by Finnish company, piezo haptics
Senseg. The company can make smooth glass technology in a
surfaces feel like gravel or sandpaper by altering remote control.
electronicspecifier.com 17
Enabling Technologies design
the way the fingers perceive friction from the
surface using electrostatics.

In Sensegs technology, the skin of the fingers is

attracted to an oppositely charged electrode,
made of a proprietary coating called Tixel.
Applying a very low current to the Tixel electrode
creates the force, and it can be modulated to
produce a range of sensations, including
textured surfaces and edges, to vibrations
(Figure 4). The electrode coating can be applied
to transparent or opaque, flat or curved surfaces.
The benefits of using Sensegs electrostatic
haptics include completely silent operation, unlike
technologies that use vibration as a form of
feedback. And as there are no moving parts, its Figure 5: Ultrahaptics technology lets the user feel
quick to respond and operates reliably with low virtual objects in mid-air.
power consumption.

This technique can be used to create haptic
feedback for on-screen controls, perhaps in the
automotive environment where feeling
feedback without looking at the screen is
desirable. There is also lots of potential for
tablet-based games with the sensations
representing different textures, or for
accessibility for users who are visually impaired,
but it would, of course, depend on
manufacturers incorporating the Tixel electrode
technology into tablets.
Although the technology is still at an early stage,
the company is working with its investor, NXP,
who is developing an ASIC chipset for controlling
the electrode. The electronics will be deployed
next year, but in the mean time, development kits
are available, which include an Android based
tablet customised with Senseg electronics and
software for developing applications.
Feel without touching
Bristol-based startup Ultrahaptics is using
ultrasound to provide haptic feedback to a users
hand. Modulated ultrasound projected towards
the hand can deliver different sensations, and
software can produce projections that allow the
user to feel virtual shapes in mid-air. The user

Figure 4: Sensegs
electrode uses
Coulombs force to
attract the fingertip.
The effect can be
modulated to make
smooth glass feel
rough like gravel or
sandpaper.

18 electronicspecifier.com
design
doesnt have to actually wear or touch anything
just hold their hand above the emitter to get
feedback for mid-air gestures or interact with
virtual optics (Figure 5).
Ultrahaptics latest demo of the technology,
debuted at CES, uses an array of standard
ultrasound emitters exactly like those used in
vehicle parking sensors (Figure 6). Ultrasound is
emitted at 40kHz, which is modulated (turned on
and off) at much lower frequencies so that it can
be felt, typically 200Hz.
This technology will soon begin to be
designed-in to a number of different
applications, says Steve Cliffe, CEO of
Ultrahaptics: For automotive
applications, physical feedback allows the
user to know that their gesture has been
recognised by the vehicle without the
need to take their eye off the road, Cliffe
says, adding that although automotive
design cycles are well-known for being
amongst the longest in the industry,
automotive gesture systems have been
worked on for some time. Ultrahaptics is
piggy-backing on the work already
completed, to bring ultrasonic haptics to
vehicles soon.
Enabling Technologies
The computer industry is very much the same,
in that gesture systems such as Intels RealSense
have already seen significant advancements, and
Ultrahaptics completes the solutions, he adds.
However, the control of your home audio
system is likely to be the first application to reach
the market containing Ultrahaptics technology.
Another obvious candidate for technology that
allows feeling without touching is virtual reality
and the world of gaming; as well as seeing and
hearing, the user could actively feel their
environment. Although its a perfect fit, says
Cliffe, hardware platforms have to be built and
then games built based on that, so reaching the
market takes a lot longer than for other types of
consumer electronics.
Ultrahaptics will soon be making available an
evaluation kit which includes hardware and
software. The hardware is an array of 256
ultrasound transducers mounted on a PCB
along with a motion sensor (Cliffe says 256
transducers is overkill for most applications, but
the evaluation kit is designed for the highest
levels of flexibility). Demo software in the kit
includes simple switches and dials as well as
more complex demos such as bubbles popping
on your hand. !
Figure 6: Ultrahaptics demo kit uses an array of 256 standard ultrasound transducers.
Photo Credit: Kinner Dufort
electronicspecifier.com 19
Enabling Technologies
A Hot Topic
Ewan Ramsay, Principal Engineer with
Raytheon UK, explains why Silicon
Carbide holds the key to high power
semiconductor technology and how it
can help push electronics further into
harsh environments
Silicon-based (Si) components dominate the
electronics industry and are an enabling
technology for numerous applications. However,
all components have operational limits, imposed
by the material properties of Silicon, which
restrict the extent to which electronics can be
used in harsh environments and which restrict
the power densities that can be achieved by
power semiconductors. Accordingly, alternative
materials are needed to extend the use of
electronics further into virtually every industrial
sector. Silicon Carbide (SiC) is one such material,
as its properties can allow higher temperature
and higher voltage operation, along with higher
Figure 1: Raytheons HiTSiC process allows for the creation of p- and n-channel transistors within a thin
layer of monolithic 4H Silicon Carbide substrate. The doping profiles, dielectrics and deposited films are thermal management when
designed to allow 15V operation at more than 300.
20 electronicspecifier.com
design
speed switching, improved power densities and
a greater tolerance to radiation.
Conventional Silicon-based device ambient
temperature must generally be kept well below
125C and though technology variants, such as
Silicon on Insulator (SOI), can raise the bar by
about 100C, thermal management is an
essential requirement for the vast majority of
industrial applications. However, thermal
management adds considerable weight to
conventional electronics systems, and in the
aerospace and automotive sectors where
electrical powered systems are increasingly
replacing those which have historically employed
hydraulics or pneumatics this is very much at
odds with the overall weight-reducing goals
necessary to achieve greater fuel efficiency.
In addition, the aerospace, automotive sectors
and other harsh environment applications are
seeking to get sensing, control and actuation
electronics much closer to heat
sources. For example, to improve
gas turbine efficiency and reduce
CO2 emissions, it is necessary to
make accurate measurements of
exhaust gas temperatures.
Another application is deep drilling,
and the use of electronics to
monitor and control the extraction
of geothermal energy. There is
therefore considerable interest in
using alternative materials to
fabricate semiconductor devices
which can a) work in harsher
environments and b) require less
handling high power.
design
The two strongest contenders within
semiconductor materials are Gallium Nitride
(GaN) and Silicon Carbide (SiC). These are wide
bandgap materials and, compared to Silicon,
both enable the construction of devices which
can operate at higher temperatures (more than
300C) and deliver high power densities. Also,
both have higher breakdown electric fields (circa
10 times more than Si) which allows for higher
voltage operation than Si-based devices.
However, a key differentiator between the two
materials when considering applications in very
high power applications is thermal conductivity.
It governs how efficiently heat can be removed,
which in turn governs how hard power
semiconductor devices can be driven.
Specifically, SiCs thermal conductivity is about
5Watts/cm3K, compared to Silicons 1.5
Watts/cm3K, and GaN is lower still at about 1.3
Watts/cm3K.
Also worthy of note, when comparing the use of
GaN and SiC for fabricating power switches, is
the fundamental difference between device
architectures. Currently, the inability to grow bulk
GaN crystal means transistors are built laterally
(flat). SiC power components on the other hand
can be built vertically, so that the electrical
current flows through the thickness of the
substrate material. This puts GaN-based lateral
devices at a disadvantage, as the heat
conduction path is typically through the
substrate; and if the GaN has be placed on a
low-cost Si substrate, the thermal performance
will be no better than that of a Si device. Also,
surface breakdown can limit the voltage
performance to about 600V. SiC vertical devices
do not suffer in the same way, allowing for the
construction of devices for use in much higher
voltage applications (well into the kV region).
Components that have been fabricated in SiC
include diodes, a variety of transistor types (such
as MOSFETs, JFETs and IGBTs) and gate-turnoff
thyristors. Hence, with access to such
fundamental building blocks, it is possible to
create smaller, lighter and extremely efficient
Enabling Technologies
Figure 2: Raytheons High Temperature Silicon Carbide (HiTSiC) project is developing an
advanced Silicon Carbide (SiC) manufacturing technology and has demonstrated the
worlds first 400C CMOS transistors and a 300C CMOS IC. This breakthrough process
enables higher efficiency electrical energy management and advances in SiC wafer
processing as well as individual device design technology.
power modules for switching power to/from
loads and for conversion.
For instance, in May 2014, Toyota announced
that, through the use of SiC power
semiconductors, it aims to improve hybrid
vehicle (HV) fuel efficiency by 10 percent (under
the Japanese Ministry of Land, Infrastructure,
Transport and Tourisms (MLIT) JC08 test cycle)
and reduce automotive Power Control Unit
(PCU) size by 80 percent compared to current
PCUs with Si only power semiconductors.
SiC-based power modules also have a home in
the rail sector. For example, in late 2013,
Mitsubishi Electric launched a railcar traction
inverter system for 1.5kV DC catenaries that
incorporates what it claims to be the worlds first
all-Silicon Carbide power modules; made with
SiC transistors and SiC diodes. According to
Mitsubishi Electric, the new traction inverter
systems switching loss is approximately 55%
less than its conventional inverter system. These
reductions, along with an ability to handle more
regenerated energy (through regenerative
braking) lead to a claimed total energy
consumption reduction of about 30% compared
electronicspecifier.com 21
Enabling Technologies
Avoiding Traps
The mass adoption of Silicon Carbide will depend on the
efficiency of, and the performance that can be delivered
by, a variety of fundamental electronic building blocks;
ones which are traditionally fabricated in Silicon. For
instance, Raytheon UKs semiconductor business unit in
Glenrothes, Scotland, is working on a Knowledge Transfer
Partnership (KTP) project, in conjunction with researchers
at Newcastle University, to study the characteristics of the
interface between SiC and Silicon Dioxide (SiO2), the
region which critically impacts on the performance of a
MOSFET
Defects known as traps in the interface between the two
semiconductor materials affect the threshold voltage and
maximum current that a MOSFET can handle. A detailed
understanding of the interface behaviour will enable
Raytheon UK to optimise its SiC CMOS and Power
MOSFET manufacturing processes to minimise the
occurrence of traps, resulting in not only higher
performance devices for its own power-module devices,
products and systems but also for those customers using
the companys foundry services.
to conventional systems. Size and weight are
said to be reduced by about 65%, compared to
conventional inverter systems with IGBT power
modules, and about 30% compared to existing
hybrid inverter systems (with SiC diodes).
Closer than before
Without doubt, Silicon Carbide is the material for
high temperature and high voltage applications.
However, for high speed switching applications,
it is becoming necessary to locate control
Table 1: Silicon circuitry as close as possible to the power
Carbides high semiconductors; in order to minimise parasitic
temperature
operation Property and what it enables
combined with its
Bandgap Energy (in eV) high temperature operation
high voltage
operation and heat Breakdown Electric Field (in kV/cm) high voltage operation
transfer properties
make it the most Thermal Conductivity (in W/cm.K) excellent heat transfer
suitable material
Electron Mobility (in cm2/V.s) high speed switching
for high power
Saturated Electron Drift Velocity (x107 cm/s) high switching frequency,
semiconductors.
low reverse recovery
22 electronicspecifier.com
design
delays and losses. For example, under an
Innovate UK supported project called LAMPS,
Raytheon UKs semiconductor business in
Glenrothes, Scotland (in conjunction with UTC
Aerospace Systems and others) is developing a
revolutionary extreme temperature 3-phase
power switch module.
Packaging and internal interconnect
technologies are being explored which will
allow the co-location of SiC switches (rated at
1.2kV/50A) with base driver circuitry
fabricated using 15V HiTSiC CMOS (Figure 1)
in order to maximise the module performance,
and achieve a switching frequency of more
than 75kHz.
Also, materials and bonding techniques are
being explored with the aim of accommodating
a wide temperature range and temperature
cycling; as the intention is for the module to be
able to work at temperatures up to 300C. If
successful, this will not only represent a
significant breakthrough in PSM technology but
it will also prove that previously heat-sensitive
systems can be re-engineered for use in
harsher environments.
SiC- and GaN-based semiconductors are
starting to play a major role in a variety of
sectors, where their material properties provide
more efficient use of energy. Flat screen TVs,
server farms and photovoltaic panels are, for
example, all benefitting from lower power
losses through the use of SiC-based
components. However, for high voltage, high
power and high temperature applications SiC is
currently the only contender. !
Si SiC GaN
1.12 3.26 3.45
300 2,200 2,00
1.5 4.9 1.3
1,500 1,00 1,250
1 2 2.2
 StrongIRFET Rugged,
Reliable MOSFETs
Specifications Features:
ID RDS(on) max Qg@
Ultra low RDS(on)
BVDSS
Package @25C @Vgs = 10V Vgs = 10V Part Number High current capability
(V)
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Industrial qualified
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PQFN 5x6 30 100 1.3 50 IRFH8307TRPbF
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40 85 2.4 92 IRFH7440TRPbF
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30 192 1.3 51 IRF8301MTRPbF Inverters
DirectFET Med.Can 40 90 1.4 141 IRF7946TRPbF
60 114 3.6 120 IRF7580MTRPBF UPS
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60 120 5.34 86 IRFS7540TRLPbF ORing or Hotswap
40 195 1.5 150 IRFS7437TRL7PP
D2-Pak 7pin Battery Packs
60 240 1.4 236 IRFS7530-7PP
40 90 2.5 89 IRFR7440TRPbF
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60 90 4 86 IRFR7540TRPbF
40 195 1.3 300 IRFB7430PbF
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TO-220AB
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Enabling Technologies
Shaping the
future of
solar
Graphene has the potential to
change the photovoltaic
industry, By Dr Craig P
Dawson, 2-DTech
It is estimated that the total installed
photovoltaic capacity across the globe will
reach the 500GW mark by 2018, according
to a report compiled by market analysis firm
Solarbuzz. This would be a notable increase
on existing renewable resources, but would
still not make any major contribution to the
worlds ever-increasing energy consumption.
As yet a cost-effective and fully efficient way
by which to convert solar energy into
electrical energy still seems to allude us.
Manufacturers of photovoltaic infrastructure
currently find themselves in an awkward
position. They face having to make difficult
trade-offs, forced into trying to balance
demands to raise energy conversion
performance and lower overall cost.
The overwhelming majority of todays commercial
photovoltaic deployments rely on crystalline silicon
(c-Si), which is applied in relatively thick, rather
expensive slabs. These c-Si solar cells have the
advantage that they can offer up to 25% power
conversion efficiency levels, but nevertheless
widespread use of this technology for large
installations (i.e. ones covering areas above 100m2)
is to some extent hampered by the considerable
manufacturing costs involved. This is due to the
fact that high-purity silicon must be specified in
order to attain the expected degree of efficiency.
24 electronicspecifier.com
An alternative to the c-Si approach is to utilise thin
film technology. Though thin film solar cells, using
semiconductor materials such as copper indium
gallium selenide, can be produced more
economically, they do not perform in a
comparable manner to c-Si solar cells in terms of
their light absorption or their conversion efficiency.
There have in recent times, however, been
encouraging developments made in thin film solar
technology, through use of cells with absorbing
layers based on Methylammonium Lead Halides
(CH3NH3PbX3, where X = I, Br, Cl) which have the
perovskite (e.g. CaTiO3) crystal structure.
As they do not require inclusion of any novel or
difficult to obtain chemicals, or rely on complex
fabrication techniques, the production costs that
are associated with perovskite solar cells are far
lower than those of c-Si cells. At the same time
the perovskite cells manage to deliver
comparable power conversion efficiencies to thin
film c-Si solar cells and only a few percentage
points lower than single cell c-Si solar cells.
Perovskite crystals are, as a result of these
attributes, already being featured in the latest
generation of solar cells. As well as converting
incident light into electrical energy very efficiently
the perovskite solar cells also offer a very broad
spectral response, so the light across an
expansive range of wavelengths can be utilised.
design
Some are of the opinion, though, that there are
ways in which the conversion efficiencies of this
compound can be pushed still further; there is
now a growing interest in the role graphene
could play within perovskite-based solar cells.
Wonder Material?
For some time now graphene has been heralded
by many as the wonder material that could have
huge bearing on many different aspects of
modern society. First isolated in 2004, this single
atom thick (0.34nm) carbon-based
nanostructure is both incredibly strong (with a
tensile strength of 1Tpa) and at the same time
incredibly light (weighing only 0.77mg per square
meter). Of course it is graphenes electrical
properties that are of most importance to the
photovoltaic industry; it is recognised as the best
conductor in existence, with an electrical current
density reaching 100MA/cm2 (a million times
greater than that of copper) and an intrinsic
charge carrier mobility of approximately
105cm2/Vs at room temperature (a hundred
times greater than silicon).
The principle challenge in modern photovoltaic
cell design, with relation specifically to how well
sunlight can be translated into electricity, is being
able to maximise the cells charge collection
capacity. Through carefully engineered
incorporation of graphene into thin film solar
cells, the remarkable electronic and structural
properties it possesses could lead to a step
change improvement in efficiency levels, as well
as the additional benefit of gaining greater
surface stability. Unfortunately, so far the research
done in this particular area has been limited.
Increased efficiency levels would result in a
smaller installed area per unit of electricity
generated, thereby reducing the material
requirements as well as carbon footprint of the
manufacturing process employed. It is also
envisaged that through monolayer graphene
encapsulation there would be a significant
improvement in the durability and lifetime of
perovskite solar cells, which can be sensitive to
moisture. The encapsulation aspect would
prevent moisture ingress and additionally a
Enabling Technologies
reduction in the external toxicity of solar cells
based on perovskite could be derived, as lead
(Pb) compounds present in these cells could be
prevented from leaking into the external
environment, where they would otherwise
present a health hazard.
University of Manchester spin-out, 2-DTech, has
recognised the potential that graphene has to aid
the photovoltaic industry. The company was
recently awarded an InnovateUK grant worth
98,000 to carry out research relating to
development of a methodology by which
graphene nanoparticles could be integrated into
the perovskite charge collecting regions of the
solar cells. The company has now started to
collaborate with solar technology specialist
Dyesol to produce a baseline first generation
perovskite solar cell with graphene incorporated
into it. Next researchers will over time make a
series of small adjustments to the graphene
composition to see which combination yields the
best power conversion efficiency results for the
perovskite solar cells. Finally, the two companies
will aim to develop a large scale manufacturing
process for monolayer encapsulated graphene-
perovskite solar cells, with the end goal of
making this a commercially viable product.
Thin film solar cells simply have not, up to this
point, been able to offer the sort of power
conversion efficiencies that are needed to
compete with crystalline alternatives and until
recently the progression of thin film solar cell
technology has continued at a fairly slow rate. It
is possible that graphene could accelerate
things significantly - with the nanomaterial being
used to enhance the electrical properties of
perovskite solar cells. This may hold the key to
boosting power conversion efficiency levels
beyond their current restrictions, as well as
offering some improvements in cell durability and
environmental impact. Research now underway
in Manchester could, in time, enable advanced
photovoltaic solutions, employing previously less
favoured thin film technology, to be brought to
market that have much more attractive
cost/performance characteristics. !
electronicspecifier.com 25
Power Semiconductors
Low Power Conversion
for Energy Harvesting
Harnessing tiny amounts of ambient energy from
sustainable sources works well in theory, but are
there any practical solutions to achieving it? By
Tony Armstrong, Director of Product Marketing.
Linear Technology Corporation
There is plenty of ambient energy in the world
around us and the conventional approach for
energy harvesting has been through solar panels
and wind generators. However, new harvesting
tools allow us to produce electrical energy from a
wide variety of ambient sources. Furthermore, it is
not the energy conversion efficiency of the circuits
that is important, but more the amount of average
harvested energy that is available to power it. For
instance, thermoelectric generators convert heat to
electricity, Piezo elements convert mechanical
vibration, photovoltaics convert sunlight (or any
photon source) and galvanism converts energy from
moisture. This makes it possible to power remote
sensors, or to charge a storage device such as a
capacitor or thin film battery, so that a
microprocessor or transmitter can be powered from
a remote location without a local power source.
It is becoming more common at the lower end of
the power spectrum, such as nanopower
conversion in wireless sensor networks (WSNs) and
other sensors. This is creating a need for power
conversion ICs that can work with very low levels of
power and current; often just 10s of microwatts and
nanoamps of current, respectively. However, the
availability of such power conversion products
including battery chargers, operating at sub-1A of
current are extremely limited.
In general terms, the necessary IC performance
characteristics needed for inclusion in these
26 electronicspecifier.com
design
applications include: low standby quiescent currents
(typically less than 6A and as low as 450nA); low
start-up voltages (as low as 20mV); high input
voltage capability (up to 34V continuous and 40V
transients); the ability to handle AC inputs; multiple
output capability and autonomous system power
management; maximum Power Point Control
(MPPC) for solar inputs, and compact solution
footprints with minimal external components.
Density dilema
WSNs are basically a self-contained system consisting
of some kind of transducer to convert the ambient
energy source into an electrical signal, usually followed
by a DC/DC converter and manager to supply the
downstream electronics with the right voltage level and
current. The downstream electronics consist of an
MCU, a sensor and a transceiver.
When trying to implement WSNs, a good question
to consider is how much power is needed to
operate it. Conceptually this would seem fairly
straightforward, however in reality it is a little more
difficult due to a number of factors. For instance,
how frequently does a reading need to be taken?
Or, more importantly, how large will the data packet
be and how much power is needed for it to be
transmitted? This is due to the transceiver
consuming approximately 50% of the energy used
by the system for a single sensor reading and
transmission. Several factors affect the power
consumption characteristics of an energy
harvesting system or WSN and they all need to be
taken into consideration.
Of course, the energy provided by the energy
harvesting source depends on how long the source
is available. Therefore, the primary metric for
comparison of scavenged sources is power density,
design
not energy density. Energy harvesting is generally
subject to low, variable and unpredictable levels of
available power, so a hybrid structure that interfaces
to the harvester and a secondary power reservoir
are often used. The harvester, because of its
unlimited energy supply and deficiency in power, is
the energy source of the system. The secondary
power reservoir, either a battery or a capacitor, yields
higher output power but stores less energy,
supplying power when required but otherwise
regularly receiving charge from the harvester. Thus,
in situations when there is no ambient energy from
which to harvest power, the secondary power
reservoir must be used to power the WSN. Of
course, from a system designers perspective, this
adds a further degree of complexity since they must
now take into consideration how much energy must
be stored in the secondary reservoir to compensate
for the lack of an ambient energy source.
It is clear that WSNs must use very low levels of
energy when available. This, in turn, means that the
components used in the system must be able to deal
with these low power levels. While this has already
been attained with the transceivers and
microcontrollers, on the power conversion and
battery charging side of the equation there has been
a void. However, Linear Technology developed its
LTC3388-1/-3 and LTC4071 to specifically address
these requirements. The LTC3388-1/-3 is a 20V input
capable synchronous buck converter than can deliver
up to 50mA of continuous output current from a
3mm x 3mm (or MSOP10-E) package. It operates
from an input voltage range of 2.7V to 20V, making it
ideal for a wide range of energy harvesting and
battery-powered applications including keep-alive,
sensor and industrial control power. The LTC3388-1/-
Power Semiconductors
Figure 1: LTC3388-
1/-3 Typical
application
schematic
3 utilises hysteretic synchronous rectification to
optimise efficiency over a wide range of load currents.
It can offer over 90% efficiency for loads ranging from
15 A to 50mA and only requires 400nA of quiescent
current, enabling it to provide extended battery life
where one is used for auxiliary power.
The LT3388-1/-3 incorporates an accurate
undervoltage lock-out (ULVO) feature to disable the
converter when the input voltage drops below 2.3V,
reducing quiescent current to only 400nA. Once in
regulation (at no load), the LTC3388-1/-3 enters a
sleep mode to minimise quiescent current to only
720nA. The buck converter then turns on and off as
needed to maintain output regulation. An additional
standby mode disables switching while the output is in
regulation for short duration loads, such as wireless
modems, which require low ripple. This high efficiency,
low quiescent current design is ideal for energy
harvesting, which requires long charging cycles
accompanied by short burst loads for powering
sensors and wireless modems.
Even though portable applications and energy
harvesting systems have a broad range of power
levels for their correct operation, from microwatts
to greater than 1W, there are many power
conversion ICs available for selection by the
system designer. However, it is at the lower end of
the power range, where the levels fall into the
nanopower level that the choice becomes limited.
Fortunately, there are power conversion and
battery charging solutions available for the designer
to select from with quiescent currents of less than
a microamp to prolong battery life for keep-alive
circuits in low power sensors and a new
generation of WSNs. !
electronicspecifier.com 27
Development Tools
Beyond co-design
As designs become more complex and time-to-
market schedules become more demanding,
engineers must take advantage of pre-layout
simulation and simultaneous process design in
order to beat the competition. By Barry Olney,
CEO, In-Circuit Design Pty Ltd
Concurrent design can decrease product
development time and also the time-to-market,
leading to improved productivity and reduced
costs. As a relatively new process strategy, initial
implementation can be challenging but the
potential competitive advantage means it is
beneficial in the long term. Typically, a high-speed
computer based product takes two to three
iterations to develop a working prototype.
Figure 1: A However, these days the product life cycle is very
traditional design short and therefore time-to-market is of the
process compared essence. A board iteration can be very costly, not
to the only in engineering time, but also in the cost of
simultaneous, or delaying the products market launch. This
concurrent, design missed opportunity could cost hundreds of
process thousands of dollars. All of the above impact on
28 electronicspecifier.com
design
company profit, by increasing prototype costs
and the time-to-market.
In a concurrent approach, pre-layout simulation
can be done during design capture to establish
the required design constraints. Functional
sections of previously developed golden boards
can be reused giving high confidence in
performance and multiple designers can be
employed on the same layout. Post-layout
simulation and mechanical integration can be
done towards the end on the layout to ensure
compliance to specification prior to fabrication.
This process can dramatically reduce
development time.
Process improvement is a systematic approach to
ensure a development team optimises its
underlying processes to achieve more efficient
results. Process improvement is an aspect of
organisational development in which a series of
actions are taken to identify, analyse and improve
existing design processes to meet new goals and
objectives, such as increasing profits and
performance, reducing costs and accelerating
schedules. These actions
often follow a specific
methodology or strategy to
increase the likelihood of
successful results. There
are many ways to improve
efficiency in the PCB
design process, such as:
simulation; design reuse;
collaborative PCB Design,
and virtual Prototyping.
Simulation
Pre-layout analysis allows
a designer to identify and
eliminate signal integrity,
design Development Tools

crosstalk and EMI issues early in the design

process. This is the most cost effective way to
design a board with fewer iterations, rather than
starting with the find-and-fix based post-layout
simulation. There are multiple facets to pre-layout
analysis including: stackup planning for
controlled impedance, SI, crosstalk, and cost
8 CHANNEL
control; dielectric material selection for
manufacturing yield, and high-frequency
PC OSCILLOSCOPE
operation; PDN optimisation for product reliability For just 1395 1689 $2302
and cost reduction; I/O buffer and drive strength
selection; topology optimisation; termination
strategy; floor planning for critical components;
High resolution
deriving layout routing constraints, including trace
width, spacing and length matching, and signal
USB powered
integrity analysis to meet the design
specifications with respect to noise margins,
Deep memory
timing, skew, crosstalk, and signal distortion.

Although the trace impedance is specified on the

fabrication drawing, stackup planning is often left
until Gerbers are produced and the deliverables
are sent off to the Fab shop. However, generally
the virtual dielectric material selection and trace
width and clearance provided do not match the
desired controlled impedance. So, the CAM
engineer returns the calculations that may require
trace width and clearance changes; not what is
needed at the end of the design cycle. This flawed
process can be attributed to the fact that PCB
Designers do not have access to field solvers
during layout and either have to wait until an SI
Engineer analyses the design or, as commonly
occurs, wait for the Fab shops report.

ICD has responded to this challenge by

developing a bi-directional interface from the ICD
Stackup Planner to Altium Designer 14. This new
interface allows the designer to exact the rigid/flex INCLUDES AUTOMATIC MEASUREMENTS,
stackup from the Altium, Layer Stack Manager SPECTRUM ANALYZER, SDK, ADVANCED TRIGGERS,
COLOR PERSISTENCE, SERIAL DECODING (CAN, LIN, RS232,
into the Stackup Planner. High-speed materials IC, IS, FLEXRAY, SPI), MASKS, MATH CHANNELS, ALL AS
(up to 40GHz) can be merged from the Dielectrics STANDARD, WITH FREE UPDATES
Materials Library, of over 8,800 materials, and the
impedance of multiple differential pairs can be
simulated on the same substrate. Once finalised,
the designer simply exports the data, including
PTH and blind and buried microvia spans, trace
width and clearances and differential pair rules www.picotech.com/PS425
Development Tools
Figure 2: back into Altium Designer. This allows the
Integration of the designer to route to impedance. A fabrication
ICD Stackup drawing of the stackup specifying all HDI
Planner and Altium requirements is also exported to Excel.
Designer 14
Similarly, PDN Analysis is often overlooked
completely. It cant be overstressed how
important low AC impedance is for high-speed
designs that demand high current drain at low
core voltages. If the impedance is high at either
the fundamental frequency, or any of the odd
harmonics, then higher levels of electromagnetic
radiation can be expected. This has a direct
impact on product reliability and the ability to pass
Electromagnet Compliancy.
For years, application notes have recommended
the use of three decoupling capacitors per power
pin. This generally consisted of a 100nF, 10nF and
a 47pF capacitor. The idea behind this was that
different values provided current at different
frequencies, but unfortunately not the right
frequencies as all boards are different. As can be
seen in Figure 3, multiple capacitors per decade
are required to keep the effective impedance of
the PDN below the target up to the required
bandwidth. If too few capacitors are used, spread
widely across the frequency domain, then there is
a good chance that anti-resonance peaks in the
PDN will exacerbate the problem.
Also, in this case, the use of 3M Embedded
Capacitance Material (ECM) has been
incorporated, which is the only practical way to
30 electronicspecifier.com
design
pull the PDN low around the GHz
region. This material provides
20nF/in2 which is an excellent way of
amassing additional planar
capacitance. The tight integration
between the ICD Stackup Planner
and PDN Planner allows the
automatic transfer of the effects of
different dielectric materials to the
PDN for analysis.
Further efficiency gains
If the same switching regulator or
processor and memory chips, for
instance, are used on consecutive designs,
creating a library of matching reuse blocks or
snippets for schematic and PCB makes the
best use of existing design elements for future
designs. Simply add a sub-circuit block to the
schematic, transfer to the PCB database, and
load a predefined layout block including
component placement, tracks, copper and text.
Whether it is used for multiple channel designs,
critical digital circuitry, RF circuit blocks, or just to
replicate a commonly used layout pattern,
design reuse will save time and ensure
repeatability of design: a proven, tested, working
solution to just drop into place.
For many years designers have attempted team
design, to avoid the seemingly unavoidable
routing bottleneck, using multiple PCB
designers to route different sections of the
board at the same time.
Schematics and layouts can be divided into
function blocks for example: Power Supply,
Analog, Digital, Memory and SERDES. Or,
multiple designers can work on the same
section simultaneously in different parts of
the world. I have done this many times,
providing an over-night design service for US
based companies. Co-design implies that a
group of designers can work on a design at
the same time and all their design inputs are
accepted. But obviously, this is full of traps
and there has to be some form of priority
when merging databases.
design
In recent years some EDA companies have
developed tools to enable designers to
collaborate, compare and merge designs and
these capabilities include the ability for multiple
designers to access and merge a PCB
database; a mechanism to accurately identify
and compare databases, and the capacity to
display the differences and allow the lead
designer to informatively select the best
outcome of any conflicts.
Also, live collaboration is now possible. Each
designer defines a work region and this is
displayed clearly on each designers database
view, enabling the avoidance of conflicts. Other
tools allow designers to work with the one
database in real time with no need to partition and
re-assemble the design. The tool manages edits
from all users and continually sends updates to
the entire team. Team collaboration can result in
extreme reductions in design time with a typical
13 week complex design being reduced to 5
weeks and in some cases, providing a 60%
increase in productivity.
Like simulation, the integration of mechanical
aspects of the design process is generally not
considered until late in the design process. This
leaves the design open to change once the
mechanical issues have
been identified, hence
delay. With stylish housings,
how do designers fit the
tightly packed, complex
shaped electronics into the
box? Traditionally, designers
assumed there was no
problem and simply
handed over the CAD
drawing to be
manufactured. But after
years of denial, it has been
concluded that this
approach did not work too
well.
The challenges that many
companies face, when they
Development Tools
use both 2D and 3D, is that these tools are
fundamentally disconnected. The design that is
created in 2D, in order to be reused in 3D, has to
either be imported or recreated into the 3D tool.
This disconnection causes inefficiencies in the
design process. Also, any changes that are made
in the 2D environment are not automatically
reflected in 3D. This means that the user either
has to go through the re-import process or create
the change twice.
However, this issue has been overcome by some
tools that bridge the gap between electronics and
mechanical design so that you can be assured
that your product fits together every time. This is
accomplished by using 3D DRC interference
checking at the PCB design level and dynamically
linking the 2D back into the 3D design space.
This is a great solution to the problem; a native
3D environment.
Concurrent design offers significant benefits to
product development teams providing a
competitive advantage by reducing time-to- Figure 3: PDN
market, and cost while providing Analysis using
high-performance, reliable products on time. multiple capacitors
Delivering a product on schedule, provides higher per decade and
returns due to a longer presence in the market. 3M ECM planar
This all of course leads to higher profits. ! material
electronicspecifier.com 31
Development Tools
A new IDEa
The rise of configurability in MCU-based
devices has increased the need for better
graphical design tools. By Mark Saunders,
Cypress Semiconductor
Programmable devices with embedded CPU
cores provide an effective means for addressing
a wide range of design challenges that are
difficult or costly to solve with just hardware or
software alone. These devices combine digital
and analog hardware resources that can be
reprogrammed to provide the exact functionality
needed. But the devices offered by todays
semiconductor vendors are as varied, and
interesting, as the problems they solve. Cypress
Semiconductors PSoC, for example, integrates
an ARM CPU core with the usual microcontroller
peripherals and arrays of programmable digital
and analog blocks. This configurability allows the
user to customise the PSoC device to perfectly
suit specific applications. XMOS takes a different
approach with its xCORE technology, integrating
multiple processor tiles to create a very
powerful and flexible device. Whether the device
is a multi-core CPU or a re-programmable SoC,
developers are going to need high-quality, easy-
to-use design tools to eliminate the complexity
typically associated with programmable logic.
Figure 1:
Connecting a
DAC output to an
analog pin with
PSoC Creator
32 electronicspecifier.com
design
PSoC Creator from Cypress Semiconductor, for
example, was designed specifically to make this
task easy. Rather than forcing engineers to
complete electrically perfect circuits, PSoC
Creator allows you to draw only the relevant part
of the design - just like one would on a
whiteboard. It then figures out the best
placement and routing of peripheral blocks
(which are called components), sets up the
required clocking and power configuration, and
optimises the design.
Being a mixed-signal device, PSoC includes
integrated digital-to-analog converters (DAC) and
these can be used to output a voltage (or
current) to a pin or somewhere else on the
device. Engineers can connect a DAC to a pin by
dragging and dropping the components onto a
sheet, called a schematic, and wiring them
together. It takes just a few seconds to locate the
components and copy them into the schematic.
Notice that there are no inputs to the DAC; no
power line, no Vref input, no scary bus interface,
just a single voltage source that is wired to a pin
(the pin is equally simple, too). In reality, PSoC
pins can support a wide combination of GPIO,
SIO and analog functionality with various drive
modes, plus enable and synchronisation
features. But the analog pin used here has
already configured the physical pin in just the
way needed, so there is no need to be
concerned with how to safely turn those features
off without impacting the signal from the DAC.
Both PSoC Creator and the XMOS
xTIMEcomposer Studio (Integrated
Development Environment) ship with a fully-
validated suite of peripherals for example,
design
analog-to-digital converters (ADC), DAC and
amplifiers; UART and I2C, PWMs and Timers
which are much easier to use than the raw IP
blocks found in traditional schematic capture
tools. In these tools, the peripherals
implementation details are abstracted away and
designs are error-free the first time. Users are
able to select functionality in a parameter editor
and the tool determines the device configuration
needed to achieve your requirements. Simply
drop the required function into the project and
make your selections in the editor.
Natural APIs
Consider a UART. This is typically a firmware-
oriented component and so the editor
presents the configuration options in a way
that is natural to those engineers. No option is
given for a clock input and over-sampling rate.
The only request is what baud rate you require
and the tool automatically creates a clock
source that will supply the appropriate
frequency to the component.
Programmable devices with integrated CPUs
need tools that also integrate the hardware and
software development tasks. One of the
problems faced by silicon-centric tools is that
software engineers are typically forced to use
tools they do not particularly like, along with
having to deal with raw memory and register-
Development Tools
level interfaces to the peripherals. Without the Figure 2:
right software tools, a programmable SoC Configuring a UART
empowers the hardware designer to the is similar in both
detriment of the software team. The hardware PSoC Creator and
schedule is greatly accelerated and risk is xTIMEcomposer.
minimised, especially when compared to an Notice that the
ASIC flow. However the burden of getting things options relate to the
to work is really just being pushed onto the function, not the
software development team. implementation of
the peripheral.
Another example of a graphical design tool is
the Digital Application Virtual Engineer, or DAVE,
from Infineon Technologies. Like PSoC Creator,
DAVE allows users to select from a library of
components, or Apps, to configure and build
the hardware. Most components have a
software interface (the exceptions are low-level
components like LUTs, logic gates and
multiplexers) that make it easy to drive the
peripherals from C code. Rather than presenting
a set of memory-mapped registers with esoteric
bit fields and (often) undocumented side-effects,
components bundle the typical functionality into
C-language API calls. To start a Timer running
you call an API like Timer_1_Start(). (Youll never
guess how to stop it.) Reading the current value
of the timer is achieved by using the return value
from Timer_1_ReadCounter(). Once you get
used to the style of the APIs, you can often
guess the API names for a component that you
have never used. If you dont guess right, a
electronicspecifier.com 33
Development Tools
complete datasheet is always available from
the customiser dialog or by right-clicking on
the component.
In both PSoC Creator and DAVE, component
APIs are provided as source code, making
debugging the software-hardware interaction
very simple. There are no libraries to include in
the build and there is no need to go hunting
through web pages to find device drivers (that
always seem to be for another device anyway).
There are no restrictions on where breakpoints
are placed or what code can be stepped
through while debugging. One rarely needs to
switch to an assembler view when
troubleshooting a components behaviour.
Concurrent Design
Today, development is often split into hardware
and software teams with the two teams often not
located in the same building, or country. This
could present a problem when selecting the
project tools, debug solutions, maintenance
contracts and so on. Switching to a new
software development environment is often
34 electronicspecifier.com
design
impractical as they are usually very well
established parts of the engineering
development flow with high levels of integration
into company systems, for example source
control and documentation management.
A better approach in these environments is to
consider hardware design software as a chip
configuration tool, rather than a replacement
IDE. Hardware engineers can use the tool to
generate a design and generate all the
configuration data and APIs. The software
team merely needs to integrate these files into
their IDE of choice, such as IARs Embedded
Workbench or ARMs Microcontroller
Development Kit (MDK), and follow a familiar
edit-build-debug cycle. The hardware team is
free to use PSoC Creator or DAVE to build test
benches for their designs and the boards on
which they are used. Its even possible to
create board support packages (BSP) or
hardware abstraction layers (HAL) to share
with the software team, which makes
interaction with the device as easy and error-
free as possible.
design Development Tools

This integration with traditional software IDEs is
really important in team-based development.
Indeed, it is so important to users of ARM
Cortex M-class devices that ARM developed
CMSIS-Pack, an extension of their successful
CMSIS (Cortex Microcontroller Software
Interface Standard) hardware abstraction.
CMSIS-Pack is a means of describing a device
to an IDE, making it possible for the IDE to
support software development without having
to build the functionality into their product. The
pack describes the source, header, and library
files, plus documentation,flash programming
algorithms, source code templates, and
example projects to the IDE so that it can
provide a world-class development
environment without the need for a new
revision of the software.
DAVE and PSoC Creator embrace the CMSIS-
Pack standard by including a function to
generate a pack file for the customers design.
This makes the integration between the
hardware configuration tool and the software
IDE natural and error-free. The hardware
engineer simply generates the pack file and
shares it with the software team. Updates to the
hardware are instantaneous no waiting for the
new board to arrive - because the new
configuration is simply loaded directly into the
software project.
breed of configurable device. The configurability
takes many forms, from devices with simple pin
multiplexing, to multi-core solutions like xCORE,
up to programmable systems-on-chip (PSoC)
that enable user configuration of powerful digital
and analog arrays.
In order to extract the most from these devices,
engineers need more from their development
tools. In addition to standards, like CMSIS, that
support interoperability between hardware and
software teams, they need component-level
design, and configuration interfaces that focus
on what the component does, rather than how it
is implemented in a given device. Most Figure 3: A
importantly they need tools that take advantage screenshot of the
of all these technologies without tying the Vision IDE from
developers to a single development tool for all ARM, showing a
steps of the process. ! DAVE3 Pack in the
Project Explorer
window.

When new hardware is required, the process of

handing over an updated board to the software
engineers is infamously problematic. A machine-
generated CMSIS-Pack takes away a lot of the
time-consuming job of updating software
projects to match the new board. To alleviate
this problem even further PSoC Creator
generates a datasheet for the users actual
design. The device configuration information,
clock setup, pin selections, and descriptions of
all generated component APIs can be output
into a single datasheet file, straight from the tool.
There is no risk of a cut-paste error or a
forgotten piece of information because the
document is machine-generated. It is clear that
the traditional MCU is being replaced with a new

electronicspecifier.com 35
Development Tools design

Getting to Market
Is the phrase Fast Time to Market on the working system: extract the motor parameters;
prepare the 3-phase software to drive the
side of an MCU starter-kit confidence- motor; tune the closed loop filters for speed
inspiring, or virtually meaningless now there and torque to the application specification, and
is so much more to think about? By Steve develop the MCU based hardware system for
Norman, Core Marketing Manager, Industrial the demonstration. Both Companies A and B
took a conventional approach to preparing
and Communications Business Group, the demonstration: adapting existing hardware
Renesas Electronics Europe to support the design; adapting existing
sensorless 3-phase software; extracting the
Todays market conditions dictate that when motor parameters using an RLC meter; tuning
choosing a microcontroller there is a lot of the current Pi filter using software and external
ancillary aspects that the engineer must oscilloscope to initially be able to turn the
consider, such as availability of reference or motor, and many man-hours to tune the
production software and hardware, safety software and Pi filters to get the necessary
certification, a clear graphical user interface speed and torque responses. While Company
(GUI), expert support, and developments from A delivered a working prototype on time it was
prime third party partners. Most of all,
though, there is the application to think
about. The job of the microcontroller
vendor today is to make the designer
successful as this makes the supplier
successful. As an example, lets
assume a company wants to develop a
ventilation system managing air flow
while eliminating vibration through low
speed operation. The system will
operate from 200RPM to 4000RPM at
800W, 400V, 1Nm torque and use a
brushless AC motor driven by a
sensorless 3-phase inverter.
Companies tendering must provide a
working demonstrator in four weeks,
and three companies tender: Company
A assigned their team of three
engineers to the task; Companies B
and C assigned a single engineer to
produce the demonstrator.

All three companies needed to perform

the same development and motor
tuning operations in order to produce a

36 electronicspecifier.com
design
over budget. Company B was late and was
not considered, but company C delivered a
working demonstrator on time and to
budget. So the question is what did
Company C do differently?
A different approach
Company C took a different approach as they
had little existing collateral available, so went
looking for a complete kit in order to meet the
development timescales and budget. They
selected a motor control kit which came
complete with professionally developed
sensorless 3-phase royalty-free reference
software, a hardware reference platform
including full schematics, bill of materials,
Gerber layout files and the option of a fully
compatible external high voltage inverter unit.
All the software is fully VDE certified and comes
complete with a development environment and
graphical interface. More than you might
expect to find in a low cost motor control
package. Its a good start, although for the
Figure 1: Starter-kit control board and GUI
Development Tools
demo there is no hardware design necessary;
only simple configuration of the MCU control
board for the external inverter.
The sensorless software system is ready to go,
but still needs to be adapted to work with the
motor (i.e. parameter extraction and tuning).
The engineer is familiar with motor control but
has limited experience in tuning motors, which
is one of the key factors in choosing the
Renesas kit; the software includes some
advanced motor tuning functions such as
automatic parameter identification for most 3-
phase brushless permanent magnet motors
and auto-tuning software for Pi filter (current)
design coefficients, all embedded in the MCU
source code and designed to operate under
the control of the PC GUI without the need for
any extra hardware. Even a digital oscilloscope
is included in the GUI so no need for any
external equipment apart from a mains plug.
Once the engineer had installed all the
necessary software and GUI, and the
kit was tested with the demonstration
motor supplied, he was ready to start
development using the customers
motor. It was decided that as the
motor was required to run down to
200RPM that the demo would use a
3-shunt system to limit the effects of
the low signal levels and provide
more stable operation at low speed,
thus no changes were necessary for
the inverter.
Once the GUI has connected with
the control board software the
parameter tuning functions Current
Pi tuning and Motor Identification
(Figure 2) are available to start the
process of configuring the software
to drive the motor together with the
tab to open a digital oscilloscope. A
few parameters need to modified
and added in Parameter settings
window (Figure 3) before starting the
auto tuning process.
electronicspecifier.com 37
Development Tools design
of the system and motor parameters during
operation, utilising the oscilloscope function to
Figure 2: PC analyse the waveforms as necessary. Using the
GUI tuning GUI and the embedded measurement software
took just a few minutes to complete, from GUI
launch to a running sensorless vector-
controlled motor. While the completed
development took a little longer, this allowed
the engineer ample time to get a working
demonstration to the customer on time, to
specification and within budget in order to win
the business for his company.

This study is based on the use of the Rotate-

it Motor Control Solution Kits available for the
RX100, RX200 and RX600 families of 32-bit
microcontrollers, which form part of the next-
generation solutions from Renesas
Electronics, embracing the philosophy of more
than just time to market, by providing
professional software and hardware reference
platforms combined with unique features to
provide designers with the tools to work
Once complete clicking on Current PI tuning effectively, efficiently and successfully in a
(AUTO) automatically calculates the variety of market areas, with a low entry cost.
proportional and integral coefficients for the
current Pi control filter in just a few seconds. The way forward
The results are stored in the software. At this Continuing with the theme of providing
point the dynamic response based on these solutions rather than just hardware and a few
coefficients can be checked manually with the basic peripheral driver examples, Renesas
oscilloscope, adjusting and retuning the Electronics recently introduced the RZ/A
parameters if necessary. family, featuring a 400MHz ARM Cortex-A9
core. Combined with FPU and encryption
Next the motor Stator resistance,
Stator and Synchronous Inductance
and Permanent Magnet flux need to
be measured. Again a simple click of
the Motor Identification button is all
that is required. Once complete the
system is ready to run the motor.
The system can then be run turning
the motor so that system tuning can
be completed and the system tested
with the motor under load
conditions. This usually takes a while
and is down to the experience of the
designer. The GUI still allows full
control, monitoring and adjustment Figure 3: GUI parameter settings

38 electronicspecifier.com
design
functions, the family includes a rich peripheral
set including communications interfaces for
Ethernet, CAN, IEBUS and USB together with
advanced graphics such as Image Rendering,
JPEG codec, NTSC/PAL processing
YUV/RGB conversion, audio processing IPs
for SCUX, CDROM decoding and sound
generation, plus large 10MB embedded
SRAM to improve system, video and audio
processing performance. When combined
with the leading software ecosystem, this
family is suited to the next generation of HMI
applications. With so many choices when it
comes to the software ecosystem, it is a
difficult choice of which to use and even more
so if looking to compare those of interest, but
thats not how next-generation HMI
development should work. A single solution kit
uniquely supporting solutions such as IS2T
JVM, TES GUIliani, Segger emWIN, Altia
Design and Express Logic GUIX, now exists to
support such applications, so the designer
can chose the preferred software and start
designing quickly saving time and cost.
Developers of complex communication
technology, such as narrowband OFDM
power line systems, face a different set of
problems, not least the requirement to
support many power line standards. For
example, supporting multiple rollouts of
smart meters based on different protocols in
different countries that use different
Development Tools
Figure 4: RZ/A
frequency bands and specifications. A board
flexible PLC modem solution is available
based on a highly integrated narrowband
modem with MAC controller, high
performance digital signal processor for
physical layer implementation, an embedded
analogue front end with adaptive gain
controlled amplifier and an embedded
AES128 hardware security engine. The
solution is combined with certified software
for standards such as PRIME and G3, giving
a leading power line solution meeting todays
market requirements.
Certified software can be a key factor in a
successful design, saving the
designer time and cost. For
certification of end products,
testing can be a huge proportion
of time and cost. If software is
provided that is certified to the
appropriate standard it means the
designer spends more time on
developing the application code.
This philosophy is being applied to
new kits in development such as
Wireless Meter Bus, Smart Analog
for IO-Link; multi-protocol
Industrial Ethernet; smart LED
lighting and more to come. !
electronicspecifier.com 39
Development Tools
Software as a Process
A single software product may comprise
multiple suppliers and sources, making
safety, security and performance processes
even more important. By Rod Cope,CTO,
Rogue Wave Software
The past year was a tipping point for the
software industry, where the impacts of code
faults in the field were felt far beyond the limited
confines of our own development teams.
Widespread automotive recalls and events such
as Heartbleed and GHOST hit home for all walks
of life, linking real safety and security issues to
the phrase its a software bug. There were
plenty of good stories (the Rosetta space probe
landing on a comet) to go with the bad stories
(the Target data breach, costing shareholders
$148 million), yet the overall responsibility is on
the industry to do better.
To provide some context, in the past ten years
the number of data breaches in the United
States has climbed steadily and will reach a
predicted peak of 800 instances in 2015 (see
Figure 1). In the automotive industry, over
900,000 vehicles are affected by recalls each
year, according to The Automobile Association in
Britain. These trends are not entirely surprising.
As companies try to one-up each other with
continual innovation and more features, with
outsourcing overtaking in-house development,
software complexity has gone far beyond our
ability to find bugs effectively.
The cornerstone of embedded development is
software, and software is where most errors
are introduced. Not only has the volume of
delivered code increased, the complexity and
variety of architectures, platforms and protocols
has increased too. This pushes the number of
permutations of state, behaviour, interactions
40 electronicspecifier.com
design
and outputs well beyond our capabilities to
test. And its not just the code itself, other
influences have affected our ability to deliver
solid, reliable products.
Todays software products are the result of many
suppliers, vendors, open source repositories and
legacy code coming together in a mix of different
processes, standards and cultures. Each input
offers a chance to introduce safety, security, or
performance-related errors. While some
integrators are good at enforcing consistent
standards and quality guidelines, most struggle
to achieve comprehensive testing across all
inputs that fits into tight timelines and cost
constraints. Trust and enforcement are the key
differentiators when it comes to the software
supply chain.
New ways
Whether its the shift towards agile, continuous
integration, or the adoption of new standards,
embracing new ways of developing software
hits organisations where it counts: the
delivered product. It takes time for teams to
understand and normalise new processes and,
for companies with limited resources, its very
likely that either quality or quantity (or both)
suffer. When you add in the risks associated
with different teams using different processes,
the possibility of a defect reaching the field is
even higher.
A relatively new source of increased
complexity is the Internet of Things. No longer
do software vendors have to worry only about
their own products, they need to account for
the potentially untested or unvalidated inputs
coming from other systems as well. For
example, the connected car opens up new
opportunities for attacking automotive
systems, such as remote connections through
design
in-vehicle infotainment systems and wireless
vehicle services. With these fault vectors and
more, its no wonder that software bugs are
making the headlines. The good news for
automotive is that other industries have figured
out strategies that can help stop defects from
getting out into the open.
Combating complexity
While some industries are very familiar with
coding and safety standards, others are just
beginning to adopt them, recognising that
standards give valuable goals to achieve and
measures of how to improve. Automotive
companies have been using coding and
safety standards, such as MISRA and ISO
26262, for some time now but they are just
starting to investigate how security
standards can help protect against hackers.
Adopting common, community-driven
security standards such as OWASP, CWE,
and DISA STIGs are essential for both
educating development teams on what
makes code secure and measuring how
secure their code actually is.
Development Tools
Most companies use open source to optimise
their engineering costs without realising the
potential risks to security, technical quality or
licensing liability. Moreover, many companies
may not even know where open source is used
or delivered, as its fairly easy for any developer
or supplier to include code without anyone
knowing about it.
To minimise the risks, companies should
adopt open source policies and governance
platforms that formalise the acquisition,
provisioning and tracking of open source
code. This helps eliminate inconsistencies
in versioning and licensing and tracks
where packages are deployed, so issues
can be isolated faster. Organisations can Figure 1: Security
also adopt open source scanning tools to breaches continue
identify where both the known and to grow (source:
unknown packages are, to identify potential Identity Theft
risks, and better inform testing activities. Its Resource Center,
also important to ensure that policies and analysis: Rogue
tools are consistent across the supply Wave IMSL
chain, otherwise the weak link may cause Numerical
rise to an issue. Libraries)
electronicspecifier.com 41
Development Tools
The threat of hackers, data loss, and system
downtimes persist across all industries, and with
the advent of more communications and
connections embedded systems are not as
protected as they once were. The challenge is
two-fold: educating development teams on how
code can be exploited, and adding testing
techniques to find potential security flaws before
theyre released. The most important point to
remember when it comes to security is be
paranoid. Dont trust inputs coming into the
system, place strict controls on suppliers and
ensure that all inputs are validated and restricted,
to protect code from malicious data and control.
One method that is proven to be successful in
mitigating security risks is using automated code
analysis to look for potential flaws. Capers Jones of
Namcook Analytics found that, without tools such
as static code analysis (SCA) in particular,
developers are less than 50 percent efficient at
finding bugs in their own software. SCA is adept at
understanding patterns and behaviours in code,
across multiple compilation units and developers,
to reveal security holes such as buffer overflows,
suspicious incoming data and unvalidated inputs.
More sophisticated SCA tools can also compare
code against common security standards, such as
OWASP and CWE, to determine gaps in coverage
or generate compliance reports. Rather than
convincing teams to spend more effort on security
testing, use tools to reduce the effort for you and
your suppliers.
The benefits of continuous integration and
testing have proven to be effective for many
organisations, allowing them to deliver more
robust features at a faster pace. The is the result
of putting the burden
of common or
complex
42 electronicspecifier.com Image courtesy of sheelamohan at FreeDigitalPhotos.net
design
development tasks onto tools that perform in the
context of frequent check-ins and builds. When
switching from traditional testing methods to
continuous integration, its critical to adopt these
kinds of tools to keep defect rates low and
developer frustration to a minimum. Its also
important for these tools to be as comprehensive
as possible, testing not only for technical defects
but security flaws and standards compliance as
well. Using the static code analysis example,
adopting a tool that covers all the programmatic,
security and standards bases as well as fitting
into a continuous integration model means
additional, costlier tools wont be necessary.
Complementary with continuous integration is
continuous improvement; how effective are these
measures and how can they be made better?
The first step is to establish metrics and develop
reports that help track defect trends (both
number and source), compliance to standards,
and developer activities to better understand
where the problems are and where effort is being
spent. Ideally this data is collected and reported
automatically by the development tools so the
teams dont have to worry about it.
The second step is to monitor trends, issues and
activities regularly, to be able to respond as
quickly as possible. For open source, using a
governance platform that alerts teams to security
vulnerabilities in open source packages is an
effective method for identifying problems early
and preventing flaws from getting into the
released product. This is especially important for
open source as most developers dont think
twice about the robustness of open source code
and rarely subject it to the same rigorous testing
as their own code.
The rapid growth in automotive complexity,
connectivity and the software supply chain
emphasises the importance of getting security,
safety and reliability under control as soon as
possible. Embracing techniques and adopting
tools that are proven in other industries will help
create systems that stay out of the headlines and
deliver a solid path for future innovation. !
design
Enabling world wide mobility
for the Internet of Things
Many semiconductor and technology companies
are basing their future growth on the Internet of
Things (IoT) and while this is a very broad term,
there are three main categories of devices:
communicating devices, cellular M2M, and
Internet of Objects (IoO). The volume of
connected devices is predicted to be more than
50 billion by 2020 and the majority of the volume
is predicted to be in the Internet-of-Objects or
low-power WAN (LPWAN) category.
The technology for communicating devices and
traditional M2M is well established and a good
solution for the target products, but it does not
serve well devices that need long battery lifetime,
outdoor connectivity, and low cost
operation. The Internet of
Objects category historically
has been highly fragmented
without an ideal technology
to serve the target
applications, therefore
limiting the serviceable
available market (SAM) of the
overall market segment.
Traditionally each application has deployed a
private network to serve its needs. For example a
smart-meter network is deployed to serve just
electric meters; a separate network is deployed
for street lighting, etc. Deploying a network for a
single application has limited the return on
investment (ROI) of many applications, therefore
limiting the volume of deployed nodes. The
Internet of Objects category is quickly shifting to
the public-network concept and is the main
target of LoRa technology from Semtech. In a
public network, a telecom operator or other party
will deploy a network over an entire country or
region, and offer use of the network to multiple
applications for a small monthly or yearly fee.
Wireless
How a long range, low-power spread spectrum
technology capable of supporting millions of
nodes could enable standardisation in the IoT.
By Hardy Schmidbauer, Semtech Corporation
This eliminates significant development cost,
eases design and deployment, and accelerates
time to revenue for the end-application company.
Frequency shift keying (FSK) modulation has
been used as the modulation of choice over
the past fifteen years for sub-GHz and 2.4GHz
applications due to its low power and low cost
implementation. While great for low power,
FSK modulation suffers in the
total link budget and
associated range.
Semtechs LoRa
modulation which is
integrated along with
traditional FSK in its
SX127x family utilises
the same low power RF
architecture as FSK but
delivers significantly longer range
and better interference immunity than FSK.
LoRa is a spread spectrum based technology
that has been used for years in different
applications, but Semtech is the first to make
a low cost implementation that is suitable for
battery-operated sensor networks. When
using a low cost bill of materials without an
expensive temperature controlled oscillator
(TCXO) LoRa increases the link budget by
more than 25dB compared to conventional
FSK systems. LoRa is capable of
demodulating 20dB below the noise floor and
when combined with integrated forward error
correction (FEC) it significantly increases the
immunity to interference.
electronicspecifier.com 43
Wireless
Standardising the IoT
With the increased link budget and range
capability of LoRa there is no need for a mesh
network architecture. A mesh network extends
the range of the network but comes at the cost
of reduced network capacity, synchronisation
overhead, and reduced battery lifetime due to
synchronisation and hops. To take full
advantage of LoRa properties Semtech
designed the gateway chip set and MAC to
permit a long range star architecture with
capacity to handle tens of thousands of nodes
per gateway chip (SX1301). Multiple SX1301
chips can be placed in parallel to create a
network with capacity to handle easily hundreds
of thousands of nodes communicating to a
single gateway over a 15km or greater radius
depending on the environment. To take
advantage of the spread spectrum orthogonally
of different spreading factors, adaptive link rate
is designed into the MAC to increase the
network capacity, optimise battery life, and
create a fully scalable system.
44 electronicspecifier.com
design
Like CDMA technology, using different
spreading factors permits simultaneous use of
a single channel by multiple different data rates
at the same time. Nodes which are close to the
gateway and dont require maximum link
budget will use a high data rate to minimise
their time on air; only nodes at the limit of the
range will use the lowest LoRa data rate and
highest output power. The other critical
advantage of adaptive link rate is that it creates
a scalable system. As the network starts to
reach its capacity limits, more gateways can be
deployed and the adaptive link will
automatically scale the end-node devices to a
higher data rate communicating with the
nearest gateways and therefore increasing the
network capacity. In current systems based on
FSK modulation with a single data rate, when
the network hits its capacity limit there is
nothing that can be done except tear it down
and deploy a new architecture.
The LoRa long range star network architecture
has a link budget 5-10dB more than cellular
systems and mimics existing cellular
architecture. This permits use of existing
elevated cellular base stations to be equipped
with LoRa gateways. With the additional link
budget of LoRa, the same coverage can be
achieved with the added benefit of in-building
and basement coverage. The LoRa network
architecture is demonstrated in Figure 1. The
design Wireless

gateway acts as a pass through or packet

forwarded and the network is managed by the
network server. Eliminating duplicate packets,
scheduling acknowledgement, and adapting
data rates is managed in the cloud by the
network server making it very easy to deploy
and manage a LoRa network.

The LoRa protocol (LoRaWAN) has been

developed by IoT industry leaders including
IBM, Actility, Semtech and Microchip and now
transferred to the LoRa Alliance. Its mission is
to standardise Low Power Wide Area
Networks (LPWAN) being deployed around
the world to enable IoT, M2M, and Smart City
and Industrial applications. The Alliance
members will collaborate to drive the global
success of the LoRa protocol (LoRaWAN), by
sharing knowledge and experience to
guarantee interoperability between Telecom
operators. For more information on the LoRa
Alliance visit LoRaAlliance.org.
The LoRa system provides a cost effective, low
power, and high capacity solution with ability to
connect hundreds of thousands of nodes in multi-
tenant architecture. Whether you are a large or
small volume user, Semtech has established an
infrastructure of partner solutions including
modules, gateways, and full system solutions
based on the LoRa technology. !

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Wireless
Going Global
New wireless technologies emerging in
response to demand from the IoT are now
augmenting global cellular networks,
bringing 5G one step closer. By
Guillaume Crinon, Business Development
Manager, Avnet Memec
Twenty years ago massive investment was made
by major telecom operators around the globe in
order to seamlessly connect people to one
another: Mobile Network Operators were born.
At the same time the Internet reached every
single neighbourhood and home: optimism and
enthusiasm in the new economy fuelled the
growth of the first telecom revolution and
dot.com bubble. Twenty years and two
economic crises later, everyone agrees that it has
been a success: half the worlds population owns
a cell phone or a smart phone, has fixed or
mobile Internet access, and is now accustomed
to spending monthly on a voice and data plan for
services which have truly become vital needs.
In order for the Mobile Network Operators
(MNO) and Mobile Virtual Network Operators
(MVNO) to maintain their Average Revenue
per User (ARPU), the service delivered to the
end-user has no other choice than to improve;
compensating for the data plan natural price
erosion. This is the reason why 2G, 2.5G,
2.75G, 3G and 4G have taken over one
another for the past twenty years, always
promising more bandwidth, higher mobility,
denser coverage, better quality of service.
With more SIM cards than inhabitants in most
developed countries, the market has reached
saturation. MNOs and MVNOs have therefore
been trying hard to develop a Machine-to-
46 electronicspecifier.com
design
Machine (M2M) market for the past ten years.
Given the cost of connectivity, the cost of the
modem, the inadequacy of the technology with
long-life low-cost battery-operated systems, this
M2M market relying on legacy cellular networks
is limited to a few verticals (automotive, tracking,
vending machines, point-of-sales, security, etc),
which can accommodate these constraints. This
nevertheless leaves the vast majority of objects
or things we live and work with unconnected.
Connecting them is the challenge of the IoT,
either indirectly through a gateway, be it a smart
phone or an Internet box, or directly under a
dedicated cellular network.
Technology needs
Looking at the way the 5G Public-Private
Partnership and Mobile and wireless
communications Enablers for the Twenty-twenty
Information Society (METIS) are defining the
needs for making our cellular networks evolve by
2020, it has become obvious that different
technologies will coexist in order to best address
the needs: amazingly fast calls for more
bandwidth and bit rate; great service in a crowd
could be served by repetitive broadcast
schemes; best experience follows you will require
sophisticated signal processing and network
architecture, while ubiquitous things
communicating calls for a simple, low-power,
low-cost technology thing coupled to an agile
easy-to-deploy network infrastructure.
Among the verticals not easily served by legacy
networks are: metering (water and gas meters);
industrial logistics (pallets); extended fleet
management (bicycles, trailers); security (smoke
detector, leak detection, anti-tampering);
environmental (waste containers, weather
stations); agriculture (irrigation, sensors); health
design
(pill box, social alarm), and many more
where battery life and connection cost
is a deterrent.
For all these applications, a WiFi or
Bluetooth Smart router may not be
available behind each and every
device to service a connection to the
Internet, while a 2G/3G connection
will hinder the profitability with higher
costs of connectivity and battery
replacement. Nonetheless, all these
applications have things in common: they are
required to report only a few bytes of data per
hour or per day; they tolerate a network latency
in the order of magnitude of the second; the
objects under the network need to neither be
connected nor synchronised to the network
since they sleep most of the time; the objects do
not need to talk to one another in peer-to-peer
mode; the objects mostly need to upload data to
the network, and they can tolerate missed
packets here and there.
Considering all these properties, it becomes
possible to build a very light network
infrastructure. Taking advantage of the low
bandwidth and latency tolerance means the
physical layer can operate at a very low bit rate (a
few kbit/s or less), yielding a higher link budget
and a longer communication range between the
object and a base-station, translating into wider
cells, lighter infrastructure to deploy, lower capex
and opex for the operator, and lower cost of
communication for the object. The latency
tolerance also offers the possibility of managing
Medium Access Control from the Cloud, and
potentially in future deployments even the
physical layer itself with enhanced diversity.
Not needing to remain synchronised or peer-
connected also mean that the objects can
operate asynchronously with one another and
that the network base-stations essentially
continuously listen to the objects broadcasting
randomly, while the predominance of uplinking
allows deploying a very effective network where
base-stations operate in half-duplex mode, with
Wireless
uplink and downlink bands sitting next to one
another in a license-free ISM band.
Emerging solutions
A number of solutions now exist that can
support such networks, including: narrow-band
FSK/MSK with WmBUS metering private
networks; LoRa by Semtech based on Chirp
Sequence Spread Spectrum; Random-Phase-
Multiple-Access by On-Ramp-Wireless, and
alternative Direct-Sequence-Spread-Spectrum
layers to be standardised by Silicon Labs and
others at the IEEE. In Europe, several utility
companies are deploying their private networks
dedicated to metering based on WmBUS.
Others, such as Actility relying on the LoRa
technology, are installing private networks for the
Smart Grid and the Smart City.
But only one company has taken the step to
actually raise funds to deploy and operate a truly
global and general purpose IoT network on the
basis of their Ultra-Narrow-Band Phase-Shift-
Keying: Sigfox.
There is little doubt that other telecom operators
relying on competing technologies will also
deploy their solutions in the years to come, and
that as soon as a few hundred million
connections are sold yearly worldwide, legacy
cellular operators will consider allocating a few
hundreds of kHz of their expensive spectrum to
a similar technology, paving the way of what 5G
will eventually bring to the Internet of Things;
ubiquitous low-cost and low-power Internet
connectivity for all our things. !
electronicspecifier.com 47
 Redefining
Industry Expectations
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