DLD Complete Lab Manual

DEPARTMENT OF ELECTRICAL ENGINEERING, CIIT-WAH
Lab Manual
Digital Logic Design
DEPARTMENT OF ELECTRICAL ENGINEERING

COMSATS INSTITUTE OF INFORMATION TECHNOLOGY
WAH CAMPUS
Spring 2015
1|Page Digital Logic Design

Table of Contents
Table of Contents ......................................................................................................... 2

1 Introduction: ........................................................................................................ 3
2 Personal Tools and Components ........................................................................ 4
3 Working Code ...................................................................................................... 5
4 Experiment No. 1: Analyze the Performance of a Given IC and Draw its Truth
Table. ............................................................................................................................. 6
5 Experiment No. 2: Implementation of Boolean Expression through Logic Gates
& also verification of Demorgans Law. ..................................................................... 12
6 Experiment No. 3:Implement XOR and XNOR gates using NAND gates........ 17
7 Experiment No. 4: Write the truth table for a half adder (inputs A, B; output
SUM, CARRY) from the truth table designs a logic circuit that will act as a half adder
(using only NAND gates). ........................................................................................... 23
8 Experiment No. 5: Implement Full Adder using minimum number of two input
gates (no NAND gate). ................................................................................................ 27
9 Experiment 6: Implement Full Subtractor using minimum number of two input
gates (no NAND gate). ................................................................................................ 33
10 Experiment No. 7: Design the BCD-to-seven-segment decoder circuit. ........... 38
11 Experiment No. 8: Design circuit that converts BCD to Excess code using 4 bit
full adder. ..................................................................................................................... 44
12 Experiment No. 9: Design circuit 4 x 1 MUX, 2 x 4 DECODER and 4 x 2
ENCODER using AND, OR and NOT gates............................................................... 48
13 Experiment No. 10: Analysis of RS flip flop using NAND and NOR gates. .. 56
14 Experiment No. 11: Analysis of JK flip-flop using D Flip-Flop. ..................... 61
15 Experiment No. 12: Design a 2-bit binary counter using JK flip-flop. ............. 65
16 Experiment No. 13: Analysis of a 4-bit synchronous Decade Counter. ........... 71
17 Experiment No. 14: Analysis of a 4-bit Asynchronous Decade Counter. ........ 75
18 Appendix A: Use good construction practices ................................................... 79
19 Appendix B: Troubleshooting ............................................................................ 80
20 Appendix C: Safety ............................................................................................ 81

1 Introduction:
The primary purpose of this laboratory is to improve your ability to design, build,
characterize and troubleshoot electronic circuits. A secondary objective is to demonstrate
principles that you have covered in other classes. A third objective is to improve your written
and oral communication skills. A forth objective is to develop team skills by working on an
engineering team to develop a prototype of a product. The skills you develop in this
laboratory should make you a more valuable hardware engineer and improve your
interviewing skills. Much of the emphasis will be on very practical ideas that are not covered
in text books but are based on industrial experience. You will also consider marketing and
economic issues, efficiency, producibility, reliability and product safety. You will design
electronic circuits to meet certain electrical and economic specifications. As a team you learn
about scheduling time and resources to finish objectives on time. Laboratory safety and ESD
prevention will be stressed.
You will have opportunities to work alone and with a partner but much of your grade for the
course will depend on the performance of your "engineering team". This team will consist of
about 4 students. Teamwork, scheduling, organization and productivity will be important to
realize the design objectives of the course.
It is important for you to share your problems and solutions with the class and your instructor.
Your grade will depend on your end results. Recognizing problems and getting help to solve
them if needed is very important. You often learn more by correcting a mistake or learning
about another group's problems and solutions than you do when everything "plugs-and-plays".
If something doesn't seem right or is confusing to you, be sure to figure it out and get help if
needed. Mistakes in the laboratory are expected if you are working on something significant,
and if you learn from them you'll make fewer and fewer errors as you gain experience.
The details of the laboratory procedures, reports, prelab work, and grading will be covered by
your laboratory instructor during the laboratory sessions. As mentioned earlier frequent
discussions of your ideas, progress and problems with your instructors will save time in the
end and should result in a better design. You are expected to attend all lecture sessions and the
beginning of each laboratory period for your section.
Students with good laboratory skills and experience are encouraged to work with weaker
students; both will benefit. Preparations for experiments are important and will be checked.

2 Personal Tools and Components
We suggest that every student have the following tools and equipment:
Tools
Miniature flush cutters (electronic grade)
Wire strippers (12-26 AWG)
Small tool box (with engraved name)
Small screwdriver set (regular and Phillips)
Tweaker screwdriver for trimmer adjustments
3-in-1 wire wrap tool (hand tool which strips, wraps and unwraps)
Small soldering iron (for personal projects!)
Miscellaneous
Breadboard (Proto, Elite, etc.)

Dissecting Probe (for making test connections)
Electronic grade cored solder
Solder-wick (to remove solder from IC pins, etc.)
Test Leads (Clip leads)
Straight Edge (Long enough to rule a vertical line down a page of your notebook)
Components
You may obtain components for this lab from any source. Lab II kits will NOT be sold by
IEEE because selecting components for most of your designs is an important part of the
project. Since the experiments vary from group to group you should plan ahead for your
needs. Components can be checked out from the Electronics Shop near the laboratory for new
designs and some components are available in the laboratory. If you plan ahead you can get
many components as samples via the Internet. Design around available components but note
in your report and notebooks how performance could be improved with different components.

3 Working Code
WORK AREAS WILL BE KEPT CLEAN AND NEAT. At the end of each
laboratory period return all books, components and instruments that are not normally
located at your bench to their proper locations. Clean off the working surface of the
bench and put the litter into the waste can.
ABUSE OR MISUSE OF EQUIPMENT: Treat all equipment with respect and

care. If you are not sure how to operate a piece of equipment then read the manual.
LABORATORY REFERENCE MATERIAL: There is a large variety of reference

books, data books, and equipment manuals on the laboratory bookshelves. Please
replace these on the shelves after you have finished with them.

Digital Logic Design Laboratory

COMSTATS Institute of Information Technology
Department of Computer Engineering
Fall 2004
4 Experiment No. 1: Analyze the Performance of a Given IC and Draw its Truth
Table.
4.1 Apparatus:
Logic trainer
Connecting wires
14 pin ICs (7408, 7400, 7432, 7402, 7486, 74266, 7404)
Power supply
4.2 Theory:
There are about half a dozen different types of basic components (called logic gates)
used in digital electronics such as AND, OR, NOT, NAND, NOR and XOR and
NXOR etc (for details on these gates refer to course text book). If we take off the
cover of a piece of digital electronics, we will not see these gates. Instead, we find flat
boards with integrated circuits fixed to it. These integrated circuits may contain
hundred or thousands of logic gates. We can, however, get integrated circuits that
only contain a few logic gates, typically four or five for using in our experiments.
4.3 Calculations:
Following is the truth table for the above mentioned logic gates. Fill in the truth table
and get it signed by the instructor before starting the lab.
InputA InputB AND NAND OR NOR XOR XNOR NOT
Table1.1: Truth table for logic gates
Signature: ------------------------------
4.4 Procedure:
Get the ICs and other required apparatus from the lab attendant. Always touch
the metallic material such as stool legs before handling the electronic stuff. Plug in the
IC in the breadboard of the Logic Trainer and while doing so; try to avoid touching
the IC pins for safety reason. Apply 5dc power supply and ground on pins 14 and 7
respectively. The IC used has four gates each having two inputs (quad 2- in). Pin

number 1 and 2 are inputs whereas pin 3 is output of the gate. Similarly, input pair for
other gates are 4and 5, 8 and 9, 11 and 12 and the output is obtained from pin number
6, 10 and 13 respectively. Once you have wired the circuit, check it with your
instructor. If approved, power up your circuit. The output should be connected to the
LED on the Logic Trainer for monitoring purpose. Apply different input combinations
at the input and note down the corresponding output and fill in the following truth
table. From this truth table, you should be able to deduce the type of gates IC in use is
comprised of.
Same procedure will be repeated for all the ICs and in all the truth tables will be filled
in. Keep in mind any special instruction from your instructor regarding pin
configuration.
4.5 Observations:
1. IC Number: -----------------------------
Truth Table:
Input 1 Input 2 Output
Table1.2: Truth table for first IC
Type of gate in the IC is: -----------------------------
2. IC Number: -----------------------------
Truth Table:
Table1.3: Truth table for second IC
3. IC Number: -----------------------------
Truth Table:

Table1.4: Truth table for third IC
4. IC Number: -----------------------------
Truth Table:
Table1.5: Truth table for fourth C
5. IC Number: -----------------------------
Truth Table:
Table1.6: Truth table for fifth IC
6. IC Number: -----------------------------
Truth Table:

Table1.7: Truth table for IC
7. IC Number: -----------------------------
Truth Table:
Table1.8: Truth table for seventh t IC
4.6 Results:
S.No. IC Number Type of Gate
Table1.9: Result summary

INSTRUCTOR VERIFICATION SHEET
For each verification, be prepared to explain your answer and respond to other
related questions that the lab TAs or Professors might ask.
Name: Date of Lab:
Q. No. 01
Q. No. 02
10 | P a g e Digital Logic
Design
Verified: Date/Time:
Design

Fall 2004
5 Experiment No. 2: Implementation of Boolean Expression through Logic Gates

& also verification of Demorgans Law.
5.1 Apparatus:
Logic Trainer
Connecting Wires
Power Supply
14 pin ICs [ AND, OR, NOT]
5.2 Theory:
Boolean algebra is an algebra that deals with binary variables and logic operations. A
Boolean function described by an algebraic expression consists of binary variables,
the constants 0 and 1, and the logic operations symbols. For a given value of the
binary variables, the function can be equal to either 1 or 0.
5.3 Procedure:
Consider as an example for the following Boolean function:
F1 =x + y`z
The function F1 is equal to 1 if x is equal to 1 or if both y` and z are equal to 1, F1 is
equal to 0 otherwise. The complement operation dictates that when y`=1 then y=0.
Therefore, we can say that F1=1 if x=1 or if y=0 and z=1. A Boolean function
expresses the logical expression for all possible values of the variables.
A Boolean function can be represented in a truth table. A truth table is a lost of

combinations of 1s and 0s assigned to the binary variables and a column that shows
the value of the function for each binary combination. The number of rows in the truth
table is 2n, where n is the number of variables in the function. The binary
combinations for the truth table are obtained from binary numbers by counting from 0
through 2n-1. Following table shows the truth table for the function F1.
Truth Table for F1

X y z F1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
Design
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Table 2.1: Truth table for F1
Figure 2.1: Gate implementation of F1=x+y`z
5.3.1 Simplify the simpler expression for this Boolean function
By manipulating a Boolean expression according to Boolean algebra rules, it is

sometimes possible to obtain a simpler expression for the same function and thus
reduce the number of gates in the circuit and the number of inputs to the gate.
Consider for example the following function:
F2= x`y`z + x`yz +xy`
x Y z F2
Table 2.2: Truth Table for F2
Signature: ________________
Design
Implement the logic diagram for the function F2
Signature: ________________
5.3.2 Verify Demorgans Theorem
Demorgans law can be stated in terms of logic terms, which is the 1st law states that,
(x+y)`= x`y`
And the second law state that
(xy)`= x`+ y`
Truth Table that verifies the above given Theorem 1,
x y (x+y)` x`+ y`
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
Table 2.3: Truth Table of (x+y)`=x` +y`
Logic Diagram for 1st Demorgans Law:
Figure 2.2:Logic Diagram of (x+y)`=x` +y`
Design
Table 2.4: Truth Table that verifies the above given Theorem 2
Implement the logic diagram for the 2nd Demorgans Theorem:
5.4 Conclusion:
Truth tables for Demorgans Theorem are verified also Logic diagram
5.5 Precautions:
Use the lab apparatus carefully
Always connect IC in breadboard more carefully
Before plugging the power on it, its better to check the complete circuit to
instructor
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design

Fall 2004
6 Experiment No. 3:Implement XOR and XNOR gates using NAND gates.
6.1 Apparatus:
Logic trainer
Connecting wires
14 pin ICs (7400)
Power supply
6.2 Theory:
Digital circuits are more frequently constructed with NAND and OR gates
than with AND and OR gates. NAND and NOR gates are easier to fabricate with
electronic components and are the basic gates used in all IC digital logic families. The
graphic symbols for XOR, XNOR and NAND gates together with their algebraic
functions are given below:
Figure 3.1: Logic gates
Truth Table for XOR gate:
Input A Input B Output F

0 0 0
0 1 1
1 0 1
1 1 0
Table3.1: Truth table for XOR gate
The NAND logic diagram for XOR is obtained from Boolean function in the
following way:
1. The implementation of a XOR function with NAND gates requires that the
function be simplified in the sum of products form.
F = AB + AB equation. 2.1
Design
2. Draw a NAND gate for each product term of the function that has at least two
literals. This constitutes a group of first level gates.
Figure 3.2: First level gates
3. Draw a single NAND gate with in the second level, with inputs coming from
the outputs of first-level gates.
Figure 3.3: Second level gates
4. A two input NAND gate can be used as inverter by applying logic 1 at one of
the inputs.
Figure 3.4: NAND implementation of XOR gate
6.3 Calculations:
Fill in the truth table for the XNOR function:
Design
Table3.2: Truth table for XNOR gate
Write Boolean function for XNOR gate:
F = ------------------------
Draw NAND logic diagram for the XNOR gate:
6.4 Procedure:
It is clear from the logic diagram that the NAND gate implementation of XOR gate
requires five NAND gates. You will need two quad- 2 in NAND gate ICs to perform
this experiment. Get the required number of ICs containing NAND gates and other
apparatus from the lab attendant. Plug in the ICs in the breadboard of the Logic
Trainer. Connect 5Vdc power supply and ground on pins 14 and 7 respectively. For
other pin configuration consult the data sheet (we have already used NAND gates in
the first lab so it should not be a problem). Wire your circuit according to the logic
diagram for XOR gate as given above. Once you have wired the circuit, check it with
your instructor and, if approved, power up your circuit. The outputs should be
connected to the LEDs on the Logic Trainer for monitoring purpose. Apply different
input combinations at the input and note down the outputs and fill in the following
truth table. This truth table should conform to the one given in theory. If there are
problems, consult the appendix on troubleshooting given at the end of lab manual. If
the problem persists, request lab supervisor for help.
Repeat the same procedure for NAND gate implementation of XNOR gate.
Design
6.5 Observations:
Fill in the following truth table in the presence of the lab lab instructor.
Truth Table for XOR Gate:
Table3.3: Truth table for XOR gate
Signature: --------------------
Truth Table for XNOR Gate:
Table3.4: Truth table for XNOR gate
Signature: --------------------
6.6 Conclusions:
The truth tables shows XOR and XNOR gates can be implemented by using
NAND gates only.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
Design

Fall 2004
7 Experiment No. 4: Write the truth table for a half adder (inputs A, B; output
SUM, CARRY) from the truth table designs a logic circuit that will act as a half
adder (using only NAND gates).
7.1 Apparatus:
Logic trainer
Connecting wires
14 pin ICs (7400)
Power supply
7.2 Theory:
The half adder circuit to be designed is an example of combinational logic circuits
for a digital system. A combinational circuit consists of logic gates whose outputs
at any time are determined directly from the present combination of inputs.
Addition is one of the most basic arithmetic operations performed by a digital
computer for information processing.
A half adder is combinational circuit that performs the addition of two bits. From
the definition it is clear that this circuit needs two inputs and two outputs. The
inputs are augend and addend; outputs are sum and carry. Once the number of
inputs and outputs are established, it is an easy task to formulate a truth table to
identify the function of half adder.
7.3 Calculations:
Fill in the truth table for half adder:
Input A Input B CARRY SUM
Table4.1: Truth table for half adder
Write the simplified sum of products expression for SUM and CARRY:
SUM = ------------------------------
Design
CARRY = ------------------------------
Draw the logic diagram of half adder using AND-OR gates:
Write down the equivalent expression for implementing with NAND gates only:
SUM = ------------------------------
CARRY = ------------------------------
Draw the logic diagram of half adder using NAND gates:
7.4 Procedure:
Count the number of NAND gates for the implementation of the half adder. Get the
required number ICs containing NAND gates and other apparatus from the lab
instructor. Plug in the ICs in the breadboard of the Logic Trainer and while doing so;
try to avoid touching the IC pins for safety reason. Connect 5Vdc power supply and
ground on pins 14 and 7 respectively. For other pin configuration consult the data
sheet (we have already used NAND gates in the first lab so it should not be a
problem). Wire your circuit according to the logic diagram you have drawn. Once you
have wired the circuit, check it with your instructor and, if approved, power up your
circuit. The outputs should be connected to the LEDs on the Logic Trainer for
monitoring purpose. Apply different input combinations at the input and note down
the CARRY and SUM outputs and fill in the following truth table. This truth table
Design
should conform to the one given in theory. If there are problems, consult the appendix
on troubleshooting given at the end of lab manual. If the problem persists, request lab
supervisor for help.
7.5 Observations:
Input A Input B CARRY SUM
Table4.2: Truth table for Half adder
7.6 Conclusions:
The truth table shows that SUM (X-OR) and CARRY (AND) can be obtained by
using only NAND gates and which is performed in this experiment.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design

Fall 2004
8 Experiment No. 5: Implement Full Adder using minimum number of two input
gates (no NAND gate).
8.1 Apparatus:
Logic trainer
Connecting wires
14 pin ICs (7486, 7408, 7432)
Power supply
8.2 Theory:
A combinational circuit that performs the addition of three bits is a called a full adder.
Two half adders can be employed to implement a full adder. It consists of three inputs
and two outputs. Two of the inputs are the two significant bits to be added and third
input is the carry from the previous lower significant position. Two outputs are
necessary because the arithmetic sum of three digits ranges from in value from 0 to 3
and binary 2 or 3 needs two digits.
8.3 Calculation:
There are three inputs, which have eight possible combinations of 1s and 0s. The 1s
and 0s for the output are determined from the arithmetic sum of the input bits.
Truth Table for Full Adder:
Input A Input B Input C SUM CARRY

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table5.1: Truth table for full adder
The SUM output is equal to 1 when only one input is equal to 1 or when all three
inputs are equal to 1. The CARRY output is 1 when two or three inputs are equal to 1.
Design
The input-output logical relationship of the full adder circuit may be expressed in two
simplified Boolean functions, one for each SUM and CARRY.
SUM = ABC+ABC+ABC+ABC Equation (4.1)

CARRY = AB+AC+BC Equation (4.2)
The implementation of full adder in sum of product is shown below:
Figure 5.1: Logic diagram for full adder
This implementation of full adder nine gates and the product-of-sums implementation
requires the same number of gates with AND and OR gates interchanged.
A full-adder can be implemented with two half-adders and one OR gate. A half-adder
performs the addition of two bits and full adder performs the addition of three bits.
Hence first half adder is performs the addition of augend and addend and the result is
added to the carry using another half adder. We know that half-adder output is given
by:
SUMhalf = A B
SUMfull = (A B) C
And CARRY output will be one only if one of the input and previous carry is one or
both the inputs are 1:
CARRY = (A B) C + AB
The implementation of of full adder using half adder is shown below:
Design
Figure 5.2: Implementation of full adder using two half adders
This implementation requires only five gates and, hence, is the required
implementation with minimum gates.
8.4 Procedure:
In this full adder two AND gate, one OR gate and two XOR gates are used. Get the
required ICs and other apparatus from the lab attendant. Plug in the ICs in the
breadboard of the Logic Trainer and while doing so; try to avoid touching the IC pins
for safety reasons. Connect 5Vdc power supply and ground on pins 14 and 7
respectively. For other pin configuration consult the data sheet (we have already used
these gates in the first lab so it should not be a problem). Wire your circuit according
to the logic diagram you have drawn. Once you have wired the circuit, check it with
input combinations at the input and note down the CARRY and SUM outputs and fill
in the following truth table. This truth table should conform to the one given in
theory. If there are problems, consult the appendix on troubleshooting given at the end
of lab manual. If the problem persists, request lab supervisor for help.
8.5 Observations:
Fill in the following truth table while observing the output. The circuit should show
the required functionality and verify the truth table in the presence of lab instructor.
Input A Input B Input C SUM lamp CARRY lamp
Table5.2: Truth table for full adder
8.6 Conclusions:
The experiment is performed according to given task i.e. using minimum number of
gates without NAND gate.
Design
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
Design

Fall 2004
9 Experiment 6: Implement Full Subtractor using minimum number of two input

gates (no NAND gate).
9.1 Apparatus:
Logic trainer
Connecting wires
14 pin ICs (7486, 7408, 7432, 7404)
Power supply
9.2 Theory:
A combinational circuit that performs a subtraction between two bits taking into
account that a 1 may have been borrowed by a lower significant stage. This circuit has
three inputs and two outputs. The three inputs are minuend, subtrahend and previous
borrow and two outputs are difference and borrow.
The subtraction of two binary numbers may be accomplished by taking the

compliment of the subtrahend and adding it to minuend. By this method, the
subtraction operation becomes an addition operation requiring full-adders for its
implementation. Each subtrahend bit of the number is subtracted from its
corresponding significant minuend bit to form a difference bit. If the minuend bit is
smaller than the subtrahend bit, a 1 is borrowed from the next significant position.
The fact that a 1 has been borrowed must be conveyed to the next higher pair of bits
by means of a binary signal coming out of a given stage and going into next higher
stage.
9.3 Calculations:
There are three inputs, which have eight possible combinations of 1s and 0s. The 1s
and 0s for the output are determined from the arithmetic difference of the input bits.
Truth Table for full subtractor:
Input A Input B Input C DIFFERENCE BORROW

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
Design
1 1 1 1 1
Table6.1: Truth table for full subtratcor
The 1s and 0s for the output are determined from the subtraction of A-B-C.
The input-output logical relationship of the full adder circuit may be expressed in two
simplified Boolean functions, one for each SUM and CARRY.
DIFFERENCE = ABC+ABC+ABC+ABC Equation (5.1)

BORROW = AB+AC+BC Equation (5.2)
We can note that the logic function for the output DIFFERENCE in the full
subtraction is exactly the same as output SUM in the full adder. Moreover, the output
BORROW resembles the function for CARRY in full adder, except that the input
variable A is complemented. Hence, it is possible to to convert a full-adder into full-
subtractor by merely complementing input A prior to its application to the gates that
form the carry output.
DIFFERENCEfull = (A B) C Equation (5.3)
BORROWfull = (A B) C + AB Equation (5.4)
Figure 6.1: Implementation of full subtratcor

9.4 Procedure:
In this full-subtractor two AND gate, one OR gate, one invertor and two XOR gates
are used. Get the required ICs and other apparatus from the lab attendant. Plug in the
ICs in the breadboard of the Logic Trainer and while doing so; try to avoid touching
the IC pins for safety reasons. Connect 5Vdc power supply and ground on pins 14 and
7 respectively. For other pin configuration consult the data sheet (we have already
used these gates in the first lab so it should not be a problem). Wire your circuit
according to the logic diagram you have drawn. Once you have wired the circuit,
check it with your instructor and, if approved, power up your circuit. The outputs
should be connected to the LEDs on the Logic Trainer for monitoring purpose. Apply
different input combinations at the input and note down the DIFFERENCE and
BORROW outputs and fill in the following truth table. This truth table should
conform to the one given in theory. If there are problems, consult the appendix on
Design
troubleshooting given at the end of lab manual. If the problem persists, request lab
supervisor for help.
9.5 Observations:
Fill in the following truth table while observing the output. The circuit should show
the required functionality and verify the truth table in the presence of lab instructor.
Input A Input B Input C DIFFERENCE BORROW
Table6.2: Observed truth table for full subtratcor
9.6 CONCLUSION
The experiment is performed according to given task i.e. using minimum number
of gates without NAND gate.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
Design

Fall 2004
10 Experiment No. 7: Design the BCD-to-seven-segment decoder circuit.
10.1 Apparatus:
Logic trainer
Connecting wires
14 pin ICs
Seven-Segment Display
IC7447
Power supply
10.2 Theory:
For this laboratory, the combinational logic circuit is used to convert a four-bit binary
coded decimal (BCD) value to the signals required for a seven-segment display.
BCD-to-seven-segment decoder is a combinational circuit that accepts a decimal digit
in BCD (binary-coded decimal) and generates the appropriate output for selection of
segments in a display indicator used for displaying the digit. The seven outputs of the
decoder (a, b, c, d, e, f, g, h) select the corresponding segment in the display as shown
in figure:
f b
g
e c
d
Figure 7.1: Seven Segment display
You are likely familiar with the idea of a seven-segment indicator for representing
decimal numbers. Each segment of a seven-segment display is a small light-emitting
diode (LED) or liquid-crystal display (LCD), and a decimal number is indicated by
lighting a particular combination of the LED's or LCD's elements is shown below:
Design
a a a a a
f b f b f b f b f b
g g g g g
e c e c e c e c e c
d d d d d
a a a a a
f b f b f b f b f b
g g g g g
e c e c e c e c e c
d d d d d
Figure 7.2: Indication of decimal number on Seven Segment display
Bindary-coded-decimal (BCD) is a common way of encoding decimal numbers with 4

binary bits as shown below:
BCD Code Decimal Digit
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
Table 7.1: BCD encoding

10.3 Calculations:
Fill in the truth table for seven segment device whose display elements are active low.
That is, each element will be active when its corresponding input is '0'.
Truth Table:
Inputs Outputs
A B C D a B c d e f g h
Design
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
Table 7.2: Truth table for seven-segment display
Rest of bit combinations are used with dont care condition.
Write down the simplified Boolean function for each decoder output:
a = ----------------------------------
b = ----------------------------------
c = ----------------------------------
d = ----------------------------------
e = ----------------------------------
f = ----------------------------------
g = ----------------------------------
h = ----------------------------------
Draw the logic diagram for the above outputs.
Design
10.4 Procedure
Get the required ICs and other apparatus from the lab attendant. Install the seven-
segment display, ICs and resistors on the breadboard of the Logic Trainer. Connect
5Vdc power supply and ground on pins 14 and 7 respectively. For other pin
configurations consult the data sheet (we have already used these gates in the first lab
so it should not be a problem). The display has 7 inputs each connected to an LED
segment. All the anodes of LEDS are tied together and joined to 5V. (This type is
called common Anode type). A limiting resistance(1 kohm) network must be used at
the inputs to protect the 7-segment unit from overloading. Wire your circuit according
to the logic diagram you have drawn. Connect each output of your circuit to
appropriate input of 7 segment display unit. Once you have wired the circuit, check it
with your instructor and, if approved, power up your circuit. The outputs should be
connected to the LEDs on the Logic Trainer for monitoring purpose. By applying
BCD codes verify the displayed decimal digits. If there are problems, consult the
appendix on troubleshooting given at the end of lab manual. If the problem persists,
request lab supervisor for help.
Repeat the same lab by using decoder IC. In this experiment only one IC is used. The
IC used is 16 pin IC, model 7447. The IC is designed in such a way that pin number 8
is considered as ground and power is given to pin number 16 (for rest of pins
description consult data sheet). The 7447 BCD to Decimal Decoder is a common
anode, that is, produces outputs that are active low.
10.5 Conclusion
The experiment is performed according to given task i.e. using minimum number of
gates.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
Design

Fall 2004
11 Experiment No. 8: Design circuit that converts BCD to Excess code using 4 bit
full adder.
11.1 Apparatus:
Logic trainer
Connecting wires
IC7483
Power supply
11.2 Theory:
The excess-3 code for a decimal digit is the binary combination corresponding to the
decimal digit plus 3. For example, the excess-3 code for decimal digit 5 is the binary
combination for 5 + 3 = 8, which is 1000.
11.3 Calculations:
The excess-3 code use four bits to represent each decimal digit, there must be four
input variables and four output variables. Designate the inputs by A,B,C,D and the
outputs by W,X,Y,Z. The truth table relating the input and output variables will have
six combinations that will be dont cares.
Input Output
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Table8.1: Truth table for excess 3 code
The function will be implemented using IC model 7483, which has one four bit full adder.
One of the inputs set (augends) to four bit full adder is BCD code whereas the other set of
inputs is 0110 (addend) as shown in figure:
Design
A 0 B 0 C 1 D 1
FA FA FA FA
0
W X Y Z
Figure 8.1: Implementation of excess 3 code with four bit adder
11.4 Procedure:
Get the required ICs and other apparatus from the lab attendant. Install the ICs on the
breadboard of the Logic Trainer. . The IC used is 16 pin IC, model 7483. The IC is
designed in such a way that pin number 12 is considered as ground and power is given
to pin number 5. For rest of the pin configurations consult the data sheet. Wire your
circuit according to the logic diagram. Connect each output of your circuit to the
LEDs on the Logic Trainer for monitoring purpose. Once you have wired the circuit,
check it with your instructor and, if approved, power up your circuit. By applying
BCD codes verify the excess-3 code displayed by the LED. If there are problems,
consult the appendix on troubleshooting given at the end of lab manual. If the
problem persists, request lab supervisor for help.
11.5 Conclusion:
The experiment is performed according to given task i.e. using 7483 MODEL
IC.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
Design

Fall 2004
12 Experiment No. 9: Design circuit 4 x 1 MUX, 2 x 4 DECODER and 4 x 2

ENCODER using AND, OR and NOT gates.
12.1 Apparatus:
Logic trainer
Connecting wires
IC
Power supply
12.2 Theory:
Multiplexing means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. Normally, there are 2n input lines and n selection line whose bit combination
determines which input is selected. A 4-lines to 1-line multiplexer has four input
lines, two select lines and one output as shown in block diagram below:
Inputs 4 X1
Output
MUX
Select
Figure 9.1: 4 1 mux
A decoder is a combinational circuit that converts binary information from n input

lines to to maximum of 2n unique output lines. The decoders are represented as n-to-
m where n is number of inputs and m is number of outputs. Hence, 2-to-4 decoder
means that two inputs are decoded into 4 outputs.
D0
A
D1
2x4
Decoder
D2
B
48 | P a g e D i D3
gital Logic
Design
Figure 9.2: 2 4 decoder
An encoder is a digital function that produces a reverse operation from that of a

decoder. An encoder has 2n input lines and n output lines. The output lines generate
the binary coder for the 2n input variables.
D0
A
D1
2x4
Decoder
D2
B
D3
Figure 9.3: 2 4 encoder
12.3 Calculations:
The function table of the 4-line to 1-line multiplexer is shown in figure. The function
table lists the input-to-output path for each possible bit combination of selection lines.
Each of the four input lines A to D is applied to one input of an AND gate. Selection
lines s1 and s0 are decoded to select a particular AND gate.
Select inputs Output

s1 S0 Y
0 0 A
0 1 B
1 0 C
1 1 D
Table 9.1: Truth table for 4 1 mux
Each of the four input lines A to D is applied to one input of an AND gate. Selection
lines s1 and s0 are decoded to select a particular AND gate as shown in the logic
diagram below:
Design
Figure 9.4: Implementation of mux

In order to understand the operation of the circuit, consider the case when s1s0 = 10.
The AND gate associated with input C has two of its inputs equal to 1 and third input
connected to C. The other three AND gates have at least one input equal to 0, which
makes their output equal to 0. The OR-gate output is now equal to the value of C.
The truth table of 2-to-4 line decoder is given below. The output variables of a
decoder are mutually exclusive because only one output can be equal to 1 at any time.
Inputs Outputs
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Table 9.2: Truth table for 2 4 decoder
Draw the logic diagram of 2-to-4 decoder.
Design
The truth table for 4-to-2 encoder is given below
Inputs Outputs
D0 D1 D2 D3 X Y
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
Table 9.3: Truth table for 4 2 endecoder
In encoders, only one input line can be equal to one at any time. The circuit has four
inputs and could have sixteen possible input combinations. Only eight of these
combinations have any \meaning. The other combinations are dont-care conditions.
Draw the logic diagram for the encoder circuit.
12.4 Procedure:
We will implement the multiplexer circuit first. It is clear from the logic diagram that
the AND, OR and NOT gate implementation of multiplexer requires four 3-input
AND gates, one 4-input OR gate and two NOT gates. Get the required number of ICs
containing above mentioned gates and other apparatus from the lab attendant. Install
the ICs in the breadboard of the Logic Trainer. All three IC models used are 16 pin
ICs. These are designed in such a way that pin number 8 is considered as ground and
power is given to pin number 16. For other pin configuration consult the data sheet
(we have already used these gates in the first lab so it should not be a problem). Wire
your circuit according to the logic diagram for multiplexer circuit as given above.
Once you have wired the circuit, check it with your instructor and, if approved, power
up your circuit. The outputs should be connected to the LEDs on the Logic Trainer for
monitoring purpose. Apply different input combinations at the input and note down
the outputs and fill in the following truth table. This truth table should conform to the
Design
one given in theory. If there are problems, consult the appendix on troubleshooting
given at the end of lab manual. If the problem persists, request lab supervisor for help.
Repeat the same procedure for decoder and encoder circuit.
12.5 Observations:
Fill in the following truth tables while observing the outputs.
Truth table for multiplexer:
Select inputs Output

s1 S0 Y
Table 9.4: Observed truth table for 4 1 mux
Truth table for decoder:
Inputs Outputs
A B D0 D1 D2 D3
Table 9.5: Observed truth table for 2 4 decoder
Truth table for encoder:
Inputs Outputs
D0 D1 D2 D3 X Y
Design
Table 9.6: Observed truth table for 4 2 endecoder
12.6 Conclusions:
Circuit of 4 x 1 MUX, 2 x 4 DECODER and 4 x 2 ENCODER using AND, OR and

NOT gates are implemented.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
Design

Fall 2004
13 Experiment No. 10: Analysis of RS flip flop using NAND and NOR gates.
13.1 Apparatus:
Logic trainer
Connecting wires
ICs (7400, 7404)
Power supply
13.2 Theory:
Flip-flops (FFs) are devices used in the digital field for a variety of purposes. When
properly connected, flip-flops may be used to store data temporarily. Flip-flops are
bistable multivibrators. The types used in digital equipment are identified by the
inputs. They may have from two up to five inputs depending on the type. They are all
common in one respect. They have two, and only two, distinct output states. The
outputs are normally labeled Q and Q and should always be complementary. When Q
= 1, then Q = 0 and vice versa.
The R-S FF is used to temporarily hold or store information until it is needed. A
single R-S FF will store one binary digit, either a 1 or a 0. The standard symbol for
the R-S FF is shown in figure below.
S Q
FF
R Q
Figure 10.1: Symbol for R-S Flip Flop.
Design
13.3 Calculations:
RS flip-flop is constructed by feeding the outputs of two NOR gates back to the other
NOR gates input as shown in the figure below.
Figure 10.2: RS flip-flop using NOR gates
To understand the operation of the RS-flip-flop (or RS-latch) consider the case when
S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0. Hence both
inputs to the top NOR gate are equal to one, thus, Q=1. Hence, the input combination
S=1 and R=0 leads to the flip-flop being set to Q=1. S=0 and R=1: Similar to the
arguments above, the outputs become Q=0 and Q'=1. We say that the flip-flop is reset.
S=0 and R=0: Assume the flip-flop is set (Q=0 and Q'=1), then the output of the top
NOR gate remains at Q=1 and the bottom NOR gate stays at Q'=0. Similarly, when
the flip-flop is in a reset state (Q=1 and Q'=0), it will remain there with this input
combination. Therefore, with inputs S=0 and R=0, the flip-flop remains in its state.
S=1 and R=1: This input combination must be avoided.
Truth Table for RS flip-flop with NOR Gates:
Inputs Outputs Comments

R S Q Q
0 1 1 0 Set
0 0 1 0 Hold
1 0 0 1 Reset
0 0 0 1 Hold
1 1 ? ? Avoid
Table 10.1: Truth table RS flip - flop
RS flip flop can also be constructed by feeding the outputs of two NAND gates back
to the other NAND gates input as shown in the figure:
Design
Figure 10.3: RS flip-flop using NAND gates
The NAND flip-flop circuit operates with both inputs normally at 1 unless the state of
the flip-flop has to be changed. The operation of NAND flip-flop is summarized in
the following truth table.
Truth Table for RS flip-flop with NAND Gates:

R S Q Q
0 1 0 1 Rsset
1 1 0 1 Hold
1 0 1 0 Set
1 1 1 0 Hold
0 0 ? ? Avoid
Table 10.2: Truth table NAND gate RS flip - flop
13.4 Procedure:
The NOR gate implementation of RS flip-flop requires NOR gates. Get the required
ICs and other apparatus from the lab attendant. Install the IC 7400 in the breadboard
of the Logic Trainer. Connect 5Vdc power supply and ground on pins 14 and 7
respectively. For other pin configuration consult the data sheet (we have already used
these gates in the first lab so it should not be a problem). Wire your circuit according
to the logic diagram you have drawn. Once you have wired the circuit, check it with
input combinations at the input and note down the Q and Q outputs and fill in the
following truth table. This truth table should conform to the one given in theory. If
there are problems, consult the appendix on troubleshooting given at the end of lab
manual. If the problem persists, request lab supervisor for help.
13.5 Observations:
Fill in the following truth tables by observing the outputs.
Design
Truth Table for RS flip-flop with NOR Gates:

R S Q Q
1 0
0 0
0 1
0 0
1 1
Table 10.3: Observed truth table NOR gate RS flip - flop
Truth Table for RS flip-flop with NAND Gates:

R S Q Q
0 1
1 1
1 0
1 1
0 0
Table 10.4: Observed truth table NAND gate RS flip - flop
13.6 Conclusions:
Circuit of RS flip flop is implemented using NAND and NOR gates.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design

Fall 2004
14 Experiment No. 11: Analysis of JK flip-flop using D Flip-Flop.
14.1 Apparatus:
Logic trainer
Connecting wires
IC (7404, 7408, 7474, 7432)
Power supply
14.2 Theory:
A JK flip flop is a refinement of the RS flip-flop in that the undetermined state of the
RS type is defined in the JK type. It has two inputs, traditionally labeled J and K. If J
and K are different then the output Q takes the value of J at the next clock edge. If J
and K are both low then no change occurs. If J and K are both high at the clock edge
then the output will toggle from one state to the other. The JK flip-flop is represented
by the following graphic symbol:
Q Q
J K
CP
Figure 11.1: Graphic symbol for JK flip-flop
In a clocked JK flip-flop, output Q is ANDed with K and CP (clock pulse) inputs so

that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly,
output Q is ANDed with J and CP inputs so that flip-flop is set with a clock pulse
only if Q was previously 1. The logic diagram of a JK flip-flop is shown below.
Design
Characteristic table for JK flip-flop is given below:
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Table 11.1: Characteristics table for JK flip - flop
14.3 Procedure:
The implementation of JK flip-flop requires two 2-input AND gates, 2-input OR,
inverters and Dual D Flip-flop with set and reset. Get the required ICs and other
apparatus from the lab attendant. Install the ICs in the breadboard of the Logic
Trainer. Connect 5Vdc power supply and ground on pins 14 and 7 respectively. For
other pin configuration consult the data sheet (we have already used these gates in the
first lab so it should not be a problem). Wire your circuit according to the logic
diagram you have drawn. Once you have wired the circuit, check it with your
instructor and, if approved, power up your circuit. The outputs should be connected to
the LEDs on the Logic Trainer for monitoring purpose. Apply different input
combinations at the input and note down the Q (t+1) outputs and fill in the following
truth table. This truth table should conform to the one given in theory. If there are
problems, consult the appendix on troubleshooting given at the end of lab manual. If
the problem persists, request lab supervisor for help.
14.4 Observations:
Complete the Q(t + 1) column in the table and verify proper circuit operation by
completing the Q(t + 1) Lamp column. Have this verified by your instructor in his
presence before you leave the lab.
Q J K Q(t+1)lamp
Design
Table 11.2: Observed characteristics table for JK flip - flop
14.5 Conclusion:
Circuit of JK Flip Flop implemented according to the given task.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design

Fall 2004
15 Experiment No. 12: Design a 2-bit binary counter using JK flip-flop.
15.1 Theory:
One common requirement in digital circuits is counting, both forward and backward.
Digital clocks and watches are everywhere, timers are found in a range of appliances
from microwave ovens to VCRs, and counters for other reasons are found in
everything from automobiles to test equipment.
A sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called a counter. The input pulses, called count pulses,
may be clocked pulses, or they may originate from an external source.
A counter that follows the binary sequence is called a binary counter. An n bit binary
counter consists of n flip-flops and can count in binary from 0 to 2n 1. A 2 bit
counter counts up till binary four and will require two flip-flops. The flip-flops used
will be of type JK as mentioned above. The counter advances to next state only if
clock pulse is 1, else stays in the same state.
State Diagram:
0
00
1
01 11
0 1 0
1 10
Figure 12.1: State diagram for 2 bit counter
Design
State Table:
The state table for this circuit, derived from the state diagram, as given below.
Present Next State

State
x=0 x=1
A B A B A B
0 0 0 0 0 1
0 1 0 1 1 0
1 0 1 0 1 1
1 1 1 1 0 0
Table 12.1: State table for counter
Excitation Table:
Now we will drive the excitation table for the JK flip-flop from the state table.
Inputs of Comb. Outputs of Comb. Cct

Cct
Present Sate Input Next State Flip flop inputs
A B X A B JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 0 1 0 X X 0
0 1 1 1 0 1 X X 1
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
Table 12.2: Excitation table for the flip flop counter
Drawing of K-map for each output is left as an exercise for you:
Design
The simplified input functions derived from the maps are given below and your
derivation should match these one.
JA = BX Equation (10.1)
KA = BX Equation (10.2)
JB = X Equation (10.3)
KB= X Equation (10.4)
Logic Diagram:
15.2 Procedure:
The implementation of 2 bit binary counter with JK flip-flop requires four 2-input
NOR gates, four 3-input AND gates, one 2 input AND gate and one 2 input XOR
gate. Get the required ICs and other apparatus from the lab attendant. Install the ICs in
the breadboard of the Logic Trainer. Connect 5Vdc power supply and ground on pins
14 and 7 respectively. For other pin configuration consult the data sheet (we have
already used these gates in the first lab so it should not be a problem). Wire your
circuit according to the logic diagram you have drawn. Once you have wired the
circuit, check it with your instructor and, if approved, power up your circuit. The
outputs should be connected to the LEDs on the Logic Trainer for monitoring
purpose. Apply different input combinations at the input and note down the outputs
(next states) and fill in the following truth table. This truth table should conform to the
one given in theory. If there are problems, consult the appendix on troubleshooting
given at the end of lab manual. If the problem persists, request lab supervisor for help.
Design
Repeat the same procedure for implement of JK flip-flop with NAND and AND gates
15.3 Observations:
Complete the Next State columns on both the table and verify proper circuit operation
by completing the A Lamp and B Lamp column. Have this verified by your instructor
in his presence before you leave the lab.
Inputs of Comb. Cct

Present Sate Input Next State
A B x A Lamp B Lamp
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 12.3: Observed output table
15.4 Conclusions:
Circuit of 2-bit counter is implemented according to the given task.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
Design

Fall 2004
16 Experiment No. 13: Analysis of a 4-bit synchronous Decade Counter.
16.1 Apparatus:
Digital Trainer
Power Supply 5V
Function Generator
7473 (Dual Nag Edge Triggered J-K Flip Flop With Reset)
7408 (Quad 2-input AND Gate)
7400 (Quad 2-input NAND Gate)
Jumpers
16.2 Description:
A counter is a simple state machine that is count the binary numbers
sequentially according to the clock pulse. A Decade Counter is a one in which it
counts the binary numbers from 0 to 9 sequentially.
The term synchronous refers to events that have a fixed time relationship with
each other. With respect to counter operation, synchronous means that a common
clock is applied to all the Flip Flop within the counter at the same time pulse.
A Synchronous Decade Counter exhibits a truncated binary sequence and
goes from 0000 through the 1001 state. Rather then going to the 1010 state. It recycles
to the 0000 state.
16.3 Truth Table:
Decimal Code CLK Q0 Q1 Q2 Q3

INITIALLY 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Table 13.1:Truth table for decade counter
Design
16.4 Circuit Diagram:
16.5 Pin Configuration of 7473 IC:
Design
16.8 Precautions:
1) Before applying the Power Supply, all the connections must be checked.
2) Before applying the Power Supply, identify the Pin Configuration of Ics.
3) Apply exactly 5V.
16.9 Conclusion:
Circuit of 4-bit synchronous decade counter is implemented according to the
given task.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design

Fall 2004
17 Experiment No. 14: Analysis of a 4-bit Asynchronous Decade Counter.
17.1 Apparatus:
Digital Trainer
Power Supply 5V
Function Generator
7473 (Dual Nag Edge Triggered J-K Flip Flop With Reset)
7400 (Quad 2-input NAND Gate)
Jumpers
17.2 Description:
A counter is a simple state machine that is count the binary numbers
sequentially according to the clock pulse. A Decade Counter is a one in which it
counts the binary numbers from 0 to 9 sequentially.
The term asynchronous refers to events that do not have a fixed time
relationship with each other and generally, do not occur at the same time. An
asynchronous counter is one in which the Flip Flop (FF) within the counter do not
change states at exactly the same time because they do not have a common clock
pulse.
An Asynchronous Decade Counter exhibits a truncated binary sequence and
goes from 0000 through the 1001 state. Rather then going to the 1010 state. It recycles
to the 0000 state.
Design
17.3 Circuit Diagram:
17.4 Truth Table:
Decimal Code CLK Q0 Q1 Q2 Q3

INITIALLY 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Table 13.1:Truth table for decade counter
Design
17.7 Precautions:
4) Before applying the Power Supply, all the connections must be checked.
5) Before applying the Power Supply, identify the Pin Configuration of ICs.
6) Apply exactly 5V.
17.8 Conclusion:
Circuit of 4-bit asynchronous decade counter is implemented according to the
given task.
Design
Name: Date of Lab:
Q. No. 01
Q. No. 02
Design
18 Appendix A: Use good construction practices
ESD (Electro-Static Discharge) prevention: The failure rate of electronic components

(including IC's) that are produced world-wide is only a few PPM (parts per million).
The failure rate in our labs, where we don't use proper techniques to prevent ESD
damage due to handling seems to be more like 10%. Could it be that we are damaging
the parts?!! Most successful companies will train you in ESD damage prevention, but
would then FIRE you for handling parts the way we do in most KSU labs. Use wrist
straps and understand ESD damage prevention.
Use ONE common ground point.
Keep inputs and low-level signal stages away from digital, output, and high power
stages. You may even create an unwanted oscillator if you don't do this.
For some applications, you need to isolate stages with a transformer or an opto-
isolator to avoid ground problems.
Be sure that your logic levels are all the same or provide level shifters. Beware of
mixing TTL and CMOS.
Do not leave inputs of "unused" op amps, comparators, or CMOS logic gates open.
Connect them to an appropriate fixed voltage. DO leave the outputs floating.
Design
19 Appendix B: Troubleshooting
o Turn on the DC power first, and then the signals. (Avoid latch-up)
o Keep a current copy of your circuit diagram beside the circuit and correct it
as you make changes. Keep a paper trail, or listing, of your lab work.
o Keep your layout neat and label nodes on bigger circuits.
o Check your DC power supply currents. If you have current limiting on the
supplies, set it just above what you expect for the total current.
o Watch for smoke and/or hot parts. (Use saliva on your digit temperature
sensor to avoid burns.)
o Be sure that the COMmon of the power supply is connected to ground. The
"ground" of many power supplies is isolated from the supply outputs.
o Check the DC level at the output of each active device. If it's about equal to
the positive or negative supply it's saturated or cut-off. Check all DC bias
points. Vbe's should be about .7V and FET gates should be greater than VT's
if they're supposed to be on.
o Look for loose wires.
o Now start checking signals: Use an oscilloscope to monitor signals starting at
the input.
o Recheck your circuit wiring one more time. This is the most common error
and by now you should have a good idea where the problem is located.
o If you observe 60Hz where signals should be you probably had an open
ground somewhere.
o Isolate parts of the circuit if you can and test individual circuits. This will not
always work with feedback circuits, because the feedback may be required to
give a stable operating point.
o If you suspect a bad part, turn off the signal first, and then the dc power.
Finally, remove and replace the part.
o Perhaps the most important thing is to understand what each part of the
circuit is supposed to do and then play like a detective.
o Make measurements as near full scale on the meter as possible.
o Make a note of measured voltages on the circuit diagram.
o Think!
Design
20 Appendix C: Safety
Freedom from preventable accidents is an important measure of the foresight and capability
of supervision in the engineering industries. The student should give thought to the subject of
accident prevention early in his or her training. He or she should prepare mentally to
recognize and avoid dangerous situations, and to cope with emergencies. A set of rules cannot
be made to apply to all situations. The student should develop the ability to analyze a
particular situation. An engineer's reputation for reliability is seriously injured if his lack of
foresight results in injury to himself, associates, or equipment.
Haste causes many accidents. Work deliberately and carefully. Verify your work as you go
along. Documentation and good planning before coming to the laboratory will promote safety.
When working on live electrical apparatus, use only one hand as far as practical,
keeping the other hand disengaged from circuitry. All ac power circuits are
dangerous. Adjustment in energized circuits should be made with caution. Do not
permit any part of your body to complete a circuit.
Close power switches quickly and positively. Hesitant closing may result in an
electric arc. Burns from an electric arc maybe severe and slow-healing. You can
depend on the circuit breakers and fuses in the circuit to prevent over-currents.
(Electric arcs and contact lenses are a bad combination.)
Be careful to keep watch bands, rings, necklaces, and other metallic objects out of
contact with live parts when working around electrical apparatus. It is a good idea to
remove watches with metal bands while working in the laboratory.
Long hair should be "up" when working around rotating machinery. Likewise, loose
clothing, neckties, etc., should be avoided around rotating machinery.
Make sure the banana plugs fit snugly in their sockets. Sometimes they get old and
worn so that they slide out too easily. Never splice two banana cords together so that
electrically "hot" metal is exposed on the bench. There are a number of banana
sockets on the bench which can be used if splicing is necessary.
If any banana jack connectors are loose on their cords, or if any sockets are loose,
report them immediately to the lab instructor.
When wiring a circuit, always connect to the source of power as the last step. When
disassembling a circuit, disconnect from the power source as the first step.
Never work alone in the laboratory. Injury could occur and there would be no one
present to help you.
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DEPARTMENT OF ELECTRICAL ENGINEERING, CIIT-WAH

Digital Logic Design

DEPARTMENT OF ELECTRICAL ENGINEERING

1|Page Digital Logic Design

Table of Contents ......................................................................................................... 2

2|Page Digital Logic Design

3|Page Digital Logic Design

2 Personal Tools and Components

Breadboard (Proto, Elite, etc.)

4|Page Digital Logic Design

ABUSE OR MISUSE OF EQUIPMENT: Treat all equipment with respect and

LABORATORY REFERENCE MATERIAL: There is a large variety of reference

5|Page Digital Logic Design

Digital Logic Design Laboratory

InputA InputB AND NAND OR NOR XOR XNOR NOT

Table1.1: Truth table for logic gates

6|Page Digital Logic Design

Table1.2: Truth table for first IC

Type of gate in the IC is: -----------------------------

Table1.3: Truth table for second IC

Type of gate in the IC is: -----------------------------

7|Page Digital Logic Design

Table1.4: Truth table for third IC

Type of gate in the IC is: -----------------------------

Table1.5: Truth table for fourth C

Type of gate in the IC is: -----------------------------

Table1.6: Truth table for fifth IC

Type of gate in the IC is: -----------------------------

8|Page Digital Logic Design

Table1.7: Truth table for IC

Type of gate in the IC is: -----------------------------

Table1.8: Truth table for seventh t IC

Type of gate in the IC is: -----------------------------

S.No. IC Number Type of Gate

Table1.9: Result summary

9|Page Digital Logic Design

INSTRUCTOR VERIFICATION SHEET

Name: Date of Lab:

Digital Logic Design Laboratory

5 Experiment No. 2: Implementation of Boolean Expression through Logic Gates

A Boolean function can be represented in a truth table. A truth table is a lost of

Truth Table for F1

Table 2.1: Truth table for F1

Figure 2.1: Gate implementation of F1=x+y`z

5.3.1 Simplify the simpler expression for this Boolean function

By manipulating a Boolean expression according to Boolean algebra rules, it is

F2= x`y`z + x`yz +xy`

Table 2.2: Truth Table for F2

Implement the logic diagram for the function F2

5.3.2 Verify Demorgans Theorem

Truth Table that verifies the above given Theorem 1,

Table 2.3: Truth Table of (x+y)`=x` +y`

Logic Diagram for 1st Demorgans Law:

Figure 2.2:Logic Diagram of (x+y)`=x` +y`

Implement the logic diagram for the 2nd Demorgans Theorem:

INSTRUCTOR VERIFICATION SHEET

Name: Date of Lab:

Digital Logic Design Laboratory

Figure 3.1: Logic gates

Truth Table for XOR gate:

Input A Input B Output F

Table3.1: Truth table for XOR gate

Figure 3.2: First level gates

Figure 3.3: Second level gates