module exercise1(LEDG,LEDR,SW,CLOCK_50);

input [5:0] SW;

output [3:0]LEDG;
output [3:0]LEDR;
input CLOCK_50;
reg [3:0]state;
reg [3:0]state1;
assign LEDG=state;
assign LEDR=state1;

always @ (posedge CLOCK_50)

begin

i
if(SW[0] == 0 & SW[1] ==0)
begin //PARALLEL
state[3:0]<=SW[5:2];
end
else if(SW[0] == 1 & SW[1] ==0)
begin //excess 3
state[3]=SW[5]|SW[4]&(SW[2]|SW[3]);
state[2]=SW[4]^(SW[2]|SW[3]);
state[1]=~(SW[3]^SW[2]);
state[0]=~SW[2];

end
else if(SW[0] == 0 & SW[1] ==1)
begin //gray

state[3]=SW[5];
state[2]=SW[4]^SW[5];
state[1]=SW[3]^SW[4];
state[0]=SW[3]^SW[2];
if(SW[5:2] == 0000 & SW[1:0] == 2'b10)
begin
state1=4'b1111;
state=4'b0000;
end
else begin
state1=4'b0000;
end

end

else if (SW[0] == 1 & SW[1] ==1)

begin // 2'S

state[3]=~SW[5]|(~SW[4]&~SW[3]&~SW[2]);
state[2]=SW[4]^(SW[2]|SW[3]);
state[1]=(SW[3]^SW[2]);
state[0]=SW[2];
f(SW[5:2] == 0000 & SW[1:0] == 2'b11)
begin
state1=4'b1111;
state=4'b0000;
end
else begin
state1=4'b0000;
end

end

end

endmodule