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Table of contents:
Sr. Page
Contents No.
No.
A To write VHDL code, simulate with test bench, synthesis, implement on PLD
1 4 bit ALU for add, subtract, AND, NAND, XOR, XNOR, OR, & ALU 2
pass.
2 Universal shift register with mode selection input for SISO, SIPO, 5
PISO, & PIPO modes
3 FIFO memory 8
4 LCD interface 11
8 D flip-flop 33
Reviewed by Approved by
EXPERIMENT NO: 01
1.1 Aim: To write VHDL code for a 4 bit ALU to add, subtract, AND, NAND, XOR,
XNOR, OR, & ALU pass .Verify the result using FPGA board. Also write the Test
bench and verify by simulation.
1.2 Hardware/Software:
1. Computer with Xilinx software.
2. FPGA board with JTAG cable.
1.3 Procedure:
1. Write a VHDL code for 4 bit ALU.
2. Verify the functional simulation for the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA and verify the operation.
5. Observe the RTL schematic for the code.
Input A(3:0)
Input B(3:0)
1.5 Results:
1. Operation of ALU is verified on FPGA board as well as by simulation.
2. The FPGA LUTs utilized for ALU is ______out of _______.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.
1.6 Conclusion:
______________________________________________________________________
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EXPERIMENT NO: 02
2.1 Aim: To write a VHDL code for Universal shift register with mode selection input
for SISO, SIPO, PISO, & PIPO modes. Write its test bench and verify the result using
FPGA board.
2.2 Hardware/Software:
1. Computer with Xilinx software.
2. FPGA board with JTAG cable.
2.3 Procedure:
1. Write a VHDL code for Universal Shift Register by any one modeling style.
2. Verify the functional simulation of the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA and verify the operation.
5. Generate the RTL schematic for each modeling style.
X 00 PIPO
1 01 PISO
1 10 SIPO
X 11 SISO
2.6 Results:
1. Operation of Universal Shift register is verified on FPGA board.
2. The FPGAs LUTs utilized for Universal Shift Register is _____out of ________.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.
2.7 Conclusion:
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
EXPERIMENT NO: 03
3.1 Aim: To write VHDL code for of FIFO Memory and write its test bench and verify
the result using FPGA board.
3.2 Hardware/Software:
1. Computer with Xilinx software.
2. FPGA board with JTAG cable.
3.3 Procedure:
1. Write a VHDL code for FIFO memory.
2. Verify the functional simulation for the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA and verify the operation.
5. Observe the RTL schematic for the code.
Clk
Empty
FIFO
rw Memory
(23 X 4) Full
rst
3.4 Results:
1. Operation of FIFO Memory is verified on FPGA board.
2. The FPGA LUTs utilized for FIFO Memory is _____out of ________.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.
3.5 Conclusion:
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
EXPERIMENT NO: 04
4.1 Aim: To write a VHDL code to interface LCD with FPGA, verify the functionality
by simulation, and implement using CPLD.
4.2 Hardware/Software:
4.3 Procedure:
Data (7:0)
ee
Clk
RS
CPLD LCD
rst
XC9572pc84 16x2
-15 EN characters
Gnd RW
Gnd Vcc
4.7 Results:
1. Functionality of LCD interface is verified by simulation and design is implemented
using CPLD board.
2. The macrocells utilized for LCD interfacing is _____out of ________.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.
4.7 Conclusion:
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
EXPERIMENT NO: 05 A
5.1 Aim: Design CMOS Inverter Layout and verify the functionality by simulation.
5.3 Procedure:
Prepare the layout for CMOS inverter with WP=3.2Wn and perform functional
simulation with and without capacitive load.
Comment on the effect of no load and capacitive load on rise time and fall time.
5.4 Specifications:
Technology: 0.18um
Supply voltage: 2.0V
5.8 Conclusion:
Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
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EXPERIMENT NO: 05 B
5.1 Aim: Design CMOS NAND gate Layout and verify the functionality by simulation.
5.2 Procedure:
Prepare the layout for CMOS NAND gate and perform functional simulation with and
without capacitive load.
Comment on the effect of no load and capacitive load on rise time and fall time.
5.3 Specifications:
Technology: 0.18um
Supply voltage: 2.0V
5.8 Conclusion:
Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
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EXPERIMENT NO: 05 C
5.1 Aim: Design CMOS NOR gate Layout and verify the functionality by simulation.
5.3 Procedure:
Prepare the layout for CMOS NOR gate and perform functional simulation with and
without capacitive load.
Comment on the effect of no load and capacitive load on rise time and fall time.
5.4 Specifications:
Technology: 0.18um
Supply voltage: 2.0V
5.8 Conclusion:
Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
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EXPERIMENT NO: 05 D
5.1 Aim: Design CMOS Half Adder Layout and verify the functionality by simulation.
5.3 Procedure:
Prepare the layout for CMOS Half Adder and perform functional simulation with and
without capacitive load.
Comment on the effect of no load and capacitive load on rise time and fall time.
5.4 Specifications:
5.9 Conclusion:
Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
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______________________________________________________________________
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EXPERIMENT NO: 6
6.1 Aim: CMOS 2:1 Multiplexer layout design using logic gates and transmission gates
and verify the functionality by simulation
6.3 Procedure:
Prepare the layout for 2:1 multiplexer using transmission gates and logic gates. Do the
functional simulation and verify the results.
Comment on the effect of no load and capacitive load on rise time and fall time.
6.4 Specifications:
Technology: 0.18um
Supply voltage: 2.0V
D0
S Y
D1
6.9 Conclusion:
Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
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______________________________________________________________________
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EXPERIMENT NO: 7
7.1 Aim: Design of CMOS single bit SRAM cell layout and verify the functionality by
simulation
7.3 Procedure:
Prepare the CMOS layout of single bit SRAM cell. Do the functional simulation and
verify the results.
Comment on the effect of no load and capacitive load on rise time and fall time.
7.4 Specifications:
Technology: 0.18um
Supply voltage: 2.0V
7.8 Conclusion:
Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
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______________________________________________________________________
______________________________________________________________________
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EXPERIMENT NO: 8
8.1 Aim: Design of CMOS D Flip Flop layout and verify the functionality by
simulation
8.3 Procedure:
Prepare the CMOS layout of D Flip Flop. Do the functional simulation and verify the
results.
Comment on the effect of no load and capacitive load on rise time and fall time.
8.4 Specifications:
Technology: 0.18um
Supply voltage: 2.0V
8.8 Conclusion:
Comment on effect of no load and capacitive load on rise and fall time.
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