Analog Ders 1 PDF

EECE488: Analog CMOS Integrated Circuit Design
Set 2: Background
Shahriar Mirabbasi
Department of Electrical and Computer Engineering

University of British Columbia
shahriar@ece.ubc.ca
Technical contributions of Pedram Lajevardi in revising the slides is greatly acknowledged.

SM 1
EECE 488 Set 2: Background
Overview
1. Reading Assignments
2. Structure of MOS Transistors
3. Threshold Voltage
4. Long-Channel Current Equations
5. Regions of Operation
6. Transconductance
7. Second-Order Effects
8. Short-Channel Effects
9. MOS Layout
10. Device Capacitances
11. Small-signal Models
12. Circuit Impedance
13. Equivalent Transconductance
SM 2
Reading Assignments
Reading:
Chapter 2 of the textbook
Section 16.2 of the textbook
Chapter 17
All the figures in the lecture notes are Design of Analog CMOS Integrated Circuits,
McGraw-Hill, 2001, unless otherwise noted.
SM 3
Transistor
Transistor stands for
Transistor are semiconductor devices that can be classified as
Bipolar Junction Transistors (BJTs)
Field Effect Transistors (FETs)
Depletion-Mode FETs or (e.g., JFETs)
Enhancement-Mode FETs (e.g., MOSFETs)
SM 4
Simplistic Model
MOS transistors have three terminals: Gate, Source, and Drain
The voltage of the Gate terminal determines the type of connection

between Source and Drain (Short or Open).
Thus, MOS devices behave like a switch
NMOS PMOS
VG high Device is ON Device is OFF

D is shorted to S D & S are disconnected
VG low Device is OFF Device is ON
D & S are disconnected D is shorted to S
SM 5
Physical Structure - 1
Source and Drain terminals are identical except that Source provides
charge carriers, and Drain receives them.
MOS devices have in fact 4 terminals:
Source, Drain, Gate, Substrate (bulk)
Microelectronic Circuits, 2004 Oxford University Press
SM 6
Charge Carriers are electrons in NMOS devices, and holes in
PMOS devices.
Electrons have a higher mobility than holes
So, NMOS devices are faster than PMOS devices
We rather to have a p-type substrate?!
LD: Due to Side Diffusion
Poly-silicon used instead of Metal

for fabrication reasons
Actual length of the channel (Leff) is less than the length of gate
SM 7
N-wells allow both NMOS and PMOS devices to reside on the
same piece of die.
As mentioned, NMOS and PMOS devices have 4 terminals:

Source, Drain, Gate, Substrate (bulk)
In order to have all PN junctions reverse-biased, substrate of
NMOS is connected to the most negative voltage, and substrate
of PMOS is connected to the most positive voltage.
SM 8
MOS transistor Symbols:
In NMOS Devices: Source Drain

electron
Current flows from Drain to Source
In PMOS Devices: Source hole

Drain
Current flows from Source to Drain
Current flow determines which terminal is Source and which one

is Drain. Equivalently, source and drain can be determined based
on their relative voltages.
SM 9
Threshold Voltage - 1
Consider an NMOS: as the gate voltage is increased, the surface
under the gate is depleted. If the gate voltage increases more,
free electrons appear under the gate and a conductive channel is
formed.
(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion,
and (d) channel formation
As mentioned before, in NMOS devices charge carriers in the

channel under the gate are electrons.
SM 10
Intuitively, the threshold voltage is the gate voltage that forces the
interface (surface under the gate) to be completely depleted of charge (in
NMOS the interface is as much n-type as the substrate is p-type)
Increasing gate voltage above this threshold (denoted by VTH or Vt)

induces an inversion layer (conductive channel) under the gate.
SM 11
Analytically:
Qdep
VTH = MS + 2 F +
C ox
Where:
MS = Built - in Potential = gate Silicon

= the difference between the work functions of
the polysilicon gate and the silicon substrate
K T N
= Work Function (electrostatic potential) =
F
ln
sub
q n
i
Q = Charge in the depletion region =

dep
4 q N
si F sub
SM 12
In practice, the native threshold value may not be suited for
circuit design, e.g., VTH may be zero and the device may be on for
any positive gate voltage.
Typically threshold voltage is adjusted by ion implantation into the

channel surface (doping P-type material will increase VTH of
NMOS devices).
When VDS is zero, there is no horizontal electric field present in the

channel, and therefore no current between the source to the drain.
When VDS is more than zero, there is some horizontal electric field
which causes a flow of electrons from source to drain.
SM 13
Long Channel Current Equations - 1
The voltage of the surface under the gate, V(x), depends on the
voltages of Source and Drain.
If VDS is zero, VD= VS=V(x). The charge density Qd (unit C/m) is uniform.
Q C V (C oxWL ) (VGS VTH )
Qd = = =
L L L
Qd = WC ox (VGS VTH )
If VDS is not zero, the channel is tapered, and V(x) is not constant. The
charge density depends on x.
Qd ( x) = WC ox (VGS V ( x) VTH )
SM 14
Current :
dQ dQ dx
I= = = Qd velocity
dt dx dt
Velocity in terms of V(x):
dV
velocity = E , E =
dt
dV ( x)
velocity = ( )
dx
Qd in terms of V(x):
Qd ( x) = WC ox (VGS V ( x) VTH )
Current in terms of V(x):

dV ( x) Microelectronic Circuits, 2004 Oxford University Press
I D = WC ox [VGS V ( x) VTH ] n
dx
L VDS
I D dx = WC ox n [VGS V ( x) VTH ]dV

x =0 V =0
Long-channel current equation:

W 1 2
I D = n C ox [(VGS VTH )VDS VDS ]
L 2
SM 15
If VDS VGS-VTH we say the device is operating in triode (or linear) region.
1 2
(VGS VTH ) VDS VDS
W
Current in Triode Region: I D = n C ox
L 2
Terminology:
W
Aspect Ratio =
L
Overdrive Voltage = Effective Voltage = VGS VTH = Veff
SM 16
For very small VDS (deep Triode Region):

ID can be approximated to be a linear function of VDS.
The device resistance will be independent of VDS and will
only depend on Veff.
The device will behave like a variable resistor
If VDS << 2(VGS VTH ) :
(VGS VTH ) VDS

W
I D = n C ox
L
VDS 1
RON = =
n C ox (VGS VTH )
ID W
L
SM 17
Increasing VDS causes the channel to acquire a tapered shape. Eventually,
as VDS reaches VGS VTH the channel is pinched off at the drain. Increasing
VDS above VGS VTH has little effect (ideally, no effect) on the channels
shape.
When VDS is more than VGS VTH the channel is pinched off, and the
horizontal electric field produces a current.
SM 18
If VDS > VGS VTH, the transistor is in saturation (active) region,

and the channel is pinched off.
L''
L VGS VTH
I D dx = WC ox n [VGS V ( x) VTH ]dV
x=0 V =0
1 W
ID = n C ox (VGS VTH ) 2
2 L'
Lets, for now, assume that L=L. The fact that
L is not equal to L is a second-order effect
known as channel-length modulation.
Since ID only depends on VGS, MOS transistors in saturation can be
used as current sources.
SM 19
Current Equation for NMOS:

0 ; if VGS < VTH (Cut off )

n C ox (VGS VTH ) VDS ; if VGS > VTH , VDS << 2(VGS VTH ) ( Deep Triode)
W
L
I D = I DS =

L
[
n C ox (VGS VTH ) VDS V DS
W 1 2
2
]
; if VGS > VTH , V DS < VGS VTH (Triode)

1 C W (V V ) 2 ; if V > V , V > V V ( Saturation )
2 n ox L GS TH GS TH DS GS TH
SM 20
Current Equation for PMOS:

0 ; if VSG < VTH (Cut off )

p C ox (VSG VTH ) VSD ; if VSG > VTH , VSD << 2(VSG VTH ) ( Deep Triode)
W
L
I D = I SD =

L
[
p C ox (VSG VTH ) VSD VSD
W 1 2
2
]
; if VSG > VTH , VSD < VSG VTH (Triode)

1 C W (V V ) 2 ; if V > V , V > V V ( Saturation )
2 p ox L SG TH SG TH SD SG TH
SM 21
Regions of Operation - 1
Regions of Operation:
Cut-off, triode (linear), and saturation (active or pinch-off)
Once the channel is pinched off, the current through the channel is
almost constant. As a result, the I-V curves have a very small slope in
the pinch-off (saturation) region, indicating the large channel
resistance.
SM 22
The following illustrates the transition from pinch-off to triode region for
NMOS and PMOS devices.
For NMOS devices:

If VD increases (VG Const.), the device will go from Triode to Pinch-off.
If VG increases (VD Const.), the device will go from Pinch-off to Triode.
** In NMOS, as VDG increases the device will go from Triode to Pinch-off.
For PMOS devices:
If VD decreases (VG Const.), the device will go from Triode to Pinch-off.
If VG decreases (VD Const.), the device will go from Pinch-off to Triode.
** In PMOS, as VGD increases the device will go from Pinch-off to Triode.
SM 23
NMOS Regions of Operation:
Relative levels of the terminal voltages of the enhancement-type NMOS

transistor for different regions of operation.
SM 24
PMOS Regions of Operation:
The relative levels of the terminal voltages of the enhancement-type

PMOS transistor for different regions of operation.
SM 25
Example:
For the following circuit assume that VTH=0.7V.
When is the device on?
What is the region of operation if the device is on?
Sketch the on-resistance of transistor M1 as a function of VG.
SM 26
Transconductance - 1
The drain current of the MOSFET in saturation region is ideally a
function of gate-overdrive voltage (effective voltage). In reality, it is also
a function of VDS.
It makes sense to define a figure of merit that indicates how well the
device converts the voltage to current.
Which current are we talking about?
What voltage is in the designers control?
What is this figure of merit?
I D
gm =
VGS VDS = Const.
SM 27
Example:
Plot the transconductance of the following circuit as a function of VDS
(assume Vb is a constant voltage).
Transconductance in triode:
gm =

VGS
[
W
L
1 2
2
]
n C ox (VGS VTH ) V DS V DS
VDS = Const.
W
= n C ox V DS
L
Transconductance in saturation:
1 W
gm = n C ox (VGS VTH )
2

VGS2 L V DS = Const.
W
= n C ox (VGS VTH )
L
Moral: Transconductance drops if the device enters the triode region.

SM 28
Transconductance, gm, in saturation:
W W 2 ID
g m = n C ox (VGS VTH ) = 2 n C ox I D =
L L VGS VTH
If the aspect ratio is constant: gm depends linearly on (VGS - VTH).
Also, gm depends on square root of ID.
If ID is constant: gm is inversely proportional to (VGS - VTH).

Also, gm depends on square root of the aspect ratio.
If the overdrive voltage is constant: gm depends linearly on ID.

Also, gm depends linearly on the aspect ratio.
SM 29
Second-Order Effects (Body Effect)
Substrate Voltage:
So far, we assumed that the bulk and source of the transistor are at the
same voltage (VB=VS).
If VB >Vs, then the bulk-source PN junction will be forward biased, and
the device will not operate properly.
If VB <Vs,
the bulk-source PN junction will be reverse biased.
the depletion region widens, and Qdep increases.
VTH will be increased (Body effect or Backgate effect).
It can be shown that (what is the unit for ?):
2 q si N sub
VTH = VTH 0 + 2 F + VSB 2 F where =
Cox
SM 30
Body Effect - 2
Example:
Consider the circuit below (assume the transistor is in the active region):
If body-effect is ignored, VTH will be constant, and I1 will only depend on
VGS1=Vin-Vout. Since I1 is constant, Vin-Vout remains constant.
Vin Vout VTH = C = Const . Vin Vout = VTH + C = D = Conts.
In general, I1 depends on VGS1- VTH =Vin-Vout-VTH (and with body effect

VTH is not constant). Since I1 is constant, Vin-Vout-VTH remains constant:
Vin Vout VTH = C = Const . Vin Vout = VTH + C
As Vout increases, VSB1 increases, and as a result VTH increases.
Therefore, Vin-Vout Increases.
No Body Effect With Body Effect

SM 31
Body Effect - 3
Example:
For the following Circuit sketch the drain current of transistor M1 when VX
varies from - to 0. Assume VTH0=0.6V, =0.4V1/2, and 2F=0.7V.
SM 32
Channel Length Modulation - 1
When a transistor is in the saturation region (VDS > VGS VTH),

the channel is pinched off.
1 W
The drain current is I D = nCox (VGS VTH ) 2 where L' = L-L
2 L'
1
=
1 1
=
1
L' L L L 1 L
1
(
1 + L
L L
)
L
Assuming L
L
= VDS we get:
1 1
L' L
( 1
L L
)
1 + L = (1 + VDS )
(VGS VTH ) 2 n C ox (VGS VTH ) (1 + VDS )

1 W 1 W
The drain current is I D = n C ox
2
2 L' 2 L
As ID actually depends on both VGS and VDS, MOS transistors are
not ideal current sources (why?).
SM 33
represents the relative variation in effective length of the channel for a given
increment in VDS.
For longer channels is smaller, i.e., 1/L

I D
Transconductance: gm =
VGS VDS = Const.
In Triode:
W
g m = n C ox VDS
L
In Saturation (ignoring channel length modulation):

W W 2 ID
g m = n C ox (VGS VTH ) = 2 n C ox I D =
L L VGS VTH
In saturation with channel length modulation:
2 ID
(VGS VTH ) (1 + V DS ) = 2 n C ox I D (1 + VDS ) =
W W
g m = n C ox
L L VGS VTH
The dependence of ID on VDS is much weaker than its dependence on VGS.
SM 34
Example:
Given all other parameters constant, plot ID-VDS characteristic of an NMOS
for L=L1 and L=2L1
In Triode Region: W
I D n Cox
L [(
VGS VTH )V DS
1 2
2
VDS ]
I D W
Therefore :
VDS L
nCox (VGS VTH )2 (1 + VDS )

1 W
In Saturation Region: ID
2 L
I D
= nCox (VGS VTH )2
1 W
So we get :
VDS 2 L
I D W W
Therefore :
VDS L L2
Changing the length of the device from L1 to 2L1 will flatten the ID-VDS
curves (slope will be divided by two in triode and by four in saturation).
Increasing L will make a transistor a better current source, while
degrading its current capability.
Increasing W will improve the current capability.
SM 35
Sub-threshold Conduction
If VGS < VTH, the drain current is not zero.
The MOS transistors behave similar to BJTs.
VBE
In BJT: I C = I S e
VT
VGS
VT
In MOS: I D = I 0 e
As shown in the figure, in MOS transistors, the drain current drops by

one decade for approximately each 80mV of drop in VGS.
In BJT devices the current drops faster (one decade for approximately
each 60mv of drop in VGS).
This current is known as sub-threshold or weak-inversion conduction.
SM 36
CMOS Processing Technology
Top and side views of a typical CMOS process
SM EECE 588 Set 1: Introduction and Background 37

CMOS Processing Technology
Different layers comprising CMOS transistors

Photolithography (Lithography)
Used to transfer circuit layout information to the wafer

Typical Fabrication Sequence
SM 40
Self-Aligned Process
Why source and drain junctions are formed after the gate oxide
and polysilicon layers are deposited?

Back-End Processing
Oxide spacers and silicide

Back-End Processing
Contact and metal layers fabrication

Back-End Processing
Large contact areas should be avoided to minimize the
possibility of spiking

MOS Layout - 1
It is beneficial to have some insight into the layout of the MOS devices.
When laying out a design, there are many important parameters we

need to pay attention to such as: drain and source areas,
interconnects, and their connections to the silicon through contact
windows.
Design rules determine the criteria that a circuit layout must meet for a
given technology. Things like, minimum length of transistors, minimum
area of contact windows,
SM 45
MOS Layout - 2
Example:
Figures below show a circuit with a suggested layout.
The same circuit can be laid out in different ways, producing different
electrical parameters (such as different terminal capacitances).
SM 46
Device Capacitances - 1
The quadratic model determines the DC behavior of a MOS transistor.
The capacitances associated with the devices are important when
studying the AC behavior of a device.
There is a capacitance between any two terminals of a MOS transistor.
So there are 6 Capacitances in total.
The Capacitance between Drain and Source is negligible (CDS=0).
These capacitances will depend on the region of operation (Bias

values).
SM 47
The following will be used to calculate the capacitances between
terminals:

C = W LC , C =
ox
1. Oxide Capacitance: 1 t ox ox
ox
q si N sub
2. Depletion Capacitance: C 2 = C dep = W L
4F
3. Overlap Capacitance: C 3 = C 4 = C ov = W LD C ox + C fringe
4. Junction Capacitance:
Sidewall Capacitance: C jsw C j0
C jun = m
VR
Bottom-plate Capacitance: Cj 1 +
B
C 5 = C 6 = C j + C jsw
SM 48
In Cut-off:
1. CGS: is equal to the overlap capacitance. C = C = C GS ov 3
2. CGD: is equal to the overlap capacitance. C = C = C GD ov 4
3. CGB: is equal to Cgate-channel = C1 in series with Cchannel-bulk = C2.
4. CSB: is equal to the junction capacitance between source and

bulk.
5. CDB: is equal to the junction capacitance between source and
bulk.
C SB = C 5
C DB = C 6
SM 49
In Triode:
The channel isolates the gate from the substrate. This means that if VG
changes, the charge of the inversion layer are supplied by the drain
and source as long as VDS is close to zero. So, C1 is divided between
gate and drain terminals, and gate and source terminals, and C2 is
divided between bulk and drain terminals, and bulk and source
terminals.
C
1. CGS: CGS = Cov + 21
2. CGD: CGD = C ov + C1
2
3. CGB: the channel isolates the gate from the substrate. C GB = 0
C
4. CSB: C SB = C 5 + 2
2
5. CDB: C
C DB = C 6 + 2
2
SM 50
In Saturation:
The channel isolates the gate from the substrate. The voltage across
the channel varies which can be accounted for by adding two
equivalent capacitances to the source. One is between source and
gate, and is equal to two thirds of C1. The other is between source and
bulk, and is equal to two thirds of C2.
2
1. CGS: C = C + 3 C
GS ov 1
2. CGD: C =C
GD ov
3. CGB: the channel isolates the gate from the substrate. C = 0GB
4. CSB: C =C + C
SB 5
2
2
3
5. CDB: C =C
DB 6
SM 51
In summary:
Cut-off Triode Saturation
C1 2
CGS C ov C ov + C ov + C1
3
2
C1
CGD C ov C ov + C ov
2
CGB C1 C 2
C GB C1 0 0
C1 + C 2
C2
CSB C5 C5 + 2
C5 + C 2
2 3
C2
CDB C6 C6 +
2
C6
SM 52
Importance of Layout
Example (Folded Structure):
Calculate the gate resistance of the circuits shown below.
Folded structure:
Decreases the drain capacitance
Decreases the gate resistance
Keeps the aspect ratio the same
Passive Devices
Resistors

Passive Devices
Capacitors:

Passive Devices
Capacitors

Passive Devices
Inductors

Latch-Up
Due to parasitic bipolar transistors in a CMOS process

Small Signal Models - 1
Small signal model is an approximation of the large-signal model
around the operation point.
In analog circuits most MOS transistors are biased in saturation region.
In general, ID is a function of VGS, VDS, and VBS. We can use this Taylor
series approximation:
I D I I
Taylor Expansion : I D = I D 0 + VGS + D VDS + D VBS + second order terms
VGS VDS VBS
I D I I VDS
I D VGS + D VDS + D VBS = g m VGS + + g mb VBS
VGS VDS VBS ro
SM 59
(VGS VTH ) 2 n C ox (VGS VTH ) (1 + VDS )
1 W 1 W
Current in Saturation: I D = n C ox 2
2 L' 2 L
I D I I
Taylor approximation: I D VGS + D V DS + D V BS
VGS VDS V BS
Partial Derivatives:
I D
= n C ox (VGS VTH ) (1 + VDS ) = g m
W
VGS L
I D 1 W 1
= n C ox (VGS VTH ) 2 I D =
VDS 2 L ro
I D I D VTH
= n C ox (VGS VTH ) (1 + VDS )
W
=
VBS VTH VBS L 2 2 F + VSB

= g m = g m = g mb
2 2 F + VSB

SM 60
Small-Signal Model:
v DS
i D = g m vGS + + g mb v BS
ro
Terms, gmvGS and gmbvBS, can be modeled by dependent sources.

These terms have the same polarity: increasing vG, has the same
effect as increasing vB.
The term, vDS/ro can be modeled using a resistor as shown below.
SM 61
Complete Small-Signal Model with Capacitances:
Small signal model including all the capacitance makes the intuitive
(qualitative) analysis of even a few-transistor circuit difficult!
Typically, CAD tools are used for accurate circuit analysis
For intuitive analysis we try to find a simplest model that can represent
the role of each transistor with reasonable accuracy.
SM 62
Circuit Impedance - 1
It is often useful to determine the impedance of a circuit seen from a
specific pair of terminals.
The following is the recipe to do so:

1. Connect a voltage source, VX, to the port.
2. Suppress all independent sources.
3. Measure or calculate IX.
V
R =
X
X
I X
SM 63
Example:
Find the small-signal impedance of the following current
sources.
We draw the small-signal model, which is the same for both
circuits, and connect a voltage source as shown below:
v v
i =
X
+ g v =
X
m GS
X
r o
r o
v
R = X
=r X
o
i X
SM 64
Example:
Find the small-signal impedance of the following circuits.
We draw the small-signal model, which is the same for both
circuits, and connect a voltage source as shown below:
v v
i =
X
X
g v g v = + g v + g v
m GS mb BS
X
m X mb X
r
o
r o
v 1 1 1
R = = X
=r
X
i 1 g g
o
X
+g +g m mb
m mb
r o
SM 65
Example:
Find the small-signal impedance of the following circuit. This
circuit is known as the diode-connected load, and is used
frequently in analog circuits.
We draw the small-signal model and connect the voltage

source as shown below:
v v 1
i = + g v = + g v = v + g
X
X
m GS
X
m X X m
r o
r r o o
v 1 1
R = = X
=r
X
i 1 g
o
X
+g m
m
r o
If channel length modulation is ignored (ro=) we get:

1 1 1
R =rX o
= =
g
m
g g m m
SM 66
Example:
Find the small-signal impedance of the following circuit. This
circuit is a diode-connected load with body effect.
v v
i = X
X
g v g v = + g v + g v
m GS mb BS
X
m X mb X
ro
r o
1
= v + g + g
X m mb

r o
v 1 1 1 1
R = = X
=r =r
1 g +g
X o o
i X
+g +g g g m mb m mb
m mb
r o
If channel length modulation is ignored (ro=) we get:

1 1 1 1 1
R =r = = =
g +g g +g g +g
X o
m mb
g g m mb m mb m mb
SM 67
Equivalent Transconductance - 1
Recall that the transconductance of a transistor was a a figure of
merit that indicates how well the device converts a voltage to current.
I
g = D
V V = Const.
m
GS DS
It is sometimes useful to define the equivalent transconductance of a

circuit as follows:
I
G = OUT
V V = Const .
m
IN OUT
The following is a small-signal block diagram of an arbitrary circuit

with a Norton equivalent at the output port. We notice that:
VOUT=Constant so vOUT=0 in the small signal model.
i
G = OUT
=0
m
v v
IN OUT
SM 68
Example:
Find the equivalent transconductance of an NMOS transistor
in saturation from its small-signal model.
iOUT
= g v = g v
m GS m IN
i
G = m
=g
OUT
m
v IN
SM 69
Example:
Find the equivalent transconductance of the following circuit
when the NMOS transistor in saturation.
v =v +v =v +i
IN GS S GS OUT
R S
v i R
i
OUT
= g v + g v
m GS mb BS
= g (v i
S
m IN OUT
R ) + g ( i
S mb OUT
R )
S
OUT S
r O
r
O
R
i 1 + g R + g R + = g v
OUT m S mb S
S
m IN
r O
i g g r
G = =
OUT
= m m O
R r + r (g R + g R ) + R
m
v 1+ g R + g R +
IN S O O m S mb S S
m S mb S
r O
SM 70
Short-Channel Effects
Threshold Reduction
Drain-induced barrier lowering (DIBL)
Mobility degradation
Velocity saturation
Hot carrier effects

Substrate current
Gate current
Output impedance variation
SM 71
Threshold Voltage Variation in Short Channel Devices
The Threshold of transistors fabricated on the same chip decreases as

the channel length decreases.
Intuitively, the extent of depletion regions associated with drain and

source in the channel area, reduces the immobile charge that must be
imaged by the charge on the gate.
SM 72
Drain-Induced Barrier Lowering (DIBL)
When the channel is short, the drain

voltage increases the channel surface
potential, lowering the barrier to flow
charge from source (think of increased
electric field) and therefore, decreasing
the threshold.
SM 73
Effects of Velocity Saturation
Due to drop in mobility at high electric fields
(a) Premature drain current saturation and (b) reduction in gm
SM 74
Hot Carrier Effects
Short channel devices may experience high lateral drain-source
electric field
Some carriers that make it to drain have high velocity (called

hot carriers)
Hot carriers may hit silicon atoms at high speed and cause
impact ionization
The resulting electron and holes are absorbed by the drain and
substrate causing extra drain-substrate current
Really hot carriers may be injected into gate oxide and flow out
of gate causing gate current!
SM 75
Output Impedance Variation
Recall the definition of .
SM 76
Output Impedance Variation in Short-Channel Devices
SM 77

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EECE488: Analog CMOS Integrated Circuit Design

Department of Electrical and Computer Engineering

Technical contributions of Pedram Lajevardi in revising the slides is greatly acknowledged.

Chapter 2 of the textbook

Section 16.2 of the textbook

Transistor are semiconductor devices that can be classified as

Bipolar Junction Transistors (BJTs)

Field Effect Transistors (FETs)

Depletion-Mode FETs or (e.g., JFETs)

Enhancement-Mode FETs (e.g., MOSFETs)

The voltage of the Gate terminal determines the type of connection

VG high Device is ON Device is OFF

Microelectronic Circuits, 2004 Oxford University Press

LD: Due to Side Diffusion

Poly-silicon used instead of Metal

As mentioned, NMOS and PMOS devices have 4 terminals:

In NMOS Devices: Source Drain

Current flows from Drain to Source

In PMOS Devices: Source hole

Current flow determines which terminal is Source and which one

As mentioned before, in NMOS devices charge carriers in the

Increasing gate voltage above this threshold (denoted by VTH or Vt)

Microelectronic Circuits, 2004 Oxford University Press

MS = Built - in Potential = gate Silicon

Q = Charge in the depletion region =

Typically threshold voltage is adjusted by ion implantation into the

When VDS is zero, there is no horizontal electric field present in the

Current in terms of V(x):

I D dx = WC ox n [VGS V ( x) VTH ]dV

Long-channel current equation:

For very small VDS (deep Triode Region):

If VDS << 2(VGS VTH ) :

(VGS VTH ) VDS

Microelectronic Circuits, 2004 Oxford University Press

If VDS > VGS VTH, the transistor is in saturation (active) region,

Microelectronic Circuits, 2004 Oxford University Press

For NMOS devices:

Microelectronic Circuits, 2004 Oxford University Press

Relative levels of the terminal voltages of the enhancement-type NMOS

Microelectronic Circuits, 2004 Oxford University Press

The relative levels of the terminal voltages of the enhancement-type

What is the region of operation if the device is on?

Sketch the on-resistance of transistor M1 as a function of VG.

Which current are we talking about?

What voltage is in the designers control?

What is this figure of merit?

Moral: Transconductance drops if the device enters the triode region.

If ID is constant: gm is inversely proportional to (VGS - VTH).

If the overdrive voltage is constant: gm depends linearly on ID.

It can be shown that (what is the unit for ?):

In general, I1 depends on VGS1- VTH =Vin-Vout-VTH (and with body effect

No Body Effect With Body Effect

When a transistor is in the saturation region (VDS > VGS VTH),

(VGS VTH ) 2 n C ox (VGS VTH ) (1 + VDS )

For longer channels is smaller, i.e., 1/L

In Saturation (ignoring channel length modulation):

nCox (VGS VTH )2 (1 + VDS )

As shown in the figure, in MOS transistors, the drain current drops by

This current is known as sub-threshold or weak-inversion conduction.

SM EECE 588 Set 1: Introduction and Background 37

SM EECE 588 Set 1: Introduction and Background 38

SM EECE 588 Set 1: Introduction and Background 39

SM EECE 588 Set 1: Introduction and Background 41