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SystemVerilog Basic Datatypes

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Index
System Verilog Data Types

SystemVerilog Basic Datatypes

Single Dimensional Arrays

Multi Dimensional Arrays

Array Operations

Packed Arrays
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System Verilog Features

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SystemVerilog Features
Two state data types Better Performance and reduced memory usage

Queues, dynamic and associative

Reduced memory usage, built in support for searching and sorting
array

Unions and packed structures Allows multiple views of the same data

Support for abstract data structures

Classes and structures

Built in support for strings

Strings

A very powerful language to develop testbenches that can functionally verify complex RTL
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Verilog Basic Datatypes

reg

reg [dimension1:dimension2]variable_name;

Represents data storage element, cannot have multiple drivers, can be synthesized as FF, latches or combinational circuit

reg is a general purpose variable used for modeling hardware

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Verilog Basic Datatypes

reg

reg [dimension1:dimension2]variable_name;

keyword dimensions Variable name

Represents data storage element, cannot have multiple drivers, can be synthesized as FF, latches or combinational circuit

reg is a general purpose variable used for modeling hardware

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Verilog Basic Datatypes

reg [dimension1:dimension2]variable_name; example reg [0:7]a;

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reg
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Verilog Basic Datatypes

module test_xor()
reg clk=0;
reg reset=0;
reg [3:0] A;
reg [3:0] B;
always #5 clk=~clk;
initial
begin
reset=1b1;
#10reset=1b0;
#0 A=4b0001;
#0 B=4b1001;
#15 A=4b0011;
#0 B=4b1010
#15 A=4b0111;
#0 B=4b1011
end
endmodule
Verilog Code

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reg 8

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Verilog Basic Datatypes

wire

wire [dimension1:dimension2]variable_name;

keyword dimensions Variable name

Used to connect different parts of the design and can have multiple drivers
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Verilog Basic Datatypes

wire [dimension1:dimension2]variable_name; example wire [0:7]awr;

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1
2
3
4
5
6
7

wire
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Verilog Basic Datatypes

module test_xor()
reg clk=0;
reg reset=0;
reg [3:0] A,B;
reg [3:0] golden_ref;
wire [3:0] Y;
always #5 clk=~clk;
initial
begin clk
reset=1b1;
reset
#10reset=1b0;
#0 A=4b0001; A(4 bit)
#0 B=4b1001; Testbench DUT
#10 if(golden_ref==Y) B(4 bit)
$display(Test Passed); Y(4 bit)
end
xor_design u0_xor_design(.clk(clk),
.reset(reset),
.A(A),
.B(B),
.Y(Y));
endmodule

Verilog Code

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wire 11

SystemVerilog Basic Datatypes

logic

logic[dimension1:dimension2]variable_name;

SV improves the classic reg data type so that it can be driven by continuous assignments, gates and modules in addition to being a
variable. Cannot be driven by multiple drivers

logic is an improvement over classic reg data type

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SystemVerilog Basic Datatypes

logic

logic [dimension1:dimension2]variable_name;

keyword dimensions Variable name

SV improves the classic reg data type so that it can be driven by continuous assignments, gates and modules in addition to being a
variable. Cannot be driven by multiple drivers and is a 4-state variable (can have the values 0,1,x or z)

logic is an improvement over classic reg data type

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SystemVerilog Basic Datatypes

logic [dimension1:dimension2]variable_name; example logic [0:7]a;

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logic
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SystemVerilog Basic Datatypes

module test_xor()
logic clk=0;
logic reset=0;
logic [3:0] A,B;
logic [3:0] golden_ref;
logic [3:0] Y; Procedural statement
always #5 clk=~clk;
assign reset=1b0;
Continuous assignment
initial
begin
#0 A=4b0001;
#0 B=4b1001;
#10 if(golden_ref==Y)
$display(Test Passed);
end
xor_design u0_xor_design(.clk(clk),
.reset(reset),
.A(A),
.B(B), Driven by a module
.Y(Y));
endmodule

SystemVerilog Code

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logic 15

Logic data type

logic [7:0] a; logic [0:7] a;

7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7

Logic datatype creates vectors of dimensions specified 16

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Logic data type

logic [7:0] a; logic [0:7] a;

7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7

a[0]<=1; a[0]<=1;
a[1]<=1; a[1]<=1;
a[2]<=0; a[2]<=0;
a[3]<=1; a[3]<=1;
a[4]<=0; a[4]<=0;
Initialize the vector a[5]<=0; Initialize the vector a[5]<=0;
a[6]<=1; a[6]<=1;
a[7]<=1; a[7]<=1;
a[8]<=0 a[8]<=0;

Logic datatype creates vectors of dimensions specified 17

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Logic data type

logic [7:0] a; logic [0:7] a;

7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7

a[0]<=1; a[0]<=1;
a[1]<=1; a[1]<=1;
a[2]<=0; a[2]<=0;
a[3]<=1; a[3]<=1;
a[4]<=0; a[4]<=0;
initialized a[5]<=0; Initialized a[5]<=0;
a[6]<=1; a[6]<=1;
a[7]<=1; a[7]<=1;
a[8]<=0 a[8]<=0;

7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1

Logic datatype creates vectors of dimensions specified 18

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SystemVerilog 2-State Datatypes

byte a
bit[7:0] a

8 bits
User defined
signed
unsigned

byte
bit

int a shortint a longint a

32 bits 16 bits 64 bits

signed signed signed

int shortint longint

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SystemVerilog 2-State Datatypes

value of a value of a
0 to 255 byte a -127 to +127
bit[7:0] a

8 bits
User defined
signed
unsigned

byte
bit
value of a
-(2^32-1) to +(2^32-1) value of a value of a
-(2^16-1) to +(2^16-1) -(2^64-1) to +(2^64-1)

int a shortint a longint a

32 bits 16 bits 64 bits

signed signed signed

int shortint longint

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2 State Vs 4 State Datatypes

SystemVerilog introduced 2 state datatypes to improve

simulation performance and memory consumption.

A 4 state datatype can have the value 0,1,x,z

$isunknown(variable);
A 2 state datatype can only have the value 0 or 1

4 state variable being simulation with x and 2 state

Will return 1 if any bit
In built function
variable begin simulation with 0 of the variable is x or
z

Can logically assign a 4 state datatype to a 2 state

datatype. x and z are assigned as 0s in that case.

Never use 2 state variables with interfaces. If they are

used then it is hard to detect x and zs in the design

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System Verilog Single Dimensional Arrays

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Arrays

Multiple dimensions supported

logic array1 [0:7];
Out-of-bounds write ignored

Out-of-bounds read returns x or 0 depending on type 1 bit

array1

1
type array_name [dimensions]
2

3
Can be of any type A unique name given Defines the size of
logic, bit, int etc. to the array the array 4

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Initializing Single Dimension Arrays

4 bits
array1
module init_array()
logic clk=0; 0 8
logic reset=0;
Logic [3:0] array1[0:7]; 1 7
int i;
always #5 clk=~clk; 2 6
initial
begin 3 5
for(i=0;i<8;i=i+1)
begin 4 4
array1[i]<=8-i;
end 5 3
end
endmodule 2
6

7 1

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Initializing Single Dimension Arrays

$size(array_name);

$size returns the size

of an array 4 bits
array1

module init_array() 0 8
logic clk=0;
logic reset=0; 1 7
Logic [3:0] array1[0:7];
int i; 2 6
always #5 clk=~clk;
initial 3 5
begin
for(i=0;i<$size(array1);i=i+1) 4 4
begin
array1[i]<=8-i; 5 3
end
end 2
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endmodule
7 1

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System Verilog Multidimensional Arrays

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Multidimensional Arrays

Multiple dimensions supported

logic [3:0] array2d [0:7][0:7];
Out-of-bounds write ignored

Out-of-bounds read returns x or 0 depending on type

4 bits array2d

1
type array_name [dimensions][dimensions]; 2

Can be of any type A unique name given Define the size of the
4
logic, bit, int etc. to the array array
5

0 1 2 3 4 5 6 7
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Initializing Arrays
foreach (array[dim1,dim2]);

Steps through each element, there is no

need to declare the variables needed to
index

4 bits array2d

module init_array() 0
logic clk=0;
logic reset=0; 1
logic [3:0] array2d[0:7][0:7];
always #5 clk=~clk; 2
initial
begin 3
foreach(array2d[[i,j])
begin 4
array2d[i,j]<=i+j;
end 5
end
endmodule
6

0 1 2 3 4 5 6 7
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Initializing Arrays
foreach (array[dim1,dim2]);

Steps through each element, there is no

need to declare the variables needed to
index

4 bits array2d

module init_array() 0 1 2 3 4 5 6 7
0
logic clk=0;
logic reset=0; 1 1 2 3 4 5 6 7 8
logic [3:0] array2d[0:7][0:7];
always #5 clk=~clk; 2 2 3 4 5 6 7 8 9
initial
begin 3 3 4 5 6 7 8 9 10
foreach(array2d[[i,j])
begin 4 4 5 6 7 8 9 10 11
array2d[i,j]<=i+j;
end 5 5 6 7 8 9 10 11 12
end
endmodule 6 7 8 9 10 11 12 13
6

7 7 8 9 10 11 12 13 14

0 1 2 3 4 5 6 7
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Array Operations

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Bit Array Copy and Compare Operations

Can perform copy and compare without loops only == or != operations

Cannot perform aggregate operations such as additions on arrays

initial begin
bit [31:0] src[5] = {0,1,2,3,4},
dst[5] = {5,4,3,2,1}; 5 0 0
5
0
if(src==dst)
$display(src==dst); 1 1 1
4
else
2 2 2
3
$display(src!=dst);
dst=src; 3 2
3
src[0]=5; 3
if(src[1:4]==dst[1:4]) 4 1
4
4
$display(src==dst);
else
32 bits 32 bits
$display(src!=dst);
end
src dst

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Bit and Array Subscripts Together

initial
begin
bit [31:0] src[5] = {5{5}},
$displayb(src[0],src[2][2:1],src[4][5]);
end

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

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Bit and Array Subscripts Together

initial
begin
bit [31:0] src[5] = {5{5}},
$displayb(src[0],src[2][2:1],src[4][5]);
end

$display(src[2][2:1])
$display(src[0])

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

$display(src[4][5])
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Packed Arrays

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Packed Arrays
Treated as a both an array and a single value

Stored as contiguous bits in memory type [dim1][dim2] array_name;

Easy to slice

Packed bit and word dimensions should be specified Array types dimensions Name of the array

Dimensions must be specified in [lo:hi] format

bit [3:0] [7:0] array_packed;

3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

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Packed Array: Initialization

Packed arrays can be initialized at declaration using simple assignments

The assignment can be a constant value, a concatenation of constant values or a replication of constant values

logic [3:0][7:0] a = 32h0; Vector assignment

logic [3:0][7:0] b = {16hz, 16h0}; Concatenate operator
logic [3:0][7:0] c = {16{2b01}}; Replicate operator

3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

a=32h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

b={16hz,16h0} z z z z z z z z z z z z z z z z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

c={16{2b01}} 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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Packed Arrays: More Example

bit [3:0][7:0]packed_array;
packed_array=32habcd_efab;
$displayb(packed_array);

3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

packed_array 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 0 1 0 1 1

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Packed Arrays: More Examples

bit [3:0][7:0]packed_array;
packed_array=32habcd_efab;
$displayb(packed_array[3]);

3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

packed_array[3] 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 0 1 0 1 1

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Packed Arrays: More Examples

bit [3:0][7:0]packed_array;
packed_array=32habcd_efab;
$displayb(packed_array[2][5]);

3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

packed_array[2][5] 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 0 1 0 1 1

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Multidimensional Packed Arrays: Mixed Arrays

Common to have combination of packed and unpacked

array
type [dim1][dim2] array_name [dim];
p_array is an unpacked array of three packed elements

which dimension is unpacked? Packed Unpacked

Array types Name of the array dimension
dimensions

bit [3:0] [7:0] array_packed [0:2];

3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

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Mixed Arrays: Indexing

When indexing mixed arrays, unpacked dimensions are referenced first from the left-most to the right-most dimension
Packed dimensions are referenced second from the left-most dimension to the right-most dimension

0 1

3 2 1 0 3 2 1 0

2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0
0

1 1

logic [3:0][2:0]mixed_array[0:1][0:2]

mixed_array [0] [1] [2] [1] = 1b1;

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Thank You

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