CXP85112B/85116B

CXP85220A/85224A/85228A/85232A
CMOS 8-bit Single-chip Microcomputer

Description
The CXP85112B/85116B, CXP85220A/85224A/ 64 pin SDIP (Plastic) 64 pin QFP (Plastic)
85228A/85232A is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, vector interruption, on-screen display function,
I2C bus interface, PWM generator, remote control
reception circuit, HSYNC counter, power source
frequency counter and watch dog timer besides the
basic configurations of 8-bit CPU, ROM, RAM, and
l/O port.
The CXP85112B/85116B, CXP85220A/85224A/
85228A/85232A also provides a power-on reset Structure
function and a sleep function that enables lower Silicon gate CMOS IC
power consumption.

Features
Wide-range instruction system (213 instructions) to cover various types of data
16-bit arithmetic/multiplication and division/boolean bit operation instructions
Minimum instruction cycle 1s at 4MHz operation
Incorporated ROM capacity 12K bytes (CXP85112B)
16K bytes (CXP85116B)
20K bytes (CXP85220A)
24K bytes (CXP85224A)
28K bytes (CXP85228A)
32K bytes (CXP85232A)
Incorporated RAM capacity 352 bytes (CXP85112B/85116B)
448 bytes (CXP85220A/85224A/85228A/85232A)
Peripheral functions
On-screen display function 12 16 dots, 128 types
21 words 4 Iines (more than 4 Iines possible)
Double scan mode compatible, jitter elimination circuit
I2C bus interface
PWM output 14 bits, 1 channel
6 bits, 8 channels
Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO
A/D converter 4 bits, 4channels, successive approximation method
(Conversion time of 40s/4MHz)
HSYNC counter
Power supply frequency counter
Watch dog timer
Serial I/O 8-bit clock synchronization
Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer
Interruption 14 factors, 14 vectors, multi-interruption possible
Standby mode Sleep
Package 64-pin plastic SDIP/QFP
Piggyback/evaluation chip CXP85100A, CXP85190 (Custom font compatible)
CXP85200A, CXP85290 (Custom font compatible)

Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

1
E93Z17C15-PS
 Block Diagram

PD0/INT2
PE1/INT1
MP

XTAL
EXTAL
VSS

RST

PE0/INT0
VDD
EXLC
XLC
B SPC700 CLOCK GEN./ PA0 to PA7
G CPU CORE SYSTEM CONTROL
2
PORT A

ON SCREEN DISPLAY
R
BLK
HSYNC
VSYNC
PB0 to PB7
PD3/SI 2
ROM
PORT B

PD2/SO SERIAL I/O RAM

12K/16K/20K/24K/28K/32K
PD1/SCK BYTES 352/448 BYTES

INTERRUPT CONTROLLER
PD7/EC
TIMER/COUNTER PC0 to PC7
PE7/TO
PORT C

PD6/RMC REMOCON FIFO

PD0 to PD7

2
PORT D

PD4/HSI HSYNC COUNTER

WATCH DOG TIMER PRESCALER/

TIME BASE TIMER PE0 to PE5
PD5/ACI AC TIMER
PORT E

PE6 to PE7

PE2/AN0
to A/D CONVERTER
PE5/AN3
PF0 to PF7
PORT F

PF4/SCL0
PF5/SCL1 14 BIT PWM 6 BIT PWM 8CH
I2C INTERFACE UNIT
PF6/SDA0
PF7/SDA1
to

PE6/PWM
PF0/PWM0
PF7/PWM7
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Pin Assignment 1 (Top View) 64 pin SDIP Package

PA7 1 64 VDD
PA6 2 63 NC
PA5 3 62 VSS
PA4 4 61 MP
PA3 5 60 PF0/PWM0
PA2 6 59 PF1/PWM1
PA1 7 58 PF2/PWM2
PA0 8 57 PF3/PWM3
PB7 9 56 PF4/PWM4/SCL0
PB6 10 55 PF5/PWM5/SCL1
PB5 11 54 PF6/PWM6/SDA0
PB4 12 53 PF7/PWM7/SDA1
PB3 13 52 BLK
PB2 14 51 R
PB1 15 50 G
PB0 16 49 B
PC7 17 48 VSYNC
PC6 18 47 HSYNC
PC5 19 46 EXLC
PC4 20 45 XLC
PC3 21 44 PE0/INT0
PC2 22 43 PE1/INT1
PC1 23 42 PE2/AN0
PC0 24 41 PE3/AN1
PD7/EC 25 40 PE4/AN2
PD6/RMC 26 39 PE5/AN3
PD5/ACI 27 38 PE6/PWM
PD4/HSI 28 37 PE7/TO
PD3/SI 29 36 RST
PD2/SO 30 35 EXTAL
PD1/SCK 31 34 XTAL
VSS 32 33 PD0/INT2

Note) 1. NC (Pin 63) must be connected to VDD.

2. Vss for both Pins 32 and 62 must be grounded.
3. MP (Pin 61) must be connected to GND.

3
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Pin Assignment 2 (Top View) 64 pin QFP Package

PF2/PWM2
PF1/PWM1
PF0/PWM0
PA2

PA7
PA6
PA5
PA4
PA3

VSS
VDD

MP
NC
64 63 62 61 60 59 58 57 56 55 54 53 52

PA1 1 51 PF3/PWM3
PA0 2 50 PF4/PWM4/SCL0
PB7 3 49 PF5/PWM5/SCL1
PB6 4 48 PF6/PWM6/SDA0
PB5 5 47 PF7/PWM7/SDA1
PB4 6 46 BLK
PB3 7 45 R
PB2 8 44 G
PB1 9 43 B
PB0 10 42 VSYNC
PC7 11 41 HSYNC
PC6 12 40 EXLC
PC5 13 39 XLC
PC4 14 38 PE0/INT0
PC3 15 37 PE1/INT1
PC2 16 36 PE2/AN0
PC1 17 35 PE3/AN1
PC0 18 34 PE4/AN2
PD7/EC 19 33 PE5/AN3

20 21 22 23 24 25 26 27 28 29 30 31 32
RST
PD2/SO

EXTAL
PD3/SI

XTAL
PD4/HSI

PD0/INT2
PD5/ACI

PE6/PWM
VSS
PD6/RMC

PE7/TO
PD1/SCK

Note) 1. NC (Pin 56) must be connected to VDD.

2. Vss for both Pins 26 and 58 must be grounded.
3. MP (Pin 55) must be connected to GND.

4
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Pin Description

Symbol I/O Description

(Port A)
PA0 to PA7 I/O 8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port B)
PB0 to PB7 I/O 8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port C)
PC0 to PC7 I/O 8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
External interruption request input.
PD0/INT2 I/O/Input
Active at falling edge.
PD1/SCK I/O/I/O Serial clock I/O.
(Port D)
PD2/SO I/O/Output 8-bit I/O port. Serial data output.
I/O can be set ina a
PD3/SI I/O/Input Serial data input.
unit of single bits.
PD4/HSI I/O/Input Capable of driving HSYNC counter input.
12mA sink current.
PD5/ACI I/O/Input Input for power supply frequency counter.
(8 pins)
PD6/RMC I/O/Input Input for remote control reception circuit.
PD7/EC I/O/Input External event input for timer/counter.
External interruption request inputs.
PE0/INT0
Input/Input Active at falling edge.
PE1/INT1
(2 pins)
PE2/AN0 (Port E)
Analog inputs for A/D converter.
to Input/Input 8-bit port. Lower
(4 pins)
PE5/AN3 6 bits are for inputs;
upper 2 bits are for
14-bit PWM output.
PE6/PWM Output/Output outputs.
(CMOS output)
Rectangular waveform output for Timer 1.
PE7/TO Output/Output
(Duty output 50%)
PF0/PWM0 (Port F)
6-bit PWM outputs.
to Output/Output 8-bit output port,
(8 pins)
PF3/PWM3 operating as N-ch
open drain output
PF4/PWM4/
for high current
SCL0 Output/Output/ Transfer clock I/Os for I2C bus
(12mA).
PF5/PWM5/ I/O interface.
Lower 4 bits are
SCL1
medium voltage
PF6/PWM6/ drive outputs (12V),
SDA0 Output/Output/ upper 4bits are 5V
Transfer data I/Os for I2C data bus.
PF7/PWM7/ I/O drive outputs.
SDA1 (8 pins)
R, G, B, BLK Output 4-bit outputs for CRT display.
HSYNC Input Horizontal synchronizing signal input for CRT display.
VSYNC Input Vertical synchronizing signal input for CRT display.

5
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Symbol I/O Description

EXLC Input Clock oscillation I/Os for CRT display.
XLC Output Oscillation frequency is set using the external L and C.

EXTAL Input Crystai connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
XTAL Output input to XTAL.
Low-level active, system reset. RST is an I/O, from whlch Low level is
RST I/O output when the built-in power-on reset function is activated at the rise
of power on. (Mask option)
MP Input Microprocessor mode input. For this device, this pin must be grounded.
VDD Vcc supply.
Vss GND. Both Vss must be grounded.

6
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Input/Output Circuit Formats for Pins

Pin Circuit format When reset

AAAA
Port A
Port B

AAAA AA
Data for Ports
Port C A, B, and C

AAAA
PA0 to PA7

AAAA AA
PB0 to PB7 Direction for
PC0 to PC7 Ports A, B, and C Hi-Z

AA
Input protection
IP
circuit
Data bus

RD (Ports A, B, and C)
24 pins

AAAA
Port D

PD0/INT2
PD3/SI AAAA
AAAA
Port D data

Port D direction
AA
AA
AA
PD4/HSI High current
PD5/ACI 12mA
Hi-Z

AA
PD6/RMC
PD7/EC Data bus IP

RD (Port D)
INT2, SI, HSI, ACI, RMC, EC Schmitt input

6 pins

Port D

AA
SCK or SO

Output eneble

AAAA AA
AA
High current
12mA

AAAA AA
PD1/SCK
Port D data Hi-Z
PD2/SO IP

Port D direction

Schmitt input
Data bus

RD (Port D)
SCK only

2 pins

7
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

AAAA
Pin Circuit format When reset
Port E Schmitt input
PE0/INT0
IP (To interruption circuit)
PE1/INT1
Hi-Z
Data bus
2 pins
RD (Port E)

AA A
Port E
Input multiplexer

AAA
PE2/AN0 IP To A/D converter
to
PE5/AN3 Hi-Z

Data bus

4 pins RD (Port E)

Port E

AAAA AA
TO, PWM
PE6/PWM
PE7/TO

AAAA Port E data

AA High level

2 pins
AAAA Port selection

Port F
PWM

AAAAA AA
PF0/PWM0 Middle tension proof 12V
to

AAAAA AA
PF3/PWM3 Port F data Hi-Z

AAAAA
High current
Port selection 12mA
4 pins

PF4/PWM4/
Port F

SCL, SDA AA
AA
SCL0 I2C output enable
PF5/PWM5/
SCL1

AAAA AA
PWM
PF6/PWM6/
SDA0 Hi-Z

AAAA AA
PF7/PWM7/ Port F data
SDA1 IP

AAAA
Port selection
Schmitt input BUS SW
SCL, SDA To other I2C pins
(To I2C circuit)
4 pins

8
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Pin Circuit format When reset

AAAA AA
BLK BLK, R, G, B
R

AAAA
G
B Output polarity Hi-Z

Hi-Z output active

4 pins by writing into the output polarity register.

AAA
Schmitt input

AAAAAA
HSYNC IP HSYNC
VSYNC VSYNC
Hi-Z

2 pins
AAAA Input polarity

AA AA
AA AA
EXLC IP Oscillation control
EXLC

AA A
XLC Oscillation
terminated

AA A
XLC IP CRT display clock

2 pins

AA A
AA A
Diagram shows
circuit composition
EXTAL during oscillation.
EXTAL IP

AA
XTAL
Feedback resistor Oscillation
is removed during

AA
stop.

XTAL
2 pins

Pull-up resistance

AA
RST
Mask option OP Schmitt input

AA
Low level

From power-on reset circuit

(Mask option)
1 pin

MP

1 pin
AAAA IP CPU mode Hi-Z

9
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks

Supply voltage VDD 0.3 to +7.0 V
Input voltage VIN 0.3 to +7.01 V
Output voltage VOUT 0.3 to +7.01 V
Medium voltage drive output voltage VOUTP 0.3 to +15.0 V Pins PF0 to PF3
High level output current IOH 5 mA
High level total output current IOH 50 mA Total for all output pins
IOL 15 mA Excludes high current outputs
Low level output current
IOLC 20 mA High current outputs2
Low level total output current IOL 130 mA Total for all output pins
Operating temperature Topr 20 to +75 C
Storage temperature Tstg 55 to +150 C
1000 mW SDIP
Allowable power dissipation PD
600 mW QFP
1 VIN and VOUT must not exceed VDD + 0.3V.
2 The high current operation transistor is the N-ch transistor of PD and PF0 to PF3.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions.
Exceeding these conditions may adversely affect the reliability of the LSI.

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

4.5 5.5 V Guaranteed operation range
Low-speed mode guaranteed
3.5 5.5 V
Supply voltage VDD operation range1
Guaranteed data hold range
2.5 5.5 V
during stop
VIH 0.7VDD VDD V Includes I2C Schmitt input2
High level input voltage VIHS 0.8VDD VDD V CMOS Schmitt input3
VIHEX VDD 0.4 VDD + 0.3 V EXTAL4
VIL 0 0.3VDD V Includes I2C Schmitt input2
Low level input voltage VILS 0 0.2VDD V CMOS Schmitt input3
VILEX 0.3 0.4 V EXTAL4
Operating temperature Topr 20 +75 C
1 Specifies only for 1/16 frequency demultiplication mode and sleep mode.
2 Value for each pin of normal input ports (PA, PB, PC, PE2 to PE5), PF4 to PF7, and MP.
3 Value of the following pins: PD0/lNT2, PD1/SCK, PD2, PD3/Sl, PD4/HSl, PD5/ACI, PD6/RMC, PD7/EC,
PE0/INT0, PE1/lNT1, HSYNC, VSYNC, RST.
4 Specifies only during external clock input.
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 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Electrical Characteristics

DC Characteristics (Ta = 20 to +75C, Vss = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit

High level output PA to PD, PE6, PE7, VDD = 4.5V, IOH = 0.5mA 4.0 V
VOH
current R, G, B, BLK VDD = 4.5V, IOH = 1.2mA 3.5 V
PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA 0.4 V
R, G, B, BLK,
PF0 to PF3, RST1 VDD = 4.5V, IOL = 3.6mA 0.6 V
Low level output
VOL PD, PF0 to PF3 VDD = 4.5V, IOL = 12.0mA 1.5 V
current
PF4 to PF7 VDD = 4.5V, IOL = 3.0mA 0.4 V
(SCL0, SCL1,
SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA 0.6 V
IIHE VDD = 5.5V, VIH = 5.5V 0.5 40 A
EXTAL
Input current IIHL VDD = 5.5V, VIL = 0.4V 0.5 40 A
IILR RST2 VDD = 5.5V, VIL = 0.4V 1.5 400 A
PA to PE, HSYNC,
VDD = 5.5V
I/O leakage current IIZ VSYNC, R, G, B, 10 A
BLK, RST2, MP
VI = 0, 5.5V

Open drain output PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 A

leakage current ILOH
(N-ch Tr in off state) PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 A
Impedance connected VDD = 4.5V
SCL0: SCL1
to I2C bus switch RBS VSCL0 = VSCL1 = 2.25V 120
SDA0: SDA1
(output Tr in off state) VSDA0 = VSDA1 = 2.25V
Operation mode3
(1/2 frequency
IDD demultiplier clock)
8 20 mA
4MHz crystal oscillation
Power supply current VDD3 (C1 = C2 = 22pF)
All outputs open
IDDSL Sleep mode 0.5 2 mA
IDDST Stop mode4 A
Pins other than Clock 1MHz pF
Input capacity CIN 10 20
VDD and Vss 0V for all pins excluding
1 RST specifies only when the power-on reset circuit has been selected througn mask option.
2 RST specifies input current when the pull-up resistance has been selected; Ieakage current when no
resistance has been selected.
3 Specifies only when the oscillatlon of OSD has been terminated.
4 This device does not enter the stop mode.

11
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

AC Characteristics
(1) Clock timing (Ta = 20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pins Conditions Min. Max. Unit

System clock frequency XTAL 3.5 4.5 MHz

fC Fig. 1, Fig. 2
EXTAL
System clock input tXL, Fig. 1, Fig. 2
100 ns
EXTAL
pulse width tXH External clock drive
System clock input rise tCR, Fig. 1, Fig. 2
200 ns
EXTAL
time, fall time tCF External clock drive
Event clock input clock tEH, Fig. 3 tsys + 501 ns
EC
pulse width tEL
Event count input clock tER, Fig. 3 20 ms
EC
rise time, fall time tEF
1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

1/fc

VDD 0.4V
EXTAL
0.4V

tXH tCF tXL tCR

Fig. 1. Clock timing

AAAAA AAAAA
AAAAA AAAAA
Crystal oscillation
Ceramic oscillation External clock

AAAAA EXTAL

C1
XTAL

C2
AAAAA EXTAL XTAL

OPEN

Fig. 2. Clock applying condition

0.8VDD
EC
0.2VDD

tEH tEF tEL tER

Fig. 3. Event count clock timing

12
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

(2) Serial transfer (Ta = 20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

Input mode 1000 ns
SCK cycle time tKCY SCK
Output mode 8000/fc ns

SCK High and Low level tKH SCK input mode 400 ns
SCK
widths tKL SCK output mode 4000/fc 50 ns

SI input setup time SCK input mode 100 ns

tSIK SI
(for SCK ) SCK output mode 200 ns

SI input hold time SCK input mode 200 ns

tKSI SI
(for SCK ) SCK output mode 100 ns
SCK input mode 200 ns
SCK SO delay time tKSO SO
SCK output mode 100 ns

Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.

tKCY

tKL tKH

0.8VDD
SCK
0.2VDD

tSIK tKSI

0.8VDD
SI Input data
0.2VDD

tKSO

0.8VDD
SO Output data
0.2VDD

Fig. 4. Serial transfer timing

13
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

(3) Interruption, reset input (Ta = 20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

External interruption High and tIH INT0 to 1 s
Low level widths tIL INT2
Reset input Low level width tRSL RST 8/fc s

tIH tIL

INT0 to INT2 0.8VDD

(Falling edge)
0.2VDD

Fig. 5. Interruption input timing

tRSL

RST
0.2VDD

Fig. 6. RST input timing

(4) Power on reset

Power on reset (Ta = 20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

Power supply rise time tR Power-on reset 0.05 50 ms
VDD
Power supply cut-off time tOFF Repetitive power-on reset 1 ms
Specifies only when the power-on reset function has been selected.

4.5V
VDD

0.2V 0.2V

tR tOFF

The power supply should be raised smoothly.

Fig. 7. Power-on reset

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 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

(5) A/D converter characteristics (Ta = 20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit

Resolution 4 Bits
Linearity error 1 LSB
Zero transition Ta = 25C
VZT1 10 160 320 mV
voltage VDD = 5.0V
Vss = 0V
Full-scale transition
VFT2 4370 4530 4690 mV
voltage
Conversion time tCONV 160/fc s
Sampling time tSAMP 12/fc s
Analog input voltage VIAN AN0 to AN3 0 VDD V

FH
EH
Digital conversion value

1 VZT: Value at which the digital conversion value changes

from 0H to 1H and vice versa.
2 VFT: Value at which the digital conversion value changes
from EH to FH and vice versa.
Linearity error

1H
0H
VZT VFT
Analog input

Fig. 8. Definition of A/D converter terms

Note) The 4-bit conversion specifies values based on the upper 5 bits of the A/D data register (ADD: Address
00F5H), compensated into 4-bit data. A program example is shown below:

(A/D converter program example)

MOV A, ADD ; ACC conversion data
LSR A ; Shift to the right (4 times)
LSR A ;
LSR A ;
LSR A ;
ADC A, #00H ; Addition with carry (data increment if AD3 = 1)
CMP A, #10H ;
BNE ADC_SKIP ;
MOV A, #0FH ;
ADC_SKIP:

15
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

(6) I2C bus timing (Ta = 20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

SCL clock frequency fSLC SCL 0 100 kHz
Bus free time prior to transfer start tBUF SDA, SCL 4.7 s
Transfer start hold time tHD; STA SDA, SCL 4.0 s
Clock Low level width tLOW SCL 4.7 s
Clock High level width tHIGH SCL 4.0 s
Setup time during repetitive transfer tSU; STA SDA, SCL 4.7 s
Data hold time tHD; DAT SDA, SCL 01 s
Data setup time tSU; DAT SDA, SCL 250 ns
SDA, SCL rise time tR SDA, SCL 1 s
SDA, SCL fall time tF SDA, SCL 300 ns
Transfer end setup time tSU; STO SDA, SCL 4.7 s
1 The data hold time does not take into consideration SCL rise time (300ns max.). Ensure that the data hold
time exceeds 300ns.

SDA
tBUF
tR tF tHD; STA

SCL
tHD; STA
tSU; STA tSU; STO
P S tLOW tHD; DAT tHIGH tSU; DAT St P

Fig. 9. I2C bus transfer timing

I2C device I2C device

RS RS RS R S RP RP

SDA0
(or SDA1)
SCL0
(or SCL1)

Fig. 10. Recommended circuit example for I2C device

Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
Serial resistance (Rs = 300 and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise
caused by CRT flashover.

16
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

(7) OSD (On-Screen Display) timing (Ta = 20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Condition Min. Max. Unit

EXLC
OSD clock frequency fOSC Fig. 12 4 13 MHz
XLC
HSYNC pulse width tHWD HSYNC Fig. 11 1.2 s
VSYNC pulse width tVWD VSYNC Fig. 11 1.0 H*
HSYNC after-edge ns
tHCG HSYNC Fig. 11 200
rise time/fall time
VSYNC after-edge s
rise time/fall time
tVCG VSYNC Fig. 11 1.0

* H indicates 1HSYNC period.

tHCG
tHWD

HSYNC 0.8VDD
when Bit 5 of OPOL register
(01FBH) is set to "0"
0.2VDD

tVCG
tVWD

VSYNC 0.8VDD
when Bit 4 of OPOL register
(01FBH) is set to "0"
0.2VDD

Fig. 11. OSC timing

EXLC XLC

C1 C2

Fig. 12. LC oscillation circuit example

17
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Supplement

AAAAA AAAAA
AAAAA AAAAA
(i) (ii)

AAAAA EXTAL

C1
XTAL

Rd

C2
AAAAA EXTAL XTAL

Rd

C1 C2

Fig. 13. Recommended Oscillation circuit

Circuit
Manufacturer Model fc (MHz) C1 (pF) C2 (pF) Rd ()
example
CSA4.00MG 4.00
(i)
MURATA CSA4.19MG 4.19
MFG 30 30 0
CO., LTD. CST4.00MGW 4.00
(ii)
CST4.19MGW 4.19

RIVER ELETEC 4.00

HC-49/U03 10 10 0
CORPORATION 4.19
(i)
KINSEKI 4.00
HC-49/U (-S) 18 18 0
LTD. 4.19
Indicates types with on-chip grounding capacitance (C1 and C2).

Mask option table

Item Content
Reset pin pull-up resistance Non-existent Existent
Power-on reset circuit Non-existent Existent

18
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

IDD vs. VDD IDD vs. fc

(fc = 4MHz, Ta = 25C typical) (VDD = 5V, Ta = 25C typical)
15 12
1/2 frequency
10 1/2 frequency 11 demultiplication mode
demultiplication mode
10
1/4 frequency
demultiplication mode
9

IDD Power supply current [mA]

IDD Power supply current [mA]

1/16 frequency 8
demultiplication mode
7
1 1/4 frequency
6 demultiplication mode

Sleep mode 5

3 1/16 frequency
demultiplication mode
2
0.1
1
Sleep mode
0
1 2 3 4 5 6
2 3 4 5 6
VDD Supply voltage [V] fc System clock [MHz]

OSD oscillation vs. C

Calculated curves
(reference value by theoretical calculation)
100
L Inductasce [H]

5.0MHz

6.5MHz
10

13.0MHz

1
fosc = C = C1//C2
2 LC
1
0 50 100
C1, C2 Capacitance [pF]

Fig. 14. Characteristics curves

19
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Package Outline Unit: mm

64PIN SDIP (PLASTIC)

0.05
+ 0.1
+ 0.4

0.25
57.6 0.1

64 33

17.1 0.1
+ 0.3
0 to 15

19.05
1 32
1.778

4.75 0.1
+ 0.3
0.5 MIN
3.0 MIN
0.5 0.1

0.9 0.15

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-SDIP64-17.1x57.6-1.778 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 8.6g

64PIN SDIP (PLASTIC)

0.05
+ 0.1

+ 0.4
0.25

57.6 0.1

64 33
17.1 0.1
+ 0.3

0 to 15
19.05

1 32
1.778
4.75 0.1
+ 0.3
0.5 MIN
3.0 MIN

0.5 0.1

0.9 0.15

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-SDIP64-17.1x57.6-1.778 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 8.6g

LEAD SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL ALLOY 42
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18m

20
 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Package Outline Unit: mm

64PIN QFP (PLASTIC)

23.9 0.4
+ 0.4 + 0.1
20.0 0.1 0.15 0.05

51 33 0.15

52 32

14.0 0.1
+ 0.4

17.9 0.4

16.3
64 20
+ 0.2
0.1 0.05

1
19

0.8 0.2
1.0 + 0.15 + 0.35
0.4 0.1 2.75 0.15
0 to10
0.2 M

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-64P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-QFP64-14x20-1.0 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 1.5g

64PIN QFP (PLASTIC)

23.9 0.4
+ 0.4 + 0.1
20.0 0.1 0.15 0.05

51 33 0.15

52 32
14.0 0.1
+ 0.4

17.9 0.4

16.3

64 20
+ 0.2
0.1 0.05

1
19
0.8 0.2

1.0 + 0.15 + 0.35

0.4 0.1 2.75 0.15
0 to10
0.2 M

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-64P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-QFP64-14x20-1.0 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 1.5g

LEAD SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL ALLOY 42
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18m

21 Sony Corporation
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.