On-chip clock generation

and distribution
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Index
Introduction
Characteristics
Clock generation
Clock distribution
Summary
VTU questions
References
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Introduction
Clock signals are heartbeats of digital systems .

For synchronized designs, data transfer between functional elements are

synchronized by clock signals

Stability of Clock signal is important.

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Characteristics:
Minimum rise and fall times
Specified duty cycles
Zero skew
In reality, clock signals have
Non zero skews
Noticeable rise and fall times
Duty cycles may vary
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Skew
Clock skew is the maximum difference in the arrival time of a clock
signal at two different components.

So, in addition to other objectives, clock skew should be minimized

during clock routing.

Fig a
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Clock circuit used in low end microprocessor chips:

These are process dependent and unstable

Fig 1 simple on chip clock generator circuit using a ring oscillator

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Clock chips for high performance VLSI chips:

It has good frequency stability
Derivative of colpitts oscillator

Fig 2 Circuit diagram of a Pierce crystal oscillator circuit

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Continued..

VLSI chip receives one or more primary clock signals

I t is necessary to use non overlapping clock signals
Figure 3 shows circuit that generates CK-1 & CK-2 from original clock
signal CK

Fig 3 simple circuit that generates a pair of non-overlapping clock

signal from CK
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Continued..

Figure 4 shows clock decoder circuit that takes in primary clock signals &
generates 4 phase signals
INPUT OUTPUT
All clock signals have uniform delay
CK CK CK CK
1 2 3 4
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 0 1
1 1 0 0 1 0

Fig 4Clock decoder a) Symbolic representation b)Sample waveform

& gate level implementation
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Topologies:
Grid

Spine

Tree
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Grid/Mesh Clock source

n x n uniform mesh
Distributed array of k x k buffers
drives the mesh.
flip flops Flip-flops directly connected to the
nearest mesh segment
Used in modern processors
Advantages
Excellent for low skew
Robust to variations
Disadvantages
Higher wiring area, capacitance, power
Difficult to analyse
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Spine
Easyto analyze
Low cost
FPGAs use this routing scheme
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Tree
Widelyused in ASICs
Advantages
Low cost
Clock gating easy
Disadvantages
Difficult to implement
Sensitive to variations
Flip-flops
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Continued..

An ideal distribution network is H-tree structure shown in Fig 5.

Here center to all branches distance is same
It is difficult to implement

Fig 5 General layout of an H-tree clock

distribution network
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Continued..

A practicalapproach route main clock signals to macro blocks &use local clock
decoders to carefully balance the delays
Zero-skew clock routing network is shown in below figure.

Fig 6 An example of the zero-skew clock routing network. generated by

computer-aided design tool
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Continued..

To handle high fan out loads, signals must be buffered in multiple stages such a
clock distribution is a shown in below figure 7
Each buffer stage drives same number of fan out gates so that clock delays are
always balanced.
Figure 8 shows clock distribution structure network used in DEC alpha
microprocessor chips

Fig 7 : Three level buffered clock distribution network Fig 8: General structure of clock
distribution network used in DEC alpha
microprocessor chips
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For successful high speed VLSI design:

Ideal duty cycle of clock signal is 50%.
Rise time & fall time shouldnt be reduced excessively
The load capacitance should be reduced.
Adequate separation should be maintained between high speed clock lines
in order to prevent cross talk.
Inductive loads can be used
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Summary
This seminar represents generation of clock signal for low end
microprocessors, clock decoder circuit, H-tree, Zero-skew clock routing ,
buffered clock distribution networks.
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Reference
Sung-Mo Kang, Yusuf Lelblebici, CMOS digital integrated cirucits, Mc Graw
Hill education,3rd Edition
Pierce crystal oscillator,an introduction , Ramon Cerda, Director of Engineering,
Crystek Corporation,march 2008
M.K. Mandal ,B.C Sharkar ,Ring oscillators: characterisics and applications,
,Indian journal pure and applied physics,vol 48,February 2010.
https://en.wikipedia.org/wiki/Clock_skew
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Thank you