Documente Academic
Documente Profesional
Documente Cultură
Chang-Hong Wu
Distinguished Engineer, Juniper Networks
THE INTERNET EXPLOSION
12EB/yr
40M
110EB
4PB/yr 60PB/yr 9.5M
160M
1 25M 2.7B/mo
33K 1.7M
C S
C S N
C S
Information N
System
N
Digital Stored
Pipelining Microprocessor Multi-core
Computing Program
Computing
Digital Circuit Packet TCP/IP
Transmission Switching Switching HPN
Networking Flash
Digital Core
Disk DRAM
Storage Memory
Storage
224
222
220
214
212
Super Computers
210
28
26
20
88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08
222
Post-ASIC era: 2.2x /year TX T1600
220
T640
M40
216
Megabits per second
214
212
Interface CAGR: 1.7x /year
210
28
26
24
22
20
88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08
5 Copyright 2010 Juniper Networks, Inc.
SILICON
THE FOUNDATION OF PERFORMANCE
General-Purpose
Microprocessor
(G)
Services
Engine
(S)
Edge
Engine
Core (E)
Fabric Engine
Engine (C)
(F)
Software/hardware interactions
Functional partitioning
Memory choices
Stores configuration, FIB tables, etc.
Temporary working buffers
Chip partitioning
IO and logic ratio, die size, interface simplicity
Queues /
Packet Buffers
Link Memory
Input /
Input /
ASICs Output/
Output
Fabric
Control Memories
(FIB, ACL, configs, etc.)
Packet buffering
Need high throughput, high density
Long bursts ok
SDRAM or RLDRAM (Reduced Latency DRAM)
Queuing/Link memory
Need high throughput, low latency
Shorter bursts
SRAM, RLDRAM, or SDRAM
Control memory
Need high throughput, low latency
Even smaller access quantum
SRAM, TCAM, or RLDRAM
Trio/NISP
65nm
4 Chips
I-Chip
1.2Bn Transistors
IP3
180nm (90nm) 90nm 604Gbps IO
IP1, 2 10 Chips 1 Chip RLDRAM/
250nm 446m Trans 160m Transistors DDR3 SDRAM
4 Chips 412Gbps IO 219Gbps IO
18m Trans RLDRAM/
47Gbps IO
SRAM/
SRAM/ RDRAM DDR2 SDRAM
SDRAM (RLDRAM)
Slot Capacity,
3.0 10 40 100
Gbps
System
40Gbps 160Gbps 640Gbps 1600Gbps
Capacity
Max System
1.5 KW 3.15 KW 4.52 KW 8.35 KW
Draw
EER
13 25 71 96
(Gbps/KW)
Xchip
Take each subsystem, divide into
blocks, divide each block into sub-
blocks, design down to the basic X_in X_out
logic elements
Document both functionality and X_in_a X_in_b
architecture
Rigorous peer reviews of all
documents
X_in_b_cntl X_in_b_dp
always @ (sel or a or b)
a begin
out if (sel == 1)
out = a;
b else
out = b;
sel end
OR
assign out = sel ? a : b;
1) Memory placement
2) Logic placement & clocks
3) M1 routing
4) M2 routing
5) M3 routing
6) M4 routing
7) M5 routing
8) M6 routing
9) M2/M4/M6 routing
10) M1/M3/M5 routing
Copper layers
300mm wafer