Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60A

Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
logic level field-effect power
transistor in a plastic envelope. VDS Drain-source voltage 60 V
The device is intended for use in ID Drain current (DC) 50 A
Switched Mode Power Supplies Ptot Total power dissipation 150 W
(SMPS), motor control, welding, RDS(ON) Drain-source on-state resistance 26 m
DC/DC and AC/DC converters, and VGS = 5 V
in automotive and general purpose
switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION d
tab

1 gate
2 drain
g
3 source
tab drain
1 23 s

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 60 V
VDGR Drain-gate voltage RGS = 20 k - 60 V
VGS Gate-source voltage - - 15 V
VGSM Non-repetitive gate-source voltage tp 50 s - 20 V
ID Drain current (DC) Tmb = 25 C - 50 A
ID Drain current (DC) Tmb = 100 C - 38 A
IDM Drain current (pulse peak value) Tmb = 25 C - 200 A
Ptot Total power dissipation Tmb = 25 C - 150 W
Tstg Storage temperature - - 55 175 C
Tj Junction Temperature - - 175 C

THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Rth j-mb Thermal resistance junction to - - 1.0 K/W
mounting base
Rth j-a Thermal resistance junction to - 60 - K/W
ambient

April 1993 1 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60A

Logic level FET

STATIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA 60 - - V
voltage
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
IDSS Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 25 C - 1 10 A
IDSS Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj =125 C - 0.1 1.0 mA
IGSS Gate source leakage current VGS = 15 V; VDS = 0 V - 10 100 nA
RDS(ON) Drain-source on-state VGS = 5 V; ID = 25 A - 20 26 m
resistance

DYNAMIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 25 V; ID = 25 A 17 30 - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2200 2800 pF
Coss Output capacitance - 700 1000 pF
Crss Feedback capacitance - 280 400 pF
td on Turn-on delay time VDD = 30 V; ID = 3 A; - 40 50 ns
tr Turn-on rise time VGS = 5 V; - 150 250 ns
td off Turn-off delay time RGS = 50 ; - 350 450 ns
tf Turn-off fall time Rgen = 50 - 190 250 ns
Ld Internal drain inductance Measured from contact screw on - 5 - nH
tab to centre of die
Ld Internal drain inductance Measured from drain lead 6 mm - 5 - nH
from package to centre of die
Ls Internal source inductance Measured from source lead 6 mm - 12.5 - nH
from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tmb = 25 C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain - - - 50 A
current
IDRM Pulsed reverse drain current - - - 200 A
VSD Diode forward voltage IF = 50 A ; VGS = 0 V - 1.1 2.0 V
trr Reverse recovery time IF = 50 A; -dIF/dt = 100 A/s; - 80 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 30 V - 0.4 - C

AVALANCHE LIMITING VALUE

Tmb = 25 C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS Drain-source non-repetitive ID = 25 A ; VDD 25 V ; - - 150 mJ
unclamped inductive turn-off VGS = 5 V ; RGS = 50
energy

April 1993 2 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60A

Logic level FET

PD% Normalised Power Derating Zth j-mb / (K/W) BUKx56-lv

120 10
110
100
D=
90 1
80 0.5
70 0.2
60 0.1 0.1
50 0.05
40 0.02
30 0.01 PD tp tp
D=
0 T
20
10 t
T
0 0.001
0 20 40 60 80 100 120 140 160 180 1E-05 1E-03 1E-01 1E+01
Tmb / C t/s
Fig.1. Normalised power dissipation. Fig.4. Transient thermal impedance.
PD% = 100PD/PD 25 C = f(Tmb) Zth j-mb = f(t); parameter D = tp/T

ID / IDmax % Normalised Current Derating ID / A BUK5y6-60A

120 150
10 7
8 6
100 VGS / V =

80 100 5

4.5
60
4
40 50
3.5
20 3
2.5
0 0
0 20 40 60 80 100 120 140 160 180 0 2 4 6 8 10 12
Tmb / C VDS / V
Fig.2. Normalised continuous drain current. Fig.5. Typical output characteristics, Tj = 25 C.
ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V ID = f(VDS); parameter VGS

ID / A BUK556-60A RDS(ON) / Ohm BUK5y6-60A

1000 0.1
3 3.5 4 4.5 5

0.08 6
ID
S/
VD tp = 10 us
=
100 N)
(O
S 0.06
RD 100 us

1 ms 0.04
10 DC
10 ms 7
100 ms 0.02
VGS / V = 10

1 0
1 10 100 0 20 40 60 80 100 120 140
VDS / V ID / A
Fig.3. Safe operating area. Tmb = 25 C Fig.6. Typical on-state resistance, Tj = 25 C.
ID & IDM = f(VDS); IDM single pulse; parameter tp RDS(ON) = f(ID); parameter VGS

April 1993 3 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60A

Logic level FET

ID / A BUK5y6-60A VGS(TO) / V
150
max.
2
Tj / C = 25
150
100 typ.

min.
1
50

0 0
0 2 4 6 8 10 -60 -20 20 60 100 140 180
VGS / V Tj / C

Fig.7. Typical transfer characteristics. Fig.10. Gate threshold voltage.

ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS

gfs / S BUK5y6-60A ID / A SUB-THRESHOLD CONDUCTION

40 1E-01

35
1E-02
30

25 2% typ 98 %
1E-03

20
1E-04
15

10
1E-05
5

0 1E-06
0 20 40 60 80 100 0 0.4 0.8 1.2 1.6 2 2.4
ID / A VGS / V

Fig.8. Typical transconductance, Tj = 25 C. Fig.11. Sub-threshold drain current.

gfs = f(ID); conditions: VDS = 15 V ID = f(VGS); conditions: Tj = 25 C; VDS = VGS

a Normalised RDS(ON) = f(Tj) C / pF BUK5y6-60A

2.0 10000

1.5 Ciss
1000
Coss
1.0
Crss
100
0.5

0 10
-60 -20 20 60 100 140 180 0 20 40
Tj / C VDS / V
Fig.9. Normalised drain-source on-state resistance. Fig.12. Typical capacitances, Ciss, Coss, Crss.
a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 25 A; VGS = 5 V C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

April 1993 4 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60A

Logic level FET

VGS / V BUK5y6-60A WDSS%

10 120
110
9
VDS / V =12 48 100
8
90
7 80
6 70
5 60

4 50
40
3
30
2 20
1 10
0 0
0 20 40 60 80 20 40 60 80 100 120 140 160 180
QG / nC Tmb / C

Fig.13. Typical turn-on gate-charge characteristics. Fig.15. Normalised avalanche energy rating.
VGS = f(QG); conditions: ID = 50 A; parameter VDS WDSS% = f(Tmb); conditions: ID = 25 A

IF / A BUK5y6-60A
200
VDD
+
150 L
150 Tj / C = 25
VDS

100 VGS
-
-ID/100
0 T.U.T.
50
R 01
RGS
shunt
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VSDS / V
Fig.16. Avalanche energy test circuit.
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj WDSS = 0.5 LID2 BVDSS /(BVDSS VDD )

April 1993 5 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60A

Logic level FET

MECHANICAL DATA

Dimensions in mm
4,5
Net Mass: 2 g max
10,3
max
1,3
3,7

2,8 5,9
min

15,8
max

3,0 max
3,0
not tinned
13,5
min
1,3
max 1 2 3
(2x) 0,9 max (3x)
0,6
2,54 2,54 2,4

Fig.17. TO220AB; pin 2 connected to mounting base.

Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for TO220 envelopes.
3. Epoxy meets UL94 V0 at 1/8".

April 1993 6 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60A

Logic level FET

DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

April 1993 7 Rev 1.100