VLSI Design

Dynamic CMOS

[Adapted from Rabaey

Rabaeys
s Digital Integrated Circuits,
Circuits 2002,
2002 JJ. Rabaey et al
al.]]

Dynamic CMOS.1
 Dynamic CMOS
In static circuits at every point in time (except
( when
switching) the output is connected to either GND or VDD
via a low resistance path.
z fan-in of N requires 2N devices

Dynamic circuits rely on the temporary storage of signal

values on the capacitance of high impedance nodes.
z requires
i only
l N + 2 ttransistors
i t
z takes a sequence of precharge and conditional evaluation
phases to realize logic functions

Dynamic CMOS.2
 Dynamic Gate

CLK Mp CLK Mp
Out Out
In1 CL
A
In2 PDN
C
In3
B
CLK Me
CLK Me

Two phase operation

Precharge (CLK = 0)
Evaluate (CLK = 1)
Dynamic CMOS.3
 Dynamic Gate

off
CLK Mp CLK Mp on
1
Out Out
!((A&B)|C)
In1 CL
A
In2 PDN
C
In3
B
CLK Me
off
CLK Me on

Two phase operation

g ((CLK = 0))
Precharge
Evaluate (CLK = 1)
Dynamic CMOS.4
 Conditions on Output
Once the output off a dynamic gate is discharged, it
O
cannot be charged again until the next precharge
operation.
Inputs to the gate can make at most one transition during
evaluation.

Output
p can be in the high
g impedance
p state during
g and
after evaluation (PDN off), state is stored on CL

Dynamic CMOS.5
 Properties of Dynamic Gates
Logic function is implemented by the PDN only
z number of transistors is N + 2 (versus 2N for static
complementary CMOS)
z should be smaller in area than static complementary CMOS

Full swing outputs (VOL = GND and VOH = VDD)

Nonratioed - sizing of the devices is not important for
proper functioning (only for performance)
F t switching
Faster it hi speeds
d
z reduced load capacitance due to lower number of transistors per
gate (Cint) so a reduced logical effort
z reduced load capacitance due to smaller fan-out (Cext)
z no Isc, so all the current provided by PDN goes into discharging CL
z Ignoring the influence of precharge time on the switching speed of
the gate, tpLH = 0 but the presence of the evaluation transistor
slows down the tpHL
Dynamic CMOS.6
 Properties of Dynamic Gates, cont
Power dissipation should be better
z consumes only dynamic power no short circuit power
consumption since the pull-up path is not on when evaluating
z lower CL- both Cint (since there are fewer transistors connected to
the drain output) and Cext (since there the output load is one per
connected gate, not two)
z by construction can have at most one transition per cycle no
glitching

But p
power dissipation
p can be significantly
g y higher
g due to
z higher transition probabilities
z extra load on CLK

PDN starts to work as soon as the input signals exceed

VTn, so set VM, VIH and VIL all equal to VTn
z low noise margin (NML)

Needs a precharge clock

Dynamic CMOS.7
 Dynamic Behavior

CLK
2.5
Out Evaluate
In1
In2 1.5

In3
0.5 In &
In4 CLK
Out Precharge
CLK -0.5
0 0.5 1
Time ns
Time,

#Trns VOH VOL VM NMH NML tpHL tpLH tp

6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps

Dynamic CMOS.8
 Cascading Dynamic Gates
V

CLK
CLK CLK
Mp Mp
Out2
Out1 In
I
In
VTn
Out1
CLK Me CLK Me
V
Out2

Only a single 0 1 transition allowed at the

inputs during the evaluation period!
Dynamic CMOS.9
 Domino Logic

CLK Mp CLK Mp
11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

CLK Me CLK Me

Dynamic CMOS.10
 Why Domino?

CLK

In1
Ini PDN Ini PDN Ini PDN Ini PDN
Inj Inj Inj Inj
CLK

Dynamic CMOS.11
 Properties of Domino Logic

Only non-inverting logic can be implemented, fixes

include
z can reorganize the logic using Boolean transformations
z use differential logic (dual rail)
z use np-CMOS
p ((zipper)
pp )

Very high speed

z tpHL =0
z static inverter can be optimized to match fan-out (separation of
fan-in and fan-out capacitances)

Dynamic CMOS.12
 Differential (Dual Rail) Domino

off on
CLK Mp Mkp Mkp Mp CLK

Out = AB 1 0 1 0 !Out = !(AB)

A
!A !B
B

CLK Me

Due to its high-performance, differential domino is

very popular and is used in several commercial
microprocessors!
Dynamic CMOS.13
 np-CMOS (Zipper)

CLK Mp !CLK Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
CLK Me !CLK Mp

to other to other
PDNs PUNs

Only 0 1 transitions allowed at inputs of PDN

O l 1 0 transitions
Only t iti allowed
ll d att iinputs
t off PUN

Dynamic CMOS.14
 How to Choose a Logic Style
Must consider ease off design, robustness (noise
( immunity),
)
area, speed, power, system clocking requirements, fan-out,
functionality, ease of testing
4-input NAND
Style # Trans Ease Ratioed? Delay Power
Comp Static 8 1 no 3 1
CPL* 12 + 2 2 no 4 3
domino 6+2 4 no 2 2 + clk
DCVSL* 10 3 yes 1 4
* Dual Rail

Current trend is towards an increased use of

complementary static CMOS: design support through DA
t l robust,
tools, b t more amenable bl tto voltage
lt scaling.
li

Dynamic CMOS.15