SystemVerilog Update Part1 Cummings

DAC 2009 SystemVerilog-2009 Presentation
by Sunburst Design, Beaverton, Oregon, © 2009
5 of 59
The SystemVerilog Mantis Database
• The Mantis database contains corrections, clarifications &

enhancement descriptions for SystemVerilog-2009
Current
Currenterrata
errata&&proposed
proposedenhancements
enhancements
• www.eda.org/svdb Login:
Login: guest
guest
Password:
Password: guest
guest
• Mantis Item numbers are noted on appropriate slides

• Mantis items details can be viewed in the Mantis database
After
After logging
logging in
in ...
...
Enter
Enter Issue
Issue ## ...
... ...
... then
then select
select the
the
Jump
Jump button
button
890
© 2009, Sunburst Design, Inc.
6 of 59
Scheduling of New SV Commands
Mantis 890
From
Fromprevious
previous Preponed Region
Region for
for new
new
Preponed
time
timeslot
slot SV
SV commands
commands
#1step
#1step
Active
Active
Active
Active region
region
Inactive
Inactive set
set
Used
Usedfor
forsampling
sampling&& NBA
NBA
verifying
verifyingDUT
DUToutputs
outputs Evaluate
Evaluate concurrent
concurrent
(testbench
(testbenchinputs)
inputs) assertions
assertions
Observed
Observed Trigger clocking blocks
Trigger clocking blocks
Reactive
Reactive region
region
Regions
Regions for
for new
new set
Reactive
Reactive set
SV
SV commands
commands
Execute
Execute
Re-Inactive
Re-Inactive
pass/fail
pass/fail assertion
assertion code
code
Update to
Re-NBA
Re-NBA program block
program block code
code
IEEE1800-2005
Standard
New To
Tonext
Newevent
eventscheduling
scheduling Postponed
Postponed next
(already
(alreadyimplemented)
implemented) time
timeslot
slot
© 2009, Sunburst Design, Inc. Sunburst
3 of 30 Rev 1.1
7 of 59
SystemVerilog-2009
Display Enhancements
8 of 59
Field Widths in Print Formats

Mantis 1175
program print; randcase
int a, b; 3: a = $urandom_range( 5'h10);
2: a = $urandom_range( 9'h100);
initial 2: a = $urandom_range(13'h1000);
repeat (8) begin 2: a = $urandom_range(17'h10000);
endcase
... randcase
1: b = $urandom_range( 5'h10);
$display("a=%h b=%h", a, b); 2: b = $urandom_range( 9'h100);
end 2: b = $urandom_range(13'h1000);
endprogram 1: b = $urandom_range(17'h10000);
Show
Show all
all endcase
leading
leading 0's
0's
$display $display $display
("a=%h b=%h" , a, b); ("a=%0h b=%0h" , a, b); ("a=%4h b=%4h" , a, b);
a=000071ec b=000000fb a=71ec b=fb Remove

Remove leading
leading a=71ec b=00fb
a=00000003 b=00000048 a=3 b=48 0's
0's (ragged
(ragged display)
display) a=0003 b=0048
a=00000ed4 b=000000f4 a=ed4 b=f4 a=0ed4 b=00f4
a=00008fbb b=00000860 a=8fbb b=860 a=8fbb b=0860
a=00000003 b=0000003a a=3 b=3a a=0003 b=003a
4-character
4-character field
field
a=000000b1 b=00004895 a=b1 b=4895 a=00b1 b=4895
with
with leading
leading 0's
0's
a=00000010 b=0000007c a=10 b=7c (orderly a=0010 b=007c
(orderly display)
display)
a=0000097a b=000000da a=97a b=da a=097a b=00da
4 of 30 Rev 1.1
9 of 59
Print Format Specifier %x

Mantis 1749
%xisisaasynonym
%x synonymfor
for%h
%h randcase
program print;
int a, b; 3: a = $urandom_range( 5'h10);
2: a = $urandom_range( 9'h100);
initial 2: a = $urandom_range(13'h1000);
repeat (8) begin 2: a = $urandom_range(17'h10000);
endcase
... randcase
1: b = $urandom_range( 5'h10);
$display("a=%4x b=%4x", a, b); 2: b = $urandom_range( 9'h100);
end 2: b = $urandom_range(13'h1000);
endprogram 1: b = $urandom_range(17'h10000);
endcase
a=71ec b=00fb
Same a=0003 b=0048
Sameorderly
orderlyprintout
printout a=0ed4 b=00f4
a=8fbb b=0860
a=0003 b=003a
a=00b1 b=4895 %xisisjust
%x just"syntactic
"syntacticsugar"
sugar"
a=0010 b=007c (C-like
(C-like- -not
notreally
reallyneeded)
needed)
a=097a b=00da
10 of 59
Print Format Specifier %p (%4p)

Mantis 331
package complex; import complex::*;
typedef struct {
module structprint;
logic [7:0] re;
complex_s a, b, sum;
logic [7:0] im; logic clk;
} complex_s;
... initial begin
endpackage clk <= '0;
forever #(`CYCLE/2) clk = ~clk; module cplx_adder (
end output complex_s sum,
input complex_s a, b);
cplx_adder u1 (.*);
Sized
Sizedformat
format
specifier %4pfor
specifier%4p for initial $monitor(...);
assign sum = add(a, b);
orderly endmodule
orderlyprinting
printing
...
endmodule
$monitor("sum=%4p
$monitor("sum=%4p a=%4p
a=%4p b=%4p
b=%4p ",
", sum,
sum, a,
a, b);
b);
sum='{re: x, im: x} a='{re: x, im: x} b='{re: x, im: x}
sum='{re: 216, im: 240} a='{re: 193, im: 148} b='{re: 23, im: 92}
5 of 30 Rev 1.1
11 of 59
$sformatf Returns a Formatted String

Mantis 1589 & 1651
module test1;
int a = 32; SystemVerilog2005
SystemVerilog2005
logic [31:0] b = 32'haabbccdd; $sformattask
$sformat taskassigns
assigns
string s; string
stringto
tooutput
outputargument
argument(s(s) )
initial begin
$sformat(s, "\nThe value of b = %0d'h%h\n", a, b);
$display("%s", s);
Output
Outputdisplay
display
end
endmodule
The value of b = 32'haabbccdd
module test2;
int a = 32; SystemVerilog2009
SystemVerilog2009addsadds
logic [31:0] b = 32'haabbccdd; $sformatffunction
$sformatf function
string s; that
thatreturns
returnsaastring
string
initial begin
s = $sformatf("\nThe value of b = %0d'h%h\n", a, b);
$display("%s", s);
Mantis
Mantis1651:
1651:
end
$psprintf
$psprintf was
wasrejected
rejected
endmodule (Proposed synonym for $sformatf )
(Proposed synonym for $sformatf )
12 of 59
$fatal/$error/$warning/$info Display Tasks

Mantis 1641
InInSystemVerilog2005
SystemVerilog2005
module tb;
... $fatal/ /$error
$fatal $error/ /$warning
$warning/ /$info
$info
could
couldonly
onlybe
beused
usedininassertions
assertions
function void check_output;
if (cb1.y===exp) $display("PASS: y=%h exp=%h", y, exp);
else $display("FAIL: y=%h exp=%h", y, exp);
endfunction
...
endmodule
InInSystemVerilog2009
SystemVerilog2009
module tb;
... $fatal/ /$error
$fatal $error/ /$warning
$warning/ /$info
$info
can
canbe
beused
usedanywhere $displaycan
anywhere$display canbe beused
used
function void check_output;
if (cb1.y===exp) $info ("PASS: y=%h exp=%h", y, exp);
else $fatal("FAIL: y=%h exp=%h", y, exp);
endfunction
...
endmodule
6 of 30 Rev 1.1
13 of 59
SystemVerilog-2009
Design Enhancements
14 of 59
always_ff
Logic-Specific Process
• always_ff
– Conveys designer's intent module dff1 (
output bit_t q,
to infer clocked logic
input bit_t d, clk, rst_n);
always_ff @(posedge clk, negedge rst_n)

if (!rst_n) q <= 0;
Correct
Correctsensitivity
sensitivity else q <= d;
list
list endmodule
7 of 30 Rev 1.1
15 of 59
Edge Event - For DDR Logic

Mantis 2396
Equivalent
Equivalenttotoboth
• SV2009 adds edge keyword posedge /
both
negedge
posedge / negedge
Currently
Currentlyillegal
illegalsyntax
syntax No posedge(clk)
Noposedge (clk)
for
forsynthesis
synthesis No
No negedge(clk)
negedge (clk)
module ddrff ( Remove posedgeto

Removeposedge topermit
permit
output bit_t q, triggering
input bit_t d, clk, rst_n); triggering on bothedges
on both edges
??
??
always_ff @(clk, negedge rst_n)
if (!rst_n) q <= 0;
else q <= d;
endmodule always_ffshows
always_ff shows
designer's
designer'sintent
intent
always_ff @(edge clk, negedge rst_n)
Could
Couldthis
thissynthesize
synthesizeto
toaaDDR
DDRflip-flop
flip-flop
in
inan
anASIC
ASICvendor
vendorlibrary
library??
?? Sunburst
16 of 59
.name Instantiation & Unconnected Ports

Mantis 1660 SystemVerilog-2009
SystemVerilog-2009
clarification
clarification
ain bin
alu_accum.v
alu_accum.v
8 8
opcode[2:0]
alu (8-bit)
3
alu_out 8 1 1
alu_out[7] 1
zero ones
8
Dangling
Dangling zero
zero
xtend accum & ones outputs
& ones outputs
8 8
clk
.name
.nameallows
allowsunconnected
unconnected
rst_n ports
portsto
tobe
beomitted
omitted
dataout[15:8] dataout[7:0]
16
dataout Not
Notthe
theoriginal
original
intent
intentfor
for.name
.name
8 of 30 Rev 1.1
17 of 59
.name Instantiation & Unconnected Ports

Mantis 1660
module alu_accum (
output [15:0] dataout, Legal
Legal(but
(butnot
notrequired):
required):
input [7:0] ain, bin, list
input [2:0] opcode, list unconnectedports
unconnected ports
input clk, rst_n);
wire [7:0] alu_out;
alu alu (.alu_out, .zero(), .one(), .ain, .bin, .opcode);

accum accum (.dataout(dataout[7:0]), .datain(alu_out), .clk, .rst_n);
xtend xtend (.dout(dataout[15:8]), .din(alu_out[7]), .clk, .rst_n);
endmodule
Legal:
Legal:
... omit
alu alu (.alu_out, .ain, .bin, .opcode); omitunconnected
unconnectedports
ports
...
Legal
Legal(but
(butWRONG!):
WRONG!):
... omit
omitdesign
designport (alu_out) )
port(alu_out
alu alu (.ain, .bin, .opcode);
...
Another
Anothergood
goodreason
reasonto
toavoid
avoidusing
using.name
.name
18 of 59
2-to-4 Decoder w/ Enable

SystemVerilog-2005 Style
module dec2_4a ( ============================

output logic [3:0] y, | Line | full/parallel |
input logic [1:0] a, unique
unique case
case ============================
input logic en);
with
withinitial
initialdefault
default | # | user/user |
always_comb begin assignment
assignment ============================
y = 0;
unique case ({en,a})
3'b100: y[a]=1; unique
unique
3'b101: y[a]=1; Same
Sameas
asfull_case
full_case
3'b110: y[a]=1; parallel_case
parallel_case
3'b111: y[a]=1;
endcase
end
endmodule
SystemVerilog
SystemVerilog simulators
simulators are
are required
required
to
to give
give aa run-time
run-time warning
warning when
when en=0
en=0 parallel_case
parallel_case
(uniqueness)
(uniqueness)
unique means:
unique means: full_case
(1) full_case
(1) case expressioncan
case expression canonly
onlymatch
match11case
caseitem
item all
(2)
(2)case
caseexpression
expressionMUST
MUSTmatch
match11case
caseitem
item allpossible
possiblecases
casesare
aredefined
defined
(others
(others are "don'tcares")
are "don't cares")
9 of 30 Rev 1.1
19 of 59
2-to-4 Decoder with Enable

WRONG Synthesis Results!
SystemVerilog
SystemVerilogsimulation
simulation
Dangling
Danglingenable!
enable! should
shouldwarn
warnabout
aboutthis
thiserror
error
en y[3]
unique
uniquecase
case
dec2_4a
dec2_4a unique
unique
infers
infersthe
the
wrong
wronglogic
logic y[2]
y[1]
a[1]
y[0]
a[0]
20 of 59
2-to-4 Decoder w/ Enable

SystemVerilog-2005 Current Work-Around
module dec2_4b ( ============================

input logic [1:0] a, unique
unique case
case ============================
input logic en);
with
withinitial
initialdefault
default | # | auto/user |
assignment ============================
y = 0;
unique case ({en,a})
3'b100: y[a]=1;
unique with
unique withempty
emptydefault
default
3'b101: y[a]=1; same
sameas
asparallel_case
parallel_case
3'b110: y[a]=1;
3'b111: y[a]=1;
default: ; Empty
Emptydefault
default
endcase kills
killsfull_case
full_case
end
endmodule
Ugly,
Ugly,but
butfixes
fixesthe
the
synthesis
synthesisresults
results
10 of 30 Rev 1.1
21 of 59
Unique0 - parallel_case Equivalent

Mantis 2131
module dec2_4c ( ============================

input logic [1:0] a, unique0
unique0 case
case ============================
input logic en);
with
withinitial
initialdefault
default | # | auto/user |
assignment ============================
y = 0;
unique0 case ({en,a})
3'b100: y[a]=1; unique0
unique0
3'b101: y[a]=1; same
3'b110: y[a]=1; sameas
as
parallel_case
parallel_case
3'b111: y[a]=1;
endcase
end
endmodule
Simulation
Simulation is
is correct
correct when
when en=0
en=0
parallel_case
parallel_case
(uniqueness)
(uniqueness)
unique0 means:
unique0 means: NOT
(1) NOTfull_case
full_case
(1) case expressioncan
case expression canonly
onlymatch
match11case
caseitem
item (others
(2)
(2)case
caseexpression
expressioncan
canmatch
match11or
or00case
caseitems
items (otherscovered
coveredbybyinitial
initial
default
defaultassignment)
assignment)
22 of 59
2-to-4 Decoder with Enable

Correct Synthesis Results
a[1]
SystemVerilog
SystemVerilog a[0] y[3]
dec2_4b
dec2_4b en
dec2_4c
dec2_4c
y[2]
y[1]
y[0]
11 of 30 Rev 1.1
23 of 59
priority/unique/unique0 Violations
Mantis 2008
Reported
Reportedas
aswarnings
warnings
(vendors
(vendorsdid
didnot
notwant
want
• SV-2005: priority/unique warnings to
toreport
reportfalse-errors)
false-errors)
• SV-2009: priority/unique/unique0 violations Reported

Reportedas
asviolations
violations
Ask
Askvendors
vendorstotoprovide
provide
unique:Only
unique: Onlyone
onecase
case fatal-on-violation
fatal-on-violationoption
option
item
itemshould
shouldmatch
matchthe
the
caseexpression
case expression Simulation
Simulationscenario:
scenario:
(1)
(1)aagoes
goestoto11
always_comb begin: a1 (2) always_comb(a1)
(2)always_comb (a1)triggers
triggers
unique case (1’b1) (3)
(3)unique casedetects
uniquecase detectsviolation
violation
a : z = b; (a
(a&&not_a
not_aboth
bothmatch
match1'b1)
1'b1)
not_a : z = c; (4) violation report generated
(4) violation report generated
endcase (scheduled
(scheduledinto
intoObserved
ObservedRegion)
Region)
end (5) always_comb(a2)
(5)always_comb (a2)triggers
triggers
(6) not_agoes
(6)not_a goesto
to00
always_comb begin: a2 (7) always_comb(a1)
(7)always_comb (a1)re-triggers
re-triggers
not_a = !a; (8)
(8) unique case detectsNO
unique case detects NOviolation
violation
end (9)
(9)violation
violationreport
reportcleared
cleared
(before
(beforeentering
enteringObserved
ObservedRegion)
Region)
24 of 59
Default Inputs For Module/Interface Ports

Mantis 2399 (Corrects Mantis1619 Enhancement)
Old
Oldversion
versionof
of
module register ( register
registermodule
module
output logic [7:0] q,
input logic [7:0] d,
input logic clk, rst_n); Default
Defaultvalues
valuesmight
mightbe
beuseful
useful
for
forinfrequently
infrequentlyused
usedinputs
inputs
always_ff @(posedge clk, negedge rst_n)
if (!rst_n) q <= '0; Default
Defaultvalues
valuesonly
onlylegal
legal
else q <= d; with
withANSI-style
ANSI-styleport
portlist
list
endmodule
module register ( New

Newversion
versionof
of
register
registermodule
module
output logic [7:0] q,
with set_ninput
withset_n input
input logic [7:0] d, New
Newinput
inputhas
has
input logic clk, rst_n, aadefault
defaultvalue
value
input logic set_n='1 );
always_ff @(posedge clk, negedge rst_n, negedge set_n)

if (!rst_n) q <= '0;
else if (!set_n) q <= '1;
else q <= d; CAUTION:
CAUTION:instantiation
instantiationrules
rules
endmodule can
canbe
beconfusing
confusing
12 of 30 Rev 1.1
25 of 59

set_n/ /rst_n
set_n rst_n
module register ( module tb; both
bothdeclared
declared
output logic [7:0] q, logic [7:0] q;
input logic [7:0] d, logic [7:0] d;
input logic clk, logic clk;
input logic rst_n='1 , logic rst_n, set_n;
... // register
endmodule set_nand
set_n rst_ninputs
andrst_n inputs ... register
have registerinstantiation
instantiation
havedefault
defaultvalues
values endmodule
register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n), .set_n(set_n));
register r1 (.q, .d, .clk, .rst_n, .set_n); tb overrides

tb overrides default
default
set_n // rst_n
set_n rst_n values
values
register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));
register r1 (.q, .d, .clk, .rst_n); tb only

tb only overrides
overrides
default rst_n value
default rst_n value
register keeps
register keeps default
default
register r1 (.*); CAUTION:
CAUTION:this
thiscan
canbe
beconfusing
confusing
set_n // rst_n
set_n rst_n values
values
26 of 59

set_nNOT
set_n NOT
module register ( module tb; declared
declared
output logic [7:0] q, logic [7:0] q;
input logic [7:0] d, logic [7:0] d;
input logic clk, set_n
set_n logic clk;
input logic rst_n='1 , assigned
assigned logic rst_n;
... assign set_n = d[7];
endmodule set_nand
set_n rst_ninputs
andrst_n inputs // register
have
havedefault
defaultvalues
values ... register
registerinstantiation
instantiation
endmodule
register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n), .set_n(.set_n));
tb overrides
tb overrides default set_n // rst_n
default set_n rst_n values
values
register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n)); tb only

tb only overrides
overrides
default rst_n value
default rst_n value
register r1 (.q, .d, .clk, .rst_n, .set_n);

ERROR: set_n not
ERROR: set_n not
register r1 (.q, .d, .clk, .rst_n); declared
declared in
in tb
tb
13 of 30 Rev 1.1
27 of 59
Bit Selects & Part Selects of Expressions

Mantis 1197 Correction
Correctionto
toDAC2009
DAC2009
presentation
presentation
module expr_range; module expr_range;

logic [2:0] y; logic [2:0] y;
logic [7:0] a, b, c; logic [7:0] a, b, c;
logic [7:0] tmp;
assign y = {(a & b) | c}[4:2];
assign tmp = (a & b) | c;
assign y = tmp[4:2]; ...
endmodule
...
endmodule Verilog
Verilogonly
onlyallows
allowsbit
bit SystemVerilog-2009
SystemVerilog-2009
and
andpart
partselects
selectsof
of allows
allowsbit
bitand
andpart
partselects
selects
nets and variables
nets and variables ononRHS
RHSconcatenations
concatenations
Might NOTE: {concatenation}braces

NOTE:{concatenation}
Mightrequire
require ILLEGAL
ILLEGAL- -to
toreference
referenceaapart
part are
braces
extra
extracode select arerequired
requiredto
tododoaapart
partselect
select
code selecton
onthe
theLHS
LHSexpression
expression on the result of the expression
on the result of the expression
CAUTION:
CAUTION:more
moreconcise
concisebut
but
perhaps
perhapsmore
moreconfusing(?)
confusing(?)
28 of 59
SystemVerilog-2009
Packages, Parameters, Compiler Directives
14 of 30 Rev 1.1
29 of 59
Package Import in Design Element Header

Mantis 329
SystemVerilog-2005
SystemVerilog-2005
package
packageusage
usagestyle
style#1
#1
package data_pkg;
typedef logic [7:0] data_t;
typedef logic clk_t; Declare
Declarethe
thedata_pkg
data_pkg
endpackage and bit_pkg
and bit_pkg
package bit_pkg;
bit_pkg::clk_t
bit_pkg::clk_t
typedef bit clk_t;
typedef bit rst_t; not
notused
used
endpackage
module register (
Use
Usethe data_tand
thedata_t andclk_t
clk_t
output data_pkg::data_t q,
from
fromthe
thedata_pkg
data_pkg
input data_pkg::data_t d,
input data_pkg::clk_t clk,
input bit_pkg::rst_t rst_n);
Use
Usethe rst_tfrom
therst_t from
the
thebit_pkg
bit_pkg
...
endmodule
......somewhat
somewhatverbose
verbose
30 of 59

Mantis 329
SystemVerilog-2005
SystemVerilog-2005
package
packageusage
usagestyle
style#2
#2
package data_pkg;
Declarethe
thedata_pkg
data_pkg
endpackage and
andbit_pkg
bit_pkg
package bit_pkg;
bit_pkg::clk_t
bit_pkg::clk_t
typedef bit clk_t;
notused
used
endpackage
Use
Usethe data_tand
thedata_t andclk_t
clk_t
import data_pkg::*; from
fromthe
thedata_pkg
data_pkg
import bit_pkg::rst_t;
Use
Usethe rst_tfrom
therst_t from
module register ( the
thebit_pkg
bit_pkg
output data_t q,
input data_t d,
input clk_t clk,
input rst_t rst_n);
......packages
packageshave
havebeen
beenimported
imported
into
intothe $unit/$rootspace
the$unit/$root space
... (depending
endmodule (dependingupon
uponthe
thesimulator)
simulator)
15 of 30 Rev 1.1
31 of 59

SystemVerilog-2009adds
addsimport
importof
of
local
localpackage
packagedeclarations
declarationsin
inmodule,
module,
interfaceand
interface programheaders
andprogram headers
package data_pkg;
Declarethe
thedata_pkg
data_pkg
endpackage and bit_pkg
and bit_pkg
package bit_pkg;
bit_pkg::clk_t
bit_pkg::clk_t
typedef bit clk_t;
notused
used
endpackage Packages
Packagesare
areavailable
available
to
tothe
themodule
moduleheader
header Use
Usethe data_tand
thedata_t andclk_t
clk_t
module register from
import bit_pkg::rst_t, data_pkg::*; fromthe
thedata_pkg
data_pkg
(output data_t q, Use
input data_t d, Usethe rst_tfrom
therst_t from
the
thebit_pkg
bit_pkg
input clk_t clk,
input rst_t rst_n);
... ...... packages

endmodule packageshave
havebeen
beenimported
imported
locally
locallyinto
intothe registermodule
theregister module
32 of 59
Package Chaining - Export in a Package

SystemVerilog-2005did
didnot
notpermit
permit
packagenesting/import
package nesting/import
package pkg1; package pkg2a;
typedef logic [2:0] src1_t; typedef logic [2:0] src1_t;
typedef logic [2:0] dst1_t; typedef logic [2:0] dst1_t;
typedef logic [7:0] data_t; typedef logic [2:0] src2_t;
typedef struct { typedef logic [2:0] dst2_t;
src1_t fld1; typedef logic [15:0] data_t;
dst1_t fld2; typedef struct packed {
data_t fld3; src1_t fld1;
} pkt_t; dst1_t fld2;
endpackage src2_t fld3;
dst2_t fld4;
data_t fld5;
} pkt_t; import pkg2a::*;
IfIfused,
used,re-declaration
re-declarationof
ofsrc1_t
src1_t endpackage
and dst1_twas
anddst1_t wasrequired
required module register (
output pkt_t q,
input pkt_t d,
input logic clk,
importand
import anduse
usethe
the input logic rst_n);
expanded pkg2apackage
expandedpkg2a package ...
endmodule
16 of 30 Rev 1.1
33 of 59
Package Chaining - Export in a Package

SystemVerilog-2009allows
allows
packagenesting/import/export
package nesting/import/export
package pkg1; package pkg2;
typedef logic [2:0] src1_t; import pkg1::*;
typedef logic [2:0] dst1_t; export pkg1::*;
typedef logic [7:0] data_t; typedef logic [2:0] src2_t;
typedef struct { typedef logic [2:0] dst2_t;
src1_t fld1; typedef logic [15:0] data_t;
dst1_t fld2; typedef struct packed {
data_t fld3; src1_t fld1;
} pkt_t; dst1_t fld2;
Add
Addthe
thesrc2_t
src2_t
endpackage src2_t fld3;
and
anddst2_t
dst2_t types
types
dst2_t fld4;
import/export the src1_t
import/export the src1_t data_t fld5;
and dst1_ttypes
anddst1_t types } pkt_t; import pkg2::*;
endpackage
module register (
Override
Overridethe
thedata_t
data_t output pkt_t q,
and pkt_ttypes
andpkt_t types input pkt_t d,
input logic clk,
importand
import anduse
usethe
the input logic rst_n);
expanded pkg2package
expandedpkg2 package ...
endmodule
34 of 59
Multiple Package Export

Mantis 1323
package pkg3a;
typedef logic [7:0] byte_t; importeach
import eachpackage
package
separately
separately
...
endpackage
package pkg3b; package pkg4;

... import pkg3a::byte_t;
endpackage import pkg3b::*;
import pkg3c::*;
package pkg3c; import pkg3d::*;
... export *::*;
endpackage endpackage
package pkg3d; exportall

export allpackages
packages
... (using
(usingwildcards)
wildcards)
endpackage
Like
Likedoing
doingpackage
package
extension
extension...... ......with
withmultiple
multiple
inheritance
inheritance!!!!
17 of 30 Rev 1.1
35 of 59
Package Automatic Declarations

SystemVerilog-2005had:
had: SystemVerilog-2009
SystemVerilog-2009adds:
adds:
••module
module automatic
automatic ••package
package automatic
automatic
••program
program automatic
automatic
••interface
interface automatic
automatic
Normal package ......

Normalpackage automatic package ......
automatic package
package complex; package automatic complex;

typedef struct { typedef struct {
logic [7:0] re; logic [7:0] re;
logic [7:0] im; ......static
static logic [7:0] im; ......automatic
automatic
} complex_s; function
function } complex_s; function
function
function complex_s add; function complex_s add;

input complex_s a, b; input complex_s a, b;
complex_s sum; complex_s sum;
sum.re = a.re + b.re; sum.re = a.re + b.re;
sum.im = a.im + b.im; sum.im = a.im + b.im;
return(sum); return(sum);
endfunction endfunction
endpackage endpackage
36 of 59
Localparams in ANSI-Style Headers

Mantis 1134
localparamcan
localparam canbe
beinin
the
the parameter portlist
parameter port list
`timescale 1ns / 1ns
module ram #(parameter AWIDTH=10,
localparam DEPTH=1<<AWIDTH,
parameter DWIDTH=8) Cannot
Cannotoverride
overridelocalparam
localparam
(inout [DWIDTH-1:0] data,
input [AWIDTH-1:0] addr,
Ordered
Orderedparameter
parameterreplacement
replacement
input r_wn, cs_n);
omits
omitsthe localparamvalue
thelocalparam value
logic [DWIDTH-1:0] mem [DEPTH];
assign data = (!cs_n && r_wn) ? mem[addr] : 'z;
always_latch
if (!cs_n && !r_wn) mem[addr] <= data;
endmodule DEPTHnot
DEPTH not
listed
listed
raminstantiation:
ram instantiation:
AWIDTH=20(1MB)
AWIDTH=20 (1MB) ram #(20,16) ram1 (...);
DWIDTH=16
DWIDTH=16
18 of 30 Rev 1.1
37 of 59
Blank And Illegal Parameter Defaults

Mantis 907
NOTE: SIZEparameter
NOTE:SIZE parameternot
not
assigned
assignedaadefault
defaultvalue
value
module register #(SIZE) (

output logic [SIZE-1:0] q,
input logic [SIZE-1:0] d,
input logic clk, rst_n);
always_ff @(posedge clk, negedge rst_n) Parameter

if (!rst_n) q <= '0; Parametermust
mustbebe
defined
definedwhen
whenthe
the
else q <= d; module
endmodule moduleisisinstantiated
instantiated
module tb;
parameter SIZE = 64;
logic [SIZE-1:0] q;
logic [SIZE-1:0] d;
logic clk, rst_n;
register #(SIZE) r1 (.*);

//...
endmodule
38 of 59
Setting Parameters in Configurations

Mantis 2037
File:
File:rtl.cfg
rtl.cfg
module tb; config rtl;
parameter SZ = 12; design tbLib.tb;
... default liblist rtlLib;
pipeline #(.WIDTH(SZ)) p1 (.*); instance tb use (.SZ(16));
...
endmodule endconfig
module pipeline #(WIDTH=4) ( Parameter

Parametervalues
values Parameter
Parametervalues
values
output logic [WIDTH-1:0] q, before
beforeconfig
config after
afterrtl
rtlconfig
config
input logic [WIDTH-1:0] d, SZ
SZ =12 =12 SZ
SZ =16 =16
input logic clk);
logic [WIDTH-1:0] p1, p2; WIDTH=12(default
WIDTH=12 (default4)
4) WIDTH=16
WIDTH=16
SIZE =12(default
SIZE =12 (default8)
8) SIZE
SIZE =16
=16
register #(.SIZE(WIDTH)) r[1:3]
(.q({q,p2,p1}), .d({p2,p1,d}), .clk(clk));
endmodule
More
Moreconfig
configparameter
parameter
capabilities
capabilitieshave
havebeen
beenadded
added
(not
(notshown)
shown)
module register #(SIZE=8) (
output logic [SIZE-1:0] q,
input logic [SIZE-1:0] d,
input logic clk);
File:
File:lib.map
lib.map
always_ff @(posedge clk)
q <= d; library tbLib tb/*.sv;
endmodule library rtlLib rtl/*.sv;
19 of 30 Rev 1.1
39 of 59
Verilog-95 Macro Capabilities
`define CYCLE 100 Define

Defineand
anduse
useaamacro
macro
(every
... (everyVerilog
Verilogcoder
coderknows
knowsthis
thisstyle)
style)
initial begin
clk <= '0;
forever #(`CYCLE/2) clk = ~clk;
end
Line
Linecontinuation
continuation
character
character \\
Define
Defineaamulti-line
multi-linemacro
macro
(not all Verilog coders know this)
`define assert_clk( ... ) \ (not all Verilog coders know this)
assert property (@(posedge clk) disable iff (!rst_n) ... )
Pass
Passan
anargument
argumentto
to
the
themacro
macro arg
arg Define
Defineaamulti-line
multi-linemacro
macro
with
with inputarguments
input arguments
(not all Verilog coders know this)
`define assert_clk( arg ) \ (not all Verilog coders know this)
assert property (@(posedge clk) disable iff (!rst_n) arg )
40 of 59
Macros with Default Arguments

Mantis 1571
• SystemVerilog-2009 permits macros to have arguments with

default values
By
Bydefault,
default,macro
macrouses
usesclk
clk
for
forassertion
assertionsampling
sampling
`define assert_clk(arg, ck=clk) \

assert property (@(posedge ck) disable iff (!rst_n) arg)
ERROR_q_did_not_follow_d:
Use
Usedefault
defaultclk
clk
àssert_clk(q==$past(d));
ERROR_q_did_not_follow_d:
Use
Useclk2
clk2
àssert_clk(q==$past(d), clk2);
20 of 30 Rev 1.1
41 of 59
Verilog `define & ùndef
`define DSIZE 8 `definedata

`define datasize,
size,
`define ASIZE 10 `defineaddress
`define addresssize
size
`define MDEPTH 1024 `definememory
`define memorydepth
depth
module ram1 (
inout [`DSIZE-1:0] data,
input [ÀSIZE-1:0] addr,
input en, rw_n);
logic [`DSIZE-1:0] mem [0:`MEM_DEPTH-1];
assign data = (rw_n && en) ? mem[addr]

: {`DSIZE{1'bz}};
always @* begin
if (!rw_n && en) mem[addr] <= data;
end
endmodule
ùndef DSIZE ùndefdata
ùndef datasize,
size,
ùndef ASIZE ùndefaddress
ùndef addresssize
size
ùndef MDEPTH ùndefmemory
ùndef memorydepth
depth
42 of 59
ùndefineall
Mantis 1090
`define DSIZE 8 `definedata

`define datasize,
size,
`define ASIZE 10 `defineaddress
`define addresssize
size
`define MDEPTH 1024 `definememory
`define memorydepth
depth
module ram1 (
inout [`DSIZE-1:0] data,
input [ÀSIZE-1:0] addr,
input en, rw_n);
logic [`DSIZE-1:0] mem [0:`MEM_DEPTH-1];
assign data = (rw_n && en) ? mem[addr]

: {`DSIZE{1'bz}};
always_latch begin
end
endmodule
ùndefineall ùndefineallun-defines
ùndefineall un-defines
all `definemacros
all`define macros
21 of 30 Rev 1.1
43 of 59
SystemVerilog Parameterized Model

A Better Solution Consider
Considerthis:
this:
IfIfyou
youare
areusing
usingùndefineall
ùndefineall
ititlooks
lookslike
likeaalocal
localconstant
constant
module ram1 #(parameter ASIZE=10, Declare

Declareparameters,
parameters,
DSIZE=8) local
localto
tothe
themodule
module
(inout [DSIZE-1:0] data,
input [ASIZE-1:0] addr,
input en, rw_n);
localparam MEM_DEPTH = 1<<ASIZE; Make

Makethe
thememory
memorydepth
depth
logic [DSIZE-1:0] mem [0:MEM_DEPTH-1]; aalocalparam
localparam
assign data = (rw_n && en) ? mem[addr] Calculate

Calculatethe
thememory
memorydepth
depth
: {DSIZE{1'bz}}; from
fromthe
theaddress
addresssize
size
always_latch begin
end
endmodule
Guideline:
Guideline:choose parameterfirst
chooseparameter first
Guideline:
Guideline:choose `defineonly
choose`define onlyififneeded
needed
44 of 59
SystemVerilog-2009
Arrays & Queues Enhancements
22 of 30 Rev 1.1
45 of 59
Associative Array Clarifications

Mantis 1457
foreachcommand
foreach commandworks
workswith
with SV2009
non-[*] SV2009clarifies
clarifies
non-[*]associative
associativearrays
arrays foreachfails
foreach failswith
with
module aa2;
[*]assoc
[*] assocarrays
arrays
typedef bit [7:0] byte_t;
byte_t aa [int]; byte_t aa [*];
1 ARRAY ELEMENTS
initial begin aa[1234]=aa
aa[2143] = 8'hAA; 9 ARRAY ELEMENTS
aa_display; aa[ 0]=cc 12 ARRAY ELEMENTS
for (int i=0; i<8; i++) aa[ 1]=cc aa[ 0]=cc
aa[i]=8'hCC; aa[ 2]=cc aa[ 1]=cc
aa_display; aa[ 3]=cc aa[ 2]=cc
for (int i=5; i<21; i+=5) aa[ 4]=cc aa[ 3]=cc
aa[i]=8'hDD; aa[ 5]=cc aa[ 4]=cc
aa_display; aa[ 6]=cc aa[ 5]=dd
end aa[ 7]=cc aa[ 6]=cc
aa[1234]=aa aa[ 7]=cc
endmodule aa[ 10]=dd
aa[ 15]=dd
function void aa_display; aa[ 20]=dd
$display("%0d ARRAY ELEMENTS %0d", aa.num()); aa[1234]=aa
foreach (aa[i]) $display("aa[%4d]=%2", i, aa[i]);
endfunction foreach stores
foreach stores each aa[] index
each aa[] index in
in the
the ii variable
variable
46 of 59
Associative Array Clarifications

Mantis 1723
• SystemVerilog 2005 array types & methods Returns

Returnsthe
thesize
sizeof
of
– Dynamic arrays: .size() method the
thedynamic
dynamicarray
array
– Queues: .size() method Returns
Returnsthe
thesize
sizeof
of
– Asosciative arrays: .num() method the
thequeue
queue
Returns
Returnsthe
thenumber
numberof of
elements
elementsininthe
the
associative
associativearray
array
function void aa_display;
$display("%0d ARRAY ELEMENTS %0d", aa.num());
...
endfunction SV2009
SV2009defines
defines
.size()method
.size() method- -
synonym
synonymfor
for
function void aa_display;
.num()method
.num() method
$display("%0d ARRAY ELEMENTS %0d", aa.size());
...
endfunction
23 of 30 Rev 1.1
47 of 59
Queue Delete SV2009

SV2009adds
to
addsaabuilt-in
built-inmethod
method
todelete
deletean
anentire
entirequeue
queue
Mantis 1560
data=8'h00 8'hA0
program q_methods; Initial
Initial
8'hA1
values
values
bit [7:0] q[$] = '{8'hA0, 8'hA1, 8'hA2}; 8'hA2
bit [7:0] data; q.size=3 8'hA0
int q_size;
$display
$display 8'hA1
8'hFF
initial begin insert(@2)
insert(@2) 8'hA2
$display("q.size=%0d", q.size());
q.insert(2,8'hff); 8'hA0
delete(@1)
delete(@1) 8'hFF
q.delete(1);
8'hA2
data=q.pop_front(); pop_front
pop_front
data=q.pop_back(); 8'hFF
q.push_front(8'hbb); data=8'hA0 8'hA2
pop_back
pop_back
q.push_back(8'hcc);
data=8'hA2 8'hFF
q.delete()
end push_front
push_front 8'hBB
endprogram 8'hFF
push_back
push_back
No 8'hBB
Noargument
argument New
New toto SV2009
SV2009
means 8'hFF
meansto todelete
delete delete
delete entire
entire queue
queue
entire 8'hCC
entirequeue
queue
<empty>
48 of 59
SystemVerilog-2009
Classes & Verification Enhancements
24 of 30 Rev 1.1
49 of 59
Static Variable In-Line Initialization

Mantis 1556
module top;
int svar1 = 1; statickeyword
static keywordisisoptional
optional- -
initialization
initializationhappens
happensbefore
beforetime
time00
initial begin
for (int i=0; i<3; i++) begin
automatic int loop3 = 0; automaticvariable
automatic variable
for (int j=0; j<3; j++) begin assignment
assignmentexecutes
executeseach
each
time
time the outer loopisiscalled
the outer loop called
loop3++;
$write("%3d", loop3);
Display
Display values
values
end
end 1 2 3 1 2 3 1 2 3
$display("\n");
for (int i=0; i<3; i++) begin
static int loop2 = 0; The staticvariable
Thestatic variable
for (int j=0; j<3; j++) begin assignment
assignmentexecutes
executes
once
oncebefore
beforetime
time00
loop2++;
$write("%3d", loop2);
end Display
Display values
values
end 1 2 3 4 5 6 7 8 9
$display("\n");
end
endmodule
50 of 59
Pure Virtual Methods

Mantis 1308
• pure virtual is an abstract method prototype defined in an

abstract class (virtual class)
• virtual requires: virtualrequires
virtual requires
argument compatibility argument compatibility
– argument types must match
– argument directions must match
– number of arguments must match
– return types must match purecreates
pure createsaaplace-holder
place-holder
purerequires
pure requiresthat
thataa
• pure requires: method
methodbebeoverridden
overriddenwith
with
an
anactual
actualimplementation
implementation
– method shall only be a prototype
– no code can be included for the prototype
– not even allowed to have endfunction/endtask keywords
– pure virtual methods MUST be overridden in non-abstract classes
25 of 30 Rev 1.1
51 of 59
Pure Constraint
Mantis 2514
• pure constraint is an constraint prototype defined in an

abstract class (virtual class)
• pure requires:
– constraint shall only be a prototype
pure constraint constraint-name;
– Every pure constraint MUST be overridden in non-abstract classes
Again: purecreates
Again: pure createsaaplace-holder
place-holder
purerequires
pure requiresthat
thataa
constraint
constraintbe
beoverridden
overridden
with
withan
anactual
actualconstraint
constraint
52 of 59
Allow Functions to Spawn Processes

Mantis 1336
fork/ /join_none
fork join_noneallows
allows
functions
functionsto
tospawn
spawnoff
off
module forkprocess;
time-consuming
time-consumingcode
code
int b;
initial $timeformat(-9,0,"ns",6);
initial startup; Nonblocking
Nonblockingassignment
assignmentlegal
legal
ininfunction
functionwhen
whensurrounded
surrounded
function void startup; by fork / join_none
by fork / join_none
fork
b <= 8'hcc;
time-1
time-1 #1 $display("%t: 2nd Sequence started - b=%2h", $time, b);
#3 run;
time-2
time-2 #2 $display("%t: 3rd Sequence started", $time); taskcall
task callthat
thatconsumes
consumes
time
time(3+3+4=10ns)
(3+3+4=10ns)
join_none
time-0
time-0 $display("%t: Initial Sequence started", $time);
endfunction
task run;
int a;
endmodule #3 a=8'h88;
Output
#4 $display("RUN(%t): a=%2h",
Outputdisplay
display $time, a);
0ns: Initial Sequence started endtask
1ns: 2nd Sequence started - b=cc
2ns: 3rd Sequence started
RUN( 10ns): a=88
26 of 30 Rev 1.1
53 of 59
External Methods w/ Parameterized Classes

Mantis 1857
SystemVerilog-2005
SystemVerilog-2005doesdoesnot
not
allow
allowaaclass
classtype
typeto
touse
useboth
both
class C #(int p = 1);
parameters and external methods
parameters and external methods
extern static function int f();
endclass
function int C::f(); Fixed

return p + p; Fixedmethod
method
return
returntype
type Output
Outputdisplay
display
endfunction
2 10
initial $display("%0d %0d", C#()::f(),C#(5)::f());
SystemVerilog-2009
SystemVerilog-2009addsaddsthe
the
ability
abilityto
tohave
haveparameterized
parameterized
class C #(int p = 1, type T = int); classes with external methods
classes with external methods
extern static function T f();
endclass
Declaration
Declarationof
of
extern
externstatic
staticfunction
function(method)
(method)
function C::T C::f();
with
withreturn
returntype
typeTT (parameterized
(parameterizedtype)
type)
return p + C::p;
endfunction
initial $display(“%0d %0d”, C#()::f(),C#(5)::f());

54 of 59
Covergroup Sample Method w/ Arguments

Mantis 2149
covergroupwith
covergroup withsample
sample
arguments
argumentsaaand
andxx
covergroup p_cg with function sample(bit a, int x);

coverpoint x;
cross x, a;
endgroup
......ififccisishigh ##1cycle
high##1 cyclelater,
later,sample
samplethe
the
p_cg cg1 = new; When
Whenaaisishigh,
high,set
set covergroup
covergroupcg1 cg1(p_cg
(p_cg) )and
andpass
passthe
the
local
localvariable x=b ...... sampled
variablex=b sampledaaand andxxvalues
valuestotothe
thecovergroup
covergroup
property p1;
int x;
@(posedge clk)(a, x = b) ##1 (c, cg1.sample(a, x));
endproperty
c1: cover property (p1);
27 of 30 Rev 1.1
55 of 59
SystemVerilog-2009
Miscellaneous Enhancements
timeunit
$system task
`__FILE__ & `__LINE__ Macros
SDF Annotation of $timeskew & $fullskew
56 of 59
New Concise timeunit Syntax

Mantis 1623
SystemVerilog-2005
SystemVerilog-2005 SystemVerilog-2009
SystemVerilog-2009
`timescale 1ns/1ns 1ns/1ns `timescale 1ns/1ns
module tb; 1ns/1ns module tb;
timescale
timescale
... ...
active
active
endmodule endmodule
module register ( module register (

output logic [7:0] q, output logic [7:0] q,
input logic [7:0] d, input logic [7:0] d,
input logic clk); 100ps/100ps
100ps/100ps input logic clk);
timeunit 100ps; local
localtimescale
timescale timeunit 100ps/100ps;
timeprecision 100ps;
Combined
Combined 1-line
1-line syntax
syntax
2-line
2-line syntax
syntax
always_ff @(posedge clk) Must
Must be
be placed
placed always_ff @(posedge clk)
q <= #1 d; immediately
immediately after
after q <= #1 d;
endmodule module header
module header endmodule
module blka (...); 1ns/1ns module blka (...);

... 1ns/1ns ...
timescale
timescale
endmodule endmodule
again
againactive
active
28 of 30 Rev 1.1
57 of 59
$system Task to Invoke SystemCommands

Mantis 1863
• The $system task allows SystemVerilog code to call operating

system commands
module top;
initial $system("mv design.v adder.v");
endmodule
Most
MostVerilog
Verilogsimulators
simulatorsalready
already
have
havethis
thistask,
task,but
butititwas
wasnever
never
part
partof
ofthe
theVerilog
Verilogstandard
standard
58 of 59
`__FILE__ & `__LINE__ Macros

Mantis 1588
• SystemVerilog-2009 adds the C-like macros

‘__FILE__
‘__LINE__
• These macros allow access to the current file and line number
from within SystemVerilog code
29 of 30 Rev 1.1
59 of 59
SDF Annotation of $timeskew & $fullskew

Mantis 1140
• Verilog-2001 added the timing skew checks

$timeskew
$fullskew
• SystemVerilog-2009 defines how these checks are annotated

from SDF files
60 of 59
SystemVerilog Is Getting Even Better!

An Update on the Proposed 2009 SystemVerilog Standard
Part 1
Presented by
Clifford E. Cummings Stuart Sutherland

Sunburst Design, Inc. Sutherland HDL, Inc.
cliffc@sunburst-design.com stuart@sutherland-hdl.com
www.sunburst-design.com www.sutherland-hdl.com
sponsored by
30 of 30 Rev 1.1

SystemVerilog Update Part1 Cummings

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DAC 2009 SystemVerilog-2009 Presentation

by Sunburst Design, Beaverton, Oregon, © 2009

The SystemVerilog Mantis Database

• The Mantis database contains corrections, clarifications &

• Mantis Item numbers are noted on appropriate slides

© 2009, Sunburst Design, Inc.

Field Widths in Print Formats

("a=%h b=%h" , a, b); ("a=%0h b=%0h" , a, b); ("a=%4h b=%4h" , a, b);

a=000071ec b=000000fb a=71ec b=fb Remove

Print Format Specifier %x

© 2009, Sunburst Design, Inc.

Print Format Specifier %p (%4p)

$sformatf Returns a Formatted String

$fatal/$error/$warning/$info Display Tasks

© 2009, Sunburst Design, Inc.

© 2009, Sunburst Design, Inc.

always_ff @(posedge clk, negedge rst_n)

© 2009, Sunburst Design, Inc.

Edge Event - For DDR Logic

module ddrff ( Remove posedgeto

always_ff @(edge clk, negedge rst_n)

.name Instantiation & Unconnected Ports

.name Instantiation & Unconnected Ports

alu alu (.alu_out, .zero(), .one(), .ain, .bin, .opcode);

2-to-4 Decoder w/ Enable

module dec2_4a ( ============================

2-to-4 Decoder with Enable

© 2009, Sunburst Design, Inc.

2-to-4 Decoder w/ Enable

module dec2_4b ( ============================

© 2009, Sunburst Design, Inc.

Unique0 - parallel_case Equivalent

module dec2_4c ( ============================

2-to-4 Decoder with Enable

© 2009, Sunburst Design, Inc.

• SV-2009: priority/unique/unique0 violations Reported

Default Inputs For Module/Interface Ports

module register ( New

always_ff @(posedge clk, negedge rst_n, negedge set_n)

Default Inputs For Module/Interface Ports

register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n), .set_n(set_n));

register r1 (.q, .d, .clk, .rst_n, .set_n); tb overrides

register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));

register r1 (.q, .d, .clk, .rst_n); tb only

Default Inputs For Module/Interface Ports

register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n), .set_n(.set_n));

register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n)); tb only

register r1 (.q, .d, .clk, .rst_n, .set_n);

Bit Selects & Part Selects of Expressions

module expr_range; module expr_range;

Might NOTE: {concatenation}braces

© 2009, Sunburst Design, Inc.

© 2009, Sunburst Design, Inc.

Package Import in Design Element Header

Package Import in Design Element Header

Package Import in Design Element Header

... ...... packages

© 2009, Sunburst Design, Inc.

Package Chaining - Export in a Package

© 2009, Sunburst Design, Inc.

Package Chaining - Export in a Package

© 2009, Sunburst Design, Inc.

Multiple Package Export

`FILE & `LINE Macros