10/10/2017 Review Test Submission: ACK5 2016 Fall - ELEN 5324_48F...

Kandarp Jayeshbhai Shah

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H module5 (weeks-13-15) COMPLETE Review Test Submission: ACK5

Review Test Submission: ACK5

User Kandarp Jayeshbhai Shah

Course 2016 Fall - ELEN 5324_48F_1 - CMOS Digital IC DSN - Parent
Test ACK5
Started 12/3/16 2:08 AM
Submitted 12/3/16 2:20 AM
Due Date 12/6/16 12:00 PM
Status Completed
Attempt Score 87 out of 100 points
Time Elapsed 11 minutes out of 1 hour
Results Displayed Correct Answers

Question 1

T / F Eliminating the lead and decontamination steps are viable approaches for commercial chips to
battle alpha-particle-induced problems.

Correct Answer: False

Question 2

T / F In newer technologies, there are fewer logic gates in between storage elements as a result logical
masking effects are less.

Correct Answer: True

Question 3

T/F Circuit level hardening requires a change on fabrication process.

Correct Answer: False

Question 4

T / F If we switch to SOI Technology from Bulk CMOS, the collection volume of MOS transistor reduces.
As a result, we obtain less sensitivity to radiation.

Correct Answer: True

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Question 5

The ability of a given test pattern to detect a given fault on the device under test (DUT) is
called_______________

Correct Answer: fault coverage

Question 6

In the circuit below, radiation hit occurs at the output of 2nd inverter. Although the input to the very first
inverter is at ground (Vss), due to particle strike a pulse is generated at the output of 2nd inverter and
propagates two more inverters. In the figure, all the transient magnitudes and signals are shown along
with the clock edge being present. When we observe the output of the edge triggered D-type flip flop, we
still observe no change in the logic. What masking effect might be present in this circuit?

Correct Answer: logical masking

Question 7

In the circuit below, radiation hit occurs at the output of 2nd inverter. Although the input to the very first
inverter is at ground (Vss), due to particle strike a pulse is generated at the output of 2nd inverter and
propagates until it arrives at the D-type flip flop input ( Only waveforms after the OR gate are shown with
its magnitudes shown ).

When we observe the output of the edge triggered D-type flip flop, we still observe no change in the
logic. What masking effect(s) might be present in this circuit?

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10/10/2017 Review Test Submission: ACK5 2016 Fall - ELEN 5324_48F...

Correct Answer: timing (latching) window masking

Tuesday, October 10, 2017 5:06:08 PM CDT

OK

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