Documente Academic
Documente Profesional
Documente Cultură
1. Description
The AT26DF081A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT26DF081A, with its eras\e granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF081A have been opti-
mized to meet the needs of todays code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
3600GDFLASH06/09
The AT26DF081A also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT26DF081A incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and
erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for
programming and erasing.
2 AT26DF081A
3600GDFLASH06/09
AT26DF081A
3
3600GDFLASH06/09
Figure 2-1. 8-SOIC Top View
CS 1 8 VCC
SO 2 7 HOLD
WP 3 6 SCK
GND 4 5 SI
3. Block Diagram
SRAM
DATA BUFFER
SCK INTERFACE
CONTROL
SI
AND
LOGIC Y-DECODER Y-GATING
SO
ADDRESS LATCH
FLASH
MEMORY
WP X-DECODER ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
4 AT26DF081A
3600GDFLASH06/09
AT26DF081A
4KB 0E6FFFh 0E6000h
4KB 0E5FFFh 0E5000h
4KB 0E4FFFh 0E4000h 256 Bytes 0017FFh 001700h
32KB
4KB 0E3FFFh 0E3000h 256 Bytes 0016FFh 001600h
4KB 0E2FFFh 0E2000h 256 Bytes 0015FFh 001500h
4KB 0E1FFFh 0E1000h 256 Bytes 0014FFh 001400h
4KB 0E0FFFh 0E0000h 256 Bytes 0013FFh 001300h
256 Bytes 0012FFh 001200h
5
3600GDFLASH06/09
5. Device Operation
The AT26DF081A is controlled by a set of instructions that are sent from a host controller, com-
monly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via
the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial
Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT26DF081A supports the two most common modes, SPI
modes 0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always
output on the falling edge of SCK.
SCK
SI MSB LSB
SO MSB LSB
6 AT26DF081A
3600GDFLASH06/09
AT26DF081A
7
3600GDFLASH06/09
7. Read Commands
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OPCODE ADDRESS BITS A23-A0 DON'T CARE
SI 0 0 0 0 1 0 1 1 A A A A A A A A A X X X X X X X X
MSB MSB MSB
DATA BYTE 1
HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB
8 AT26DF081A
3600GDFLASH06/09
AT26DF081A
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE ADDRESS BITS A23-A0
SI 0 0 0 0 0 0 1 1 A A A A A A A A A
MSB MSB
DATA BYTE 1
HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB
9
3600GDFLASH06/09
reset back to the logical 0 state if the program cycle aborts due to an incomplete address being
sent, an incomplete byte of data being sent, or because the memory location to be programmed
is protected.
While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the tPP time to determine if the data bytes have finished programming. At
some point before the program cycle completes, the WEL bit in the Status Register will be reset
back to the logical 0 state.
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
The Byte/Page Program mode is the default programming mode after the device powers-up or
resumes from a device reset.
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE ADDRESS BITS A23-A0 DATA IN
SI 0 0 0 0 0 0 1 0 A A A A A A A A A D D D D D D D D
MSB MSB MSB
HIGH-IMPEDANCE
SO
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE ADDRESS BITS A23-A0 DATA IN BYTE 1 DATA IN BYTE n
SI 0 0 0 0 0 0 1 0 A A A A A A D D D D D D D D D D D D D D D D
MSB MSB MSB MSB
HIGH-IMPEDANCE
SO
10 AT26DF081A
3600GDFLASH06/09
AT26DF081A
11
3600GDFLASH06/09
sectors; therefore, once the highest unprotected memory location in a programming sequence
has been programmed, the device will automatically exit the Sequential Program mode and
reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0
was currently being programmed, once the last byte of Sector 0 was programmed, the Sequen-
tial Program mode would automatically end. To continue programming with Sector 2, the
Sequential Program mode would have to be restarted by supplying the ADh or AFh opcode, the
three address bytes, and the first byte of Sector 2 to program.
While the device is programming a byte, the Status Register can be read and will indicate that
the device is busy. For faster throughput, it is recommended that the Status Register be polled at
the end of each program cycle rather than waiting the tBP time to determine if the byte has fin-
ished programming before starting the next Sequential Program mode cycle.
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
Seqeuntial Program Mode Status Register Read Seqeuntial Program Mode Seqeuntial Program Mode Write Disable
Command Command Command Command Command
SI Opcode A23-16 A15-8 A7-0 Data 05h Opcode Data 05h Opcode Data 04h 05h
HIGH-IMPEDANCE
SO
Figure 8-4. Sequential Program Mode Waiting Maximum Byte Program Time
CS
tBP tBP tBP
Seqeuntial Program Mode Seqeuntial Program Mode Seqeuntial Program Mode Write Disable
Command Command Command Command
SI Opcode A23-16 A15-8 A7-0 Data Opcode Data Opcode Data 04h
HIGH-IMPEDANCE
SO
12 AT26DF081A
3600GDFLASH06/09
AT26DF081A
13
3600GDFLASH06/09
Figure 8-5. Block Erase
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31
SCK
OPCODE ADDRESS BITS A23-A0
SI C C C C C C C C A A A A A A A A A A A A
MSB MSB
HIGH-IMPEDANCE
SO
14 AT26DF081A
3600GDFLASH06/09
AT26DF081A
0 1 2 3 4 5 6 7
SCK
OPCODE
SI C C C C C C C C
MSB
HIGH-IMPEDANCE
SO
0 1 2 3 4 5 6 7
SCK
OPCODE
SI 0 0 0 0 0 1 1 0
MSB
HIGH-IMPEDANCE
SO
15
3600GDFLASH06/09
9.2 Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-
ister to the logical 0 state. With the WEL bit reset, all program, erase, Protect Sector, Unprotect
Sector, and Write Status Register commands will not be executed. The Write Disable command
is also used to exit the Sequential Program Mode. Other conditions can also cause the WEL bit
to be reset; for more details, refer to the WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be reset to a logical 0. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
0 1 2 3 4 5 6 7
SCK
OPCODE
SI 0 0 0 0 0 1 0 0
MSB
HIGH-IMPEDANCE
SO
Before the Protect Sector command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical 1. To issue the Protect
Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into
the device followed by three address bytes designating any address within the sector to be
locked. Any additional data clocked into the device will be ignored. When the CS pin is deas-
serted, the Sector Protection Register corresponding to the physical sector addressed by
A23 - A0 will be set to the logical 1 state, and the sector itself will then be protected from
16 AT26DF081A
3600GDFLASH06/09
AT26DF081A
program and erase operations. In addition, the WEL bit in the Status Register will be reset back
to the logical 0 state.
The complete three address bytes must be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation, the state of the Sector Protection Register will be
unchanged, and the WEL bit in the Status Register will be reset to a logical 0.
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector
Protection Registers can themselves be locked from updates by using the SPRL (Sector Protec-
tion Registers Locked) bit of the Status Register (please refer to the Status Register description
for more details). If the Sector Protection Registers are locked, then any attempts to issue the
Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Reg-
ister back to a logical 0 and return to the idle state once the CS pin has been deasserted.
0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31
SCK
OPCODE ADDRESS BITS A23-A0
SI 0 0 1 1 0 1 1 0 A A A A A A A A A A A A
MSB MSB
HIGH-IMPEDANCE
SO
17
3600GDFLASH06/09
Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status
Register back to a logical 0 and return to the idle state once the CS pin has been deasserted.
0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31
SCK
OPCODE ADDRESS BITS A23-A0
SI 0 0 1 1 1 0 0 1 A A A A A A A A A A A A
MSB MSB
HIGH-IMPEDANCE
SO
18 AT26DF081A
3600GDFLASH06/09
AT26DF081A
Essentially, if the SPRL bit of the Status Register is in the logical 0 state (Sector Protection
Registers are not locked), then writing a 00h to the Status Register will perform a Global Unpro-
tect without changing the state of the SPRL bit. Similarly, writing a 7Fh to the Status Register will
perform a Global Protect and keep the SPRL bit in the logical 0 state. The SPRL bit can, of
course, be changed to a logical 1 by writing an FFh if software-locking or hardware-locking is
desired along with the Global Protect.
19
3600GDFLASH06/09
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-
tect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit from
a logical 1 to a logical 0 provided the WP pin is deasserted. Likewise, the system can write an
F0h to change the SPRL bit from a logical 0 to a logical 1 without affecting the current sector
protection status (no changes will be made to the Sector Protection Registers).
When writing to the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will be
decoded by the device for the purposes of the Global Protect and Global Unprotect functions.
Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading the Status Register,
bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of
the WP pin and the sector protection status. Please refer to the Read Status Register section
and Table 10-1 on page 23 for details on the Status Register format and what values can be
read for bits 5, 4, 3, and 2.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
In addition to reading the individual Sector Protection Registers, the Software Protection Status
(SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are
software protected (refer to the Status Register Commands on page 23 for more details).
20 AT26DF081A
3600GDFLASH06/09
AT26DF081A
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE ADDRESS BITS A23-A0
SI 0 0 1 1 1 1 0 0 A A A A A A A A A
MSB MSB
DATA BYTE
HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB
21
3600GDFLASH06/09
Tables 9-4 and 9-5 detail the various protection and locking states of the device.
X 0 Unprotected
(Don't Care) 1 Protected
22 AT26DF081A
3600GDFLASH06/09
AT26DF081A
23
3600GDFLASH06/09
10.1.1 SPRL Bit
The SPRL bit is used to control whether the Sector Protection Registers can be modified or not.
When the SPRL bit is in the logical 1 state, all Sector Protection Registers are locked and can-
not be modified with the Protect Sector and Unprotect Sector commands (the device will ignore
these commands). In addition, the Global Protect and Global Unprotect features cannot be per-
formed. Any sectors that are presently protected will remain protected, and any sectors that are
presently unprotected will remain unprotected.
When the SPRL bit is in the logical 0 state, all Sector Protection Registers are unlocked and
can be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Pro-
tect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to the
logical 0 state after a power-up or a device reset.
The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin
is asserted, then the SPRL bit may only be changed from a logical 0 (Sector Protection Regis-
ters are unlocked) to a logical 1 (Sector Protection Registers are locked). In order to reset the
SPRL bit back to a logical 0 using the Write Status Register command, the WP pin will have to
first be deasserted.
The SPRL bit is the only bit of the Status Register that can be user modified via the Write Status
Register command.
24 AT26DF081A
3600GDFLASH06/09
AT26DF081A
If the WEL bit is in the logical 1 state, it will not be reset to a logical 0 if an operation aborts
due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is
deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire
opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-
mand must have been clocked into the device.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
OPCODE
SI 0 0 0 0 0 1 0 1
MSB
HIGH-IMPEDANCE
SO D D D D D D D D D D D D D D D D D D
MSB MSB MSB
25
3600GDFLASH06/09
10.2 Write Status Register
The Write Status Register command is used to modify the SPRL bit of the Status Register
and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-
ter command can be issued, the Write Enable command must have been previously issued to
set the WEL bit in the Status Register to a logical 1.
To issue the Write Status Register command, the CS pin must first be asserted and the opcode
of 01h must be clocked into the device followed by one byte of data. The one byte of data con-
sists of the SPRL bit value, a dont care bit, four data bits to denote whether a Global Protect or
Unprotect should be performed, and two additional dont care bits (see Table 10-2). Any addi-
tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the
SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be
reset back to a logical 0. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before
the Write Status Register command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be performed. Please refer to the
Global Protect/Unprotect section on page 18 for more details.
The complete one byte of data must be clocked into the device before the CS pin is deasserted;
otherwise, the device will abort the operation, the state of the SPRL bit will not change, no
potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register
will be reset back to the logical 0 state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical 1. If an attempt is made
to reset the SPRL bit to a logical 0 while the WP pin is asserted, then the Write Status Register
command will be ignored, and the WEL bit in the Status Register will be reset back to the logical
0 state. In order to reset the SPRL bit to a logical 0, the WP pin must be deasserted.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
OPCODE STATUS REGISTER IN
SI 0 0 0 0 0 0 0 1 D X D D D D X X
MSB MSB
HIGH-IMPEDANCE
SO
26 AT26DF081A
3600GDFLASH06/09
AT26DF081A
MLC Code Product Version Code MLC Code: 000 (1-bit/cell technology)
Device ID (Part 2) 01h
0 0 0 0 0 0 0 1 Product Version:00001 (First major revision)
27
3600GDFLASH06/09
Figure 11-1. Read Manufacturer and Device ID
CS
0 6 7 8 14 15 16 22 23 24 30 31 32 38
SCK
OPCODE
SI 9Fh
HIGH-IMPEDANCE
SO 1Fh 45h 01h 00h
Note: Each transition shown for SI and SO represents one byte (8 bits)
The Deep Power-down command will be ignored if an internally self-timed operation such as a
program or erase cycle is in progress. The Deep Power-down command must be reissued after
the internally self-timed operation has been completed in order for the device to enter the Deep
Power-down mode.
28 AT26DF081A
3600GDFLASH06/09
AT26DF081A
0 1 2 3 4 5 6 7
SCK
OPCODE
SI 1 0 1 1 1 0 0 1
MSB
HIGH-IMPEDANCE
SO
Active Current
ICC
Standby Mode Current
Deep Power-Down Mode Current
0 1 2 3 4 5 6 7
SCK
OPCODE
SI 1 0 1 0 1 0 1 1
MSB
HIGH-IMPEDANCE
SO
Active Current
ICC
Standby Mode Current
Deep Power-Down Mode Current
29
3600GDFLASH06/09
11.4 Hold
The HOLD pin is used to pause the serial communication with the device without having to stop
or reset the clock sequence. The Hold mode, however, does not have an affect on any internally
self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in prog-
ress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until
it is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated
simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during
the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low
pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are
asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin
and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while
in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted
during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the
Hold mode won't end until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may
have been started will be aborted, and the device will reset the WEL bit in the Status Register
back to the logical 0 state.
SCK
HOLD
30 AT26DF081A
3600GDFLASH06/09
AT26DF081A
12.3 DC Characteristics
Symbol Parameter Condition Min Typ Max Units
CS, WP, HOLD = VCC,
ISB Standby Current 25 35 A
all inputs at CMOS levels
CS, WP, HOLD = VCC,
IDPD Deep Power-down Current 25 35 A
all inputs at CMOS levels
f = 70 MHz; IOUT = 0 mA;
11 16
CS = VIL, VCC = Max
f = 66 MHz; IOUT = 0 mA;
10 15
CS = VIL, VCC = Max
f = 50 MHz; IOUT = 0 mA;
ICC1 Active Current, Read Operation 9 14 mA
CS = VIL, VCC = Max
f = 33 MHz; IOUT = 0 mA;
8 12
CS = VIL, VCC = Max
f = 20 MHz; IOUT = 0 mA;
7 10
CS = VIL, VCC = Max
ICC2 Active Current, Program Operation CS = VCC, VCC = Max 12 18 mA
ICC3 Active Current, Erase Operation CS = VCC, VCC = Max 14 20 mA
ILI Input Leakage Current VIN = CMOS levels 1 A
ILO Output Leakage Current VOUT = CMOS levels 1 A
VIL Input Low Voltage 0.3 x VCC V
VIH Input High Voltage 0.7 x VCC V
VOL Output Low Voltage IOL = 1.6 mA; VCC = Min 0.4 V
VOH Output High Voltage IOH = -100 A VCC - 0.2V V
31
3600GDFLASH06/09
12.4 AC Characteristics
Symbol Parameter Min Max Units
fSCK Serial Clock (SCK) Frequency 70 MHz
fRDLF SCK Frequency for Read Array (Low Frequency - 03h opcode) 33 MHz
tSCKH SCK High Time 6.4 ns
tSCKL SCK Low Time 6.4 ns
(1)
tSCKR SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tCSH Chip Select High Time 50 ns
tCSLS Chip Select Low Setup Time (relative to SCK) 5 ns
tCSLH Chip Select Low Hold Time (relative to SCK) 5 ns
tCSHS Chip Select High Setup Time (relative to SCK) 5 ns
tCSHH Chip Select High Hold Time (relative to SCK) 5 ns
tDS Data In Setup Time 2 ns
tDH Data In Hold Time 3 ns
tDIS(1) Output Disable Time 6 ns
tV(2) Output Valid Time 6 ns
tOH Output Hold Time 0 ns
tHLS HOLD Low Setup Time (relative to SCK) 5 ns
tHLH HOLD Low Hold Time (relative to SCK) 5 ns
tHHS HOLD High Setup Time (relative to SCK) 5 ns
tHHH HOLD High Hold Time (relative to SCK) 5 ns
tHLQZ(1) HOLD Low to Output High-Z 6 ns
tHHQX(1) HOLD High to Output Low-Z 6 ns
tWPS(1)(3) Write Protect Setup Time 20 ns
(1)(3)
tWPH Write Protect Hold Time 100 ns
tSECP(1) Sector Protect Time (from Chip Select High) 20 ns
tSECUP(1) Sector Unprotect Time (from Chip Select High) 20 ns
(1)
tEDPD Chip Select High to Deep Power-down 3 s
tRDPD(1) Chip Select High to Standby Mode 3 s
Notes: 1. Not 100% tested (value guaranteed by design and characterization).
2. 15 pF load at 70 MHz, 30 pF load at 66 MHz.
3. Only applicable as a constraint for the Write Status Register command when SPRL = 1
32 AT26DF081A
3600GDFLASH06/09
AT26DF081A
Notes: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles.
2. Not 100% tested (value guaranteed by design and characterization).
AC 2.4V AC
DRIVING 1.5V MEASUREMENT
LEVELS 0.45V LEVEL
DEVICE
UNDER
TEST
30 pF
33
3600GDFLASH06/09
13. Waveforms
Figure 13-1. Serial Input Timing
tCSH
CS
tCSLS tCSLH tCSHH
tSCKH tSCKL tCSHS
SCK
tDS tDH
HIGH-IMPEDANCE
SO
SCK
SI
tOH
tV tV
SO
SCK
tHHH tHLS
tHLH tHHS
HOLD
SI
HIGH-IMPEDANCE
SO
34 AT26DF081A
3600GDFLASH06/09
AT26DF081A
SCK
tHHH tHLS
tHLH tHHS
HOLD
SI
tHLQZ tHHQX
SO
Figure 13-5. WP Timing for Write Status Register Command When SPRL = 1
CS
tWPS tWPH
WP
SCK
SI 0 0 0 X MSB
MSB OF LSB OF MSB OF
WRITE STATUS REGISTER WRITE STATUS REGISTER NEXT OPCODE
OPCODE DATA BYTE
HIGH-IMPEDANCE
SO
35
3600GDFLASH06/09
14. Ordering Information
Package Type
8S1 8-lead, 0.150 Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.209 Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
36 AT26DF081A
3600GDFLASH06/09
AT26DF081A
E E1
N L
TOP VIEW
END VIEW
e b
A COMMON DIMENSIONS
(Unit of Measure = mm)
A1 0.10 0.25
SIDE VIEW
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 Small Outline (JEDEC SOIC) 8S1 C
R
37
3600GDFLASH06/09
15.2 8S2 EIAJ SOIC
E E1
L
N
TOP VIEW
END VIEW
e b COMMON DIMENSIONS
A (Unit of Measure = mm)
4/15/08
TITLE GPC DRAWING NO. REV.
Package Drawing Contact: 8S2, 8-lead, 0.208 Body, Plastic Small
packagedrawings@atmel.com Outline Package (EIAJ) STN 8S2 F
38 AT26DF081A
3600GDFLASH06/09
AT26DF081A
39
3600GDFLASH06/09
Headquarters International
Product Contact
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMELS WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmels products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
2009 Atmel Corporation. All rights reserved. Atmel , Atmel logo and combinations thereof, Everywhere You Are , DataFlash and others
are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
3600GDFLASH06/09