International Journal of IT, Engineering and Applied Sciences Research (IJIEASR) ISSN: 2319-4413 25

Volume 1, No. 3, December 2012

Comparison of multilevel inverters with PWM Control Method

Vijay Kumar M.G, Dept. of Electronics & Communication Engineering, Basavakalyan Engineering College,
Basavakalyan, Bidar. Karnataka
Manjunath D, Dept. of Electronics & Communication Engineering, Basavakalyan Engineering College,
Basavakalyan, Bidar. Karnataka
Anil W. Patil, Dept. of Electronics & Communication Engineering, Basavakalyan Engineering College,
Basavakalyan, Bidar. Karnataka

ABSTRACT
This paper presents the most important multilevel
inverter topologies like diode-clamped inverter
(neutral-point clamped), capacitor-clamped (flying
capacitor), and cascaded multicell( H-Bridge ) with
separate dc sources. A Comparison of 5-level hybrid
cascaded inverter with PWM method, 5 level diode
clamped inverter & 5 level capacitor coupled inverter is
also presented in this paper. This paper also presents
the most relevant control and modulation methods
developed for this family of inverters i.e. multilevel
sinusoidal pulse width modulation. A simulation model
based MATLAB/SIMULINK is developed for hybrid
cascaded multilevel inverter, diode clamped multilevel
inverter & Capacitor clamped multilevel inverter with
PWM control method. The results experimentally
validate the proposed paper.
Keywords: Induction machine, Space Vector pulse
width modulation, Pulse width modulation, Torque,
Speed, Simulink model.
INTRODUCTION
A multilevel inverter is a power electronic device built
to synthesize a desired AC voltage from several levels
of DC voltages. Such inverters have been the subject of
research in the last several years where the DC levels
were considered to be identical in that all of them were
capacitors, batteries, solar cells, etc.
In Recent Years, industry has begun to demand higher
power equipment, which now reaches the megawatt
level. Controlled ac drives in the megawatt range are
usually connected to the medium-voltage network.
Today, it is hard to connect a single power
semiconductor switch directly to medium voltage grids
(2.3, 3.3, 4.16, or 6.9 kV). For these reasons, a new
family of multilevel inverters has emerged as the
solution for working with higher voltage levels [1][3].
Multilevel inverters include an array of power
semiconductors and capacitor voltage sources, the
output of which generate voltages with stepped
waveforms. The commutation of the switches permits
the addition of the capacitor voltages, which reach high
voltage at the output, while the power semiconductors
must withstand only reduced voltages. Fig. 1 shows a
schematic diagram of one phase leg of inverters with
different numbers of levels, for which the action of the
power semiconductors is represented by an ideal switch
with several positions.
Fig. 1. One phase leg of an inverter with (a) two levels,
(b) three levels, and (c) n levels.
A two-level inverter generates an output voltage with
two values (levels) with respect to the negative terminal
of the capacitor [see Fig. 1(a)], while the three-level
inverter generates three voltages, and so on.
Considering that m is the number of steps of the phase
voltage with respect to the negative terminal of the
inverter, then the number of steps in the voltage
between two phases of the load is k
K=2m+1 (1)
and the number of steps p in the phase voltage of a
three-phase load in wye connection is
p=2k-1 (2)
The term multilevel starts with the three-level inverter
introduced by Nabae I t. [4]. By increasing the number
of levels in the inverter, the output voltages have more
steps generating a staircase waveform, which has a
reduced harmonic distortion. However, a high number
of levels increases the control complexity and
introduces voltage imbalance problems. Three different
topologies have been proposed for multilevel inverters:
diode-clamped (neutral-clamped) [4]; capacitor-
clamped (flying capacitors) [1], [5], [6]; and cascaded
multicell with separate dc sources [1], [7][9]. In
addition, several modulation and control strategies have
been developed or adopted for multilevel inverters
including the following: multilevel sinusoidal pulse
width modulation (PWM), multilevel selective

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International Journal of IT, Engineering and Applied Sciences Research (IJIEASR)
Volume 1, No. 3, December 2012
harmonic elimination, and space-vector modulation
(SVM).
II. INVERTER TOPOLOGIES
A. Diode-Clamped Inverter.
Fig. 2 shows a five-level diode-clamped inverter in
which the dc bus consists of four capacitors, C1, C2, C3,
and C4. For dc-bus voltage Vdc, the voltage across each
capacitor is Vdc/4, and each device voltage stress will be
limited to one capacitor voltage level Vdc/4 through
clamping diodes.
Fig. 2. Five-level Diode-clamped multilevel inverter
circuit topology.
To explain how the staircase voltage is synthesized, the
neutral point n is considered as the output phase voltage
reference point. There are five switch combinations to
synthesize five level voltages across a and n.
1) For voltage level Van = Vdc/2, turn on all upper
switches S1 S4.
2) For voltage level Van = Vdc/4, turn on three upper
switches S2 S4 and one lower switch S1.
3) For voltage level Van = 0, turn on two upper switches
S3 and S4 and two lower switches s1 and s2.
4) For voltage level Van = -Vdc/4, turn on one upper
switch S4 and three lower switches s1 s3.
5) For voltage level Van = Vdc/2, turn on all lower
switches S1 S4.
Four complementary switch pairs exist in each phase.
The complementary switch pair is defined such that
turning on one of the switches will exclude the other
from being turned on. In this example, the four
complementary pairs are (S1-S1), (S2-S2), (S3- S3),
and (S4 -S4).
B. Capacitor-Clamped Inverter.
Fig. 3 illustrates the fundamental building
block of a phase-leg capacitor-clamped inverter. The
circuit has been called the flying capacitor inverter [1],
i-Xplore International Research Journal Consortium
ISSN: 2319-4413 26
[5], [6] with independent capacitors clamping the
device voltage to one capacitor voltage level.
Fig. 3. Five-level Capacitor-clamped multilevel inverter
circuit topology.
The voltage synthesis in a five-level capacitor-clamped
converter has more flexibility than a diode-clamped
converter. Using Fig. 3(b) as the example, the voltage
of the five-level phase-leg a output with respect to the
neutral point n, Van , can be synthesized by the
following switch combinations.
1) For voltage level Van = Vdc/2, turn on all upper
switches S1 S4.
2) For voltage level Van = Vdc/4, there are three
combinations:
a) S1,S2, S3, S1. (Van = Vdc/2 of upper C4s - Vdc/4 of
C1);
b) S2, S3, S4, S4. (Van = 3Vdc/4 of upper C3s - Vdc/2 of
C4);
c) S1, S3, S4, S3. (Van = Vdc/2 of upper C4s - 3Vdc/4 of
C3
+Vdc/2 of C2);
3) For voltage level Van = 0, there are six combinations:
a) S1,S2, S3, S2.(Van= Vdc/2 of upper C4s -Vdc/2 of C2);
b) S3, S4, S3, S4.(Van=Vdc/2 of upper C2s -Vdc/2 of C4);
c) S1, S3, S1, S3.(Van=Vdc/2 of upper C4s - 3Vdc/4 of
C3+Vdc/2 of C2s -Vdc/4 of C1);
d) S1, S4, S2, S3. (Van = Vdc/2 of upper C4s - 3Vdc/4 of
C3s +Vdc/4 of C1);
e) S2, S4, S2, S4. (Van = 3Vdc/4 of C3s - Vdc/2 of C2s
+Vdc/4 of C1, - Vdc/2 of lower C4s);
f) S2, S3, S1, S4. (Van = 3Vdc/4 of C3s - Vdc/4 of C1
-Vdc/2 of lower C4s).
4) For voltage level -Van = Vdc/4, there are three
combinations:
a) S1,S1, S2, S3(Van=Vdc/2 of upper C4s -3Vdc/4
of C3s);
b) S4, S2, S3, S4. (Van=Vdc/4 of C1 -Vdc/2 of lower
C4s); and
c) S3, S1, S3, S4. (Van=Vdc/2 of C2s -Vdc/4 of C1
-Vdc/2 of lower C4s).
5) For voltage level Van = -Vdc/2, turn on all lower
switches, S1 S4.
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International Journal of IT, Engineering and Applied Sciences Research (IJIEASR) ISSN: 2319-4413 27
Volume 1, No. 3, December 2012

In the preceding description, the capacitors with switching methods can be used for the hybrid multilevel
positive signs are in discharging mode, while those with inverter.
negative sign are in charging mode. By proper selection Multilevel carrierbased PWM strategies are the most
of capacitor combinations, it is possible to balance the popular methods because they are easily implemented.
capacitor charge. Similar to diode clamping, the Three major carrier-based techniques that are used in a
capacitor clamping requires a large number of bulk conventional inverter can be applied in a multilevel
capacitors to clamp the voltage. inverter: sinusoidal PWM (SPWM), third harmonic
injection PWM (THPWM), and space vector PWM
C. Cascaded Multicell (H-bridge) Inverters. (SVM). SPWM is a popular method in industrial
applications. It uses several triangle carrier signals, one
A different converter topology is introduced here, carrier for each level and one reference, or modulation,
which is based on the series connection of single-phase signal per phase. In the proposed inverter, the top H-
inverters with separate dc sources [7]. Fig. 4 shows the bridge inverter is operated under the SPWM mode and
power circuit for one phase leg of a five-level inverter the bottom standard 3-leg inverter is operated under
with one cell in each phase. The resulting phase voltage square-wave mode in order to reduce switching loss.
is synthesized by the addition of the voltages generated
by this cell. In this paper, the simulation model is developed with
MATALB/SIMULINK. The MATALB/SIMULINK
model for the power circuit of hybrid cascaded
multilevel inverter, diode clamped multilevel inverter,
capacitor clamped multilevel inverter is shown in Fig.
5, fig 6 and fig 7 respectively.
Discrete,
s = 5e-006
powergui

Inverter output
Voltage & H-hridge o /p voltage Output H -Bride
PWM Subsystem
inverter volage &
current
Vabc
1
Pulse Pulse Pulse
g

g
C

C
R Hbridgevolteg
Generator Generator 1 Generator 2 Gain
From
C/2
m

m
1
E

E
H-bridge 1 Gain 1
1 2
A a A Vabc
DC Power H-bridge 2 Iabc
Figure 4: one phase leg of a five-level inverter with one Supply
40V
B b 1

H-Bridge 3
2 B a
b
A
B
A
B
C c C
c C C
H-bridge cell. Three phase
V-I measurment block
1 2

Three phase 3 Phase Resistance

NOT NOT V-I measurment block

NOT
Logical
g
C

Logical
g

g
C

Operator 1 Logical
Operator
The bottom is one leg of a standard 3-leg inverter with a C/2
Operator 2
m
E

m
E

DC power source. The top is an H-bridge in series with

each standard inverter leg. The H-bridge can use a
separate DC power source or a capacitor as the dc
power source. The output voltage V1 of this leg (with
respect to the ground) is either +Vdc/2 (S5 closed) or -
Vdc/2 (S6 closed).
i.e V1= +Vdc/2 when S11, S13, S15 closed (for
each leg) & V1= -Vdc/2 when S12, S14, S16
closed (for each leg) Figure 5: Simulink model for cascaded H-bridge
This leg is connected in series with a full H-bridge that inverter.
in turn is supplied by a capacitor voltage. If the
capacitor is kept charged to Vdc/2, then the output
Discrete ,
voltage of the H bridge can take on the values +Vdc/2 s = 1e -006
powergui
when (S1and S4 closed), 0 when (S1and S2 closed or
S3 and S4 closed), or -Vdc/2 (S2 and S3 closed).
1
pwm Subsystem
Gain

III. MATLAB SIMULINK SIMULATION 1

The modulation control schemes for the multilevel C Gain 1

A Vabc
inverter can be divided into two categories, fundamental b B
Iabc
a A A
switching frequency and high switching frequency C
b
c
B
C
B
C
PWM such as multilevel carrierbased PWM, selective A Three phase
V-I measurment block
3 Phase Resistance

harmonic elimination and multilevel space vector Three -phase 5-level

diode clamped inverter .
PWM. Both PWM and fundamental frequency
Figure 6: Simulink model for Diode clamped inverter.

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International Journal of IT, Engineering and Applied Sciences Research (IJIEASR) ISSN: 2319-4413 28
Volume 1, No. 3, December 2012

Discrete ,
s = 1e -006
powergui IV. EXPERIMENTAL RESULTS
1

pwm Subsystem
Gain
A simulation of the multilevel inverter was carried out.
C
Gain 1
1
The DC link voltage Vdc was set to 40 V so that the 3-
A Vabc leg inverter puts out 20 V. The capacitors were
Iabc
B a
b
A
B
A
B
regulated to 20 V. The experimental results including
b C c C
3 Phase Resistance
C
phase voltage, phase-phase voltage, and phase current
Three phase
V-I measurment block
of hybrid cascaded multilevel inverter are shown in Fig.
A 10.
Three -phase 5-level
capacitor clamped inverter .

Phase voltage Phase-

Figure 7: Simulink model for capacitor clamped
inverter.
1
C

C E C E C E C E C E C E C E C E
g m g m g m g m g m g m g m g m
20 From
22 From

21 From
16 From

19 From
18 From

32s
17 From

23 From
31s

33s
31s

34s
33s
32s

34s

Phase current
17C
13C

14C
18C

16C

15C
2
b

C E C E C E C E C E C E C E C E
g m g m g m g m g m g m g m g m
13 From
10 From

12 From

15 From

14 From
8

22s
9

11 From
23s

21s

23s

24s
21s

22s

24s
From

From

11C

Figure 10: phase voltage, phase-phase voltage, and

7C

8C

phase current hybrid cascaded multilevel inverter.

12C

10C

9C
3
A

C E

The output phase voltage is five-level. The phase

C E C E C E C E C E C E C E
g m
g m g m g m g m g m g m g m
4

6
2

11s

12s
1

7
From

From

1
11s

From

13s

14s

From
12s

14s
From

From

current waveform is close to sinusoidal. A simulation of

From

From
5C
1C

2C

the diode clamped multilevel inverter was carried out.

6C

4C

3C

The DC link voltage Vdc was set to 500 V so that the 3-

leg inverter puts out 200 V. The capacitors were
1

regulated to 200 V.
Series RLC Branch

Series RLC Branch

Series RLC Branch

Series RLC Branch

The experimental results including phase voltage,

DC V

Figure 8: internal model of five level capacitor clamped phase-phase voltage, and phase current of diode
inverter. clamped inverter are shown in Fig.11.
1
C

D S D D D D D D
S S D S S S S S
g m g m g m g m g m g m g m
g m
19

22

21

12

24

23

11
20

20 From
22 From
16 From

19 From

21 From
18 From

32s
17 From

23 From
31s
31s

34s
Mosfet

33s
33s
Mosfet

Mosfet

Mosfet

Mosfet

Mosfet

Mosfet
32s

Mosfet

34s
2
b

D S D S D S D S D S D S D S D S
g m g m g m g m g m g m g m g m
9
16

13

15

14

18

17
10
13 From
10 From

12 From

15 From

14 From
8

22s
9

11 From
23s

Mosfet
21s

23s

24s
21s

Mosfet

Mosfet

Mosfet

Mosfet

Mosfet

Mosfet
22s

24s
From

Mosfet
From

3
A

D S D D D D D D
S S D S S S S S
g m g g g g g g
m m g m m m m m
2

8
5

6
2

11s

12s
1 Mosfet

7
Mosfet

From

From

1s
11s

Mosfet

Mosfet

Mosfet

Mosfet

Mosfet
From

13s

14s

Mosfet

From
12s

14s
From

From
From

From

Figure 11: phase voltage (blue), phase-phase voltage

(green), and phase current (red) of diode clamped
multilevel inverter.
2

3
1

A simulation of the capacitor clamped multilevel

Series RLC Branch

Series RLC Branch

Series RLC Branch

Series RLC Branch

inverter was carried out. The DC link voltage Vdc was

DC V

set to 500 V so that the 3-leg inverter puts out 200 V.

The capacitors were regulated to 200 V.
Figure 9: internal model of five level diode clamped The experimental results including phase voltage,
inverter. phase-phase voltage, and phase current of diode
clamped inverter are shown in Fig.12.

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International Journal of IT, Engineering and Applied Sciences Research (IJIEASR)
Volume 1, No. 3, December 2012
Figure 12: phase voltage (blue), phase-phase voltage
(green), and phase current (red) of capacitor clamped
inverter.
The THD of phase currents of five-level hybrid
cascaded multilevel inverter is 2.71%, The THD of
phase currents of five level diode clamped inverter is
20.55% and The THD of phase currents of five level
capacitor clamped inverter is 18.27%. From above
THDs it is clear that the five-level hybrid cascaded
multilevel inverter is better than of five level diode
clamped inverter as well as five level capacitor coupled
inverter.
V. CONCLUSION
This paper has provided a brief summary of multilevel
inverter circuit topologies and their control strategies. A
simulation model for the hybrid cascaded multilevel
inverter, diode clamped multilevel inverter and
capacitor coupled inverter are developed in SIMULINK
co-simulation platform. The hybrid cascaded multilevel
inverter output is a five level phase voltage while the
diode clamped multilevel inverter output is a five level
phase voltage with high distortion in phase current . The
paper presents the main circuit model in MATLAB and
simulation results in detail. The experiment and FFT
analysis results verified the proposed hybrid cascaded
multilevel inverter with a PWM control method.
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