USN 10BCs6

Fifth Semester B.E. Degree Examination, Dec.20l4l Ja,n.2DlS

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Fundamentals of GMOS VLSI
TiEhe: 3 hrs.
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Note: Answer any FIW fall questions, selecting
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atleast TWO questions from each part.
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I a. Expldffi;:;the nMOS enhancement mode transistor operation ,#., different values of
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b. Explain the ,fllt4os inverter transfer characteristics highlighting tlre regions of operations of
! the MOS tranSis$ol' "r ,"." (10 Marks)
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2 a. Draw the circuit
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andlstick diagram for the nMOS and C?vIOS implementation of the Boolean

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expression y = , (10 Marks) ;:',.
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b. With neat diagram, explain, i based design *i., fot wired (nMOS and CMOS) and
( :i- transistor design rules (nMOS itvtOS and ClffiS;. (10 Marks)
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3 a. Explain the differences between CMO$.e lementary logic and BICMOS logic.
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3e b. Explain the following: i) nyoup _ tp'Sic; triffilocked CMOS logic. (12 Marks)
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oO 4 a. Provide scaling factors for:
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i) Saturation current.
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Power dissip-?t,i ;nit
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Maximum,'oprating .,,,
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5u b. circuits:
Discuss the forlltlwing in scaling of MOS ",. " ,
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i) Limits oirniniuturaizatioi. .*
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ir) L.'irnjf,s'of interconnect and contact resistance. ''
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5 a. . to sub system
,b.i'JOuss the architectural issues related
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Ei'E^Rtain switch logic (nMOS and CMOS) implementation for 4-way multiplexr. "ru
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'o= 'tfi t a. Discuss the general arrangements of a 4-bit arithmetic processor. 1Il Mg[9
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b. Explain 4 x Abarrel shifter with neat diagram. (08 Marks)
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qr< 7 a. Explain 3-transistor dynamic RAM-cell. (10 Marks) "'.,,"
J c.i b. Explain write operation, read operation for four transistor dynamic and six transistor static
o CMOS memory cell. (10 Marks)
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8 a. Explain the scan design techniques. (10 Marks)
b. Write a note on testability and testing. (10 Marks)