K Baba Hussain Vali

9916426443, babahussaink@gmail.com
Objective
To succeed in an environment of growth and excellence and obtain a challenging position. I
could certainly make contribution to your esteemed organization by using my skills and hard
work.
Technical Skills

Thorough knowledge of physical design flow from Net list to GDS-II.

Good understanding of methodologies of floor planning, place and route, timing closure,
upf and physical verification.
Experience in resolving various Block level issues related to STA, Noise, Place and
Route (P and R), DRC, UPF and EM issues.
Working experience in different nodes of 28 nm, 16ff and 10nm, can easily adapt to their
flow methodologies.
Tools and Languages:
IC Compiler 2 (ICC2), IC Compiler (ICC), ICV, Prime time (PT), StarRCXT, Caliber, TCL and scripting.

Total Work Experience (~approx. 5 years)

SENIOR SOC DESIGN ENGINEER INTEL INDIA PVT.LTD NOV.18.2014 TO PRESENT

Nokia Project: Worked on 4 blocks. Technology: 10nm Tools: ICC2, ICC and PT
Description:
Design 1 has 507 macros and ~2 million instances with power switch implementation and an
operating at a frequency of 614 MHz
Challenges: Timing closure issues and performed various ICC experiments at Implementation
level and provide feedback to customer to implement at synthesis level.
Design 2 has 407 macros and ~1.6 million instances with two sub blocks (Design 3 and Design 4)
embedded in them. Created the block abstraction flow in ICC2.
Additional tasks/Assignments:
Worked on always on buffering/voltage area approach for routing a single net in top level which
was operating at a different voltage.
Helped the entire team in ramping up the 10nm flow execution.
Mentored few interns and also currently tracking the block execution of few other team members.
Ericsson Project: Block level implementation of 4 blocks including DRC and power integrity checks.
Technology: 16ff Tools: ICC2, ICC and PT, ICV and Caliber
Description:
Design 1 has 196 macros and ~800k instances. Design 2 has 112 macros and ~900k instances.
Design 3 and Design 4 are ~400 k instances.
Challenges: I/O timing criticality. Lot of metal DRCs and DPT violations.
Additional tasks/Assignments:
Explored ICV auto fix drc flow and delivered presentation to the entire team which helped
overall turnaround time for DRC fixing.

DRC Cleanup for three timing critical blocks and a lot of effort has been put to clean the
DRC violations manually.
R & D ENGINEER IC DESIGN 1 LSI INDIA R & D PVT.LTD OCT.1.2013 TO NOV.17.2014
ZTE project: ICC implementation and timing closure of the blocks and worked till the metal eco phase of
the project.
Ericsson Project: Worked on Block closure of the 2 blocks. Initial exposure to a macro dominant design
and able to progress on parallel databases with minimal re-work and provide deliverables to top-level on-
time.
INTERN LSI INDIA R & D PVT.LTD JAN 7 2013 TO SEP.30.2013
Worked in a ZTE Project (BRAGI B0). Successfully executed the assigned tasks of block level
implementation.

Academic Profile

Year of
Class/Course Name of Institute Board/University CGPA/%
Passing
M.E Embedded
BITS PILANI BITS PILANI (RAJASTHAN) 2013 8.54
Systems
B.Tech in
Mahaveer Institute of
Electronics and JNTU Hyderabad 2010 73.09%
Science and Technology
Communication
Sri Raghavendra Junior Board of Intermediate Education
Class 11th and 12th 2006 93%
college , Andhra Pradesh
Sri Raghavendra Public Board of Secondary Education ,
2004 89%
SSC (Class 10th) School Andhra Pradesh

Declaration:
I, hereby declare that the above furnished information is true to the best of my knowledge and I
will be held responsible for any deviation from them at a later stage.

Place: Bangalore K Baba Hussain Vali