Numicro™ Family Nuc140 Data Sheet: Arm Cortex™-M0 32-Bit Microcontroller

NuMicro NUC140 Data Sheet
ARM Cortex-M0
32-BIT MICROCONTROLLER
NuMicro Family
NUC140 Data Sheet
The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
Publication Release Date: Jan. 2, 2012

-1- Revision V3.02
Contents
1 GENERAL DESCRIPTION ......................................................................................................... 7
2 FEATURES ................................................................................................................................. 8
2.1 NuMicro NUC140 Features Connectivity Line .......................................................... 8
3 PARTS INFORMATION LIST AND PIN CONFIGURATION .................................................... 12
3.1 NuMicro NUC140 Products Selection Guide ............................................................. 12
3.1.1 NuMicro NUC140 Connectivity Line Selection Guide ..................................................12
3.2 Pin Configuration .......................................................................................................... 13
3.2.1 NuMicro NUC140 Pin Diagram....................................................................................13
4 BLOCK DIAGRAM .................................................................................................................... 16
4.1 NuMicroNUC140 Block Diagram ............................................................................... 16
4.1.1 NuMicro NUC140 Block Diagram ................................................................................16
5 FUNCTIONAL DESCRIPTION.................................................................................................. 17
5.1 ARM Cortex-M0 Core .............................................................................................. 17
5.2 System Manager........................................................................................................... 19
5.2.1 Overview ........................................................................................................................19
5.2.2 System Reset .................................................................................................................19
5.2.3 System Power Distribution .............................................................................................20
5.2.4 System Memory Map......................................................................................................21
5.2.5 System Timer (SysTick) .................................................................................................23
5.2.6 Nested Vectored Interrupt Controller (NVIC) ..................................................................24
5.3 Clock Controller ............................................................................................................ 28
5.3.1 Overview ........................................................................................................................28
5.3.2 Clock Generator .............................................................................................................30
5.3.3 System Clock and SysTick Clock ...................................................................................31
5.3.4 Peripherals Clock ...........................................................................................................32
5.3.5 Power Down Mode Clock ...............................................................................................32
5.3.6 Frequency Divider Output...............................................................................................33
5.4 USB Device Controller (USB) ....................................................................................... 34
5.4.1 Overview ........................................................................................................................34
5.4.2 Features .........................................................................................................................34
5.5 General Purpose I/O (GPIO) ........................................................................................ 35
5.5.1 Overview ........................................................................................................................35
5.5.2 Features .........................................................................................................................35
5.6 I2C Serial Interface Controller (Master/Slave) (I2C) ...................................................... 36
5.6.1 Overview ........................................................................................................................36
5.6.2 Features .........................................................................................................................37
5.7 PWM Generator and Capture Timer (PWM) ................................................................ 38
5.7.1 Overview ........................................................................................................................38
5.7.2 Features .........................................................................................................................39
5.8 Real Time Clock (RTC)................................................................................................. 40

-2- Revision V3.02
5.8.1 Overview ........................................................................................................................40

5.8.2 Features .........................................................................................................................40
5.9 Serial Peripheral Interface (SPI) ................................................................................... 41
5.9.1 Overview ........................................................................................................................41
5.9.2 Features .........................................................................................................................41
5.10 Timer Controller (TMR)................................................................................................. 42
5.10.1 Overview ......................................................................................................................42
5.10.2 Features .......................................................................................................................42
5.11 Watchdog Timer (WDT)................................................................................................ 43
5.11.1 Overview ......................................................................................................................43
5.11.2 Features .......................................................................................................................45
5.12 UART Interface Controller (UART) ............................................................................... 46
5.12.1 Overview ......................................................................................................................46
5.12.2 Features .......................................................................................................................48
5.13 Controller Area Network (CAN) .................................................................................... 49
5.13.1 Overview ......................................................................................................................49
5.13.2 Features .......................................................................................................................49
5.14 PS/2 Device Controller (PS2D)..................................................................................... 50
5.14.1 Overview ......................................................................................................................50
5.14.2 Features .......................................................................................................................50
5.15 I2S Controller (I2S)......................................................................................................... 51
5.15.1 Overview ......................................................................................................................51
5.15.2 Features .......................................................................................................................51
5.16 Analog-to-Digital Converter (ADC) ............................................................................... 52
5.16.1 Overview ......................................................................................................................52
5.16.2 Features .......................................................................................................................52
5.17 Analog Comparator (CMP) ........................................................................................... 53
5.17.1 Overview ......................................................................................................................53
5.17.2 Features .......................................................................................................................53
5.18 PDMA Controller (PDMA) ............................................................................................. 54
5.18.1 Overview ......................................................................................................................54
5.18.2 Features .......................................................................................................................54
5.19 External Bus Interface (EBI) ......................................................................................... 55
5.19.1 Overview ......................................................................................................................55
5.19.2 Features .......................................................................................................................55
6 FLASH MEMORY CONTROLLER (FMC) ................................................................................ 56
6.1 Overview ....................................................................................................................... 56
6.2 Features........................................................................................................................ 56
7 ELECTRICAL CHARACTERISTICS......................................................................................... 57
7.1 Absolute Maximum Ratings .......................................................................................... 57
7.2 DC Electrical Characteristics ........................................................................................ 58
7.2.1 NuMicro NUC130/NUC140 DC Electrical Characteristics............................................58
-3- Revision V3.02
7.3 AC Electrical Characteristics ........................................................................................ 63

7.3.1 External 4~24 MHz High Speed Oscillator .....................................................................63
7.3.2 External 4~24 MHz High Speed Crystal .........................................................................63
7.3.3 External 32.768 kHz Low Speed Crystal ........................................................................64
7.3.4 Internal 22.1184 MHz High Speed Oscillator..................................................................64
7.3.5 Internal 10 kHz Low Speed Oscillator.............................................................................64
7.4 Analog Characteristics.................................................................................................. 65
7.4.1 Specification of 12-bit SARADC .....................................................................................65
7.4.2 Specification of LDO and Power management...............................................................66
7.4.3 Specification of Low Voltage Reset ................................................................................67
7.4.4 Specification of Brown-Out Detector...............................................................................67
7.4.5 Specification of Power-On Reset (5 V) ...........................................................................67
7.4.6 Specification of Temperature Sensor .............................................................................68
7.4.7 Specification of Comparator ...........................................................................................68
7.4.8 Specification of USB PHY ..............................................................................................69
7.5 Flash DC Electrical Characteristics .............................................................................. 70
7.6 SPI Dynamic Characteristics ........................................................................................ 71
8 PACKAGE DIMENSIONS ......................................................................................................... 73
8.1 100L LQFP (14x14x1.4 mm footprint 2.0mm) .............................................................. 73
8.2 64L LQFP (10x10x1.4mm footprint 2.0 mm) ................................................................ 74
8.3 48L LQFP (7x7x1.4mm footprint 2.0mm) ..................................................................... 75
9 REVISION HISTORY ................................................................................................................ 76

-4- Revision V3.02
Figures
Figure 3-1 NuMicro NUC100 Series selection code ................................................................... 12

Figure 3-5 NuMicro NUC140 LQFP 100-pin Pin Diagram .......................................................... 13
Figure 3-6 NuMicro NUC140 LQFP 64-pin Pin Diagram ............................................................ 14
Figure 3-7 NuMicro NUC140 LQFP 48-pin Pin Diagram ............................................................ 15
Figure 4-2 NuMicro NUC140 Block Diagram .............................................................................. 16
Figure 5-1 Functional Controller Diagram...................................................................................... 17
Figure 5-2 NuMicro NUC140 Power Distribution Diagram.......................................................... 20
Figure 5-4 Clock generator global view diagram ........................................................................... 29
Figure 5-5 Clock generator block diagram..................................................................................... 30
Figure 5-6 System Clock Block Diagram ....................................................................................... 31
Figure 5-7 SysTick Clock Control Block Diagram .......................................................................... 31
Figure 5-8 Clock Source of Frequency Divider .............................................................................. 33
Figure 5-9 Block Diagram of Frequency Divider ............................................................................ 33
Figure 5-10 I2C Bus Timing ............................................................................................................ 36
Figure 5-11 Timing of Interrupt and Reset Signal .......................................................................... 44
Figure 7-1 Typical Crystal Application Circuit ................................................................................ 64
Figure 7-2 SPI Master dynamic characteristics tiMINg .................................................................. 72
Figure 7-3 SPI Slave dynamic characteristics timing..................................................................... 72

-5- Revision V3.02
Tables
Table 1-1 Connectivity Supported Table.......................................................................................... 7
Table 5-1 Address Space Assignments for On-Chip Controllers................................................... 22
Table 5-2 Exception Model ............................................................................................................ 25
Table 5-3 System Interrupt Map..................................................................................................... 26
Table 5-4 Vector Table Format ...................................................................................................... 27
Table 5-5 Watchdog Timeout Interval Selection ............................................................................ 44
Table 5-6 UART Baud Rate Equation ............................................................................................ 46
Table 5-7 UART Baud Rate Setting Table ..................................................................................... 47

-6- Revision V3.02
1 GENERAL DESCRIPTION
The NuMicro NUC100 Series is 32-bit microcontrollers with embedded ARM Cortex-M0 core
for industrial control and applications which need rich communication interfaces. The Cortex-M0
is the newest ARM embedded processor with 32-bit performance and at a cost equivalent to
traditional 8-bit microcontroller. NuMicro NUC100 Series includes NUC100, NUC120, NUC130
and NUC140 product line.
The NuMicro NUC140 Connectivity Line with USB 2.0 full-speed and CAN functions embeds
Cortex-M0 core running up to 50 MHz with 32K/64K/128K-byte embedded flash, 4K/8K/16K-
byte embedded SRAM, and 4K-byte loader ROM for the ISP.. It also equips with plenty of
peripheral devices, such as Timers, Watchdog Timer, RTC, PDMA, UART, SPI, I2C, I2S, PWM
Timer, GPIO, LIN, CAN, PS/2, USB 2.0 FS Device, 12-bit ADC, Analog Comparator, Low Voltage
Reset Controller and Brown-out Detector.
Product Line UART SPI I2 C USB LIN CAN PS/2 I2 S
NUC100
NUC120
NUC130
NUC140
Table 1-1 Connectivity Supported Table

-7- Revision V3.02
2 FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 NuMicro NUC140 Features Connectivity Line

Core
ARM Cortex-M0 core runs up to 50 MHz
One 24-bit system timer
Supports low power sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Build-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V
Flash Memory
32K/64K/128K bytes Flash for program code
4KB flash for ISP loader
Support In-system program (ISP) application code update
512 byte page erase for flash
Configurable data flash address and size for 128KB system, fixed 4KB data flash for
the 32KB and 64KB system
Support 2 wire ICP update through SWD/ICE interface
Support fast parallel programming mode by external programmer
SRAM Memory
4K/8K/16K bytes embedded SRAM
Support PDMA mode
PDMA (Peripheral DMA)
Support 9 channels PDMA for automatic data transfer between SRAM and peripherals
Clock Control
Flexible selection for different applications
Built-in 22.1184 MHz high speed OSC for system operation
Trimmed to 1 % at +25 and VDD = 5 V
Trimmed to 3 % at -40 ~ +85 and VDD = 2.5 V ~ 5.5 V
Built-in 10 KHz low speed OSC for Watchdog Timer and Wake-up operation
Support one PLL, up to 50 MHz, for high performance system operation
External 4~24 MHz high speed crystal input for USB and precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
High driver and high sink IO mode support

-8- Revision V3.02
Timer
Support 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Support event counting function
Support input capture function
Watchdog Timer
Multiple clock sources
8 selectable time out period from 1.6ms ~ 26.0sec (depends on clock source)
WDT can wake-up from power down or idle mode
Interrupt or reset selectable on watchdog time-out
RTC
Support software compensation by setting frequency compensate register (FCR)
Support RTC counter (second, minute, hour) and calendar counter (day, month, year)
Support Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
Support wake-up function
PWM/Capture
Built-in up to four 16-bit PWM generators provide eight PWM outputs or four
complementary paired PWM outputs
Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-Zone generator for complementary paired PWM
Up to eight 16-bit digital Capture timers (shared with PWM timers) provide eight
rising/falling capture inputs
Support Capture interrupt
UART
Up to three UART controllers
UART ports with flow control (TXD, RXD, CTS and RTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Support IrDA (SIR) and LIN function
Support RS-485 9-bit mode and direction control.
Programmable baud-rate generator up to 1/16 system clock
Support PDMA mode
SPI
Up to four sets of SPI controller
Master up to 32 MHz, and Slave up to 10 MHz (chip working @ 5V)
Support SPI master/slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 1 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
2 slave/device select lines when it is as the master, and 1 slave/device select line
when it is as the slave
Support byte suspend mode in 32-bit transmission
Support PDMA mode
Support three wire, no slave select signal, bi-direction interface

-9- Revision V3.02
I2C
Up to two sets of I2C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Programmable clocks allow versatile rate control
Support multiple address recognition (four slave address with mask option)
2
I S
Interface with external audio CODEC
Operate as either master or slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Mono and stereo audio data supported
I2S and MSB justified data format supported
Two 8 word FIFO data buffers are provided, one for transmit and one for receive
Generates interrupt requests when buffer levels cross a programmable boundary
Support two DMA requests, one for transmit and one for receive
CAN 2.0
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1M bit/s
32 Message Objects
Each Message Object has its won identifier mask
Programmable FIFO mode (concatenation of Message Object)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Support power down wake-up function
PS/2 Device Controller
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
S/W override bus
USB 2.0 Full-Speed Device
One set of USB 2.0 FS Device 12Mbps
On-chip USB Transceiver
Provide 1 interrupt source with 4 interrupt events
Support Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provide 6 programmable endpoints
Include 512 Bytes internal SRAM as USB buffer
Provide remote wake-up capability
EBI (External bus interface) support (100-pin and 64-pin Package Only)
Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode
Support 8-/16-bit data width
- 10 - Revision V3.02
Support byte write in 16-bit data width mode

ADC
12-bit SAR ADC with 700K SPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion start by software programming or external input
Support PDMA Mode
Analog Comparator
Up to two analog comparators
External input or internal bandgap voltage selectable at negative node
Interrupt when compare result change
Power down wake-up
One built-in temperature sensor with 1 resolution
Brown-Out detector
With 4 levels: 4.5 V/3.8 V/2.7 V/2.2 V
Support Brown-Out Interrupt and Reset option
Low Voltage Reset
Threshold voltage levels: 2.0 V
Operating Temperature: -40~85
Packages:
All Green package (RoHS)
LQFP 100-pin / 64-pin / 48-pin

3 PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1 NuMicro NUC140 Products Selection Guide
3.1.1 NuMicro NUC140 Connectivity Line Selection Guide

ISP Connectivity
Data ISP
Part number APROM RAM Loader I/O Timer I2S Comp. PWM ADC RTC EBI Package
Flash ICP
ROM UART SPI 2
IC USB LIN CAN
NUC140LC1CN 32 KB 4 KB 4 KB 4 KB up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v LQFP48
NUC140LD2CN 64 KB 8 KB 4 KB 4 KB up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v LQFP48
NUC140LE3CN 128 KB 16 KB Definable 4 KB up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v LQFP48
NUC140RC1CN 32 KB 4 KB 4 KB 4 KB up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v LQFP64
NUC140RD2CN 64 KB 8 KB 4 KB 4 KB up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v LQFP64
NUC140RE3CN 128 KB 16 KB Definable 4 KB up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v LQFP64
NUC140VE3CN 128 KB 16 KB Definable 4 KB up to 76 4x32-bit 3 4 2 1 2 1 1 2 8 8x12-bit v v v LQFP100
NUC 1 0 0 - X X X X X
ARM-Based
32-bit Microcontroller Temperature
N: -40 ~ +85
E: -40 ~ +105
CPU core C: -40 ~ +125
1: Cortex-M0
5/7: ARM7 Reserve
9: ARM9
Function RAM Size

1: 4K
0: Advance Line
2: 8K
2: USB Line
3: 16K
3: Automotive Line
4: Connectivity Line
APROM Size
Package Type A: 8K
B: 16K
Y: QFN 36
C: 32K
L: LQFP 48
D: 64K
R: LQFP 64
E: 128K
V: LQFP 100
Figure 3-1 NuMicro NUC100 Series selection code

3.2 Pin Configuration
3.2.1 NuMicro NUC140 Pin Diagram

3.2.1.1 NuMicro NUC140 LQFP 100 pin
PA.15/PWM3/I2SMCLK
PA.12/PWM0/AD13
PA.13/PWM1/AD14
PA.14/PWM2/AD15
PA.3/ADC3/AD10
PA.2/ADC2/AD11
PA.1/ADC1/AD12
PA.4/ADC4/AD9
PC.10/MISO10
PC.11/MOSI10
PC.12/MISO11
PC.13/MOSI11
PC.9/SPICLK1
PC.8/SPISS10
PE.0/PWM6
PE.1/PWM7
PA.0/ADC0
ICE_DAT
ICE_CK
AVSS
PE.2
PE.3
PE.4
VDD
VSS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AD8/ADC5/PA.5 76 50 PB.9/SPISS11/TM1
AD7/ADC6/PA.6 77 49 PB.10/SPISS01/TM2
AD6/ADC7/SPISS21/PA.7 78 48 PB.11/TM3/PWM4
VREF 79 47 PE.5/PWM5/T1EX
AVDD 80 46 PE.6
SPISS20/PD.0 81 45 PC.0/SPISS00/I2SLRCLK
SPICLK2/PD.1 82 44 PC.1/SPICLK0/I2SBCLK
MISO20/PD.2 83 43 PC.2/MISO00/I2SDI
MOSI20/PD.3 84 42 PC.3/MOSI00/I2SDO
MISO21/PD.4 85 41 PC.4/MISO01
MOSI21/PD.5 86 40 PC.5/MOSI01
AD5/CPN0/PC.7
AD4/CPP0/PC.6
87
88
NUC140VxxCN 39
38
PD.15/TXD2
PD.14/RXD2
AD3/CPN1/PC.15 89 LQFP 100-pin 37 PD.7/CANTX0
AD2/CPP1/PC.14 90 36 PD.6/CANRX0
T0EX/INT1/PB.15 91 35 PB.3/CTS0/nWRH/T3EX
XT1_OUT 92 34 PB.2/RTS0/nWRL/T2EX
XT1_IN 93 33 PB.1/TXD0
/RESET 94 32 PB.0/RXD0
VSS 95 31 D+
VDD 96 30 D-
PS2DAT 97 29 VDD33
PS2CLK 98 28 VBUS
PVSS 99 27 PE.7
STADC/TM0/PB.8 100 26 PE.8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
VSS
AD0/CLKO/CPO0/
X32I
PE.15
PE.14
PE.13
SPISS31/INT0/PB.14
AD1/CPO1/PB.13
PB.12
SPISS30/PD.8
MISO30/PD.10
X32O
nRD/I2C1SCL/PA.11
nWR/I2C1SDA/PA.10
I2C0SCL/PA.9
I2C0SDA/PA.8
MOSI30/PD.11
MISO31/PD.12
MOSI31/PD.13
SPICLK3/PD.9
RXD1/PB.4
TXD1/PB.5
ALE/RTS1/PB.6
nCS/CTS1/PB.7
LDO
VDD
Figure 3-2 NuMicro NUC140 LQFP 100-pin Pin Diagram

3.2.1.2 NuMicro NUC140 LQFP 64 pin
PA.15/PWM3/I2SMCLK
PA.12/PWM0/AD13
PA.13/PWM1/AD14
PA.14/PWM2/AD15
PA.3/ADC3/AD10
PA.2/ADC2/AD11
PA.1/ADC1/AD12
PA.4/ADC4/AD9
PC.10/MISO10
PC.11/MOSI10
PC.9/SPICLK1
PC.8/SPISS10
PA.0/ADC0
ICE_DAT
ICE_CK
AVSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD8/ADC5/PA.5 49 32 PC.0/SPISS00/I2SLRCLK
AD7/ADC6/PA.6 50 31 PC.1/SPICLK0/I2SBCLK
AD6/ADC7PA.7 51 30 PC.2/MISO00/I2SDI
AVDD 52 29 PC.3/MOSI00/I2SDO
AD5/CPN0/PC.7 53 28 PD.15/TXD2
AD4/CPP0/PC.6 54 27 PD.14/RXD2
AD3/CPN1/PC.15 55 26 PD.7/CANTX0
AD2/CPP1/PC.14 56 NUC140RxxCN 25 PD.6/CANRX0
T0EX/INT1/PB.15 57
LQFP 64-pin 24 PB.3/CTS0/nWRH/T3EX
XT1_OUT 58 23 PB.2/RTS0/nWRL/T2EX
XT1_IN 59 22 PB.1/TXD0
/RESET 60 21 PB.0/RXD0
VSS 61 20 D+
VDD 62 19 D-
PVSS 63 18 VDD33
STADC/TM0/PB.8 64 17 VBUS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
SPISS31/INT0/PB.14
I2C0SDA/PA.8
AD1/CPO1/PB.13
AD0/CLKO/CPO0/PB.12
X32O
X32I
nWR/I2C1SDA/PA.10
I2C0SCL/PA.9
RXD1/PB.4
TXD1/PB.5
ALE/RTS1/PB.6
VDD
nCS/CTS1/PB.7
nRD/I2C1SCL/PA.11
LDO
VSS

3.2.1.3
CLKO/CPO0/PB.12 1 36 PA.4/ADC4
X32O 2 35 PA.3/ADC3
X32I 3 34 PA.2/ADC2
I2C1SCL/PA.11 4 33 PA.1/ADC1
NuMicro NUC140 LQFP 48 pin
I2C1SDA/PA.10 5 32 PA.0/ADC0
I2C0SCL/PA.9 6 31 AVSS
I2C0SDA/PA.8 7 30 ICE_CK
- 15 -
RXD1/PB.4 8 29 ICE_DAT
TXD1/PB.5 9 28 PA.12/PWM0
LDO 10 27 PA.13/PWM1
VDD 11 26 PA.14/PWM2
VSS 12 25 PA.15/PWM3/I2SMCLK


Revision V3.02
4 BLOCK DIAGRAM
4.1 NuMicroNUC140 Block Diagram
4.1.1 NuMicro NUC140 Block Diagram
FLASH Cortex-M0
PDMA
128KB 50MHz 10 kHz
P 32.768 kHz
L
L 22.1184 MHz
SRAM GPIO 4~24 MHz

ISP 4KB CLK_CTL
16KB A,B,C,D,E
2.5V~
LDO
PS2 RTC 5.5V
SPI 2/3 WDT SPI 0/1 12-bit ADC
Analog
I2C 1 Timer 0/1/ UART 0 -3M
Comparator
UART 1 -115K Timer 2/3 CAN 0 POR

Brown-out
UART 2 -115K PWM 4~7 PWM 0~3 LVR
USB-FS
I2S I2C 0 USBPHY
512BRAM
Peripherals with PDMA
Figure 4-1 NuMicro NUC140 Block Diagram

5 FUNCTIONAL DESCRIPTION
5.1 ARM Cortex-M0 Core

The Cortex-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex-M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 5-1 shows the functional controller of processor.
Cortex-M0 components
Cortex-M0 processor Debug
Interrupts Nested
Breakpoint
Vectored Cortex-M0
and
Interrupt Processor
Watchpoint
Controller Core
Unit
(NVIC)
Wakeup Debug
Interrupt Access
Debugger Port
Controller Bus Matrix
interface (DAP)
(WIC)
AHB-Lite Serial Wire or

interface JTAG debug port
Figure 5-1 Functional Controller Diagram
The implemented device provides:

z A low gate count processor that features:
The ARMv6-M Thumb instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
The system interface supports little-endian data accesses
The ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers

Low power sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
z NVIC that features:
32 external interrupt inputs, each with four levels of priority
Dedicated Non-Maskable Interrupt (NMI) input.
Support for both level-sensitive and pulse-sensitive interrupt lines
Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode
support.
z Debug support
Four hardware breakpoints.
Two watchpoints.
Program Counter Sampling Register (PCSR) for non-intrusive code profiling.
Single step and vector catch capabilities.
z Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory.
Single 32-bit slave port that supports the DAP (Debug Access Port).

5.2 System Manager
5.2.1 Overview
System management includes these following sections:
z System Resets
z System Memory Map
z System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
z System Timer (SysTick)
z Nested Vectored Interrupt Controller (NVIC)
z System Control registers
5.2.2 System Reset

The system reset can be issued by one of the below listed events. For these reset event flags can
be read by RSTSRC register.
z The Power-On Reset
z The low level on the /RESET pin
z Watchdog Time Out Reset
z Low Voltage Reset
z Brown-Out Detector Reset
z CPU Reset
z System Reset
System Reset and Power-On Reset all reset the whole chip including all peripherals. The
difference between System Reset and Power-On Reset is external crystal circuit and ISPCON.BS
bit. System Reset doesnt reset external crystal circuit and ISPCON.BS bit, but Power-On Reset
does.

5.2.3 System Power Distribution

In this chip, the power distribution is divided into three segments.
z Analog power from AVDD and AVSS provides the power for analog components
operation.
z Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 2.5 V power for digital operation and I/O pins.
z USB transceiver power from VBUS offers the power for operating the USB transceiver.
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
voltage level of the digital power (VDD). Figure 5-2 shows the power distribution of NuMicro
NUC140.
X32O
VDD
PVSS
VSS
X32I
Figure 5-2 NuMicro NUC140 Power Distribution Diagram

5.2.4 System Memory Map

NuMicro NUC100 Series provides 4G-byte addressing space. The memory locations assigned
to each on-chip controllers are shown in the following table. The detailed register definition,
memory space, and programming detailed will be described in the following sections for each on-
chip peripherals. NuMicro NUC100 Series only supports little-endian data format.
Address Space Token Controllers
Flash and SRAM Memory Space
0x0000_0000 0x0001_FFFF FLASH_BA FLASH Memory Space (128KB)
0x2000_0000 0x2000_3FFF SRAM_BA SRAM Memory Space (16KB)
0x6000_0000 0x6001_FFFF EXTMEM_BA External Memory Space (128KB)
AHB Controllers Space (0x5000_0000 0x501F_FFFF)
0x5000_0000 0x5000_01FF GCR_BA System Global Control Registers
0x5000_0200 0x5000_02FF CLK_BA Clock Control Registers
0x5000_0300 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers
0x5000_4000 0x5000_7FFF GPIO_BA GPIO Control Registers
0x5000_8000 0x5000_BFFF PDMA_BA Peripheral DMA Control Registers
0x5000_C000 0x5000_FFFF FMC_BA Flash Memory Control Registers
0x5001_0000 0x5001_03FF EBI_BA External Bus Interface Control Registers
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 0x4000_7FFF WDT_BA Watchdog Timer Control Registers
0x4000_8000 0x4000_BFFF RTC_BA Real Time Clock (RTC) Control Register
0x4001_0000 0x4001_3FFF TMR01_BA Timer0/Timer1 Control Registers
2
0x4002_0000 0x4002_3FFF I2C0_BA I C0 Interface Control Registers
0x4003_0000 0x4003_3FFF SPI0_BA SPI0 with master/slave function Control Registers
0x4004_0000 0x4004_3FFF PWMA_BA PWM0/1/2/3 Control Registers
0x4005_0000 0x4005_3FFF UART0_BA UART0 Control Registers
0x4006_0000 0x4006_3FFF USBD_BA USB 2.0 FS device Controller Registers

Address Space Token Controllers
0x400D_0000 0x400D_3FFF ACMP_BA Analog Comparator Control Registers
0x400E_0000 0x400E_FFFF ADC_BA Analog-Digital-Converter (ADC) Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4010_0000 0x4010_3FFF PS2_BA PS/2 Interface Control Registers
0x4011_0000 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers

2
0x4012_0000 0x4012_3FFF I2C1_BA I C1 Interface Control Registers
0x4014_0000 0x4014_3FFF PWMB_BA PWM4/5/6/7 Control Registers
0x4018_0000 0x4018_3FFF CAN0_BA CAN0 Bus Control Registers
0x401A_0000 0x401A_3FFF I2S_BA I2S Interface Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 0xE000_E0FF SCS_BA System Timer Control Registers
0xE000_E100 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers
0xE000_ED00 0xE000_ED8F SCS_BA System Control Registers
Table 5-1 Address Space Assignments for On-Chip Controllers

5.2.5 System Timer (SysTick)

The Cortex-M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value
Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the
counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on
reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer will count from the SYST_RVR value
rather than an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the documents ARM Cortex-M0 Technical
Reference Manual and ARM v6-M Architecture Reference Manual.

5.2.6 Nested Vectored Interrupt Controller (NVIC)

Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named as
Nested Vectored Interrupt Controller (NVIC). It is closely coupled to the processor kernel and
provides following features:
z Nested and Vectored interrupt support
z Automatic processor state saving and restoration
z Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in Handler
Mode. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running ones priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers PC, PSR, LR,
R0~R3, R12 to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports Tail Chaining which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports Late Arrival which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the documents ARM Cortex-M0 Technical
Reference Manual and ARM v6-M Architecture Reference Manual.

5.2.6.1 Exception Model and System Interrupt Map

Table 5-2 lists the exception model supported by NuMicro NUC100 Series. Software can set
four levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as 0 and the lowest priority is denoted as 3. The default priority
of all the user-configurable interrupts is 0. Note that priority 0 is treated as the fourth priority on
the system, after three system exceptions Reset, NMI and Hard Fault.
Exception Name Vector Number Priority
Reset 1 -3
NMI 2 -2
Hard Fault 3 -1
Reserved 4 ~ 10 Reserved
SVCall 11 Configurable
Reserved 12 ~ 13 Reserved
PendSV 14 Configurable
SysTick 15 Configurable
Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable
Table 5-2 Exception Model
Interrupt
Vector Number Interrupt
Source IP Interrupt description
Number (Bit in Interrupt Name
Registers)
0 ~ 15 - - - System exceptions
16 0 BOD_OUT Brown-Out Brown-Out low voltage detected interrupt
17 1 WDT_INT WDT Watchdog Timer interrupt
18 2 EINT0 GPIO External signal interrupt from PB.14 pin
19 3 EINT1 GPIO External signal interrupt from PB.15 pin
20 4 GPAB_INT GPIO External signal interrupt from PA[15:0]/PB[13:0]
21 5 GPCDE_INT GPIO External interrupt from PC[15:0]/PD[15:0]/PE[15:0]
22 6 PWMA_INT PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt
23 7 PWMB_INT PWM4~7 PWM4, PWM5, PWM6 and PWM7 interrupt
24 8 TMR0_INT TMR0 Timer 0 interrupt

Interrupt
Vector Number Interrupt
Source IP Interrupt description
Number (Bit in Interrupt Name
Registers)
28 12 UART02_INT UART0/2 UART0 and UART2 interrupt
29 13 UART1_INT UART1 UART1 interrupt
30 14 SPI0_INT SPI0 SPI0 interrupt
34 18 I2C0_INT I2C0 I2C0 interrupt
35 19 I2C1_INT I2C1 I2C1 interrupt
36 20 CAN0_INT CAN0 CAN0 interrupt
37 21 Reserved Reserved Reserved
39 23 USB_INT USBD USB 2.0 FS Device interrupt
40 24 PS2_INT PS/2 PS/2 interrupt
41 25 ACMP_INT ACMP Analog Comparator-0 or Comaprator-1 interrupt
42 26 PDMA_INT PDMA PDMA interrupt
43 27 I2S_INT I2S 2
I S interrupt
Clock controller interrupt for chip wake-up from

44 28 PWRWU_INT CLKC
power down state
45 29 ADC_INT ADC ADC interrupt
47 31 RTC_INT RTC Real time clock interrupt
Table 5-3 System Interrupt Map

5.2.6.2 Vector Table

When any interrupts is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset Description
0 SP_main The Main stack pointer
Vector Number Exception Entry Pointer using that Vector Number
Table 5-4 Vector Table Format
5.2.6.3 Operation Description

NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.

5.3 Clock Controller
5.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter power down mode until CPU sets the power down enable bit (PWR_DOWN_EN) and
Cortex-M0 core executes the WFI instruction. After that, chip enter power down mode and wait for
wake-up interrupt source triggered to leave power down mode. In the power down mode, the
clock controller turns off the external 4~24 MHz high speed crystal and internal 22.1184 MHz high
speed oscillator to reduce the overall system power consumption.

Figure 5-3 Clock generator global view diagram

5.3.2 Clock Generator

The clock generator consists of 5 clock sources which are listed below:
z One external 32.768 kHz low speed crystal
z One external 4~24 MHz high speed crystal
z One programmable PLL FOUT(PLL source consists of external 4~24 MHz high speed
crystal and internal 22.1184 MHz high speed oscillator)
z One internal 22.1184 MHz high speed oscillator
z One internal 10 kHz low speed oscillator
XTL32K_EN (PWRCON[1])
X32I
External
32.768 kHz
32.768 kHz
Crystal
X32O
XTL12M_EN (PWRCON[0])
4~24 MHz
XT_IN
External
4~24 MHz PLL_SRC (PLLCON[19])
Crystal
XT_OUT 0 PLL FOUT
PLL
OSC22M_EN (PWRCON[2]) 1
Internal
22.1184 MHz
Oscillator
22.1184 MHz
OSC10K_EN(PWRCON[3])
Internal
10 kHz
10 kHz
Oscillator
Figure 5-4 Clock generator block diagram

5.3.3 System Clock and SysTick Clock

The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
showed in Figure 5-5.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
111
10 kHz
011 CPUCLK
CPU
PLLFOUT
010 HCLK
1/(HCLK_N+1) AHB
32.768 kHz
001 HCLK_N (CLKDIV[3:0]) PCLK
APB
4~24 MHz
000
CPU in Power Down Mode
Figure 5-5 System Clock Block Diagram

The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is showed in Figure 5-6.
Figure 5-6 SysTick Clock Control Block Diagram

5.3.4 Peripherals Clock

The peripherals clock had different clock source switch setting which depends on the different
peripheral. Please refer the CLKSEL1 and CLKSEL2 register description in 5.3.7.
5.3.5 Power Down Mode Clock

When chip enters into power down mode, system clocks, some clock sources, and some
peripheral clocks will be disabled. Some clock sources and peripherals clock are still active in
power down mode.
For theses clocks which still keep active list below:
z Clock Generator
Internal 10 kHz low speed oscillator clock
External 32.768 kHz low speed crystal clock
z Peripherals Clock (When these IP adopt external 32.768 kHz low speed crystal or 10
kHz low speed oscillator as clock source)

5.3.6 Frequency Divider Output

This device is equipped a power-of-2 frequency divider which is composed by16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with
the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When write 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When write 0 to
DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
Figure 5-7 Clock Source of Frequency Divider
Figure 5-8 Block Diagram of Frequency Divider

5.4 USB Device Controller (USB)
5.4.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and support control/bulk/interrupt/
isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE.
Users need to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (USB_BUFSEGx).
There are 6 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB
controller will force the output of USB_DP and USB_DM to level low and its function is disabled.
After disable the DRVSE0 bit, host will enumerate the USB device again.
Reference: Universal Serial Bus Specification Revision 1.1
5.4.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature listing of this USB.
z Compliant with USB 2.0 Full-Speed specification
z Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS)
z Support Control/Bulk/Interrupt/Isochronous transfer type
z Support suspend function when no bus activity existing for 3 ms
z Provide 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 512 bytes buffer size
z Provide remote wake-up capability

5.5 General Purpose I/O (GPIO)
5.5.1 Overview
NuMicro NUC130/NUC140 has up to 80 General Purpose I/O pins can be shared with other
function pins; it depends on the chip configuration. These 80 pins are arranged in 5 ports named
with GPIOA, GPIOB, GPIOC, GPIOD and GPIOE. Each port equips maximum 16 pins. Each one
of the 80 pins is independent and has the corresponding register bits to control the pin mode
function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or quasi-bidirectional mode. After reset, the I/O type of all pins stay in quasi-bidirectional
mode and port data register GPIOx_DOUT[15:0] resets to 0x0000_FFFF. Each I/O pin equips a
very weakly individual pull-up resistor which is about 110 K~300 K for VDD is from 5.0 V to 2.5
V.
5.5.2 Features
z Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
z TTL/Schmitt trigger input selectable
z I/O pin can be configured as interrupt source with edge/level setting
z High driver and high sink IO mode support

5.6 I2C Serial Interface Controller (Master/Slave) (I2C)
5.6.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is
sampled during the high period of SCL; therefore, the SDA line may be changed only during the
low period of SCL and must be held stable during the high period of SCL. A transition on the SDA
line while SCL is high is interpreted as a command (START or STOP). Please refer to the Figure
5-9 for more detail I2C BUS Timing.
Figure 5-9 I2C Bus Timing
The devices on-chip I2C logic provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1
in I2CON should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL.
Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O pins are
used as I2C port, user must set the pins function to I2C in advance.

5.6.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus are:
z Master/Slave mode
z Bidirectional data transfer between masters and slaves
z Multi-master bus (no central master)
z Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
z Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
z Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
z Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
z External pull-up are needed for high output
z Programmable clocks allow versatile rate control
z Supports 7-bit addressing mode
z I2C-bus controllers support multiple address recognition ( Four slave address with
mask option)

5.7 PWM Generator and Capture Timer (PWM)
5.7.1 Overview
NuMicro NUC130/NUC140 has 2 sets of PWM group supports total 4 sets of PWM Generators
which can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4 complementary
PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) with 4
programmable dead-zone generators.
Each PWM Generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1,
1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-
counters for PWM period control, two 16-bit comparators for PWM duty control and one dead-
zone generator. The 4 sets of PWM Generators provide eight independent PWM interrupt flags
which are set by hardware when the corresponding PWM period down counter reaches zero.
Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM
interrupt. The PWM generators can be configured as one-shot mode to produce only one PWM
cycle signal or auto-reload mode to output PWM waveform continuously.
When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the
paired PWM period, duty and dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching zero. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM-
timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with PWM
Counter Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set
as one-shot mode, the down counter will stop and generate one interrupt request when it reaches
zero.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and
CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur.
Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18].
And capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, they are: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write
1 to clear PIIR to zero. If interrupt latency will take time T0 to finish, the capture signal mustnt
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For
example:
HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
So the maximum capture frequency will is 1/900ns 1000 kHz
5.7.2 Features
5.7.2.1 PWM function features:
z PWM group has two PWM generators. Each PWM generator supports one 8-bit
prescaler, one clock divider, two PWM-timers (down counter), one dead-zone
generator and two PWM outputs.
z Up to 16-bit resolution
z PWM Interrupt request synchronized with PWM period
z One-shot or Auto-reload mode PWM
z Up to 2 PWM group (PWMA/PWMB) to support 8 PWM channels or 4 PWM paired
channels
5.7.2.2 Capture Function Features:

z Timing control logic shared with PWM Generators
z Support 8 Capture input channels shared with 8 PWM output channels
z Each channel supports one rising latch register (CRLR), one falling latch register
(CFLR) and Capture interrupt flag (CAPIFx)

5.8 Real Time Clock (RTC)
5.8.1 Overview
Real Time Clock (RTC) controller provides user the real time and calendar message. The clock
source of RTC is from an external 32.768 kHz low speed crystal connected at pins X32I and
X32O (reference to pin descriptions) or from an external 32.768 kHz low speed oscillator output
fed at pin X32I. The RTC controller provides the time message (second, minute, hour) in Time
Loading Register (TLR) as well as calendar message (day, month, year) in Calendar Loading
Register (CLR). The data message is expressed in BCD format. It also offers alarm function that
user can preset the alarm time in Time Alarm Register (TAR) and alarm calendar in Calendar
Alarm Register (CAR).
The RTC controller supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt
has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by
TTR (TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR
and CAR, the alarm interrupt flag (RIIR.AIF) is set and the alarm interrupt is requested if the alarm
interrupt is enabled (RIER.AIER=1). Both RTC Time Tick and Alarm Match can cause chip wake-
up from power down mode if wake-up function is enabled (TWKE (TTR[3])=1).
5.8.2 Features
z There is a time counter (second, minute, hour) and calendar counter (day, month, year) for
user to check the time
z Alarm register (second, minute, hour, day, month, year)
z 12-hour or 24-hour mode is selectable
z Leap year compensation automatically
z Day of week counter
z Frequency compensate register (FCR)
z All time and calendar message is expressed in BCD code
z Support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2
and 1 second
z Support RTC Time Tick and Alarm Match interrupt
z Support wake-up chip from power down mode

5.9 Serial Peripheral Interface (SPI)
5.9.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which
operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-direction
interface. The NuMicro NUC130/NUC140 contains up to four sets of SPI controller performing a
serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial
conversion on data transmitted to a peripheral device. Each set of SPI controller can be set as a
master, it also can be configured as a slave device controlled by an off-chip master device.
This controller supports a variable serial clock for special application and it also supports 2-bit
transfer mode to connect 2 off-chip slave devices at the same time. The SPI controller also
supports PDMA function to access the data buffer.
5.9.2 Features
z Up to four sets of SPI controller
z Support master or slave mode operation
z Support 1-bit or 2-bit transfer mode
z Configurable bit length up to 32-bit of a transfer word and configurable word numbers up to 2
of a transaction, so the maximum bit length is 64-bit for each data transfer
z Provide burst mode operation, transmit/receive can be transferred up to two times word
transaction in one transfer
z Support MSB or LSB first transfer
z 2 device/slave select lines in master mode, but 1 device/slave select line in slave mode
z Support byte reorder function
z Support byte or word suspend mode
z Variable output serial clock frequency in master mode
z Support two programmable serial clock frequencies in master mode
z Support two channel PDMA request, one for transmitter and another for receiver
z Support three wire, no slave select signal, bi-direction interface
z The SPI clock rate can be configured to equal the system clock rate

5.10 Timer Controller (TMR)
5.10.1 Overview
The timer controller includes four 32-bit timers, TIMER0~TIMER3, which allows user to easily
implement a timer control for applications. The timer can perform functions like frequency
measurement, event counting, interval measurement, clock generation, delay timing, and so on.
The timer can generate an interrupt signal upon timeout, or provide the current value during
operation.
5.10.2 Features
z 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
z Independent clock source for each timer
z Provides one-shot, periodic, toggle and continuous counting operation modes
z Time out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit TCMP)
z Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
z 24-bit timer value is readable through TDR (Timer Data Register)
z Support event counting function to count the event from external pin
z Support input capture function to capture or reset counter value

5.11 Watchdog Timer (WDT)
5.11.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports another function to wake-up chip from power down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals. Table 5-5 show the
watchdog timeout interval selection and Figure 5-64 shows the timing of watchdog interrupt signal
and reset signal.
Setting WTE (WDTCR [7]) enables the watchdog timer and the WDT counter starts counting up.
When the counter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will
be set immediately to request a WDT interrupt if the watchdog timer interrupt enable bit WTIE is
set, in the meanwhile, a specified delay time (1024 * TWDT) follows the time-out event. User must
set WTR (WDTCR [0]) (Watchdog timer reset) high to reset the 18-bit WDT counter to avoid chip
from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by
hardware after WDT counter is reset. There are eight time-out intervals with specific delay time
which are selected by Watchdog timer interval select bits WTIS (WDTCR [10:8]). If the WDT
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (WTRF) high and reset chip. This reset will last 63 WDT clocks (TRST)
then chip restarts executing program from reset vector (0x0000_0000). WTRF will not be cleared
by Watchdog reset. User may poll WTRF by software to recognize the reset source. WDT also
provides wake-up function. When chip is powered down and the Watchdog Timer Wake-up
Function Enable bit (WDTR[4]) is set, if the WDT counter reaches the specific time interval
defined by WTIS (WDTCR [10:8]) , the chip is waken up from power down state. First example, if
WTIS is set as 000, the specific time interval for chip to wake up from power down state is 24 *
TWDT. When power down command is set by software, then, chip enters power down state. After
24 * TWDT time is elapsed, chip is waken up from power down state. Second example, if WTIS
(WDTCR [10:8]) is set as 111, the specific time interval for chip to wake up from power down
state is 218 * TWDT. If power down command is set by software, then, chip enters power down
state. After 218 * TWDT time is elapsed, chip is waken up from power down state. Notice if WTRE
(WDTCR [1]) is set to 1, after chip is waken up, software should clear the Watchdog Timer
counter by setting WTR(WDTCR [0]) to 1 as soon as possible. Otherwise, if the Watchdog Timer
counter is not cleared by setting WTR (WDTCR [0]) to 1 before time starting from waking up to
software clearing Watchdog Timer counter is over 1024 * TWDT , the chip is reset by Watchdog
Timer.

Timeout Interval WTR Timeout startingInterval

Interrupt Period
WTIS Selection (WDT_CLK=10 kHz)
TINT
TTIS MIN. TWTR ~ Max. TWTR
000 24 * TWDT 1024 * TWDT 1.6 ms ~ 104 ms
001 26 * TWDT 1024 * TWDT 6.4 ms ~ 108.8 ms

8
010 2 * TWDT 1024 * TWDT 25.6 ms ~ 128 ms
10
011 2 * TWDT 1024 * TWDT 102.4 ms ~ 204.8 ms
100 212 * TWDT 1024 * TWDT 409.6 ms ~ 512 ms
101 214 * TWDT 1024 * TWDT 1.6384 s ~ 1.7408 s
110 216 * TWDT 1024 * TWDT 6.5536 s ~ 6.656 s
111 218 * TWDT 1024 * TWDT 26.2144 s ~ 26.3168 s
Table 5-5 Watchdog Timeout Interval Selection
TWDT
TTIS TINT
INT
1024 * TWDT
TRST
RST Minimum TWTR 63 * TWDT
Maximum TWTR
TWDT : Watchdog Engine Clock Time Period

TTIS : Watchdog Timeout Interval Selection Period
TINT : Watchdog Interrupt Period
TRST : Watchdog Reset Period
TWTR : Watchdog Timeout Interval Period
Figure 5-10 Timing of Interrupt and Reset Signal

5.11.2 Features
z 18-bit free running counter to avoid chip from Watchdog timer reset before the delay time
expires.
z Selectable time-out interval (2^4 ~ 2^18) and the time out interval is 104 ms ~ 26.3168 s (if
WDT_CLK = 10 kHz).
z Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz.

5.12 UART Interface Controller (UART)

NuMicro NUC130/NUC140 provides up to three channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform
Normal Speed UART, besides, only UART0 and UART1 support flow control function.
5.12.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR Function, LIN
master/slave mode function and RS-485 mode functions. Each UART channel supports seven
types of interrupts including transmitter FIFO empty interrupt (INT_THRE), receiver threshold
level reaching interrupt (INT_RDA), line status interrupt (parity error or framing error or break
interrupt) (INT_RLS), receiver buffer time out interrupt (INT_TOUT), MODEM/Wake-up status
interrupt (INT_MODEM), Buffer error interrupt (INT_BUF_ERR) and LIN receiver break field
detected interrupt (INT_LIN_RX_BREAK). Interrupts of UART0 and UART2 share the interrupt
number 12 (vector number is 28); Interrupt number 13 (vector number is 29) only supports
UART1 interrupt. Refer to Nested Vectored Interrupt Controller chapter for System Interrupt Map.
The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO
(RX_FIFO) that reduces the number of interrupts presented to the CPU and the UART1~2 are
equipped 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU
can read the status of the UART at any time during the operation. The reported status information
includes the type and condition of the transfer operations being performed by the UART, as well
as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur
while receiving data. The UART includes a programmable baud rate generator that is capable of
dividing clock input by divisors to produce the serial clock that transmitter and receiver need. The
baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and BRD are defined in
Baud Rate Divider Register (UA_BAUD). Table 5-6 lists the equations in the various conditions
and Table 5-7 list the UART baud rate setting table.
Mode DIV_X_EN DIV_X_ONE Divider X BRD Baud rate equation
0 0 0 B A UART_CLK / [16 * (A+2)]
1 1 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8
2 1 1 Dont care A UART_CLK / (A+2), A must >=3
Table 5-6 UART Baud Rate Equation
System clock = internal 22.1184 MHz high speed oscillator
Mode0 Mode1 Mode2

Baud rate
Parameter Register Parameter Register Parameter Register
921600 x x A=0,B=11 0x2B00_0000 A=22 0x3000_0016
A=1,B=15 0x2F00_0001
460800 A=1 0x0000_0001 A=46 0x3000_002E
A=2,B=11 0x2B00_0002

System clock = internal 22.1184 MHz high speed oscillator
Mode0 Mode1 Mode2

Baud rate
Parameter Register Parameter Register Parameter Register
A=4,B=15 0x2F00_0004
230400 A=4 0x0000_0004 A=94 0x3000_005E
A=6,B=11 0x2B00_0006
A=10,B=15 0x2F00_000A
115200 A=10 0x0000_000A A=190 0x3000_00BE
A=14,B=11 0x2B00_000E
A=22,B=15 0x2F00_0016
57600 A=22 0x0000_0016 A=382 0x3000_017E
A=30,B=11 0x2B00_001E
A=62,B=8 0x2800_003E
38400 A=34 0x0000_0022 A=46,B=11 0x2B00_002E A=574 0x3000_023E
A=34,B=15 0x2F00_0022
A=126,B=8 0x2800_007E
19200 A=70 0x0000_0046 A=94,B=11 0x2B00_005E A=1150 0x3000_047E
A=70,B=15 0x2F00_0046
A=254,B=8 0x2800_00FE
9600 A=142 0x0000_008E A=190,B=11 0x2B00_00BE A=2302 0x3000_08FE
A=142,B=15 0x2F00_008E
A=510,B=8 0x2800_01FE
4800 A=286 0x0000_011E A=382,B=11 0x2B00_017E A=4606 0x3000_11FE
A=286,B=15 0x2F00_011E
Table 5-7 UART Baud Rate Setting Table
The UART0 and UART1 controllers support auto-flow control function that uses two low-level
signals, /CTS (clear-to-send) and /RTS (request-to-send), to control the flow of data transfer
between the UART and external devices (ex: Modem). When auto-flow is enabled, the UART is
not allowed to receive data until the UART asserts /RTS to external device. When the number of
bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the /RTS is de-
asserted. The UART sends data out when UART controller detects /CTS is asserted from external
device. If a valid asserted /CTS is not detected the UART controller will not send data out.
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
IrDA_EN (UA_FUN_SEL [1]) to enable IrDA function). The SIR specification defines a short-range
infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. The
maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR
Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and
receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer
delay between transmission and reception. This delay feature must be implemented by software.
The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN
mode is selected by setting the UA_FUN_SEL[1:0] to 01. In LIN mode, one start bit and 8-bit
data format with 1-bit stop bit are required in accordance with the LIN standard.
For NuMicro NUC100 Series, another alternate function of UART controllers is RS-485 9-bit
mode function, and direction control provided by RTS pin or can program GPIO (PB.2 for RTS0
and PB.6 for RTS1) to implement the function by software. The RS-485 mode is selected by
setting the UA_FUN_SEL register to select RS-485 function. The RS-485 driver control is
implemented using the RTS control signal from an asynchronous serial port to enable the RS-485
driver. In RS-485 mode, many characteristics of the RX and TX are same as UART.
5.12.2 Features
z Full duplex, asynchronous communications
z Separate receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data
payloads
z Support hardware auto flow control/flow control function (CTS, RTS) and programmable
RTS flow control trigger level (UART0 and UART1 support)
z Programmable receiver buffer trigger level
z Support programmable baud-rate generator for each channel individually
z Support CTS wake-up function (UART0 and UART1 support)
z Support 7-bit receiver buffer time out detection function
z UART0/UART1 can be served by the DMA controller
z Programmable transmitting data delay time between the last stop and the next start bit by
setting UA_TOR [DLY] register
z Support break error, frame error, parity error and receive / transmit buffer overflow detect
function
z Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
z Support IrDA SIR function mode
Support for 3-/16-bit duration for normal mode
z Support LIN function mode
Support LIN master/slave mode
Support programmable break generation function for transmitter
Support break detect function for receiver
z Support RS-485 function mode.
Support RS-485 9-bit mode
Support hardware or software direct enable control provided by RTS pin

5.13 Controller Area Network (CAN)
5.13.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface (Refer Error! Reference source not found.). The CAN Core performs
communication according to the CAN protocol version 2.0 part A and B. The bit rate can be
programmed to values up to 1MBit/s. For the connection to the physical layer, additional
transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the
Message RAM. All functions concerning the handling of messages are implemented in the
Message Handler. These functions include acceptance filtering, the transfer of messages
between the CAN Core and the Message RAM, and the handling of transmission requests as well
as the generation of the module interrupt.
The register set of the C_CAN can be accessed directly by the software through the module
interface. These registers are used to control/configure the CAN Core and the Message Handler
and to access the Message RAM.
5.13.2 Features
z Supports CAN protocol version 2.0 part A and B.
z Bit rates up to 1 MBit/s.
z 32 Message Objects.
z Each Message Object has its own identifier mask.
z Programmable FIFO mode (concatenation of Message Objects).
z Maskable interrupt.
z Disabled Automatic Re-transmission mode for Time Triggered CAN applications.
z Programmable loop-back mode for self-test operation.
z 16-bit module interfaces to the AMBA APB bus.
z Support wake-up function

5.14 PS/2 Device Controller (PS2D)
5.14.1 Overview
PS/2 device controller provides basic timing control for PS/2 communication. All communication
between the device and the host is managed through the CLK and DATA pins. Unlike PS/2
keyboard or mouse device controller, the received/transmit code needs to be translated as
meaningful code by firmware. The device controller generates the CLK signal after receiving a
request to send, but host has ultimate control over communication. DATA sent from the host to
the device is read on the rising edge and DATA sent from device to the host is change after rising
edge. A 16 bytes FIFO is used to reduce CPU intervention. S/W can select 1 to 16 bytes for a
continuous transmission.
5.14.2 Features
z Host communication inhibit and request to send detection
z Reception frame error detection
z Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
z Double buffer for data reception
z S/W override bus

5.15 I2S Controller (I2S)
5.15.1 Overview
The I2S controller consists of IIS protocol to interface with external audio CODEC. Two 8 word
deep FIFO for read path and write path respectively and is capable of handling 8 ~ 32 bit word
sizes. DMA controller handles the data movement between FIFO and memory.
5.15.2 Features
z I2S can operate as either master or slave
z Capable of handling 8-, 16-, 24- and 32-bit word sizes
z Mono and stereo audio data supported
z I2S and MSB justified data format supported
z Two 8 word FIFO data buffers are provided, one for transmit and one for receive
z Generates interrupt requests when buffer levels cross a programmable boundary
z Two DMA requests, one for transmit and one for receive

5.16 Analog-to-Digital Converter (ADC)
5.16.1 Overview
NuMicro NUC100 Series contains one 12-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 8 input channels. The A/D converter supports three
operation modes: single, single-cycle scan and continuous scan mode. The A/D converters can
be started by software and external STADC pin.
5.16.2 Features
z Analog input voltage range: 0~VREF
z 12-bit resolution and 10-bit accuracy is guaranteed
z Up to 8 single-end analog input channels or 4 differential analog input channels
z Maximum ADC clock frequency is 16 MHz
z Up to 700K SPS conversion rate
z Three operating modes
Single mode: A/D conversion is performed one time on a specified channel
Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the lowest numbered channel to the highest
numbered channel
Continuous scan mode: A/D converter continuously performs Single-cycle scan mode
until software stops A/D conversion
z An A/D conversion can be started by
Software write 1 to ADST bit
External pin STADC
z Conversion results are held in data registers for each channel with valid and overrun
indicators
z Conversion result can be compared with specify value and user can select whether to
generate an interrupt when conversion result is equal to the compare register setting
z Channel 7 supports 3 input sources: external analog voltage, internal bandgap voltage,
and internal temperature sensor output
z Support Self-calibration to minimize conversion error

5.17 Analog Comparator (CMP)
5.17.1 Overview
NuMicro NUC100 Series contains two comparators. The comparators can be used in a number
of different configurations. The comparator output is a logical one when positive input greater than
negative input, otherwise the output is a zero. Each comparator can be configured to cause an
interrupt when the comparator output value changes. The block diagram is shown in Error!
Reference source not found..
5.17.2 Features
z Analog input voltage range: 0~5.0 V
z Hysteresis function supported
z Two analog comparators with optional internal reference voltage input at negative end
z One interrupt vector for both comparators

5.18 PDMA Controller (PDMA)
5.18.1 Overview
NuMicro NUC130/NUC140 contains a peripheral direct memory access (PDMA) controller that
transfers data to and from memory or transfer data to and from APB devices. The PDMA has nine
channels of DMA (Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-Memory). For
each PDMA channel (PDMA CH0~CH8), there is one word buffer as transfer buffer between the
Peripherals APB devices and Memory.
Software can stop the PDMA operation by disable PDMA [PDMACEN]. The CPU can recognize
the completion of a PDMA operation by software polling or when it receives an internal PDMA
interrupt. The PDMA controller can increase source or destination address or fixed them as well.
Notice: The partial of NuMicro NUC130/NUC140 only has 1 PDMA channel (channel 0).
5.18.2 Features
z Support nine DMA channels. Each channel can support a unidirectional transfer
z AMBA AHB master/slave interface compatible, for data transfer and register read/write
z Support source and destination address increased mode or fixed mode
z Hardware channel priority. DMA channel 0 has the highest priority and channel 8 has the
lowest priority

5.19 External Bus Interface (EBI)
5.19.1 Overview
The NuMicro NUC130/NUC140 LQFP-64 and LQFP-100 package equips an external bus
interface (EBI) for external device used.
To save the connections between external device and this chip, EBI support address bus and
data bus multiplex mode. And, address latch enable (ALE) signal supported differentiate the
address and data cycle.
5.19.2 Features
External Bus Interface has the following functions:
z External devices with max. 64K-byte size (8-bit data width)/128K-byte (16-bit data width)
supported
z Variable external bus base clock (MCLK) supported
z 8-bit or 16-bit data width supported
z Variable data access time (tACC), address latch enable time (tALE) and address hold
time (tAHD) supported
z Address bus and data bus multiplex mode supported to save the address pins
z Configurable idle cycle supported for different access condition: Write command finish
(W2X), Read-to-Read (R2R)

6 FLASH MEMORY CONTROLLER (FMC)
6.1 Overview
NuMicro NUC100 Series equips with 128/64/32K bytes on chip embedded Flash for application
program memory (APROM) that can be updated through ISP procedure. In System Programming
(ISP) function enables user to update program memory when chip is soldered on PCB. After chip
power on, Cortex-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in
Config0. By the way, NuMicro NUC100 Series also provides additional DATA Flash for user, to
store some application dependent data before chip power off. For 128K bytes APROM device, the
data flash is shared with original 128K program memory and its start address is configurable and
defined by user application request in Config1. For 64K/32K bytes APROM device, the data flash
is fixed at 4K.
6.2 Features
z Run up to 50 MHz with zero wait state for continuous address read access
z 128/64/32KB application program memory (APROM)
z 4KB in system programming (ISP) loader program memory (LDROM)
z Configurable or fixed 4KB data flash with 512 bytes page erase unit
z Programmable data flash start address for 128K APROM device
z In System Program (ISP) to update on chip Flash

7 ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings

PARAMETER SYMBOL MIN. MAX UNIT
DC Power Supply VDDVSS -0.3 +7.0 V
Input Voltage VIN VSS-0.3 VDD+0.3 V
Oscillator Frequency 1/tCLCL 4 24 MHz
Operating Temperature TA -40 +85 C
Storage Temperature TST -55 +150 C
Maximum Current into VDD - 120 mA
Maximum Current out of VSS 120 mA
Maximum Current sunk by a I/O pin 35 mA
Maximum Current sourced by a I/O pin 35 mA
Maximum Current sunk by total I/O pins 100 mA
Maximum Current sourced by total I/O pins 100 mA
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of
the device.

7.2 DC Electrical Characteristics
7.2.1 NuMicro NUC130/NUC140 DC Electrical Characteristics

(VDD-VSS=3.3 V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER SYM. TEST CONDITIONS
MIN. TYP. MAX. UNIT
Operation voltage VDD 2.5 5.5 V VDD =2.5 V ~ 5.5 V up to 50 MHz
VSS
Power Ground -0.3 V
AVSS
LDO Output Voltage VLDO -10% 2.5 +10% V VDD > 2.7 V
Analog Operating Voltage AVDD 0 VDD V
Analog Reference Voltage Vref 0 AVDD V
VDD = 5.5 V@50 MHz,

IDD1 51 mA enable all IP and PLL, XTAL=12
MHz
VDD = 5.5 V@50 MHz,

IDD2 25 mA disable all IP and enable PLL,
Operating Current
XTAL=12 MHz
Normal Run Mode
VDD = 3 V@50 MHz,
@ 50 MHz
IDD3 48 mA enable all IP and PLL, XTAL=12
MHz
VDD = 3 V@50 MHz,

IDD4 23 mA disable all IP and enable PLL,
XTAL=12 MHz
Operating Current VDD = 5.5 V@12 MHz,

Normal Run Mode IDD5 19 mA enable all IP and disable PLL,
XTAL=12 MHz
@ 12 MHz
VDD = 5.5 V@12 MHz,
IDD6 7 mA disable all IP and disable PLL,
XTAL=12 MHz
VDD = 3 V@12 MHz,

IDD7 17 mA enable all IP and disable PLL,
XTAL=12 MHz

SPECIFICATION
MIN. TYP. MAX. UNIT
VDD = 3 V@12 MHz,

XTAL=12 MHz
VDD = 5 V@4 MHz,

XTAL=4 MHz
VDD = 5 V@4 MHz,

Operating Current
XTAL=4 MHz
Normal Run Mode
VDD = 3 V@4 MHz,
@ 4 MHz
XTAL=4 MHz
VDD = 3 V@4 MHz,

IDD12 2.5 mA disable all IP and disable PLL,
XTAL=4 MHz
VDD= 5.5 V@50 MHz,

IIDLE1 35 mA enable all IP and PLL, XTAL=12
MHz
VDD=5.5 V@50 MHz,

IIDLE2 15 mA disable all IP and enable PLL,
Operating Current
XTAL=12 MHz
Idle Mode
VDD = 3 V@50 MHz,
@ 50 MHz
IIDLE3 33 mA enable all IP and PLL, XTAL=12
MHz
VDD = 3 V@50 MHz,

IIDLE4 13 mA disable all IP and enable PLL,
XTAL=12 MHz
Operating Current VDD = 5.5 V@12 MHz,

Idle Mode IIDLE5 10 mA enable all IP and disable PLL,
XTAL=12 MHz
@ 12 MHz
VDD = 5.5 V@12 MHz,
IIDLE6 4.5 mA disable all IP and disable PLL,
XTAL=12 MHz
VDD = 3 V@12 MHz,

IIDLE7 9 mA enable all IP and disable PLL,
XTAL=12 MHz

SPECIFICATION
MIN. TYP. MAX. UNIT
VDD = 3 V@12 MHz,

XTAL=12 MHz
VDD = 5 V@4 MHz,

IIDLE9 4 mA enable all IP and disable PLL,
XTAL=4 MHz
VDD = 5 V@4 MHz,

Operating Current
XTAL=4 MHz
Idle Mode
VDD = 3 V@4 MHz,
@ 4 MHz
IIDLE11 3.5 mA enable all IP and disable PLL,
XTAL=4 MHz
VDD = 3 V@4 MHz,

XTAL=4 MHz
VDD = 5.5 V, RTC OFF, No load

IPWD1 12 A
@ Disable BOV function
VDD = 3.3 V, RTC OFF, No load
Standby Current IPWD2 9 A
Power down Mode VDD = 5.5 V, RTC run , No load
IPWD3 A
VDD = 3.3 V, RTC run , No load
IPWD4 A
Input Current PA, PB, PC,
PD, PE (Quasi-bidirectional IIN1 -50 -60 A VDD = 5.5 V, VIN = 0 V or VIN=VDD
mode)
Input Current at /RESET[1] IIN2 -55 -45 -30 A VDD = 3.3 V, VIN = 0.45 V
Input Leakage Current PA,
PB, PC, PD, PE ILK -2 - +2 A VDD = 5.5 V, 0<VIN<VDD
Logic 1 to 0 Transition Current

PA~PE (Quasi-bidirectional ITL [3] -650 - -200 A VDD = 5.5 V, VIN<2.0 V
mode)
Input Low Voltage PA, PB, -0.3 - 0.8 VDD = 4.5 V

PC, PD, PE (TTL input) VIL1 V
-0.3 - 0.6 VDD = 2.5 V
VDD VDD = 5.5 V

2.0 -
Input High Voltage PA, PB, +0.2
PC, PD, PE (TTL input) VIH1 V
VDD VDD =3.0 V
1.5 -
+0.2
Input Low Voltage PA, PB,
PC, PD, PE (Schmitt input) VIL2 -0.5 - 0.3 VDD V

SPECIFICATION
MIN. TYP. MAX. UNIT
Input High Voltage PA, PB,

PC, PD, PE (Schmitt input) VIH2 0.7 VDD - VDD+0.5 V
Hysteresis voltage of PA~PE

VHY 0.2 VDD V
(Schmitt input)
0 - 0.8 VDD = 4.5 V

Input Low Voltage XT1[*2] VIL3 V
0 - 0.4 VDD = 3.0 V
VDD VDD = 5.5 V

3.5 - V
[*2] +0.2
Input High Voltage XT1 VIH3
VDD VDD = 3.0 V
2.4 -
+0.2
Input Low Voltage X32I[*2] VIL4 0 - 0.4 v
[*2]
Input High Voltage X32I VIH4 1.7 2.5 V
Negative going threshold
VILS -0.5 - 0.3 VDD V
(Schmitt input), /RESET
Positive going threshold

VIHS 0.7 VDD - VDD+0.5 V
(Schmitt input), /RESET
ISR11 -300 -370 -450 A VDD = 4.5 V, VS = 2.4 V

Source Current PA, PB, PC,
PD, PE (Quasi-bidirectional ISR12 -50 -70 -90 A VDD = 2.7 V, VS = 2.2 V
Mode)
ISR13 -40 -60 -80 A VDD = 2.5 V, VS = 2.0 V
ISR21 -20 -24 -28 mA VDD = 4.5 V, VS = 2.4 V

Source Current PA, PB, PC,
PD, PE (Push-pull Mode) ISR22 -4 -6 -8 mA VDD = 2.7 V, VS = 2.2 V
ISR23 -3 -5 -7 mA VDD = 2.5 V, VS = 2.0 V
ISK11 10 16 20 mA VDD = 4.5 V, VS = 0.45 V

Sink Current PA, PB, PC, PD,
PE (Quasi-bidirectional and ISK12 7 10 13 mA VDD = 2.7 V, VS = 0.45 V
Push-pull Mode)
ISK13 6 9 12 mA VDD = 2.5 V, VS = 0.45 V
Brown-Out voltage with
BOV_VL [1:0] =00b VBO2.2 2.1 2.2 2.3 V

BOV_VL [1:0] =01b VBO2.7 2.6 2.7 2.8 V

BOV_VL [1:0] =10b VBO3.8 3.6 3.8 4.0 V

BOV_VL [1:0] =11b VBO4.5 4.3 4.5 4.7 V
Hysteresis range of BOD

voltage VBH 30 - 150 mV VDD = 2.5 V~5.5 V

SPECIFICATION
MIN. TYP. MAX. UNIT
Bandgap voltage VBG 1.20 1.26 1.32 V VDD = 2.5 V~5.5 V
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. Pins of PA, PB, PC, PD and PE can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD=5.5 V, 5he transition current reaches its maximum value when VIN approximates to 2 V.

7.3 AC Electrical Characteristics
7.3.1 External 4~24 MHz High Speed Oscillator

t CLCL
t CLCH
t CLCX
t CHCL t CHCX
Note: Duty cycle is 50%.
SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT
tCHCX Clock High Time 20 - - nS
tCLCX Clock Low Time 20 - - nS
tCLCH Clock Rise Time - - 10 nS
tCHCL Clock Fall Time - - 10 nS
7.3.2 External 4~24 MHz High Speed Crystal

PARAMETER CONDITION MIN. TYP. MAX. UNIT
Input clock frequency External crystal 4 12 24 MHz
Temperature - -40 - 85
VDD - 2.5 5 5.5 V
Operating current 12 MHz@ VDD = 5V - 1 - mA
7.3.2.1 Typical Crystal Application Circuits
CRYSTAL C1 C2 R
4 MHz ~ 24 MHz without without without

Figure 7-1 Typical Crystal Application Circuit
7.3.3 External 32.768 kHz Low Speed Crystal

Input clock frequency External crystal - 32.768 - kHz
Temperature - -40 - 85
VDD - 2.5 - 5.5 V
7.3.4 Internal 22.1184 MHz High Speed Oscillator

Supply voltage[1] - 2.5 - 5.5 V
Center Frequency - - 22.1184 - MHz
+25; VDD =5 V -1 - +1 %
Calibrated Internal Oscillator Frequency -40~+85;
-3 - +3 %
VDD=2.5 V~5.5 V
Operation Current VDD =5 V - 500 - uA
7.3.5 Internal 10 kHz Low Speed Oscillator

Supply voltage[1] - 2.5 - 5.5 V
Center Frequency - - 10 - kHz
+25; VDD =5 V -30 - +30 %

Calibrated Internal Oscillator Frequency -40~+85;
-50 - +50 %
VDD=2.5 V~5.5 V
Note: Internal operation voltage comes from LDO.

7.4 Analog Characteristics
7.4.1 Specification of 12-bit SARADC

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
- Resolution - - 12 Bit
DNL Differential nonlinearity error - 3 - LSB
INL Integral nonlinearity error - 4 - LSB
EO Offset error - 1 10 LSB
EG Gain error (Transfer gain) - 1 1.005 -
- Monotonic Guaranteed
FADC ADC clock frequency (AVDD=5V/3V) - - 16/8 MHz
FS Sample rate - - 700 K SPS
VDDA Supply voltage 3 - 5.5 V
IDD - 0.5 - mA
Supply current (Avg.)
IDDA - 1.5 - mA
VREF Reference voltage - VDDA - V
IREF Reference current (Avg.) - 1 - mA
VIN Input voltage 0 - VREF V

7.4.2 Specification of LDO and Power management

PARAMETER MIN. TYP. MAX. UNIT NOTE
Input Voltage 2.7 5 5.5 V VDD input voltage
Output Voltage -10% 2.5 +10% V VDD > 2.7 V
Temperature -40 25 85
Cbp - 1 - uF Resr=1ohm
Note:
1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and the
closest VSS pin of the device.
2. For ensuring power stability, a 1uF or higher capacitor must be connected between LDO pin and the closest VSS pin of
the device.

7.4.3 Specification of Low Voltage Reset

Operation voltage - 1.7 - 5.5 V
Quiescent current VDD=5.5 V - - 5 uA
Temperature - -40 25 85
Temperature=25 1.7 2.0 2.3 V
Threshold voltage Temperature=-40 - 2.4 - V
Temperature=85 - 1.6 - V
Hysteresis - 0 0 0 V
7.4.4 Specification of Brown-Out Detector

Operation voltage - 2.5 - 5.5 V
Quiescent current AVDD=5.5 V - - 125 A
BOV_VL[1:0]=11 4.3 4.5 4.7 V
BOV_VL [1:0]=10 3.6 3.8 4.0 V

Brown-out voltage
BOV_VL [1:0]=01 2.6 2.7 2.8 V
BOV_VL [1:0]=00 2.1 2.2 2.3 V
Hysteresis - 30 - 150 mV
7.4.5 Specification of Power-On Reset (5 V)

Reset voltage V+ - 2 - V
Quiescent current Vin>reset voltage - 1 - nA

7.4.6 Specification of Temperature Sensor

PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply voltage[1] 2.5 - 5.5 V
Temperature -40 - 125
Current consumption 6.4 - 10.5 uA
Gain -1.76 mV/
Offset Temp=0 720 mV
Note: Internal operation voltage comes from LDO.
7.4.7 Specification of Comparator

VDD - 2.4 3 5.5 V
VDD current 20 uA@VDD=3 V - 20 40 uA
Input offset voltage - - 5 15 mV
Output swing - 0.1 - VDD-0.1 V
Input common mode range - 0.1 - VDD-1.2 V
DC gain - - 70 - dB
@VCM=1.2 V and
Propagation delay - 200 - ns
VDIFF=0.1 V
20 mV@VCM=1 V
50 mV@VCM=0.1 V
Comparison voltage 50 mV@VCM=VDD-1.2 10 20 - mV
@10 mV for non-

hysteresis
One bit control

Hysteresis W/O and W. hysteresis - 10 - mV
@VCM=0.4 V ~ VDD-1.2 V
@CINP=1.3 V
Wake-up time - - 2 us
CINN=1.2 V

7.4.8 Specification of USB PHY

7.4.8.1 USB DC Electrical Characteristics
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VIH Input high (driven) 2.0 V
VIL Input low 0.8 V
VDI Differential input sensitivity |PADP-PADM| 0.2 V
Differential
VCM Includes VDI range 0.8 2.5 V
common-mode range
VSE Single-ended receiver threshold 0.8 2.0 V
Receiver hysteresis 200 mV
VOL Output low (driven) 0 0.3 V
VOH Output high (driven) 2.8 3.6 V
VCRS Output signal cross voltage 1.3 2.0 V
RPU Pull-up resistor 1.425 1.575 k
Termination Voltage for

VTRM 3.0 3.6 V
upstream port pull up (RPU)
ZDRV Driver output resistance Steady state drive* 10
CIN Transceiver capacitance Pin to GND 20 pF
*Driver output resistance doesnt include series resistor resistance.
7.4.8.2 USB Full-Speed Driver Electrical Characteristics
TFR Rise Time CL=50p 4 20 ns
TFF Fall Time CL=50p 4 20 ns
TFRFF Rise and fall time matching TFRFF=TFR/TFF 90 111.11 %
7.4.8.3 USB Power Dissipation
Standby 50 uA
IVDDREG
VDDD and VDDREG Supply Current
(Full Input mode uA
(Steady State)
Speed)
Output mode uA

7.5 Flash DC Electrical Characteristics

Nendu Endurance 10000 cycles[1]
Tret Retention time Temp=25 100 year
Terase Page erase time 20 40 ms
Tmass Mass erase time 40 50 60 ms
Tprog Program time 35 40 55 us
Vdd Supply voltage 2.25 2.5 2.75 V[2]
Idd1 Read current 14 mA
Idd2 Program/Erase current 7 mA
Ipd Power down current 10 uA

1. Number of program/erase cycles.
2. Vdd is source from chip LDO output voltage.
3. This table is guaranteed by design, not test in production.

7.6 SPI Dynamic Characteristics

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
SPI master mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor)
tDS Data setup time 4 2 - ns
tDH Data hold time 0 - - ns
tV Data output valid time - 7 11 ns
SPI master mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor)
tDS Data setup time 5 3 - ns
tDH Data hold time 0 - - ns
tV Data output valid time - 13 18 ns
SPI slave mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor)
tDS Data setup time 0 - - ns
tDH Data hold time 2*PCLK+4 - - ns
tV Data output valid time - 2*PCLK+11 2*PCLK+19 ns
SPI slave mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor)
tDS Data setup time 0 - - ns
tDH Data hold time 2*PCLK+6 - - ns
tV Data output valid time - 2*PCLK+19 2*PCLK+25 ns

Figure 7-2 SPI Master dynamic characteristics tiMINg
Figure 7-3 SPI Slave dynamic characteristics timing

8 PACKAGE DIMENSIONS
8.1 100L LQFP (14x14x1.4 mm footprint 2.0mm)

HD
D
A
A2
7 51 A1
7
50
HE E
100 26
L1
L
1 25
e c
b

Y
Controlling Dimension : Millimeters
Dimension in inch Dimension in mm
Symbol
Min Nom Max Min Nom Max
A 0.063 1.60
A1 0.002 0.05
A 0.053 0.055 0.057 1.35 1.40 1.45
2b
0.007 0.009 0.011 0.17 0.22 0.27
c 0.004 0.006 0.008 0.10 0.15 0.20
D 0.547 0.551 0.556 13.90 14.00 14.10
E 0.547 0.551 0.556 13.90 14.00 14.10
e 0.020 0.50
HD 0.622 0.630 0.638 15.80 16.00 16.20
HE 0.622 0.630 0.638 15.80 16.00 16.20
L 0.018 0.024 0.030 0.45 0.60 0.75
L1 0.039 1.00
y 0.004 0.10
0 7 0 7

8.2 64L LQFP (10x10x1.4mm footprint 2.0 mm)

Symbol
A 0.063 1.60
A1 0.002 0.006 0.05 0.15

A2 0.053 0.055 0.057 1.35 1.40 1.45
b 0.007 0.008 0.011 0.17 0.20 0.27

c 0.004 0.008 0.09 0.20
D 0.393 10.00
E 0.393 10.00
e 0.020 0.50
HD 0.472 12.00
HE 0.472 12.00
L 0.018 0.024 0.030 0.45 0.60 0.75
L1 0.039 1.00
y 0.004 0.10
0 0 3.5 7 0 3.5 7

8.3 48L LQFP (7x7x1.4mm footprint 2.0mm)

HD
D A
A2 A1
36 25
37 24
HE E
48 13
1 e b 12
c
SEATING PLANE
Y L
L1
Controlling dimension : Millimeters

Symbol
A
A1 0.002 0.004 0.006 0.05 0.10 0.15
A2 0.053 0.055 0.057 1.35 1.40 1.45
b 0.006 0.008 0.010 0.15 0.20 0.25

c 0.004 0.006 0.008 0.10 0.15 0.20
D 0.272 0.276 0.280 6.90 7.00 7.10
E 0.272 0.276 0.280 6.90 7.00 7.10

e 0.014 0.020 0.026 0.35 0.50 0.65
HD 0.350 0.354 0.358 8.90 9.00 9.10
HE 0.350 0.354 0.358 8.90 9.00 9.10
L 0.018 0.024 0.030 0.45 0.60 0.75
L1 0.039 1.00
Y 0.004 0.10
0 0 7 0 7

9 REVISION HISTORY
PAGE/
VERSION DATE DESCRIPTION
CHAP.
V1.00 March 1, 2010 - Preliminary version initial issued
V1.01 April 9, 2010 Ch4 Modify the block diagram
V1.02 May 31, 2010 7.2 Add operation current of DC characteristics
V1.03 Aug. 23, 2010 7.2 Modify operation current of DC characteristics
V2.00 Nov. 11, 2010 - Update low density and selection table
Revise from NUC140XXXAN or NUC140XXXBN to NUC140XXXCN

Revise NUC140 selection guide
V3.00 May 6, 2011 All
Revise Functional Description
Revise DC Electrical Characteristics
modify temperature sensor spec

Revise Pin description position for multi-function T2EX, T3EX, nRD, nWR
V3.01 June 22, 2011 -
update title of SPI Dynamic Characteristics
update BOD spec
1. Remove feature Dynamic priority changing for NVIC

V3.02 Jan. 2, 2012 - 2. Modify ADC analog characteristic spec
3. Remove SPI FIFO mode

Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, Insecure Usage.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customers risk, and in the event that third parties lay
claims to Nuvoton as a result of customers Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.


Numicro™ Family Nuc140 Data Sheet: Arm Cortex™-M0 32-Bit Microcontroller

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Numicro™ Family Nuc140 Data Sheet: Arm Cortex™-M0 32-Bit Microcontroller

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NuMicro NUC140 Data Sheet

The information described in this document is the exclusive intellectual property of

For additional information or questions, please contact: Nuvoton Technology Corporation.

Publication Release Date: Jan. 2, 2012

Publication Release Date: Jan. 2, 2012

5.8.1 Overview ........................................................................................................................40

7.3 AC Electrical Characteristics ........................................................................................ 63

Publication Release Date: Jan. 2, 2012

Figure 3-1 NuMicro NUC100 Series selection code ................................................................... 12

Publication Release Date: Jan. 2, 2012

Publication Release Date: Jan. 2, 2012

Product Line UART SPI I2 C USB LIN CAN PS/2 I2 S

Table 1-1 Connectivity Supported Table

Publication Release Date: Jan. 2, 2012

2.1 NuMicro NUC140 Features Connectivity Line

Publication Release Date: Jan. 2, 2012

Publication Release Date: Jan. 2, 2012

Support byte write in 16-bit data width mode

Publication Release Date: Jan. 2, 2012

3 PARTS INFORMATION LIST AND PIN CONFIGURATION

3.1 NuMicro NUC140 Products Selection Guide

3.1.1 NuMicro NUC140 Connectivity Line Selection Guide

NUC140LC1CN 32 KB 4 KB 4 KB 4 KB up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v LQFP48

NUC140LD2CN 64 KB 8 KB 4 KB 4 KB up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v LQFP48

NUC140LE3CN 128 KB 16 KB Definable 4 KB up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v LQFP48

NUC140RC1CN 32 KB 4 KB 4 KB 4 KB up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v LQFP64

NUC140RD2CN 64 KB 8 KB 4 KB 4 KB up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v LQFP64

NUC140RE3CN 128 KB 16 KB Definable 4 KB up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v LQFP64

NUC140VE3CN 128 KB 16 KB Definable 4 KB up to 76 4x32-bit 3 4 2 1 2 1 1 2 8 8x12-bit v v v LQFP100

Function RAM Size

Figure 3-1 NuMicro NUC100 Series selection code

Publication Release Date: Jan. 2, 2012

3.2 Pin Configuration

3.2.1 NuMicro NUC140 Pin Diagram

Figure 3-2 NuMicro NUC140 LQFP 100-pin Pin Diagram

Publication Release Date: Jan. 2, 2012

3.2.1.2 NuMicro NUC140 LQFP 64 pin

Figure 3-3 NuMicro NUC140 LQFP 64-pin Pin Diagram

Publication Release Date: Jan. 2, 2012

Figure 3-4 NuMicro NUC140 LQFP 48-pin Pin Diagram

Publication Release Date: Jan. 2, 2012

4.1 NuMicroNUC140 Block Diagram

4.1.1 NuMicro NUC140 Block Diagram

SRAM GPIO 4~24 MHz

SPI 2/3 WDT SPI 0/1 12-bit ADC

UART 1 -115K Timer 2/3 CAN 0 POR

Peripherals with PDMA

Figure 4-1 NuMicro NUC140 Block Diagram

Publication Release Date: Jan. 2, 2012

5.1 ARM Cortex-M0 Core

AHB-Lite Serial Wire or

Figure 5-1 Functional Controller Diagram

The implemented device provides:

Publication Release Date: Jan. 2, 2012

Publication Release Date: Jan. 2, 2012

5.2 System Manager

5.2.2 System Reset

Publication Release Date: Jan. 2, 2012

5.2.3 System Power Distribution

Figure 5-2 NuMicro NUC140 Power Distribution Diagram

Publication Release Date: Jan. 2, 2012

5.2.4 System Memory Map

Address Space Token Controllers