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1, JANUARY 2013
Manuscript received July 11, 2012; revised October 29, 2012; accepted
November 06, 2012. Date of publication December 19, 2012; date of current
II. DESIGN OF X-BAND CMOS T/R CHIPSET
version January 17, 2013. This work was supported in part by the National
Fig. 2 shows the circuit block diagram of the proposed
Research Foundation of Korea (NRF) Grant funded by the Korea government
(MEST) (No. 2009-0080362) and in part by the Dual Use Technology Program X-band CMOS bi-directional T/R chipset. The T/R chipset
of the DUTC. This paper is an expanded paper from the IEEE MTT-S Interna- is comprised of a BDGA, 5-bit attenuation block, and a 6-bit
tional Microwave Symposium, Montreal, QC, Canada, June 1722, 2012.
digital phase shifter. The proposed BDGA provides bi-direc-
S. H. Sim and L. Jeon are with the RFcore Co, Ltd., Seongnam-si,
Gyeonggi-do 463-760, Korea (e-mail: romantic@rfcore.com). tional amplification without two T/R switches. This results in
J.-G. Kim is with the Department of Electronic Engineering, Kwangwoon reducing the switches losses and the chip size. The attenuator
University, Seoul 139-701, Korea (e-mail: junggun@kw.ac.kr).
is split to three attenuation sections with two BDGAs that
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. compensate the insertion loss. The 6-bit digital phase shifter
Digital Object Identifier 10.1109/TMTT.2012.2227786 is implemented with DPDT switches to improve the insertion
Fig. 2. Circuit block diagram of the proposed X-band CMOS T/R chipset.
Fig. 4. Schematic of the switched T-type resistive attenuator with the phase
error correction capacitance of .
TABLE I
DESIGN PARAMETERS OF THE T-TYPE RESISTIVE ATTENUATORS
Fig. 7. Microphotograph of the X-band CMOS T/R chipset (chip size: 2.06 0.58 including pads).
Fig. 10. Measured noise figure of the bi-directional amplifier as varying the Fig. 12. Measured insertion losses of the phase shifter in major phase states.
operation temperatures.
Fig. 13. Measured phase characteristic of the phase shifter in major phase
states.
Fig. 11. Measured attenuation characteristics of the attenuation block in major
attenuation states.
Fig. 18. Measured transmission gain of the T/R chipset as varying the operation
Fig. 15. Measured input and output return losses of the T/R chipset. temperatures.
Fig. 16. Measured phase characteristics of the T/R chipset in all phase shift Fig. 19. Measured RMS phase and amplitude errors of the T/R chipset due to
states. the attenuator as varying the operating temperatures.
Fig. 20. Measured RMS phase and amplitude errors of the T/R chipset due to
Fig. 17. Measured output power and gain of the T/R chipset. the phase shifter as varying the operating temperatures.
The input and output return losses are db at 811 GHz Fig. 17. The total DC power consumption is around 154 mW
as shown in Fig. 15. Fig. 16 shows the measured phase charac- with 2.4 V supply voltage, which is only from three BDGAs.
teristics in all phase states at the reference state of 0 dB in the Fig. 18 shows the measured gain characteristics due to the
attenuation block. temperature variation from 20 to 80 at the supply voltage
The output P1dB of the T/R chipset is dBm and the of 2.4 V as well as the supply voltage variation from 2.16 V
saturated output power is dBm at 8.510.5 GHz as in to 2.64 V at 20 . The gain is decreased due to biasing the
568 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 1, JANUARY 2013
TABLE II
PERFORMANCE COMPARISON OF THE X-BAND PHASED-ARRAY T/R CHIPSETS
IV. CONCLUSION
This paper presents an X-band bi-directional T/R chipset in
a commercial 0.13 m CMOS technology. The low loss circuit
topologies such as the phase shifter using DPDT switches and
floating body techniques are incorporated in the T/R circuit. The
BDGA without T/R switches is proposed to provide the bi-di-
rectional operation with the moderate gain and compact size.
The circuit provides the phase shift of 360 with 5.625 , and the
attenuation of 31 dB with 1 dB with low RMS phase and am-
plitude errors. The gain is db at 8.510 GHz. The output
P1dB of the T/R chipset is dBm and the noise figure is
db at 8.510 GHz. The compact chip size of 2.08 0.58
is achieved with the low DC power consumption of 154
Fig. 22. Measured noise figure of the T/R chipset as varying the operation tem-
mW. The demonstrated X-band T/R circuit shows the compet-
peratures. itive RF performance except the output power, which can be
overcome by increasing the transistor size and the stages. The
proposed CMOS T/R chipset can be applied to the low cost
constant voltage at the gate of the BDGAs as increasing the X-band phased array antenna.
temperatures. This can be solved with PTAT bias circuits. The
gain variation due to the supply voltage variation is around 1 ACKNOWLEDGMENT
dB from 2.16 V to 2.64 V. As shown in Fig. 19, the measured The authors thank Prof. G. M. Rebeiz in University of Cali-
RMS amplitude error of db and the RMS phase error of fornia, San Diego, Prof. Y. Eo in Kwangwoon University, and
are achieved at the reference state of the phase shifter Prof. D. Baek in Chung-Ang University for the helpful discus-
as varying the temperature from 20 to 80 . In Fig. 20, the sion and encouragement.
SIM et al.: COMPACT X-BAND BI-DIRECTIONAL PHASED-ARRAY T/R CHIPSET 569
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