Sunteți pe pagina 1din 3

A 77 GHz CMOS Low Noise Amplier for Automotive Radar

Receiver
H.V. Le 1 , H.T. Duong 2 , C.M. Ta 1 , A.T. Huynh 1 , R. J. Evans 1,2 , E. Skadas 1,2
1
NICTA Victoria Research Laboratory, Department of Electrical & Electronic Engineering
University of Melbourne, Vic 3010, Australia
2
Department of Electrical & Electronic Engineering
University of Melbourne, Vic 3010, Australia
Email: hoangviet.le@nicta.com.au

Abstract This paper presents the design of a low noise


amplier (LNA) for automotive radar application operating
at 76-77 GHz. The LNA consists of 5 cascade common source
ampliers. The output of each stage is positioned close to
the gate of the next stage creating a LC resonance output
load, therefore complex interstage matching networks are RXW RXW
eliminated. Moreover, transmission lines (T Ls) are utilized
to create matching and load inductors. As a result, chip size LQ LQ
is signicantly reduced. The proposed LNA is implemented
in a 65 nm CMOS technology and measurement results show
11 dB voltage gain, and 7.8 dB noise gure (NF) while
dissipating 21.5 mA from 1.2 V supply. D E
Index Terms 77 GHz amplier, Automotive Radar,
CMOS, Common source, ESD, Low Noise Amplier.
Fig. 1. LNA topology: (a) Common source (CS), (b) Cascode.

I. I NTRODUCTION
Today, automotive radar systems are widely installed in radio receiver. With the motivation to develop a low cost,
many transportation vehicles to assist driving safely and high integration radar transceiver, this paper presents a
easily. These systems provide driver information about design of LNA operating in 76-77 GHz band.
distance between the vehicle and any other vehicles as
well as obstacles present on the road. The radar systems II. C IRCUITS D ESIGN
can take a further step into automatically controlling
the accelerate/brake system of the vehicles to avoid any The LNAs circuit topology is usually based on 3 com-
crashing accidents. The transceiver for such automotive mon structures: common gate (CG), common source (CS),
radar system operates in the band of 76-77 GHz frequency. and cascode amplier. However, to achieve high gain,
There has been work developing the radar transceiver two structures (shown in Fig. 1) can be adopted in LNA
for this operating frequency [1]-[3], and many of them design: CS and cascode topology. Although the cascode
are realized in SiGe Bipolar technology due to its robust, structure has the advantages of bandwidth improvement,
well-modeled, high frequency operating in comparison input-output isolation, and high output impedance, it is
with CMOS technology. However it is expensive and not adopted in this design since it has more transistors, i.e.
challenging to integrate SiGe Bipolar analog components more noise sources than the CS structure does. And at 77
with digital parts implemented CMOS. There is a desire GHz, the gain provided by the CS transistor of the cascode
to provide cheap radar system for every single vehicle structure is not high, as a result the noise contributed by
on the road. CMOS technology is attractive due to its the cascode transistor is signicant [1], [4], and [7]. So
low cost, higher level of integrability, and technology the CS topology is chosen for this LNA design.
scaling. However, in CMOS technology, the maximum The simplied schematic of the proposed 5 stage LNA
unity current gain frequency fT is much lower than that of is shown in Fig. 2. In the rst stage, the transistor (M1 )
bipolar technology. Therefore, developing the transceiver bias is set to optimal N Fmin current density, which is
working at 77 GHz in CMOS is very challenging [4]-[6]. 0.2 mA/m in this process. The optimal nger width to
In the receiver, the low noise amplier (LNA) is typically maximize fmax is chosen and equal to 1 m. Then the
the rst block and its performance dominates the receivers number of ngers is selected to match the optimal noise
sensitivity [4], [5]. Thus, it is a key block in building a impedance, which is 20 ngers [2]. Thus, the transistors

978-1-4673-2305-5/12/$31.00 2012
c IEEE 174
S+ S+ S+ S+ S+

7S /S
S+ 7LQ /*
S+ RXW
LQ 0 0 0 0 0
P P P P P
&SDG
=,1 7V /6 7V
S+ S+

Fig. 2. Proposed 5 stages 77 GHz LNA.

total width is 20 m with minimum channel length of T Ls in the proposed LNA (Fig. 2) is 80 Ohm except Tp .
65 nm. The degeneration and gate matching inductors LS Because Tp is also the ESD path for the input gate of
and LG are added to bring the input impedance of the CS the LNA, its width is made wider to reduce resistance, its
transistor M1 to match 50 Ohm source impedance. The characteristic impedance is 50 Ohm.
input impedance can be expressed by (1) [2], [8]:

  III. S IMULATION AND E XPERIMENT R ESULTS


T
ZIN = RG +RS +T LS +j LS + LG (1) The experimental test of the proposed LNA is performed
gm
on-wafer using probe station. Fig. 3 shows the simulated
where RG and RS are gate and source resistance respec- and measured S parameter the proposed LNA. The simu-
tively, T is the maximum unity current gain frequency, lated S11 , S22 , S21 and S12 at 76.5 GHz are -8 dB, -10 dB,
and gm is transconductance of M1 . 18 dB and -48 dB respectively. And the measured S11 , S22 ,
As expressed in (1), the values of LS and LG are chosen S21 and S12 at 76.5 GHz are -10 dB, -5 dB, 11 dB and -
to cancel out the imaginary part of Zin while making the 40 dB respectively. The simulation and measurement result
real part of Zin close to 50 Ohm. In this design LS and shapes are correlated, however the measured gain S21 is 7
LG are 100 pH and 130 pH and implemented by T Ls dB lower when compared to the simulated gain S21 . The
having lengths of 200 m and 250 m respectively. At reduction in measured gain is due to the worse measured
77 GHz the capacitive parasitics due to the input pad of output return loss S22 . Another reason for lower gain of
the LNA can not be neglected, it is presented by Cpad in the LNA is due to the mismatch of parasitics in simulation
Fig. 2. A shunt 70 pH Lp made of 250m Tp is added to extraction and real measurements. As can be seen in Fig.
cancel out this parasitic capacitance [9]. Furthermore, Tp 2 the proposed LNA is made of 5 cascade CS ampliers,
plays as electrostatic discharge (ESD) path to protect the which creates 4 interstage LC resonance nodes. Higher
gate of M1 . The output drain of the rst stage is placed RC parasitic in the fabricated chip comparing to the
very close to the gate of the second stage in layout. So simulated chip is expected, consequently the Q factor of
the 100 pH output load, made of 200 m T L, creates each LC resonance load of each stage is reduced leading to
a LC resonance circuit, which maximizes the gain and reduction in the gain of each stage [8]. The LNA consists
avoids complex interstage matching network. This design of 5 stage amplier, so slight reduction in each stage of
method is adopted to every stage of the proposed LNA. the LNA could lead to signicant reduction in the total
The second stage transistor M2 (Fig. 2) has the same gain of the LNA. One more reason is due to the metal ll
size and bias point as the transistor M1 of the rst stage. process of the foundry under input and output pads, higher
In the second stage, because the isolation of CS topology capacitive parasitics of the pads leads to higher signal loss.
is low, input impedance of the second stage will affect Therefore 7 dB gain deduction is within expectation. Fig.
the input impedance of the rst stage. Therefore, 40 pH 4 shows the simulated and measured NF of the proposed
degeneration inductor made of 80 m T L (Ts2 ) is adopted LNA. The simulated and measured NF at 75 GHz are
in this stage to obtain better input matching for the LNA 6.7 and 7.8 respectively. Due to the gain deduction, 1
[1]-[3], [7]. The output load of this stage is 75 pH inductor dB higher of NF can be explained. The simulated and
made of 150 m T L. measured 1 dB compression point of the proposed LNA
The last three stage are identical CS amplier and have are -29 dBm and -22 dBm respectively. Fig. 5 shows the
the same transistor size as well as bias point with the chip microphotograph where the chip size is 0.3 mm2
rst two stages. The detail component size of those stages including pads. The LNA, including bias circuit, consumes
are shown in Fig. 2. The characteristic impedance of all total 21.5 mA from 1.2 V supply. The performances of the

2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) 175


fabricated LNA is comparable to other works [3], [7], [10]
and can be adopted for automotive radar receiver.

LQ RXW

Fig. 5. Microphotograph of the fabricated LNA.

ACKNOWLEDGEMENT
NICTA is funded by the Australian Government as
represented by the Department of Broadband, Communica-
tions and the Digital Economy and the Australian Research
Council through the ICT Centre of Excellence program.

R EFERENCES
Fig. 3. Simulated and measured S parameters of the proposed
LNA. [1] L. Wang, J. Borngraeber, and W. Winkler, A Single-Ended
Fully Integrated SiGe 77/79 GHz Receiver for Automotive
Radar, IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 388-
391, Sep. 2006.
[2] S. T. Nicolson, K. H. K. Yau, S. Pruvost, V. Danelon,
P. Chevalier, P. Garcia, A. Chantre, B. Sautreuil, and S.
P. Voinigescu, A Low-Voltage SiGe BiCMOS 77-GHz
Automotive Radar Chipset, IEEE Trans. Microwave Theory
& Tech., vol. 56, no. 5, pp. 1092-1104, May. 2008.
[3] J. Lee, Y. A. Li, M. H. Hung, and S. J. Huang, A
fully-integrated 77-GHz FMCW radar transceiver in 65-nm
CMOS technology, IEEE J. Solid-State Circuits, vol. 45,
no. 12, pp. 27462756, Dec. 2010.
[4] C.M. Ta, B.N. Wicks, F. Zhang, B. Yang, Y. Mo, K. Wang,
Z. Liu, G. Felic, P. Nadagouda, T. Walsh, R.J. Evans, I.
Mareels, and E. Skadas, Issues in the Implementation of
a 60GHz Transceiver on CMOS, IEEE Int. Workshop on
RFIT. Dig., pp. 135-140, 2007.
[5] B.N. Wicks, C.M. Ta, F. Zhang, P. Nadagouda, B. Yang,
Z. Liu, Y. Mo, K. Wang, T. Walsh, G. Felic, R. J. Evans,
I. Mareels, and E. Skadas, 60-GHz direct-conversion
transceiver on 130-nm CMOS with integrated digital control
interface, IEEE Conf. MIC. Dig., pp. 41-44, 2009
[6] C. M. Ta, E. Skadas, and Robin J. Evans, A 60-GHz
CMOS Transmit/Receive Switch, IEEE RFIC Symp. Dig.,
pp. 725-728, 2007.
Fig. 4. Simulated and measured NF of the proposed LNA. [7] R. Berenguer, G. Liu, and Y. Xu, A Low Power 77
GHz Low Noise Amplier With an Area Efcient RF-
ESD Protection in 65 nm CMOS, IEEE Let. Microwave
& Wireless Components, vol. 20, no. 12, pp. 678-680, Dec,
2010.
[8] V.H. Le, S.K. Han, J.S. Lee, and S.G. Lee, Current-Reused
IV. C ONCLUSIONS Ultra Low Power, Low Noise LNA Mixer, IEEE Let.
Microwave & Wireless Components, vol. 11, no. 11, pp.
A 5 stage LNA realized in 65 nm CMOS for automotive 755-757, Nov. 2009.
[9] F. Zhang, B. Yang, E. Skadas, and W. Shieh, 5-75 GHz
radar is presented. The structure consideration and circuit common-gate subharmonic mixer in 65 nm CMOS, IET
design to optimize the performance operating in 77 GHz JOURNALS & MAGAZINES, vol. 46, no. 17, pp. 1203-1205,
band frequency is discussed. The experiment of the pro- 2010.
[10] Y. Kawano, T. Suzuki, M. Sato, T. Hirose, K. Joshin, A
posed LNA shows 11 dB voltage gain, 7.8 dB NF at the 77GHz Transceiver in 90nm CMOS, IEEE Int. Solid-State
middle of operating band of 77 GHz while dissipating 21.5 Circuits Conf. Dig., 2009.
mA from 1.2 V supply. The proposed LNA can be adopted
for automotive radar receiver.

176 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

S-ar putea să vă placă și