Us DSNBK 193 2604532510 HTG s5 Pcie QSFP Ug Aug2012 PDF

HTG-S510 User Manual
HiTech Global Stratix V PCI Express Ethernet Networking Development Platform
Version 1.0 August 2012

Copyright HiTech Global 2002-2012
1
www.HiTechGlobal.com
Disclaimer
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rights of others. HiTech Global reserves the right to make changes, at any time, in order to improve
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Revision History
Date Version Notes

8/22/2012 1.0 Preliminary
2
Table Of Contents
Chapter 1 - Introduction to Stratix V

1.1) Summary of Stratix V FPGA Features 4
1.2) Stratix V Family Serial I/O Protocol Support 5
Chapter 2 Development Platform Introduction
2.1) Introduction 8
2.2) Features & Block Diagram 8
2.3) FPGA Bank Assignment 10
2.4) Clock Distribution 12
2.5) PCI Express 13
2.6) DDR III Memory 18
2.7) QDR-II Interface 23
2.8) 10G/40F SFP+/QSFP+ Interfaces 29
2.9) FPGA Mezzanine Card Interfaces 31
2.10 Legacy Serial I/O Expansions 39
2.11) USB To UART Bridge 40
2.12) LEDs, GPIO Headers & Pushbuttons 41
2.12) Configuration
Chapter 3 FMC Modules
3
Chapter 1: Introduction to Altera Stratix V FPGAs
1.1) Overview
The Stratix V FPGA family includes four device variants:
Stratix V GX FPGAs with transceivers: Integrate up to 66 full-duplex, 14.1-Gbps transceivers and

up to 6 x72-bit DIMM DDR3 memory interfaces supporting 1,066 MHz
Stratix V GS FPGAs with enhanced digital signal processing (DSP) capabilities and transceivers:
Integrate up to 3,926 18x18, high-performance, variable-precision multipliers, 48 full-duplex,
14.1-Gbps transceivers , and up to 6 x72-bit DIMM DDR3 memory interfaces supporting 1,066
MHz
Stratix V GT FPGAs with transceivers: Integrate four 28-Gbps transceivers and 32 full-duplex,
12.5-Gbps transceivers with up to 4 x72-bit DIMM DDR3 memory interfaces supporting 1,066
MHz
Stratix V E FPGAs: Up to 950K logic elements (LEs), 52-megabit (Mb) RAM, 704 18x18 high-
performance, variable-precision multipliers, and 840 I/Os
Table (1) illustrates key features of the Stratix V family.
Feature Stratix V Stratix V Stratix V Stratix V

E GS GX GT
FPGA FPGA FPGA FPGA
High-performance adaptive logic modules 359,200 262,400 359,200 234,720

(ALMs)
Variable-precision DSP blocks (18x18) 704 3,926 798 512
M20K memory blocks 2,640 2,567 2,660 2,560
External memory interface
Partial reconfiguration
fPLL
Design security
SEU mitigation
PCI Express Gen3, Gen2, Gen1 hard IP - Up to 2 Up to 4 1

blocks
Embedded HardCopy Blocks and hard IP -
Transceivers - 14.1 Gbps / 14.1 Gbps / 28.05 Gbps /

48 66 4
12.5 Gbps /
32
Table (1) Summary of Stratix V FPGA Features
4
1.2) Stratix V Family Serial I/O Protocol Support
Serial transceivers of the Stratix V devices support different ranges of serial protocol standards. Table (2)
illustrates the supported standards and protocols.
Serial Protocols
V GX/GS V GT
10G-SDI
CEI-11G/SR/LR
CPRI
DisplayPort - -
Fibre Channel
HiGig2
IEEE 802.3ae
10GBASE-R
IEEE 802.3ba
10GBASE-KR
IEEE 802.3ba 40G
IEEE 802.3ba 100G
Interlaken (10G)
PCI ExpressGen3
QDR InfiniBand
QPI
SFP+
SFI-5.2
SONET OC-192
XFP
CEI-6G/SR/LR
CPRI
DDR-XAUI
DisplayPort - -
5
Fibre Channel
HiGig+
HyperTransportTM 3.0
Interlaken
OTU-2 (G.709)
OTU-3
OTU-4
PCI Express Gen2
SAS
SFI-4.2
SFI-5.1
SPI-4.2
SPI-5.1
3G-SDI
10-Gbps Ethernet XAUI
ASI
Basic Mode
CPRI
DDR-XAUI
DisplayPort - -
Fibre Channel
GbE
GPON
JESD204A
OBSAI
SAS
SATA
SDI SD/HD
6
SerialLite II
Serial RapidIO
SFP+
SFI-4.2
SGMII
SONET OC-3/OC-12/OC-48
SPI-4.2
SPI-5.1
V-by-One - -
Table (2) Stratix V Supported Serial Protocols
7
Chapter 2:Development Platform Introduction
2.1) Introduction
The HTG-S510 series are powered by Altera Stratix V GX and GS FPGA devices with different densities
and resources in KF40-F1517 package. Designed for high performance networking applications (i.e
configurable/customizable 40Gbps NIC, 40Gbps network analyzer, etc.), these platforms provide access to
two QSFP+ (40Gbps each) IEEE802.3ba compliant Ethernet ports, two SFP+ (10Gbps each) ports, 8-lane
PCI Express Gen 3 (64Gbps), one high-speed mezzanine connector (FMC), two additional board-to-board
connectors, two DDR3 SO-DIMMs (up to 8GB), and three independent QDRII memory components
(144Mb each).
Functionality of the HTG-S510 platforms are extended by one Vita57 compliant FMC (FPGA Mezzanine
Connector) port providing access to 80 LVDS I/Os and 8 additional Serial Transceivers. HiTech Global
offers wide range of FMC modules supporting these platforms for debugging, serial/parallel port
expansion, AD/DA, and even FPGA density enhancement. In addition, number of these platforms can be
connected together in series through the FMC ports in either PCI Express or Stand-Alone mode.
Supported by 10G / 40G Ethernet, PCI Express Gen3, DDR3, and QDR-II reference designs along with
PCI Express Linux/Windows drivers, the HTG-S510 minimizes engineering efforts for complex design
integration and verification.
2.2) Features
Altera Stratix V 5SGXA5, 5SGXA7, 5SGXA9, 5SGXAB, or 5SGSD5
x8 PCI Express Gen 3 edge connector (Root is also supported through HTG-FMC-PCIE module)
x2 QSFP+ IEEE802.3ba compliant Ethernet ports (40Gbps each)- or x8 SFP+ ports using the Avago
QSFP+ to SFP+ conversion module
x2 SFP+ Ports (10Gbps each)
x2 DDR3 SODIMM sockets supporting up to 16GB of memory
x3 144Mb QDR-II SRAMs
x1 FMC Connector (80 LVDS and 8 serial transceivers)
x2 high-speed board to board connectors
PCI Express or Stand-Alone mode operation
9.5" x 4.25"
8
Figure (1) Block Diagram & Placement
9
2.3) FPGA Bank Assignment

Common footprint of different Stratix V devices in KF40-F1517 package allows usage of the same PCB
multiple devices as shown by table (3)
Features 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB

Logic Elements (K) 340 420 490 622 840 952
Registers (K) 513 634 740 939 1,268 1,437
14.1-Gbps
36 36 36 36 36 36
Transceivers
PCIe hard IP Blocks 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 1, 2, or 4 1, 2, or 4
Fractional PLLs 20 24 28 28 28 28
M20K Memory Blocks 957 1,900 2,304 2,560 2,640 2,640
M20K Memory
19 37 45 50 52 52
(MBits)
Variable Precision
512 512 512 512 704 704
Multipliers (18x18)
Variable Precision
256 256 256 256 352 352
Multipliers (27x27)
DDR3 SDRAM x72
4 4 6 6 6 6
DIMM Interfaces
User I/Os, Full-Duplex LVDS, 14.1-Gbps Transceivers
Package 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB
KF40-F1517 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36H 696, 174, 36H
Table (3) Supported Stratix V Devices
The HTG-S510 platform is available with the GXA5, GXA7, GXA9, and GXAB Stratix V FPGAs.
Different FPGA speed grades are also supported.
FPGA bank allocation for each interface is illustrated by figure (2).
10
Figure (2): FPGA Bank Assignment
11
2.4) Clock Distribution

For effective utilization of the FPGA resources, the HTG-S510board is supported by different low-jitter
crystal oscillators. These clock components provide maximum performance and flexibility for different
interfaces. Figure (3) illustrates the entire boards clock diagram.
Figure (3): Clock Diagram
12
2.5) PCI Express

The PCI Express hard intellectual property (IP) block embeds the PCI Express protocol stack into the
Altera FPGA. The hard IP block includes the transceiver modules, physical layer, data link layer, and
transaction layer. In Stratix V GT, GX, and GS FPGAs, the hard IP block targets PCI Express Base
Specification Rev. 3.0, 2.0, and 1.1.
The HTG-S510 provides 8 lanes of PCI Express Gen3 end-point interface (8x8Gbps) through the edge
connectors and one embedded hard block PCI Express controller. The root interface can be achieved
through the FPGA Mezzanine Connector (FMC) and the HiTech Global PCIe FMC module (HTG-FMC-
PCIR-RC). Figure (4) illustrates high level block diagram of the PCI Express block.
Figure (4): Hard Block PCI Express Block Diagram
The interface provides data throughput of approximately about 64Gbps from a host PC to the FPGA and
vice versa. The lane configuration is selected through setting of the J6 jumper header. The factory default
setting is for the x8 configuration.
Table (4) and (5) illustrate FPGA pins assignment for the PCI Express signals.
A Side Signal Name FPGA Pin # FPGA Pin Name

A1 PCIE_PRSNT1_
A2 +12 VOLTS
A3 +12 VOLTS
A4 GND
A5 JTAG_TCK NC
A6 JTAG_TDI NC
A7 JTAG_TDO NC
A8 JTAG_TMS NC
A9 +3.3 VOLTS NC
A10 +3.3 VOLTS NC
A11 PCIE_PERST B32
A12 GND
13
PCIE_CLK0_L0_P,
A13 PCIE_REFCLKP AF34, AB34 PCIE_CLK2_L1_P
PCIE_CLK0_L0_N
A14 PCIE_REFCLKN AF35, AB35 PCIE_CLK2_L1_N
A15 GND
A16 PER0P AU36 PCIE_TX[0]_P
A17 PER0N AU37 PCIE_TX[0]_N
A18 GND
A19 RESERVED NC
A20 GND
A21 PER1P AR36 PCIE_TX[1]_P
A22 PER1N AR37 PCIE_TX[1]_N
A23 GND
A24 GND
A25 PER2P AN36 PCIE_TX[2]_P
A26 PER2N AN37 PCIE_TX[2]_N
A27 GND
A28 GND
A29 PER3P AL36 PCIE_TX[3]_P
A30 PER3N AL37 PCIE_TX[3]_N
A31 GND
A32 RESERVED NC
A33 RESERVED NC
A34 GND
A35 PER4P AH38 PCIE_TX[4]_P
A36 PER4N AH39 PCIE_TX[4]_N
A37 GND
A38 GND
A39 PER5P AF38 PCIE_TX[5]_P
A40 PER5N AF39 PCIE_TX[5]_N
A41 GND
A42 GND
A43 PER6P AD38 PCIE_TX[6]_P
A44 PER6N AD39 PCIE_TX[6]_N
A45 GND
A46 GND
A47 PER7P AB38 PCIE_TX[7]_P
A48 PER7N AB39 PCIE_TX[7]_N
A49 GND
Table (4): PCI Express Upstream Connections Summary -A Side
14
B Side Signal Name FPGA Pin # FPGA Pin Name

B1 +12 VOLTS
B2 +12 VOLTS
B3 +12 VOLTS
B4 GND
B5 SMCLK
B6 SMDAT
B7 GND
B8 +3.3 VOLTS
B9 JTAG_TRST_B
B10 +3.3 VOLTSAUX
B11 PCIE_WAKE_B A32
B12 RESERVED
B13 GND
B14 PET0P AV38 PCIE_RX[0]_P
B15 PET0N AV39 PCIE_RX[0]_N
B16 GND
B17 PCIE_PRSNT2_B
B18 GND
B19 PET1P AT38 PCIE_RX[1]_P
B20 PET1N AT39 PCIE_RX[1]_N
B21 GND
B22 GND
B23 PET2P AP38 PCIE_RX[2]_P
B24 PET2N AP39 PCIE_RX[2]_N
B25 GND
B26 GND
B27 PET3P AM38 PCIE_RX[3]_P
B28 PET3N AM39 PCIE_RX[3]_N
B29 GND
B30 RESERVED
B31 PCIE_PRSNT2_B
B32 GND
B33 PET4P AG36 PCIE_RX[4]_P
B34 PET4N AG37 PCIE_RX[4]_N
B35 GND
B36 GND
B37 PET5P AE36 PCIE_RX5]_P
B38 PET5N AE37 PCIE_RX[5]_N
B39 GND
B40 GND
B41 PET6P AC36 PCIE_RX[6]_P
B42 PET6N AC37 PCIE_RX[6]_N
B43 GND
B44 GND
B45 PET7P AA36 PCIE_RX[7]_P
B46 PET7N AA37 PCIE_RX[7]_N
B47 GND
15
B48 PCIE_PRSNT2_B
B49 GND
Table (5) PCI Express FPGA Pin Assignments
2.5.1) PCI Express Clock
Figure (5) illustrates different sources for creation of required clock for PCI Express interface.
Figure (5): PCI Express Clock Circuit
To clean the 100MHz clock provided by host PC or Server, the HTG-S510 board is equipped with IDT
PCI Express Jitter Attenuator chip (ICS871S1022). The ICS871S1022 is a PLL-based clock generator
specifically designed by IDT for PCI Express Clock Generation applications. The device generates
100MHz, 125MHz, 250MHz or 500MHz from either a 25MHz fundamental mode crystal or a 100MHz
recovered clock.
The ICS871S1022 has two modes of operation: (1) high frequency jitter attenuator and (2) high
performance clock synthesizer mode. When in jitter attenuator mode, the ICS871S1022 is able to both
suppress high frequency noise components and function as a frequency translator. Designed to receive a
jittery and noisy clock from an external source, the ICS871S1022 uses FemtoClock technology to clean
up the incoming clock and translate the frequency to one of the four common PCI Express frequencies.
When in synthesizer mode, the device is able to generate high performance SSC and non-SSC clocks from a
low cost external, 25MHz, fundamental mode crystal. The ICS871S1022 uses FemtoClock technology to
generate low noise clock outputs capable of providing the seed frequencies for the common PCI
Express link rates.
The first two differential outputs (PCIE_CLK0 and PCIE_CLK2) of the Jitter Attenuator chip are used as
reference clocks for the serial transceivers of the Stratix V FPGA use for the PHY interface. The 3rd output
is used as Global Clock to the FPGA (as shown by figure (6) , the OEB signal should be pulled up to 3.3V)
16
Figure (6): Jitter Attenuator Output Diagram
Table (6) illustrates different settings of the Jitter Attenuator chip for different output frequencies.
Inputs
Output Frequency
CLK_SEL Input Frequency (MHz) N1:N0 N Divider Value
(MHz)
0 100 00 5 100
0 100 01 4 125
0 100 10 2 250
0 100 11 1 500
Table (6): Jitter Attenuator Output Setting
17
2.6) DDR-III Interface

The HTG-S510 platform is populated with two 204-pin DDR3 SO-DIMMs (J11 and J16 on the board) each
supporting up to 8 GB of density. Each SODIMM operates independently with dedicated data and address
lines.
Table (7) illustrates FPGA pin assignment for the DDR3_A interface.
DDR3 A Signal Name (J11) FPGA Pin Number

DDR3_A_A[0] A16
DDR3_A_A[1] G17
DDR3_A_A[2] B16
DDR3_A_A[3] H17
DDR3_A_A[4] C16
DDR3_A_A[5] G16
DDR3_A_A[6] D18
DDR3_A_A[7] D16
DDR3_A_A[8] H16
DDR3_A_A[9] K18
DDR3_A_A[10] G18
DDR3_A_A[11] E18
DDR3_A_A[12] K16
DDR3_A_A[13] J18
DDR3_A_A[14] F18
DDR3_A_A[15] E17
DDR3_A_BA[0] E19
DDR3_A_BA[1] C18
DDR3_A_BA[2] L18
DDR3_A_CAS_N H19
DDR3_A_CK0_N J17
DDR3_A_CK0_P J16
DDR3_A_CK1_N A17
DDR3_A_CK1_P B17
DDR3_A_CKE0 L16
DDR3_A_CKE1 F17
DDR3_A_CS0_N B19
DDR3_A_CS1_N K19
DDR3_A_DM[0] N9
DDR3_A_DM[1] P10
DDR3_A_DM[2] C8
DDR3_A_DM[3] D10
DDR3_A_DM[4] D25
DDR3_A_DM[5] D27
DDR3_A_DM[6] N26
DDR3_A_DM[7] R27
DDR3_A_DQ[0] T9
DDR3_A_DQ[1] P8
DDR3_A_DQ[2] L8
DDR3_A_DQ[3] K9
DDR3_A_DQ[4] R9
DDR3_A_DQ[5] N8
DDR3_A_DQ[6] M8
DDR3_A_DQ[7] J9
18
DDR3_A_DQ[8] U9
DDR3_A_DQ[9] R10
DDR3_A_DQ[10] P11
DDR3_A_DQ[11] J11
DDR3_A_DQ[12] T10
DDR3_A_DQ[13] R11
DDR3_A_DQ[14] N10
DDR3_A_DQ[15] K10
DDR3_A_DQ[16] G8
DDR3_A_DQ[17] E8
DDR3_A_DQ[18] D9
DDR3_A_DQ[19] B8
DDR3_A_DQ[20] G9
DDR3_A_DQ[21] F8
DDR3_A_DQ[22] C9
DDR3_A_DQ[23] A8
DDR3_A_DQ[24] H10
DDR3_A_DQ[25] H11
DDR3_A_DQ[26] A10
DDR3_A_DQ[27] A11
DDR3_A_DQ[28] J10
DDR3_A_DQ[29] G11
DDR3_A_DQ[30] C10
DDR3_A_DQ[31] B11
DDR3_A_DQ[32] C24
DDR3_A_DQ[33] C25
DDR3_A_DQ[34] G24
DDR3_A_DQ[35] G25
DDR3_A_DQ[36] F24
DDR3_A_DQ[37] D24
DDR3_A_DQ[38] A25
DDR3_A_DQ[39] H25
DDR3_A_DQ[40] A26
DDR3_A_DQ[41] C27
DDR3_A_DQ[42] E27
DDR3_A_DQ[43] F26
DDR3_A_DQ[44] H26
DDR3_A_DQ[45] B26
DDR3_A_DQ[46] G26
DDR3_A_DQ[47] J26
DDR3_A_DQ[48] M26
DDR3_A_DQ[49] P25
DDR3_A_DQ[50] T25
DDR3_A_DQ[51] U25
DDR3_A_DQ[52] J25
DDR3_A_DQ[53] L26
DDR3_A_DQ[54] N25
DDR3_A_DQ[55] P26
DDR3_A_DQ[56] N27
DDR3_A_DQ[57] M27
DDR3_A_DQ[58] P28
DDR3_A_DQ[59] T27
DDR3_A_DQ[60] K27
19
DDR3_A_DQ[61] L27
DDR3_A_DQ[62] U27
DDR3_A_DQ[63] U26
DDR3_A_DQS_N[0] L9
DDR3_A_DQS_N[1] L11
DDR3_A_DQS_N[2] F9
DDR3_A_DQS_N[3] E11
DDR3_A_DQS_N[4] E25
DDR3_A_DQS_N[5] F27
DDR3_A_DQS_N[6] R26
DDR3_A_DQS_N[7] T28
DDR3_A_DQS_P[0] M9
DDR3_A_DQS_P[1] M11
DDR3_A_DQS_P[2] G10
DDR3_A_DQS_P[3] F11
DDR3_A_DQS_P[4] E24
DDR3_A_DQS_P[5] G27
DDR3_A_DQS_P[6] R25
DDR3_A_DQS_P[7] U28
DDR3_A_EVENT_N M18
DDR3_A_ODT0 A19
DDR3_A_ODT1 D19
DDR3_A_RAS_N C19
DDR3_A_RST_N M17
DDR3_A_WE_N G19
DDR3_AB_I2C_SCL U31
DDR3_AB_I2C_SDA T31
REF_CLK_DDR3_A P16
Table (7) DDR3 A SODIMM FPGA Pin Assignment
Table (8) illustrates FPGA pin assignment for the DDR3_B (J16) interface.
DDR3 B Signal Name (J16) FPGA Pin Number

DDR3_B_A[0] G22
DDR3_B_A[1] C21
DDR3_B_A[2] G21
DDR3_B_A[3] C20
DDR3_B_A[4] H20
DDR3_B_A[5] D21
DDR3_B_A[6] G20
DDR3_B_A[7] H22
DDR3_B_A[8] E23
DDR3_B_A[9] E20
DDR3_B_A[10] D22
DDR3_B_A[11] J21
DDR3_B_A[12] E21
DDR3_B_A[13] A23
DDR3_B_A[14] K21
DDR3_B_A[15] K22
DDR3_B_BA[0] A22
DDR3_B_BA[1] J22
DDR3_B_BA[2] F20
20
DDR3_B_CAS_N C22
DDR3_B_CK0_N A20
DDR3_B_CK0_P B20
DDR3_B_CK1_N G23
DDR3_B_CK1_P H23
DDR3_B_CKE0 F21
DDR3_B_CKE1 L20
DDR3_B_CS0_N J24
DDR3_B_CS1_N B23
DDR3_B_DM[0] N13
DDR3_B_DM[1] U14
DDR3_B_DM[2] F12
DDR3_B_DM[3] B14
DDR3_B_DM[4] C28
DDR3_B_DM[5] E31
DDR3_B_DM[6] P29
DDR3_B_DM[7] K30
DDR3_B_DQ[0] U11
DDR3_B_DQ[1] P13
DDR3_B_DQ[2] L12
DDR3_B_DQ[3] J12
DDR3_B_DQ[4] T12
DDR3_B_DQ[5] N12
DDR3_B_DQ[6] M12
DDR3_B_DQ[7] K12
DDR3_B_DQ[8] U13
DDR3_B_DQ[9] M14
DDR3_B_DQ[10] K15
DDR3_B_DQ[11] J15
DDR3_B_DQ[12] U12
DDR3_B_DQ[13] T13
DDR3_B_DQ[14] N14
DDR3_B_DQ[15] J14
DDR3_B_DQ[16] G12
DDR3_B_DQ[17] D12
DDR3_B_DQ[18] A13
DDR3_B_DQ[19] B13
DDR3_B_DQ[20] H13
DDR3_B_DQ[21] G13
DDR3_B_DQ[22] E12
DDR3_B_DQ[23] C12
DDR3_B_DQ[24] G14
DDR3_B_DQ[25] F15
DDR3_B_DQ[26] C14
DDR3_B_DQ[27] E14
DDR3_B_DQ[28] G15
DDR3_B_DQ[29] F14
DDR3_B_DQ[30] A14
DDR3_B_DQ[31] C15
DDR3_B_DQ[32] H28
DDR3_B_DQ[33] D28
DDR3_B_DQ[34] B28
DDR3_B_DQ[35] A29
21
DDR3_B_DQ[36] G28
DDR3_B_DQ[37] E28
DDR3_B_DQ[38] A28
DDR3_B_DQ[39] B29
DDR3_B_DQ[40] B31
DDR3_B_DQ[41] C30
DDR3_B_DQ[42] G30
DDR3_B_DQ[43] G31
DDR3_B_DQ[44] A31
DDR3_B_DQ[45] D30
DDR3_B_DQ[46] E30
DDR3_B_DQ[47] F30
DDR3_B_DQ[48] J28
DDR3_B_DQ[49] K28
DDR3_B_DQ[50] M29
DDR3_B_DQ[51] V29
DDR3_B_DQ[52] J29
DDR3_B_DQ[53] N28
DDR3_B_DQ[54] R29
DDR3_B_DQ[55] U29
DDR3_B_DQ[56] J30
DDR3_B_DQ[57] J31
DDR3_B_DQ[58] L31
DDR3_B_DQ[59] R31
DDR3_B_DQ[60] L30
DDR3_B_DQ[61] M30
DDR3_B_DQ[62] N30
DDR3_B_DQ[63] R30
DDR3_B_DQS_N[0] K13
DDR3_B_DQS_N[1] P14
DDR3_B_DQS_N[2] C13
DDR3_B_DQS_N[3] D15
DDR3_B_DQS_N[4] G29
DDR3_B_DQS_N[5] C31
DDR3_B_DQS_N[6] T30
DDR3_B_DQS_N[7] N31
DDR3_B_DQS_P[0] L13
DDR3_B_DQS_P[1] R14
DDR3_B_DQS_P[2] D13
DDR3_B_DQS_P[3] E15
DDR3_B_DQS_P[4] H29
DDR3_B_DQS_P[5] D31
DDR3_B_DQS_P[6] U30
DDR3_B_DQS_P[7] P31
DDR3_B_EVENT_N N23
DDR3_B_ODT0 K24
DDR3_B_ODT1 L24
DDR3_B_RAS_N J23
DDR3_B_RST_N N24
DDR3_B_WE_N B22
REF_CLK_DDR3_B M23
Table (8) DDR3 B SODIMM FPGA Pin Assignment
22
2.6.1) DDR3 Clock
Figure (7) illustrates clock generation through a 100MHz Oscillator and clock buffer.
Figure (7): DDR3 Clock Circuit
2.7) QDRII Memory

The HTG-S510 board is supported by three independent 8MX18 (144Mbit) Cypress QDRII SRAM
components (CY7C2663KV18). Each component is connected to the onboard Stratix V FPGA via separate
address and data lines.
The CY7C2663KV18 is a 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture.
Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the
write port to access the memory array. The read port has dedicated data outputs to support read
operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture
has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus
that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for
read and write addresses are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with DDR interfaces. Each address location is
associated with four 18-bit words that burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both input clocks (K and K), memory
bandwidth is maximized while simplifying system design by eliminating bus turn arounds.
The device has an ODT feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area, and simplify board routing. Depth
expansion is accomplished with port selects, which enables each port to operate independently.
All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs
pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Figure (8) illustrates block diagram of the QDR II device.
23
Figure (8): QDR-II Block Diagram
Additional product information is available at http://www.cypress.com/?mpn=CY7C2663KV18-450BZXC
Table (9), (10), and (11) illustrate pin assignment for each QDR-II SRAM component.
QDRII A Pin Number (U3) Signal Name FPGA Pin Number

P10 QDRII_A_D[0] AE9
N11 QDRII_A_D[1] AC10
M11 QDRII_A_D[2] AC9
K10 QDRII_A_D[3] AD9
J11 QDRII_A_D[4] AG9
G11 QDRII_A_D[5] AF10
E10 QDRII_A_D[6] AG10
D11 QDRII_A_D[7] AH9
C11 QDRII_A_D[8] AJ10
B3 QDRII_A_D[9] AM10
C3 QDRII_A_D[10] AN9
D2 QDRII_A_D[11] AP9
F3 QDRII_A_D[12] AR9
G2 QDRII_A_D[13] AT9
J3 QDRII_A_D[14] AW10
L3 QDRII_A_D[15] AV10
M3 QDRII_A_D[16] AU9
N2 QDRII_A_D[17] AU10
P11 QDRII_A_Q[0] AB12
M10 QDRII_A_Q[1] AC12
L11 QDRII_A_Q[2] AD12
K11 QDRII_A_Q[3] AE11
J10 QDRII_A_Q[4] AE10
F11 QDRII_A_Q[5] AL11
E11 QDRII_A_Q[6] AL12
C10 QDRII_A_Q[7] AW11
B11 QDRII_A_Q[8] AV11
B2 QDRII_A_Q[9] AR12
24
D3 QDRII_A_Q[10] AT12
E3 QDRII_A_Q[11] AN11
F2 QDRII_A_Q[12] AM11
G3 QDRII_A_Q[13] AF11
K3 QDRII_A_Q[14] AG12
L2 QDRII_A_Q[15] AJ12
N3 QDRII_A_Q[16] AK12
P3 QDRII_A_Q[17] AK11
R9 QDRII_A_A[0] AA12
R8 QDRII_A_A[1] AB13
B4 QDRII_A_A[2] AM14
B8 QDRII_A_A[3] AH13
C5 QDRII_A_A[4] AL13
C7 QDRII_A_A[5] AJ15
N5 QDRII_A_A[6] AE14
N6 QDRII_A_A[7] AE15
N7 QDRII_A_A[8] AD14
P4 QDRII_A_A[9] AG13
P5 QDRII_A_A[10] AF13
P7 QDRII_A_A[11] AC14
P8 QDRII_A_A[12] AA13
R3 QDRII_A_A[13] AH15
R4 QDRII_A_A[14] AG14
R5 QDRII_A_A[15] AF14
R7 QDRII_A_A[16] AC13
A9 QDRII_A_A[17] AK14
A3 QDRII_A_A[18] AN13
A10 QDRII_A_A[19] AJ13
A2 QDRII_A_A[20] AN12
A7 QDRII_A_A[21] AL14
A4 QDRII_A_WSP AM13
A8 QDRII_A_RPS AK15
H1 QDRII_A_DOFF AB10
B7 QDRII_A_BWS0 AH10
A5 QDRII_A_BWS1 AL10
A11 QDRII_A_CQ_P AR11
A1 QDRII_A_CQ_N AH12
R6 QDRII_A_ODT AB9
P6 QDRII_A_QVLD AE12
B6 QDRII_A_K_P AN10
A6 QDRII_A_K_N AP10
Table (9) QDRII A FPGA Pin Assignment
QDRII B Pin Number (U4) Signal Name FPGA Pin Number

P10 QDRII_B_D[0] AF16
N11 QDRII_B_D[1] AE16
M11 QDRII_B_D[2] AG16
K10 QDRII_B_D[3] AG17
J11 QDRII_B_D[4] AH16
G11 QDRII_B_D[5] AJ17
E10 QDRII_B_D[6] AK17
D11 QDRII_B_D[7] AL16
25
C11 QDRII_B_D[8] AL17

B3 QDRII_B_D[9] AV16
C3 QDRII_B_D[10] AU16
D2 QDRII_B_D[11] AV17
F3 QDRII_B_D[12] AW17
G2 QDRII_B_D[13] AU17
J3 QDRII_B_D[14] AM17
L3 QDRII_B_D[15] AN17
M3 QDRII_B_D[16] AT17
N2 QDRII_B_D[17] AR17
P11 QDRII_B_Q[0] AE19
M10 QDRII_B_Q[1] AG19
L11 QDRII_B_Q[2] AG18
K11 QDRII_B_Q[3] AP18
J10 QDRII_B_Q[4] AN18
F11 QDRII_B_Q[5] AT18
E11 QDRII_B_Q[6] AU18
C10 QDRII_B_Q[7] AW19
B11 QDRII_B_Q[8] AR19
B2 QDRII_B_Q[9] AP19
D3 QDRII_B_Q[10] AV19
E3 QDRII_B_Q[11] AM19
F2 QDRII_B_Q[12] AJ19
G3 QDRII_B_Q[13] AR18
K3 QDRII_B_Q[14] AJ18
L2 QDRII_B_Q[15] AH19
N3 QDRII_B_Q[16] AK18
P3 QDRII_B_Q[17] AL18
R9 QDRII_B_A[0] AW14
R8 QDRII_B_A[1] AV14
B4 QDRII_B_A[2] AR15
B8 QDRII_B_A[3] AR14
C5 QDRII_B_A[4] AL15
C7 QDRII_B_A[5] AP15
N5 QDRII_B_A[6] AA14
N6 QDRII_B_A[7] AG15
N7 QDRII_B_A[8] AT14
P4 QDRII_B_A[9] AB15
P5 QDRII_B_A[10] AD16
P7 QDRII_B_A[11] AV13
P8 QDRII_B_A[12] AU14
R3 QDRII_B_A[13] AB16
R4 QDRII_B_A[14] AC15
R5 QDRII_B_A[15] AD15
R7 QDRII_B_A[16] AW13
A9 QDRII_B_A[17] AP13
A3 QDRII_B_A[18] AU15
A10 QDRII_B_A[19] AP12
A2 QDRII_B_A[20] AA15
A7 QDRII_B_A[21] AN15
A4 QDRII_B_WSP AT15
A8 QDRII_B_RPS AN14
H1 QDRII_B_DOFF AE18
26
B7 QDRII_B_BWS0 AM16
A5 QDRII_B_BWS1 AW16
A11 QDRII_B_CQ_P AN19
A1 QDRII_B_CQ_N AF19
R6 QDRII_B_ODT AD17
P6 QDRII_B_QVLD AH18
B6 QDRII_B_K_P AN16
A6 QDRII_B_K_N AP16
Table (10) QDRII B FPGA Pin Assignment
QDRII C Pin Number (U5) Signal Name FPGA Pin Number

P10 QDRII_C_D[0] AF22
N11 QDRII_C_D[1] AD23
M11 QDRII_C_D[2] AD22
K10 QDRII_C_D[3] AE23
J11 QDRII_C_D[4] AE22
G11 QDRII_C_D[5] AG22
E10 QDRII_C_D[6] AV22
D11 QDRII_C_D[7] AV23
C11 QDRII_C_D[8] AW23
B3 QDRII_C_D[9] AP22
C3 QDRII_C_D[10] AU23
D2 QDRII_C_D[11] AT23
F3 QDRII_C_D[12] AN22
G2 QDRII_C_D[13] AN23
J3 QDRII_C_D[14] AH22
L3 QDRII_C_D[15] AM23
M3 QDRII_C_D[16] AM22
N2 QDRII_C_D[17] AJ22
P11 QDRII_C_Q[0] AR21
M10 QDRII_C_Q[1] AN20
L11 QDRII_C_Q[2] AP21
K11 QDRII_C_Q[3] AN21
J10 QDRII_C_Q[4] AM20
F11 QDRII_C_Q[5] AL22
E11 QDRII_C_Q[6] AK21
C10 QDRII_C_Q[7] AU21
B11 QDRII_C_Q[8] AW20
B2 QDRII_C_Q[9] AV20
D3 QDRII_C_Q[10] AU20
E3 QDRII_C_Q[11] AT20
F2 QDRII_C_Q[12] AT21
G3 QDRII_C_Q[13] AG21
K3 QDRII_C_Q[14] AD21
L2 QDRII_C_Q[15] AD20
N3 QDRII_C_Q[16] AE20
P3 QDRII_C_Q[17] AE21
R9 QDRII_C_A[0] AD24
R8 QDRII_C_A[1] AE24
B4 QDRII_C_A[2] AT26
B8 QDRII_C_A[3] AK24
C5 QDRII_C_A[4] AT27
27
C7 QDRII_C_A[5] AL24
N5 QDRII_C_A[6] AR24
N6 QDRII_C_A[7] AT24
N7 QDRII_C_A[8] AB24
P4 QDRII_C_A[9] AU25
P5 QDRII_C_A[10] AV26
P7 QDRII_C_A[11] AG24
P8 QDRII_C_A[12] AC24
R3 QDRII_C_A[13] AW25
R4 QDRII_C_A[14] AV25
R5 QDRII_C_A[15] AW26
R7 QDRII_C_A[16] AH24
A9 QDRII_C_A[17] AU26
A3 QDRII_C_A[18] AP27
A10 QDRII_C_A[19] AJ24
A2 QDRII_C_A[20] AR25
A7 QDRII_C_A[21] AU27
A4 QDRII_C_WSP AR27
A8 QDRII_C_RPS AN24
H1 QDRII_C_DOFF AP24
B7 QDRII_C_BWS0 AW22
A5 QDRII_C_BWS1 AR22
A11 QDRII_C_CQ_P AH21
A1 QDRII_C_CQ_N AR20
R6 QDRII_C_ODT AU24
P6 QDRII_C_QVLD AJ21
B6 QDRII_C_K_P AF23
A6 QDRII_C_K_N AG23
Table (11) QDRII C FPGA Pin Assignment
2.71) QDR-II Clock
Figure (9) illustrates clock generation through a 100MHz Oscillator and clock buffer.
Figure (9) QDRII Clock Generation
28
2.8) 10G/40G SFP+/QSFP+ Interfaces

Providing aggregated data rate of 100Gbps through the front panel ports, the HTG-S510 board is supported
by two QSFP+ (40Gbps each) and two SFP+ (10Gbps each) connectors. These ports are directly connected
to the serial transceivers of the Stratix V FPGA.
2.8.1) QSFP+ Ports
The HTG-S510 QSFP+ ports are connected to eight serial transceivers (L2-GBX) of the Stratix V FPGA
and clocked through either the on board 644.53125 MHz oscillators (U32) or external clock generator
(SMA connectors X3 and X4). Using the Avago Technologies AFBR-79E4Z D, each QSFP+ port can be
used as four SFP+ interfaces.
The AFBR-79E4Z -D is a Four-Channel Pluggable, Parallel, Fiber-Optic QSFP + Transceiver for

40GBASE-SR4 applications. This transceiver is a high performance module for short-range multi-lane data
communication and interconnect applications. It integrates four data lanes in each direction with 40 Gbps
aggregate bandwidth. Each lane can operate at 10.3125 Gbps up to 100 m using OM3 fiber. These
modules are designed to operate over multimode fiber systems using a nominal wavelength of 850nm. The
electrical interface uses a 38 contact edge type connector. The optical interface uses an 8 or 12 fiber
MTP (MPO) connector.
Table (12) illustrates FPGA pin assignment for the QSFP+ port 0 and 1.
Signal Name FPGA Pin Number QSFP+ Connector

QSFP0_IntL_F AU29 J2
QSFP0_ModPrsL_F AW29 J2
QSFP0_RST_N_F AP28 J2
QSFP0_RX1_N AV1 J2
QSFP0_RX1_P AV2 J2
QSFP0_RX2_N AT1 J2
QSFP0_RX2_P AT2 J2
QSFP0_RX3_N AP1 J2
QSFP0_RX3_P AP2 J2
QSFP0_RX4_N AM1 J2
QSFP0_RX4_P AM2 J2
QSFP0_SCL_F AN28 J2
QSFP0_SDA_F AR28 J2
QSFP0_TX1_N AU3 J2
QSFP0_TX1_P AU4 J2
QSFP0_TX2_N AR3 J2
QSFP0_TX2_P AR4 J2
QSFP0_TX3_N AN3 J2
QSFP0_TX3_P AN4 J2
QSFP0_TX4_N AL3 J2
QSFP0_TX4_P AL4 J2
QSFP1_IntL_F AL30 J3
QSFP1_ModPrsL_F AT30 J3
QSFP1_RST_N_F AK30 J3
QSFP1_RX1_N P39 J3
29
QSFP1_RX1_P P38 J3
QSFP1_RX2_N M39 J3
QSFP1_RX2_P M38 J3
QSFP1_RX3_N K39 J3
QSFP1_RX3_P K38 J3
QSFP1_RX4_N H39 J3
QSFP1_RX4_P H38 J3
QSFP1_SCL_F AM29 J3
QSFP1_SDA_F AL29 J3
QSFP1_TX1_N N37 J3
QSFP1_TX1_P N36 J3
QSFP1_TX2_N L37 J3
QSFP1_TX2_P L36 J3
QSFP1_TX3_N J37 J3
QSFP1_TX3_P J36 J3
QSFP1_TX4_N G37 J3
QSFP1_TX4_P G36 J3
Table (12) QSFP+ Ports FPGA Pin Assignment
2.8.2) SFP+ Ports
The HTG-S510 SFP+ ports are connected to two serial transceivers (L1-GBX) of the Stratix V FPGA and
clocked through either the on board 644.53125 MHz oscillators (U7). Table (13) illustrates FPGA pin
assignment for the SFP+ port 0 and 1.
Signal Name FPGA Pin Number QSFP+ Connector

SFP0_RX_LOS AG27 J5
SFP0_RX_N Y39 J5
SFP0_RX_P Y38 J5
SFP0_SCL_F AH27 J5
SFP0_SDA_F AJ27 J5
SFP0_TX_DIS_F AK27 J5
SFP0_TX_N W37 J5
SFP0_TX_P W36 J5
SFP1_RX_LOS AE27 J4
SFP1_RX_N T39 J4
SFP1_RX_P T38 J4
SFP1_SCL_F AC27 J4
SFP1_SDA_F AB27 J4
SFP1_TX_DIS_F AD27 J4
SFP1_TX_N R37 J4
SFP1_TX_P R36 J4
Table (13) SFP+ Ports FPGA Pin Assignment
30
2.9) FPGA Mezzanine Card Interfaces

The HTG-S510 development platform is populated with one 400-pin Samtec connectors for High Pin
Count (HPC) implementation of Vita 57 FPGA Mezzanine Card (FMC) interface. The Vita57 calls for
fixed location of IOs, Power, Clocks, and Jtag signals so any compliant module can easily be pluggable
into any compliant carrier card.
The HPC FMC A connector (J7- located on the left side of the board) provides access to 8 LVDS pairs,
8 Serial Transceivers , JTAG signals, 12V/3.3V/2.5VAdjustable supplies, I2C signals, and multiple
differential clocks.
HiTech Global provides the following add-on FMC modules with CX4, SFP, SFP+, SATA, SMA, RJ45,
PCI Express Root, and dual QSFP+.
x4 SFP/x4 SATA FMC Module (Part #: HTG-FMC-X4SFP-X4SATA)

x8 SMA FMC Module Part #: HTG-FMC-X8SMA)
x8 SMA/x33 LVDS FMC Module Part #: HTG-FMC-SMA-LVDS)
x2 SFP+ FMC Module (Part #: HTG-FMC-SFP-PLUS)
x1 PCIE Root FMC Module (Part #: HTG-FMC-PCIE-RC)
x4 RJ45 FMC Module (Part #: HTG-FMC-SGMII)
x2 CX4 FMC Module (Part #: HTG-FMC-2CX4)
x1 QSFP+/x2 SFP+ FMC Module (Part #: HTG-FMC-SFP-OC)
Quad SFP+ FMC Module connectors (Part #: HTG-FMC-X4SFP+)
Dual QSFP+ FMC Module connectors (Part #: HTG-FMC-X2QSFP+)
Additional information for the HiTech Globals FMC modules is available at:
http://www.hitechglobal.com/Accessories/FMC_Modules.htm
Figure (10) illustrates carrier card connector (Samtec Part # ASP-134486-01) grid labeling (used on the
HTG-S510board)
Figure (10): Carrier Card Connector Grid Labeling
Figure (11) illustrates FMC Module connector (Samtec Part # ASP-134488-01) grid labeling (used on the
HTG-FMC-xxx modules)
31
Figure (11): FMC Module Connector Grid Labeling
Table (14) illustrates the exact location of the fixed functional pins on a High Pin Count (HPC) FMC
connector.
K J H G F E D C B A
VREF_B_M2C GND VREF_A_M2C GND PG_M2C GND PG_C2M GND CLK_DIR GND
GND CLK3_BIDIR_P PRSNT_M2C_L CLK1_M2C_P GND HA01_P_CC GND DP0_C2M_P GND DP1_M2C_P
GND CLK3_BIDIR_N GND CLK1_M2C_N GND HA01_N_CC GND DP0_C2M_N GND DP1_M2C_N
CLK2_BIDIR_P GND CLK0_M2C_P GND HA00_P_CC GND GBTCLK0_M2C_P GND DP9_M2C_P GND
CLK2_BIDIR_N GND CLK0_M2C_N GND HA00_N_CC GND GBTCLK0_M2C_N GND DP9_M2C_N GND
GND HA03_P GND LA00_P_CC GND HA05_P GND DP0_M2C_P GND DP2_M2C_P
HA02_P HA03_N LA02_P LA00_N_CC HA04_P HA05_N GND DP0_M2C_N GND DP2_M2C_N
HA02_N GND LA02_N GND HA04_N GND LA01_P_CC GND DP8_M2C_P GND
GND HA07_P GND LA03_P GND HA09_P LA01_N_CC GND DP8_M2C_N GND
HA06_P HA07_N LA04_P LA03_N HA08_P HA09_N GND LA06_P GND DP3_M2C_P
HA06_N GND LA04_N GND HA08_N GND LA05_P LA06_N GND DP3_M2C_N
GND HA11_P GND LA08_P GND HA13_P LA05_N GND DP7_M2C_P GND
HA10_P HA11_N LA07_P LA08_N HA12_P HA13_N GND GND DP7_M2C_N GND
HA10_N GND LA07_N GND HA12_N GND LA09_P LA10_P GND DP4_M2C_P
GND HA14_P GND LA12_P GND HA16_P LA09_N LA10_N GND DP4_M2C_N
HA17_P_CC HA14_N LA11_P LA12_N HA15_P HA16_N GND GND DP6_M2C_P GND
HA17_N_CC GND LA11_N GND HA15_N GND LA13_P GND DP6_M2C_N GND
GND HA18_P GND LA16_P GND HA20_P LA13_N LA14_P GND DP5_M2C_P
HA21_P HA18_N LA15_P LA16_N HA19_P HA20_N GND LA14_N GND DP5_M2C_N
HA21_N GND LA15_N GND HA19_N GND LA17_P_CC GND GBTCLK1_M2C_P GND
GND HA22_P GND LA20_P GND HB03_P LA17_N_CC GND GBTCLK1_M2C_N GND
HA23_P HA22_N LA19_P LA20_N HB02_P HB03_N GND LA18_P_CC GND DP1_C2M_P
HA23_N GND LA19_N GND HB02_N GND LA23_P LA18_N_CC GND DP1_C2M_N
GND HB01_P GND LA22_P GND HB05_P LA23_N GND DP9_C2M_P GND
HB00_P_CC HB01_N LA21_P LA22_N HB04_P HB05_N GND GND DP9_C2M_N GND
HB00_N_CC GND LA21_N GND HB04_N GND LA26_P LA27_P GND DP2_C2M_P
GND HB07_P GND LA25_P GND HB09_P LA26_N LA27_N GND DP2_C2M_N
HB06_P_CC HB07_N LA24_P LA25_N HB08_P HB09_N GND GND DP8_C2M_P GND
HB06_N_CC GND LA24_N GND HB08_N GND TCK GND DP8_C2M_N GND
GND HB11_P GND LA29_P GND HB13_P TDI SCL GND DP3_C2M_P
HB10_P HB11_N LA28_P LA29_N HB12_P HB13_N TDO SDA GND DP3_C2M_N
HB10_N GND LA28_N GND HB12_N GND 3P3VAUX GND DP7_C2M_P GND
GND HB15_P GND LA31_P GND HB19_P TMS GND DP7_C2M_N GND
HB14_P HB15_N LA30_P LA31_N HB16_P HB19_N TRST_L GA0 GND DP4_C2M_P
HB14_N GND LA30_N GND HB16_N GND GA1 12P0V GND DP4_C2M_N
GND HB18_P GND LA33_P GND HB21_P 3P3V GND DP6_C2M_P GND
HB17_P_CC HB18_N LA32_P LA33_N HB20_P HB21_N GND 12P0V DP6_C2M_N GND
HB17_N_CC GND LA32_N GND HB20_N GND 3P3V GND GND DP5_C2M_P
GND VIO_B_M2C GND VADJ GND VADJ GND 3P3V GND DP5_C2M_N
VIO_B_M2C GND VADJ GND VADJ GND 3P3V GND RES0 GND
LPC Connector LPC Connector LPC Connector LPC
Connector
Table (14): Vita57 FMC Pin Assignment
32
2.9.1 FMC
Table (15) illustrates FPGA pin assignment for the FMC connector
Column B Column A
FPGA FPGA
FMC Pin Name Pin Description FMC Pin Name Pin Description
Pin # Pin #
1 CLK_DIR FMC_F_CLK_SEL L33 1 GND GND
2 GND GND 2 DP1_M2C_P FMC_DP[1]_M2C_P P2
3 GND GND 3 DP1_M2C_N FMC_DP[1]_M2C_N P1
4 DP9_M2C_P NC 4 GND GND
5 DP9_M2C_N NC 5 GND GND
6 GND GND 6 DP2_M2C_P FMC_DP[2]_M2C_P M2
7 GND GND 7 DP2_M2C_N FMC_DP[2]_M2C_N M1
8 DP8_M2C_P NC 8 GND GND
9 DP8_M2C_N NC 9 GND GND
10 GND GND 10 DP3_M2C_P FMC_DP[3]_M2C_P Y2
11 GND GND 11 DP3_M2C_N FMC_DP[3]_M2C_N Y1
12 DP7_M2C_P FMC_DP[7]_M2C_P T2 12 GND GND
13 DP7_M2C_N FMC_DP[7]_M2C_N T1 13 GND GND
14 GND GND 14 DP4_M2C_P FMC_DP[4]_M2C_P AB2
15 GND GND 15 DP4_M2C_N FMC_DP[4]_M2C_N AB1
16 DP6_M2C_P FMC_DP[6]_M2C_P AD2 16 GND GND
17 DP6_M2C_N FMC_DP[6]_M2C_N AD1 17 GND GND
18 GND GND 18 DP5_M2C_P FMC_DP[5]_M2C_P AF2
18 GND GND 18 DP5_M2C_N FMC_DP[5]_M2C_N AF1
FMC_GBTCLK[1]_M2
20 GBTCLK1_M2C_P V6 20 GND GND
C_P
FMC_GBTCLK[1]_M2
21 GBTCLK1_M2C_N V5 21 GND GND
C_N
22 GND GND 22 DP1_C2M_P FMC_DP[1]_C2M_P N4
23 GND GND 23 DP1_C2M_N FMC_DP[1]_C2M_N N3
24 DP9_C2M_P NC 24 GND GND
25 DP9_C2M_N NC 25 GND GND
26 GND GND 26 DP2_C2M_P FMC_DP[2]_C2M_P L4
27 GND GND 27 DP2_C2M_N FMC_DP[2]_C2M_N L3
28 DP8_C2M_P NC 28 GND GND
29 DP8_C2M_N NC 29 GND GND
30 GND GND 30 DP3_C2M_P FMC_DP[3]_C2M_P W4
31 GND GND 31 DP3_C2M_N FMC_DP[3]_C2M_N W3
32 DP7_C2M_P FMC_DP[7]_C2M_P R4 32 GND GND
33 DP7_C2M_N FMC_DP[7]_C2M_N R3 33 GND GND
34 GND GND 34 DP4_C2M_P FMC_DP[4]_C2M_P AA4
35 GND GND 35 DP4_C2M_N FMC_DP[4]_C2M_N AA3
36 DP6_C2M_P FMC_DP[6]_C2M_P AC4 36 GND GND
37 DP6_C2M_N FMC_DP[6]_C2M_N AC3 37 GND GND
38 GND GND 38 DP5_C2M_P FMC_DP[5]_C2M_P AE4
39 GND GND 39 DP5_C2M_N FMC_DP[5]_C2M_N AE3
40 RES0 40 GND GND
33
Column D Column C
FPGA FPGA
Pin # Pin #
1 PG_C2M FMC_F_PG_C2M P34 1 GND NC
2 GND GND 2 DP0_C2M_P FMC_DP[0]_C2M_P J4
3 GND GND 3 DP0_C2M_N FMC_DP[0]_C2M_N J3
FMC_GBTCLK[0]_M2
4 AB6 4
GBTCLK0_M2C_P C_P GND GND
FMC_GBTCLK[0]_M2
5 AB5 5
GBTCLK0_M2C_N C_N GND GND
6 GND GND 6 DP0_M2C_P FMC_DP[0]_M2C_P K2
7 GND GND 7 DP0_M2C_N FMC_DP[0]_M2C_N K1
8 LA01_P_CC FMC_LA[1]_CC_P AL7 8 GND GND
9 LA01_N_CC FMC_LA[1]_CC_N AM7 9 GND GND
10 GND GND 10 LA06_P FMC_LA[6]_P AN8
11 LA05_P FMC_LA[5]_P AJ6 11 LA06_N FMC_LA[6]_N AM8
12 LA05_N FMC_LA[5]_N AJ7 12 GND GND
13 GND GND 13 GND GND
14 LA09_P User defined signal NC 14 LA10_P User defined signal NC
15 LA09_N User defined signal NC 15 LA10_N User defined signal NC
17 LA13_P User defined signal NC 17 GND GND
18 LA13_N User defined signal NC 18 LA14_P User defined signal NC
18 GND GND 18 LA14_N User defined signal NC
20 LA17_P_CC User defined signal NC 20 GND GND
21 LA17_N_CC User defined signal NC 21 GND GND
22 GND GND 22 LA18_P_CC User defined signal NC
23 LA23_P User defined signal NC 23 LA18_N_CC User defined signal NC
24 LA23_N User defined signal NC 24 GND GND
26 LA26_P User defined signal NC 26 LA27_P User defined signal NC
27 LA26_N User defined signal NC 27 LA27_N User defined signal NC
29 TCK JTAG 29 GND GND
30 TDI JTAG 30 SCL FMC_F_SCL N33
31 TDO JTAG 31 SDA FMC_F_SDA M33
32 3P3VAUX 3.3V Aux. Supply 32 GND GND
33 TMS JTAG 33 GND GND
34 TRST_L Asynch. Init. 34 GA0 Geographical address
35 GA1 Geographical address 35 12P0V 12V Supply
36 3P3V 3.3V Supply 36 GND GND
37 GND GND 37 12P0V 12V Supply
39 GND GND 39 3P3V 3.3V Supply
34
Column F Column E
FPGA FPGA
Pin # Pin #
1 PG_M2C FMC_F_PG_M2C N34 1 GND GND
2 GND GND GND 2 HA01_P_CC User defined signal NC
3 GND GND GND 3 HA01_N_CC User defined signal NC
4 HA00_P_CC User defined signal NC 4 GND GND GND
5 HA00_N_CC User defined signal NC 5 GND GND GND
6 GND GND GND 6 HA05_P User defined signal NC
7 HA04_P User defined signal NC 7 HA05_N User defined signal NC
8 HA04_N User defined signal NC 8 GND GND GND
21 GND GND GND 21 HB03_P User defined signal NC
22 HB02_P User defined signal NC 22 HB03_N User defined signal NC
23 HB02_N User defined signal NC 23 GND GND GND
39 GND GND GND 39 VADJ Adjustable Voltage
40 VADJ Adjustable Voltage 40 GND GND GND
35
Column H Column G
FPGA FPGA
Pin # Pin #
1 VREF_A_M2C Reference voltage 1 GND GND
2 PRSNT_M2C_L FMC_PRSNT_M2C_L H7 2 CLK1_M2C_P FMC_CLK[1]_M2C_P R32
3 GND GND 3 CLK1_M2C_N FMC_CLK[1]_M2C_N P32
4 CLK0_M2C_P FMC_CLK[0]_M2C_P AT8 4 GND GND
5 CLK0_M2C_N FMC_CLK[0]_M2C_N AR8 5 GND GND
6 GND GND 6 LA00_P_CC FMC_LA[0]_CC_P AN6
7 LA02_P FMC_LA[2]_P AU7 7 LA00_N_CC FMC_LA[0]_CC_N AN7
8 LA02_N FMC_LA[2]_N AU8 8 GND GND
9 GND GND 9 LA03_P FMC_LA[3]_P AV8
10 LA04_P FMC_LA[4]_P AP6 10 LA03_N FMC_LA[3]_N AW8
11 LA04_N FMC_LA[4]_N AR6 11 GND GND
12 GND GND 12 LA08_P User defined signal
13 LA07_P FMC_LA[7]_P AT6 13 LA08_N User defined signal
14 LA07_N FMC_LA[7]_N AU6 14 GND GND
15 GND GND 15 LA12_P User defined signal NC
16 LA11_P User defined signal NC 16 LA12_N User defined signal NC
33 GND 33 LA31_P User defined signal NC
36 GND 36 LA33_P User defined signal NC
39 GND GND 39 VADJ Adjustable Voltage
40 VADJ Adjustable Voltage 40 GND GND
36
Column K Column J
FPGA FPGA
Pin # Pin #
1 VREF_B_M2C Reference voltage 1 GND GND
2 GND GND 2 CLK3_M2C_P Differential Clock NC
3 GND GND 3 CLK3_M2C_N Differential Clock NC
4 CLK2_M2C_P FMC_A_CLK[2]_BI_P 4 GND GND
5 CLK2_M2C_N FMC_A_CLK[2]_BI_N 5 GND GND
6 GND GND 6 HA03_P User defined signal NC
8 HA02_N User defined signal NC 8 GND GND
16 HA17_P_CC User defined signal NC 16 HA14_N User defined signal NC
17 HA17_N_CC User defined signal NC 17 GND GND
24 GND GND 24 HB01_P User defined signal NC
25 HB00_P_CC User defined signal NC 25 HB01_N User defined signal NC
26 HB00_N_CC User defined signal NC 26 GND GND
32 HB10_N User defined signal NC 32 GND GND
35 HB14_N User defined signal NC 35 GND GND
39 GND GND 39 VIO_B_M2C IO Bank Voltage
40 VIO_B_M2C IO Bank Voltage 40 GND GND
Table (15): FPGA Mezzanine Connector (FMC) pin assignment
37
2.9.1.1 FMC Clock Generation
In addition to the clock provided by the FMC daughter cards, the HTG-S510 board can also generate the
required clocks through its onboard clock circuitry. These clocks are generated by U24 (Si570
programmable oscillator) and U28 (4:4 differential to LVPECL/LVDS clock multiplexer). Page 8 of the
boards schematic provides additional details. The generated clocks (as well as other clocks generated by
other Si570 oscillators) can be turned ON/OFF by the S1 switch.
2.9.1.2) V_Adjust
As illustrated by figure (12), V_adjust for the FMC is set to 2.5V by default (R4=28.7k Ohm).
By populating the R4 resistor with different resistance values the V_adjust voltage can be set to 3.3V, 1.8V
or 1.5V subsequently.
Figure (12): V_Adjust Configuration for FMC A
38
2.10 Legacy Serial I/O Expansions

The HTG-S510 board is supported with two legacy QSE connectors from Samtec. These connectors
provide access to 5 serial transceivers of the onboard Stratix V FPGA. These connectors can be used for
board-to-board and board-to-daughter card applications.
Table (16) illustrated FPGA and connector pin assignments.

Signal Name FPGA Pin Number Samtec Connector Pin Number
R0_CLK1_N AD6 J9-39
R0_CLK1_P AD7 J9-37
R0_RX4_N AK1 J9-4
R0_RX4_P AK2 J9-2
R0_RX5_N AH1 J9-10
R0_RX5_P AH2 J9-8
R0_TX4_N AJ3 J9-3
R0_TX4_P AJ4 J9-1
R0_TX5_N AG3 J9-7
R0_TX5_P AG4 J9-9
R1_RX10_N V1 J9-16
R1_RX10_P V2 J9-14
R1_RX15_N H1 J9-22
R1_RX15_P H2 J9-20
R1_TX10_N U3 J9-15
R1_TX10_P U4 J9-13
R1_TX15_N G3 J9-21
R1_TX15_P G4 J9-19
R2_RX16_N F1 J9-28
R2_RX16_P F2 J9-26
R2_RX17_N D1 J9-32
R2_RX17_P D2 J9-34
R2_TX16_N E3 J9-27
R2_TX16_P E4 J9-25
R2_TX17_N C3 J9-33
R2_TX17_P C4 J9-31
L0_CLK1_N AD34 J10-39
L0_CLK1_P AD33 J10-37
L0_RX4_N AK39 J10-4
L0_RX4_P AK38 J10-2
L0_TX4_N AJ37 J10-3
L0_TX4_P AJ36 J10-1
L1_RX10_N V39 J10-16
L1_RX10_P V38 J10-14
L1_TX10_N U37 J10-15
L1_TX10_P U36 J10-13
L2_RX16_N F39 J10-28
L2_RX16_P F38 J10-26
L2_RX17_N D39 J10-34
L2_RX17_P D38 J10-32
39
L2_TX16_N E37 J10-27

L2_TX16_P E36 J10-25
L2_TX17_N C37 J10-33
L2_TX17_P C36 J10-31
Table (16): Serial IO Legacy Expansion Connector Pin Assignment
2.11) USB To UART Bridge

The HTG-S510 board provides one UART port through a peripheral USB connector. The port is supported
by the Silicon labs CP2102 (U40) USB to UART controller chip.
The CP2102 is a highly-integrated USB-to-UART Bridge Controller providing a simple solution for
updating RS-232 designs to USB using a minimum of components and PCB space. The CP2102 includes a
USB 2.0 full-speed function controller, USB transceiver, oscillator, EEPROM, and asynchronous serial
data bus (UART) with full modem control signals in a compact 5 x 5 mm QFN-28 package. No other
external USB components are required.
The on-chip EEPROM may be used to customize the USB Vendor ID, Product ID, Product Description
String, Power Descriptor, Device Release Number, and Device Serial Number as desired for OEM
applications. The EEPROM is programmed on-board via the USB, allowing the programming step to be
easily integrated into the product manufacturing and testing process.
Virtual COM Port (VCP) device drivers provided by Silicon Laboratories allow a CP2102-based
product to appear as a COM port to PC applications. The CP2102 UART interface implements all RS-232
signals, including control and handshaking signals, so existing system firmware does not need to be
modified. In many existing RS-232 designs, all that is required to update the design from RS-232 to USB is
to replace the RS-232 level-translator with the CP2102. Direct access driver support is available through
the Silicon Laboratories USBXpress driver set.
There are two sets of device drivers available for the CP2102 devices: the Virtual COM Port (VCP) drivers
and the USBXpress Direct Access drivers. Only one set of drivers is necessary to interface with the device.
The latest drivers are available at:
http://www.silabs.com/products/mcu/pages/usbtouartbridgevcpdrivers.aspx
Additional device information is available at

http://www.silabs.com/Support%20Documents/TechnicalDocs/cp2102.pdf
Table (17) illustrates FPGA pin assignment for the USB-TO-UART interface:
UART/USB Bridge (U4) Signal Name FPGA (2U8) Pin #

USB_PERI_PWR AH28
UART_RST AG28
UART_SUSPEND AG30
UART_RI AA28
UART_DCD AE29
UART_DTR AB28
UART_DSR AA29
UART_RXD AA27
UART_TXD AF28
UART_RTS AA26
UART_CTS AF29
40
Table (17): USB To UART FPGA pin assignment
2.11) LEDs, GPIO Headers & Pushbuttons

The HTG-S510 provides user LEDs, user switches and Push Buttons.
Signal Name FPGA Pin #

CONF_DONE AH6
CPLD_FPGA_IO0 AE30
CPLD_FPGA_IO1 AD30
CPLD_FPGA_IO2 AC30
CPLD_FPGA_IO3 AB30
CPLD-GC_FPGA AN29
CvPCIe_CONFDONE AT29
FPGA_CLKUSER AN34
FPGA_CRC_ERR AN33
FPGA_DEV_OE AP34
FPGA_SYS_RST AM34
FPGA_USER_IO0 G33
FPGA_USER_IO1 G34
FPGA_USER_IO2 A34
FPGA_USER_IO3 C34
FPGA_USER_IO4 H34
FPGA_USER_IO5 J34
FPGA_USER_IO6 A36
FPGA_USER_IO7 A37
FPGA_USER_LED0 N6
FPGA_USER_LED1 M6
FPGA_USER_LED2 A6
FPGA_USER_LED3 A7
FPGA_USER_LED4 N7
FPGA_USER_LED5 P7
FPGA_USER_LED6 K6
FPGA_USER_LED7 L6
FPGA_USER_PB A5
FPGA_USER_SW0 K7
FPGA_USER_SW1 J7
FPGA_USER_SW2 A4
FPGA_USER_SW3 A3
FPGA-GC_CPLD AV29
Table (18): User Interface FPGA pin assignment
41
Chapter 3:Mezannine Cards
Vita 57 provides a mechanical standard for I/O mezzanine modules. This standard introduces a
methodology that shall allow the front panel IO of IEEE 1101 form factor cards to be configured via
mezzanine boards. Vita 57 modules have fixed locations for serial/parallel IOs, clocks, Jtag signals, VCC,
and GND. HiTech Global's Vita 57 modules work with any Vita 57 compliant carrier boards.
The FMC standard specifies Samtecs SEARAY connector set. The VITA 57 SEAM/SEAF Series
system provides 400 I/Os in a 40 x 10 configuration or 160 I/Os in a selectively loaded 40 x 10
configuration, in 8.5mm and 10mm stack heights.
HiTech Global offers a wide range of FMC daughter cards which can be used for expanding functionality
of the main board.
3.1) Dual SFP+

The Dual SFP+ FMC daughter card provides access to two SFP+ ports (10Gbps each) interfacing to total of
8 serial transceivers (XUAI).
The onboard 10Gig PHY device is a physical layer transceiver with an integrated Electronic Dispersion
Compensation (EDC) engine - compliant with IEEE802.3aq specifications. The device integrates industry-
leading SerDes/PHY technology with low-power EDC engine with up to 5db of margin over the symmetric
stress test pulse sensitivity specifications defined in the 10GASE-LRM standard.
Each PHY device provides full PCS, PMA, and XG XS sub-layer functionality through the consolidation of
the receiver and transmitter PHY functions on a single chip along with the integration of
encode/decode/alignment logic, FIFOs, on-chip clock drivers, multiple loop-back features and PRBS &
Ethernet frame generation & verification for both the line side and the system side.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_SFP+.htm
3.2) Dual CX4

The dual CX4 FMC daughter card provides access to two CX4 ports (10Gbps) interfacing to total of 8
serial transceivers (XUAI).
More information is available at http://www.hitechglobal.com/FMCModules/FMC_Dual_CX4.htm
3.3) CX4/SATA/SMA Serial Connectivity

The Serial Connectivity FMC daughter card provides access to one CX4, two SATA, and two SMA ports
(interfacing to total of 8 serial transceivers). Each port has its own on-board dedicated clock for maximum
flexibility and ease of use.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_CX4-SMA-SATA.htm
3.4) PCI Express Root Complex

42
The PCI Express Root FMC daughter card provides access to 8 lanes of PCI Express Gen 1 and port. The
module is supported by 100MHz and 250MHz low-jitter clocks.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_PCIExpress.htm
3.5) 8-Port SMA

The 8-Port SMA FMC daughter card provides access to 32 SMA connecters providing access to 8 Serial
Transceivers. The module is supported by on-board and external clocks.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_SMA.htm
3.6) Quad SFP/SATA

The Quad SFP/SATA FMC daughter card provides access to four SFP and four SATA connectors. Each
interface is supported by its own independent clock.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_x4SFP_x4SATA.htm
3.7) Quad SFP+

3.8) Dual QSFP+
Technical Support:
Technical support can be provided by contacting support@HiTechGlobal.com Support requests are

responded in less than 24 hours.
Sales Support:
Sales support can be provided by contacting info@HiTechGlobal.com or +1 408 781-7778 (8:00 AM

6:00 PM Pacific Standard Time)
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HTG-S510 User Manual

HiTech Global Stratix V PCI Express Ethernet Networking Development Platform

HTG-S510 User Manual

Version 1.0 August 2012

Date Version Notes

Chapter 1 - Introduction to Stratix V

Chapter 1: Introduction to Altera Stratix V FPGAs

The Stratix V FPGA family includes four device variants:

Stratix V GX FPGAs with transceivers: Integrate up to 66 full-duplex, 14.1-Gbps transceivers and

Table (1) illustrates key features of the Stratix V family.

Feature Stratix V Stratix V Stratix V Stratix V

High-performance adaptive logic modules 359,200 262,400 359,200 234,720

Variable-precision DSP blocks (18x18) 704 3,926 798 512

M20K memory blocks 2,640 2,567 2,660 2,560

External memory interface

PCI Express Gen3, Gen2, Gen1 hard IP - Up to 2 Up to 4 1

Embedded HardCopy Blocks and hard IP -

Transceivers - 14.1 Gbps / 14.1 Gbps / 28.05 Gbps /

Table (1) Summary of Stratix V FPGA Features

1.2) Stratix V Family Serial I/O Protocol Support

IEEE 802.3ba 40G

IEEE 802.3ba 100G

PCI Express Gen2

10-Gbps Ethernet XAUI

Table (2) Stratix V Supported Serial Protocols

Chapter 2:Development Platform Introduction

Figure (1) Block Diagram & Placement

2.3) FPGA Bank Assignment

Features 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB

Table (3) Supported Stratix V Devices

FPGA bank allocation for each interface is illustrated by figure (2).

Figure (2): FPGA Bank Assignment

2.4) Clock Distribution

Figure (3): Clock Diagram

2.5) PCI Express

Figure (4): Hard Block PCI Express Block Diagram

A Side Signal Name FPGA Pin # FPGA Pin Name

Table (4): PCI Express Upstream Connections Summary -A Side

B Side Signal Name FPGA Pin # FPGA Pin Name

Table (5) PCI Express FPGA Pin Assignments

2.5.1) PCI Express Clock

Figure (5): PCI Express Clock Circuit

Figure (6): Jitter Attenuator Output Diagram

Table (6): Jitter Attenuator Output Setting

2.6) DDR-III Interface

DDR3 A Signal Name (J11) FPGA Pin Number

Table (7) DDR3 A SODIMM FPGA Pin Assignment

DDR3 B Signal Name (J16) FPGA Pin Number

Table (8) DDR3 B SODIMM FPGA Pin Assignment

2.6.1) DDR3 Clock

Figure (7): DDR3 Clock Circuit

2.7) QDRII Memory

Figure (8) illustrates block diagram of the QDR II device.

Figure (8): QDR-II Block Diagram

Additional product information is available at http://www.cypress.com/?mpn=CY7C2663KV18-450BZXC

QDRII A Pin Number (U3) Signal Name FPGA Pin Number

Table (9) QDRII A FPGA Pin Assignment

QDRII B Pin Number (U4) Signal Name FPGA Pin Number

C11 QDRII_B_D[8] AL17

Table (10) QDRII B FPGA Pin Assignment

QDRII C Pin Number (U5) Signal Name FPGA Pin Number

Table (11) QDRII C FPGA Pin Assignment

2.71) QDR-II Clock