Simplified control model for

HVDC Classic

Master of Science Thesis

by
Jonas Karlsson
Royal Institute of Technology
Stockholm, 2006

Examiner
Professor Stefan stlund
Royal Institute of Technology
Department of Electrical Systems
Division for Electrical Machines and Power Electronics
Abstract
In this Masters project, a simplified control model for HVDC classic has been
built in the EMTDC simulation program with PSCAD v.4.2 interface. The control
functions in the simplified control are based on functions from ABB Power
Systems. A number of cases have been simulated to evaluate the simplified
control model, which demand correct function during earth fault and load
disturbances. The main functions in the simplified control are the Voltage
Dependent Current Order Limiter (VDCOL), Current Order Amplifier (CCA), as
well as functions that are acting on the upper and lower limits of the CCA.
The VDCOL will reduce the current order at direct voltage reduction. This will
avoid voltage instabilities during and after AC disturbances. It will also ease the
stresses on the valves and speed up the recovery after disconnection of the earth
fault. The CCA is principally a proportional-integral controller, which give the
current control loop proper dynamics. For an inverter, it will decrease the firing
angle and for a rectifier it will increase the firing angle. Furthermore, the CCA
controller may also be used for controlling the DC voltage to a constant value.
Through simulation it has been shown that during single-phase ground fault
disturbances between the converter transformers and the rectifier, the current and
the voltage curve shapes are practically the same, independent of which model is
used in the surge arresters that are connected in parallel with each thyristor valve.
The current and the voltage curve shapes in the surge arrestors connected to the
neutral line deviate in some cases. However, the shape of the DC voltage when
the system is disturbed is practically the same when the simplified control model
is used compared to the detailed model. This is probably the best result that can
expected with a simplified control. Unfortunately the simplified model cannot
control the DC voltage when there is a disturbance in the AC network.
Preface
This Masters thesis constitutes the final of my Master of Science programme in
Electrical Engineering at the Royal Institute of Technology. With this preface, I
would like to acknowledge those who have assisted me and contributed to this
work.
I especially would like to thank all at ABB Power Systems that participated in the
study for all their support during this work. Furthermore, I would like to thank my
supervisor at KTH, Professor Stefan stlund for his input on this work.
Table of Contents
1 Introduction...................................................................................................................... 2
1.1 Background............................................................................................................... 2
1.2 Purpose ..................................................................................................................... 2
2 HVDC system .................................................................................................................. 3
2.1 Why use direct current transmission? ....................................................................... 3
2.2 Basic conversion principle........................................................................................ 3
2.2.1 The commutation process .................................................................................. 4
2.2.3 Triggering delay................................................................................................. 5
3 Control of HVDC converters ........................................................................................... 9
3.1 Basics principles of control....................................................................................... 9
3.1.1 Operation requirements.................................................................................... 10
3.1.2 Control characteristics ..................................................................................... 10
3.2 Valve blocking and bypassing ................................................................................ 12
4 Methods ......................................................................................................................... 13
4.1 Current control amplifier ........................................................................................ 14
4.2 Voltage Dependent Current Order Limiter ............................................................. 15
4.3 Voltage controller ................................................................................................... 17
4.4 Overvoltage limiter ................................................................................................. 18
4.5 Rectifier alpha min limiter ...................................................................................... 18
4.6 Alphamax controller ............................................................................................... 19
4.7 GAMMA0 controller .............................................................................................. 20
5 Results............................................................................................................................ 22
5.1 Ground fault between the valve bridge and the converter transformer................... 22
5.1.1 Valve arrester stresses...................................................................................... 22
5.1.2 Stresses on ground return bus arrester ............................................................. 26
5.1.3 Stresses on metallic return bus arrester............................................................ 29
5.2 Energizing an open DC line.................................................................................... 32
5.3 Lost of AC network at inverter ............................................................................... 33
5.4 Commutation failure ............................................................................................... 35
6 Discussion...................................................................................................................... 36
6.1 The project .............................................................................................................. 37
6.2 Future work............................................................................................................. 37
7 Conclusions.................................................................................................................... 39
8 References...................................................................................................................... 40
Appendix A....................................................................................................................... 41
1 Introduction
1.1 Background
This Masters project is performed at ABB Power Systems, a company
specialized in High Voltage Direct Current (HVDC) technology. In a HVDC
system, electric power is taken from one point in a three-phase alternating current
(AC) network, converted to direct current (DC) in a converter station, then
transmitted to the receiving point by an overhead line or cable and converted back
to AC in another converter station and finally injected into the receiving AC
network. DC current and voltage are precisely controlled to modulate the desired
power transfer in level and direction. Therefore the control system in a HVDC
system complex has several different parameters that need fine adjustments for
each project before the control systems can be used. To start the dimension studies
before the project specific control is developed, ABB Power Systems requires a
control model to the simulation program PSCAD/EMTDC which should not be
project specific, but rather adjustable to any individual projects.
For the PSCAD/EMTDC program CIGR has developed a benchmark system for
HVDC, know as the CIGR Benchmark Model [1][2]. The control system in
the CIGR model is based on the control systems from Siemens HVDC systems,
and can be used as a complement for this work.

1.2 Purpose
The purpose of this thesis is to develop a simplified control system to HVDC
Classic based on the control function from ABB Power Systems by using the
EMTDC simulation program with PSCAD v.4.2 user interface. ABB Power
Systems are in need of a simplified control model so the employees that are not
specialized on how the detailed control is built up and function can start with
dimension studies while waiting for the project specific control to be ready. The
studies the control will be used for require a correct function during earth fault
and load disturbances. The control should not be project specific and should be
easy to adjust to individual projects i.e. a basic control.

2
2 HVDC system
In this chapter a general description of HVDC systems and power conversion will
be given.

2.1 Why use direct current transmission?

Electrical plants generate power in form of AC voltages and currents. This power
is transmitted to the load on three-phase AC transmission lines. Under certain
circumstances, it becomes desirable to use HVDC to transmit this power over DC
transmission lines. For example:
Transmitting electric power over long distances by overhead transmission
lines can be designed to be less costly per unit of length than an equivalent
AC line designed to transmit the same level of electric power.
Transmissions by submarine AC cable cannot exceed 50 km but DC cable
transmission systems are possible hundreds of kilometres.
To interconnect separate power systems that are not synchronized, for
example Japan where half the country is a 60 Hz network and the other is a
50 Hz system.

2.2 Basic conversion principle

The HVDC transmission systems today use three-phase bridges (figure 2.1).
Using this configuration results in lower reverse voltage across the valves and
better utilisation of the converter transformers. In high voltage application several
series connected valves are used to reach the desired voltage level. The dominant
valve type is the thyristor that is able to carry high currents, several kilo amps and
can block high voltages [5]. The turn-on of the thyristor can be controlled but it
turns-off automatically at the zero crossing of the current.

Figure 2.1 6-pulse converter bridge.

3
2.2.1 The commutation process
To understand basic principle of three-phase rectification we will consider the
idealised case of a converter bridge connected to an infinitely strong voltage
source, i.e. of zero source impedance.
In figure 2.1, the cathodes of valves 1, 3 and 5 at the top are connected together.
Therefore the thyristor with its anode at the highest potential will conduct id,
which is when the phase to neutral voltage is more positive than the voltages of
the other two phases. In the bottom group where 4, 6 and 2 are connected
together, the thyristor with its cathode at the lowest potential will conduct [4].
The resulting DC voltage has a ripple of six times the system frequency, the
voltage waveforms in the circuit of figure 2.1 are show in figure 2.2. In the graph
(figure 2.2) the phase voltages va, vb and vc are shown as dotted curves, cathode
potential (v1) and anode potential (v2) are shown as solid curves.
The average value of the ideal no load voltage, Vd0, which is the maximum output
voltage, can be calculated by integrating the instantaneous value over a 60
period.
6
1
2VLL cos wt d ( wt ) = 1.35VLL
3 - 6
Vd 0 = (2.1)

Where VLL is the root mean square (rms) value of AC phase-to-phase voltage.

1.5

v1
1

0.5
Voltage [p.u.]

-0.5

-1

v2
-1.5
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
t [rad]

Figure 2.2 Dotted curves are phase to ground voltages and solid curves
are cathode potential (v1), anode potential (v2).

4
 2.5

2 Vd
1.5

0.5

Voltage [p.u.]
0

-0.5

-1

-1.5

-2

-2.5
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
t [rad]

Figure 2.3 Dotted curves are phase-to-phase voltages and solid curve is
direct voltage (Vd).

2.2.3 Triggering delay

When using thyristor valves the instant firing of each valve can be delayed with
respect to natural firing, the effect of this is a controllable bridge output voltage.
The firing delay time is described by the angle , and is as follows where
= delay time2f
The DC voltage can be expressed as:
Vd = Vd 0 cos (2.2)
Examples of voltage waveforms with a delay angle of = 15, are shown in
figure 2.4 and 2.5.

0.8

0.6 v1
0.4

0.2
Voltage [p.u.]

-0.2

-0.4

-0.6

-0.8 v2
-1
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
t [rad]

Figure 2.4 Dotted curves are phase to ground voltages and solid curves
are cathode potential (v1), anode potential (v2).

5
 1.5

0.5

Voltage [p.u.]
0

-0.5

-1

-1.5
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
t [rad]

Figure 2.5 Dotted curves are phase-to-phase voltages and solid curve is
direct voltage (Vd).

2.2.4 The effect of commutation reactance

Now we will include the transformer reactance Xc, thus the commutation will not
be instantaneous and the DC voltage will be reduced by the voltage drop across
the reactance [4].
As an example, a commutation from valve 5 to valve 1 is described. Prior to this,
the current id is flowing through valve 5 and 6.
The commutation voltage between phases A and C is vcomm = van - vcn. The
commutation current iu flows through the short circuit path provided by the
conducting valve 5.
ia = iu
ic = I d iu (2.3)
dia diu
v Xa = X c = Xc (2.4)
d (t ) d (t )
dic diu
v Xc = X c = Xc (2.5)
d (t ) d (t )
diu
vcomm = van vcn = v Xa v Xc = 2 X c (2.6)
d (t )
Integrating the right hand side of Eq. 2.6 between 0 to Id yields the voltage drop
area Au.
Au = X c I d
This area is lost each 60 (/3 rad) interval, as shown in figure 2.5. The voltage
drop during the commutation then is (Eq. 2.7):
X c Id 3
Vd = = X I (2.7)
3 c d

6
With commutation overlap and triggering delay the average DC voltage output is:
3X c
Vd = Vd 0 Vd = Vd 0 cos Id (2.8)

Figure 2.6 describes the commutation process.

Xc ia 1
- + a
+ vXa - Id
Va iu
Xc 5 +
- + c
n + vXc - ic
Vb Vd
Xc Id 6
- + b -

Vc
(a)
ic ia
Id Id

(b)

Figure 2.6 (a) Equivalent circuit of the commutation from valve 5 to valve 1.
(b) The commutating currents [4].

2.3 HVDC configuration

The most common configurations of HVDC transmission systems are:
Back-to-back
Monopolar
Bipolar
The back-to-back (figure 2.7) interconnection consists of two converters at the
same site. They are connected to each other without any transmission line. This
configuration is used for interconnections between power systems networks of
different frequencies (50 and 60 Hz). They are also used as interconnections
between adjacent asynchronous networks [7].
The monopolar links (figure 2.8), the two converter stations by a single conductor
line earth or sea is used as return conductor, but metallic return can also be used in
situations where the earths resistivity is too high.
The bipolar link (figure 2.9) consists of a combination of two monopolar systems,
one at positive and one at negative voltage polarity. Since each pole can operate
on its own using ground return, this configuration results in a higher reliability
than the other configurations, [3].

7
 AC AC
system system

Figure 2.7 Back-to-back configuration.

Figure 2.8 Monopolar configuration.

Figure 2.9 Bipolar configuration.

8
3 Control of HVDC converters
In this chapter, the basic control principles for an HVDC transmission are
discussed.

3.1 Basics principles of control

The single line diagrams in figure 3.1 (a) shows a HVDC link and an equivalent
circuit is shown in figure 3.1 (b).

DC-line

Id
Three- Three-
Vd0rcos Vd0icos phase ac
phase ac

Rectifier Inverter
(a)

Rcr RL -Rci
+ Id +
Vd0rcos Vdr Vdi Vd0icos
- -

(b)

Figure 3.1 (a) Schematic diagram of a HVDC link. (b) Equivalent circuit.

The direct current, Id, flowing from rectifier to the inverter is [1]:
Vdor cos Vdoi cos
Id = (3.1)
RL + Rcr + Rci
The DC voltage at the rectifier DC terminals can be expressed as:
Vdr = Vdor cos Rcr I d (3.2)
Vd0r and Vdoi are the no-load direct voltage in the rectifier and the inverter
respectively, Rcr and Rci are the equivalent commutation resistance (due to
commutation overlap it accounts for the voltage drop in the converters) and RL is
the line resistance.
By controlling the voltages Vd0rcos and Vd0icos the DC current or the active
power can be controlled. This is done either by controlling the rectifier valve
ignition angle or extinction angle of an inverter, or by controlling Vd0r and Vd0i
by the transformer tap changer. Control of valve ignition is used for rapid action
and is then followed by tap changing to restore the converter quantities to their
normal range.

9
3.1.1 Operation requirements
In practice the line and converter resistance are relatively small, hence a small
difference between Vdor and Vdoi causes a large change in Id. This implies that if
and are kept constant and small changes in the AC voltage magnitude are made
at either end, the direct current can vary over a wide range. Such variations are
unacceptable for a satisfactory performance of the power system.
The power factor should be as high as possible. This is important for several
reasons, e.g. to avoid excessive consumption of reactive power, to reduce the
amplitude of the harmonics and to minimize the stresses on the valves and the
transformers. The power factor of the converter can approximately be expressed
as [3]:

cos = 0.5 cos + cos ( + u ) for rectifier operation

cos = 0.5 cos + cos ( + u ) for inverter operation

To achieve high power factor the angle for a rectifier and for inverter must be
kept low.
In order to secure a certain positive voltage across the valve at firing the firing
control in the rectifier operation is arranged so that the angle will not be decreased
below a certain minimum value min(5). Since a too small value of the
extinction angle will make the converter too vulnerable for commutation
failures, it should never decrease below a certain minimum value min(17).

3.1.2 Control characteristics

The control characteristics are best explained by using the steady-state voltage-
current characteristics. These characteristics represent the relationship between Id
through and Vd across the converters, which are suitable for explaining how the
converter stations work together for controlling the flow of power on the DC line.
The Vd-Id characteristics of a rectifier are, if only the basics are considered
described by Eq. (3.3):

3 Ls
Vd = 1.35VLL cos + Rdc I d (3.3)

Where VLL is the rms value of line-to-line voltages and Ls is the AC-side
inductance. We see from the expression that there are three variables, VLL, and
Id, which define the level of the direct voltage. The maximum Vd is obtained if
= min at it is minimum value, and the rectifier will operate at constant ignition
angle (CIA), The Vd-Id characteristics starts at a value obtained by using Eq.(3.4).
Vd = 1.35VLL cos min (3.4)

10
and CIA being represented by a line of negative slope (segment FA in figure 3.2)
for increasing Id.

Figure 3.2 Steady-state characteristics

for converter control.

The segment AB in figure 3.2 represents the normal constant current (CC) control
mode. Operation with constant current and variable results in vertical line in the
Vd-Id diagram. This is the normal mode of rectifier operation in which the rectifier
controls the direct current by varying to meet the voltage on the DC side.
Consequently, the complete rectifier characteristics at normal voltage are defined
by FAB and E is the point of operation.
At reduced voltage the CIA characteristic would follow FA and the inverter
CEA characteristic (CD) would not intersect FAB, this would cause the current
and the power to be reduced to zero, and the system would run down.
In order to avoid the above problem, the inverter is also provided with a current
controller, which is set at a value lower than the current setting for the rectifier.
The resulting inverter CC characteristic is given by the section GH.
The difference between rectifier and inverter current order is called the current
margin and is denoted by Im in Figure 3.2 and it is normally around 0.1 p.u. [3][5].
If the AC voltage in the inverter network is slightly reduced i.e. Vdi is reduced, the
rectifier must increase its in order to keep the direct current at the requested
level and the new point of operation will be A. If the AC voltage reduction
occurs in the rectifier network, the inverter current control system will react to the
decreased direct current and increase i.e Vdr is reduced. Thus the inverter takes
over the current control and restores stable operation with direct current equal to
the current reference in the inverter, and the new point of operation will be E [3].
Most HVDC systems are provided with bidirectional power flow capability,
which means that each converter can operate both as rectifier as well as inverter.
A reversal of the power direction can be obtained by changing the voltage

11
magnitude at the converter terminals. This can be done by using a type of firing-
angle control [5]. These combined characteristics are show in figure 3.3.

Vd Vd
Converter 1 (CIA) Converter 1 (CIA)
E Converter 2 Converter 2
(CEA) (CEA)

Converter 2 Converter 1 Converter 1 Converter 2

(CC) (CC) (CC) (CC)

Im Im

Id Id

E
Converter 1 Converter 1
(CEA) (CEA)
Converter 2 Converter 2
(CIA) (CIA)
(a) (b)

Figure 3.3 Combined rectifier-inverter characteristic. (a) Power flow direction from
converter 1 to converter 2. (b) Power flow direction from converter 2 to converter 1.

3.2 Valve blocking and bypassing

It is impossible to block the valve group (take out of operation) with a mere cease
of pulses. The smoothing inductance in the system maintains current continuity
and by stopping the firing pulses the last two conducting valves would still remain
in conduction. Therefore it is necessary to bypass the bridge to block the valves.
Bypass action should be carried out immediately after fault, i.e. blocking of the
main firing pulses and the simultaneous injection of continuous firing pulses to a
bypass pair (bpp). A bpp is formed by using the last conducting valve and the
opposite valve, for example if valve 4 is commutating to 6 at the blocking signal
the bpp should be 3 and 6 [5].

12
4 Methods
The control system is described in general terms in chapter 3. This chapter
describes the function and the block diagram of the control system model that are
used in the simplified control system.

The simplified control system model is intended to be used for dimensioning

surge arresters. An arrester is a component that protects the installed equipment
against overvoltages. To dimension surge arresters, disturbances are applied in the
systems when the model is in steady state. Transient voltages and currents during
the fault are calculated in the system. i.e. the simplified control system model
should direct the HVDC system into steady state and give proper result compared
with the detailed model after the fault.
The project was started by using a detailed project specific HVDC model
developed by ABB Power System using PSCAD/EMTDC. The model is a bipolar
500 kV, 1500 MW HVDC link connected to an AC system with a rated frequency
of 50 Hz. As a starting point a project specific HVDC model was used to achieve
a satisfactory comparison between the controls. A copy was made in
PSCAD/EMTDC model, the control was removed and the simplified control was
implemented.
There are several differences between the simplified and the detailed control
system, the differences with the highest impact on the system are the function that
converts the firing angle order (order) to gate trigger signals, which are sent to the
thyristors and bypass pair function. In the simplified control system model a
PSCAD/EMTDC converter is used and its functions are modelled internally in the
converter. In the detailed control the PSCAD/EMTDC converter is also used but
the functions controlling the firing signals and the bpp are not controlled by the
converter, instead they are modelled and governed by the control itself.
Furthermore, the detailed model for all the control functions are not calculated
with the same time step as they are in the simplified control.
The control function of a converter is the closed loop system for direct current
control, as shown in figure 4.1 which includes:
Current Control Amplifier.
Firing control.
Voltage Dependent Current Order Limiter.

13
 Figure 4.1 The control system.

Only the necessary and relevant function that is required to get the model in
steady state and comparable behavior to the detailed model 60 ms after a
disturbance are used.

4.1 Current control amplifier

Current Control Amplifier (CCA) is included in both the rectifier and the inverter;
the functions are principally equal in the two stations. There may be some
differences in parameter settings inside the block.
The main task of the current control amplifier is to give the current control loop
proper dynamics. The demands for the current control loop are to get:
Fast enough step response.
Zero current error at steady state.
Stable current control.
The current order from Voltage Dependent Current Order Limiter (VDCOL) is
compared with the measured direct current and the output signal the firing angle
order is delivered to the firing control system.
The CCA has a proportional part and an integrating part, the integrating part gives
a high gain for very low frequencies. This means that the current error in steady
state is zero.
The CCA has a summing junction, in which the difference between the current
order and the current response is formed. The current control error is formed as
(Iorder Id) to get the correct sign for the change in , i.e. when the direct current
decrease below the reference value should decrease. Current margin, Im, is
added to the summing junction in inverter operation, but only in this case.
Minimum and maximum limitations are included in the proportional part,
integrating part and the final output as shown in figure 4.2. These limitations are

14
used to set restrictions on the acting range of the CCA during special
circumstances.

Figure 4.2 Current control amplifiers.

4.2 Voltage Dependent Current Order Limiter

The VDCOL will reduce the current order at direct voltage reduction, the main
reason for the VDCOL functions are:
A reduction of the direct voltage requires higher firing angles and at
constant direct current demand the reactive power consumption will
increase. For weak AC networks, if the DC current is not reduced, the
increase of the reactive power consumption will cause a too large
reduction of the AC voltage.
During a commutation failure caused by e.g. phase to ground fault in the
AC network connected to the stations, it is advantageous to reduce the
current order to lower the stresses on the valves and speed up the recovery
after disconnection of the earth fault [4].
The static characteristic of the VDCOL is shown in figure 4.3.

Iord

Io max

Io min VDCOL
Io min

Vd low Vd high Vd
Figure 4.3 The static characteristic of VDCOL.

15
The influence of the VDCOL on the Vd-Id characteristic is shown in figure 4.4 and
the block diagram of the VDCOL is shown in figure 4.5.

Figure 4.4 Influence on Vd-Id characteristic with the VDCOL.

Figure 4.5 The block diagram of VDCOL.

The low pass filter has different time constants depending on if the Vd input
increases or decreases at rectifier or inverter operation. The rectifier time constant
should be lower than the inverter time constant in order to maintain the current
margin. The difference between the time constants in the rectifier and inverter
operation has an influence on the restart time. The rectifier time constant should
also be set to a value that gives a controlled restart after disturbance. The time
constant for decreasing Vd is low, 10 ms or less, to rapidly force the current order
to a low value during disturbance.
If Vd becomes lower than Vd low the reduction of the maximum limitation will stop
and the limitation level will be kept at Io min VDCOL. The level of Io min VDCOL is
normally 0.3 p.u. to prevent stress on the valves.
The minimum limitation (Io min) of the current order prevents discontinuous
conduction of the current during conduction intervals. The typical value of Io min is
0.1 p.u.

16
4.3 Voltage controller
The controller is used for reduced voltage operation, but can also be used for
normal voltage operation.
The voltage controller is a PI-regulator acting on the minimum and maximum
limits of the current controller. In inverter operations, it will decrease the
maximum alpha limit and in rectifier operation increase the minimum alpha limit
of the CCA.
At reduced voltage operations, the reference voltage is lowered to the desired
value and the controller consequently lowers the DC voltage.
The influence of the voltage controller on the Vd-Id characteristic is shown in
figure 4.6.

Figure 4.6 Voltage controller influence on the Vd-Id characteristic.

The new operation point is moved away from min in a stable mode of operation.
Figure 4.7 shows the block diagram of the voltage controller.

Figure 4.7 Block diagram of voltage controller.

17
The voltage reference Vd ref is slightly higher in the rectifier in order to maintain
the voltage control in the inverter. To obtain the correct control function the
polarity is switched depending on the operation mode (rect/inv).

4.4 Overvoltage limiter

If the rectifier is started and the inverter is blocked, an overvoltage with
approximately zero current will occur. The CCA will lower alpha in order to
establish minimum current until reaches 5 and then the OverVoltage Limiter
(OVL) controller will increase alpha in order to decrease Vd down to Vd ref.
Figure 4.8 shows the block diagram of the OVL controller.

Figure 4.8 Block diagram of OVL controller.

4.5 Rectifier alpha min limiter

At short-circuit in the AC network connected to a rectifier, firing angle will
decrease to the minimum allowed value, min. After clearing the fault and when
the AC voltage is re-establishing, the DC current would be high since the firing
angle is at min. To prevent this Rectifier Alpha Min Limiter (RAML) controller is
used. The controller is activated when the AC voltage decreases below a chosen
value and increases firing angle to a predefined value. A block diagram of the
RAML controller is shown in figure 4.9.

18
 Figure 4.9 Block diagram of RAML controller.

4.6 Alphamax controller

The direct voltage for inverter operation can be expressed as:
I V
Vd = Vd 0 cos ( d x d r ) 0 dN (4.1)
I dN Vd 0
where dx and dr is the relative inductive and relative resistance respectively
voltage drop, VdN and IdN are the nominal voltage and current. dr only affects the
DC voltage and not the length of the commutation overlap and therefore can be
negligible.
The direct voltage can also be written as:
1
Vd = Vd 0 cos + cos ( + u ) (4.2)
2
where
= (4.3)
Thereby, can be solved by combining equation 4.1 and 4.3 into 4.2.
I 0 VdN
= arccos cos 2dx (4.4)
I dN Vd 0
Stabilization can be introduced if a contribution derived from the difference
between the current order and current response is added when calculating . The
parameters for this contribution, gain and time constant, can be varied to get the
best stability.
This contribution must be limited when the DC current reaches the current order
minus the current margin. After this point, the current will be controlled by the
inverter.
By adding this function, the equation can be formulated as below:

19
 I 0 VdN
= arccos cos 2dx K ( I o I d ) (4.5)
I dN Vd 0
The output signal alpha max is calculated as:
max =180- (4.6)

Beta I contribute to the value of Amax by the difference between the current order
and the current response. The slope of Amax is set by the gain K. A block diagram
of alpha max is shown in figure 4.10.

Figure 4.10 Block diagram of Alphamax controller.

4.7 GAMMA0 controller

If, for some reason the rectifier is blocked and the inverter is still operating the
current controller will force the inverter extinction angle, to 110. This can
happen if the communication between the rectifier and inverter is disconnected
and the rectifier is blocked by a protection. The DC voltage will increase rapidly
to a reversed polarity. This phenomenon is prevented by the addition of a
controller GAMMA0. If the DC voltage is lower for a predetermined time, the
function will force the firing angle to about 160 depending on the settings.
A block diagram of the Gamma0 controller is shown in figure 4.11.

20
 0.6 Vd low
x Comparator
inv
& to CCA
&
Vd ref T1
rect
Vd
Comparator T2

0.7 x

0.03 Comparator

GAMMA0
VCA to CCA
Amax

Figure 4.11 Block diagram of the GAMMA0 controller.

The principal function of the controller is shown in figure 4.12. The GAMMA0
controller is activated when the DC voltages becomes less than 0.6Vdref after a
given delay time, T1, the minimum firing angle is set equal to the maximum firing
angle, 110 = max. If the DC voltage is re-established before T1 is expired the
control is deactivated, otherwise the control is not deactivated until the DC
voltage rises above 0.7Vdref, and after a delay time T2.

Vd
0.7Vd
0.6Vd

time

T1 T2
max

time

Figure 4.12 Principal function of the GAMMA0 controller.

21
5 Results
This chapter presents the results from the simulations to evaluate the simplified
control model, transient over voltages generated in the AC and DC system are
calculated in the two models. Corresponding arrester stresses in form of current,
voltage and energy are compared between the models.

The energy in the arresters as shown in figure 5.1 was evaluated assuming a time
of 60 ms after the fault was applied, 10 ms for the fault detection and 50 ms for
the breaker opening.

V V V

V V V
DC EM
AC
system Filters
A2 A V V V

Filter
Subbank V V V

EL

Figure 5.1 Arrester schemas.

5.1 Ground fault between the valve bridge

and the converter transformer
The valve is in bipolar operation, single-phase ground fault between Yy converter
transformers and a valve in the upper three-pulse commutating group were
applied at time t =1.5 s.

5.1.1 Valve arrester stresses

Arrestors are connected in parallel with each thyristor valve (arresters V in figure
5.1). This fault will stress the three-pulse commutation group on the highest
potential.

22
Operation mode was ground return and the prefault conditions on the DC side
were:
Vd =1.0 p.u. (= 500 kV), Id =0.1 p.u. (= 300 A)
The following cases were investigated:
Only ground fault, without control action.
Ground fault and delayed with by-pass pair.
The following three alternative by-pass pairs were
studied:
o By-pass of valve 1 and 4
o By-pass of valve 2 and 5
o By-pass of valve 3 and 6

A summary of the results is presented in table 5.1 and 5.2

Table 5.1 Detailed model.

Case By-pass Delay Max Max
pairs in bpp Current energy Figure
[ms] [kA] [MJ]
1 no - 1.02 2.7
2 1-4 4 0.95 1.9
3 2-5 6 0.43 0.8
5.2a
4 3-6 9 1.02 2.8
5.3a

Table 5.2 Simplified model.

Case By-pass Delay Max Max Figure
pairs in bpp Current energy
[ms] [kA] [MJ]
1 no - 1.02 2.8
2 1-4 4 0.65 1.8
3 2-5 6 0.43 0.8
5.2b
4 3-6 9 1.02 2.8
5.3b

Figure 5.2, 5.3 and 5.4 shown the energies, currents and voltages in the arrestors
parallel with upper group of the thyristors connected to Yy-transformer and figure
5.5 shown the DC voltage in the rectifier of case 4. Case 4 generates more energy

23
than the other four cases. The energy difference between the detailed and the
simplified model is approximately 2 % (26 kJ), where the detailed model
generates more energy in the surge arrestors during the fault. The current graph
peaks at t =1.51 s and the detailed model is 0.3 kA higher. The shape of the
voltage curves over the thyristors (figure 5.4) and the direct voltage (figure 5.5) is
nearly identical.
The shape of the DC voltage curve in the graphs of case 3 and 4 are nearly
perfect. In case 2 the difference in curve shape of the DC voltage between the two
models could be caused by the fact that the bpp is formed in leg 1 and the fault is
applied in phase A that is connected to leg 1.
In case 1, it is approximately 6 % (0.18 MJ) more energy in the surge arresters in
the simplified model compared with the detailed model. Moreover, the shape of
the curves differs between the two models. One reason could be that a by-pass
pair is not formed after the fault and the function of the control has more influence
than in case 2 to 4.

Valve arrester energy Valve arrester energy

3500 3500
Valve 1 Valve 1
Valve 3 Valve 3
3000 Valve 5 3000 Valve 5

2500 2500
Energy [kJ]

Energy [kJ]

2000 2000

1500 1500

1000 1000

500 500

0 0
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.2 Valve arrester energy in case 4.

a) Detailed model. b) Simplified model.

24
 Valve arrester currents Valve arrester currents
0.2 0.2
Valve 1 Valve 1
Valve 3 Valve 3
0 Valve 5 0 Valve 5

-0.2 -0.2

Current [kA]

Current [kA]
-0.4 -0.4

-0.6 -0.6

-0.8 -0.8

-1 -1

-1.2 -1.2
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.3 Valve arrester currents in case 4.

a) Detailed model. b) Simplified model.

Valve arrester voltages Valve arrester voltages

500 500
Valve 1 Valve 1
Valve 3 Valve 3
400 Valve 5 400 Valve 5

300 300

200 200
Voltage [kV]

Voltage [kV]

100 100

0 0

-100 -100

-200 -200

-300 -300
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.4 Valve arrester voltages in case 4.

a) Detailed model. b) Simplified model.

Direct voltage (V d) Direct voltage (V d)

500 500

450 450

400
400

350
350
300
V oltage [k V ]

V oltage [k V ]

300
250
250
200
200
150

150
100

100 50

50 0
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.5 Direct voltage at the rectifier in case 4.

a) Detailed model. b) Simplified model.

25
5.1.2 Stresses on ground return bus arrester
In this test the current and the voltage in the arrestors EL in figure 5.1 on the
electrode line to earth are calculated.
Operation mode was ground return and the prefault conditions on the DC side
were:
Vd =1.0 p.u. (= 500 kV), Id =1.2 p.u. (= 3600 A)
The following cases were investigated:
Only ground fault, without control action.
Ground fault and delayed with bpp.
The following three alternative by-pass pairs were
studied:
o By-pass of valve 1 and 4
o By-pass of valve 2 and 5
o By-pass of valve 3 and 6

The results are summarized in table 5.3 and 5.4.

Table 5.3 Detailed model

Case By-pass Delay Max Max Figure
pairs in bpp Current energy
[ms] [kA] [MJ]
5.6a
1 no - 4.1 3.2
5.7a
2 1-4 4 4.1 2.8
3 2-5 6 4.1 2.9
4 3-6 9 1.02 3.2

Table 5.4 Simplified model

Case By-pass Delay Max Max Figure
pairs in bpp Current energy
[ms] [kA] [MJ]
5.6b
1 no - 3.9 4.6
5.7b
2 1-4 4 4.1 3.5
3 2-5 6 4.1 2.8
4 3-6 9 4.0 2.9

26
Figure 5.6, 5.7 and figure 5.8 shown the energies, currents and voltages in the
arrestors connected on the electrode line to earth and figure 5.9 shown the DC
voltage in the rectifier of case 1.
Case 1 generates more energy than the other three cases. The energy differences
in case 1 between the simplified and the detailed model is 30% (1.4 MJ), where
the simplified model generates more energy in the surge arrestors during the fault.
In case 3 and 4 the differences in surge arrestor energy between the two models is
quite similar. The reason for the larger difference versus the models in case 1
compare to case 3 and 4 is that the fault is followed by bpp in case 3 and 4, where
the controller does not have any influence at the circuit.
In case 2 the simplified model is producing approximately 20% (0.7 MJ) more
energy during the fault compared to the detailed model. In case 3 and 4, fault is
also followed by a bpp and the differences in these cases are 4% (0.1 MJ) and 9%
(0.3 MJ) respectively. The reason for the larger difference in case 2 versus to case
3 and 4 could be that the bpp is formed in leg 1 (thyristors 1 and 4) and the fault is
applied in phase A that is connected to leg 1.
Neutral bus arrester Neutral bus arrester
4 5

4.5
3.5
4
3
3.5

2.5 3
Energy [MJ]
Energy [MJ]

2 2.5

2
1.5
1.5
1
1

0.5 0.5

0 0
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.6 Neutral bus arrester energy in case 1.

a) Detailed model. b) Simplified model.

Neutral bus arrester Neutral bus arrester

0.5 2

0
1
-0.5

-1
0
-1.5
Current [kA]

Current [kA]

-2 -1

-2.5
-2
-3

-3.5
-3
-4

-4.5 -4
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.7 Neutral bus arrester current in case 1.

a) Detailed model. b) Simplified model.

27
 Neutral bus arrester Neutral bus arrester
300 300

200 200

100 100
Voltage [kV]

Voltage [kV]
0 0

-100 -100

-200 -200

-300 -300
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.8 Neutral bus arrester voltage in case 1.

a) Detailed model. b) Simplified model.

Direct voltage (V d) Direct voltage (V d)

600 600

500 500

400 400

300 300

200 200
Voltage [kV]
Voltage [kV]

100 100

0 0

-100 -100

-200 -200

-300 -300

-400 -400

-500 -500
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.9 Direct voltage at the rectifier in case 1.

a) Detailed model. b) Simplified model.

28
5.1.3 Stresses on metallic return bus arrester
In this test the current and the voltage in the arrestors EM in figure 5.1 at metallic
return bus are calculated.
Operation mode was metallic return and the prefault conditions on the DC side
were:
Vd =1.0 p.u. (= 500 kV), Id =1.2 p.u. (= 3600 A)
The following cases were investigated:
Only ground fault, without control action.
Ground fault and delayed with bpp.
The following three alternative by-pass pairs were
studied:
o By-pass of valve 1 and 4
o By-pass of valve 2 and 5
o By-pass of valve 3 and 6

A summary of the results is presented in table 5.5 and 5.6.

Table 5.5 Detailed model

Case By-pass Delay Max Max Figure
pairs in bpp Current energy
[ms] [kA] [MJ]
1 no - 5.6 11.1
2 1-4 4 4.8 3.1
5.10a
3 2-5 6 2.8 20.5
5.11a
4 3-6 9 4.8 15.3

Table 5.6 Simplified model

Case By-pass Delay Max Max Figure
pairs in bpp Current energy
[ms] [kA] [MJ]
1 no - 3.9 6.6
2 1-4 4 3.7 5.1
5.10b
3 2-5 6 2.3 20.1
5.11b
4 3-6 9 3.8 15.5

29
Figure 5.10, 5.11 and 5.12 shows the energies, currents and voltages in the
arrestors connected on the electrode line to earth and figure 5.13 shown the DC
voltage in the rectifier in case 3.
Case 3 generates more energy than the other four cases. The energy difference
versus the detailed and the simplified model is approximately 2 % (0.4 MJ),
where the simplified model generates more energy in the surge arrestors during
thefault.

Neutral bus arrester Neutral bus arrester

2 1.5

1 1

0.5
0

0
Current [kA]

Current [kA]
-1
-0.5
-2
-1

-3
-1.5

-4 -2

-5 -2.5
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.10 Neutral bus arrester energy in case 3.

a) Detailed model. b) Simplified model.

Neutral bus arrester Neutral bus arrester

40 24

22
35
20

30 18
Energy [MJ]
Energy [MJ]

16
25
14

20 12

10
15
8

10 6
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.11 Neutral bus arrester current in case 3.

a) Detailed model. b) Simplified model.

30
 Neutral bus arrester Neutral bus arrester
350 300

300
200
250

200 100
V oltage [kV ]

V oltage [kV ]
150
0
100

50 -100

0
-200
-50

-100 -300
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.12 Neutral bus arrester voltage in case 3.

a) Detailed model. b) Simplified model.

Direct voltage (V d) Direct voltage (V d)

600 600

500 500

400 400

300 300
V oltage [kV ]

V oltage [kV ]

200 200

100 100

0 0

-100 -100

-200 -200
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time [s] Time [s]

Figure 5.13 Direct voltage at rectifier in case 3.

a) Detailed model. b) Simplified model.

31
5.2 Energizing an open DC line
To energizing an open DC line is a test of the OVL controller. When energizing
an open DC line high voltage will be generated as described in section 4.4
Overvoltage Limiter.
The figures below show the DC voltage and current in the rectifier during a
simulation. The rectifier is started at time t=0.3 s and the inverter is never
deblocked. As seen in figure 5.15 the direct current is nearly zero and the direct
voltage stabilizes at 1.0 p.u. in figure 5.14a and at 1.15 p.u in figure 5.14b. In the
detailed model the OVL controller regulate the DC voltage when it is above 1.15
p.u. (between 0.41-0.48 s in figure 5.14a), after which the Voltage controller
adjust the DC voltage to 1.0 p.u. In the simplified model the OVL controller
regulates the DC voltage to the reference value 1.15 p.u. and remain at that
reference. In the simplified control model, the Voltage controller cannot act on the
lower limit of the CCA and thus cannot regulate the DC voltage to 1 p.u.

Direct voltage (V d) Direct voltage (V d)

1.4 1.2

1.2 1

1
0.8

0.8
Voltage [p.u.]
Voltage [p.u.]

0.6
0.6
0.4
0.4

0.2
0.2

0 0

-0.2 -0.2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time [s] Time [s]

Figure 5.14 Direct voltage at rectifier.

a) Detailed model. b) Simplified model.

Direct current (Id) Direct current (Id)

0.8 0.8

0.7 0.7

0.6 0.6

0.5 0.5
Current [p.u.]

Current [p.u.]

0.4 0.4

0.3 0.3

0.2 0.2

0.1 0.1

0 0

-0.1 -0.1
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time [s] Time [s]

Figure 5.15 Direct current.

a) Detailed model. b) Simplified model.

32
5.3 Lost of AC network at inverter
This test is to dimension the surge arrestors at the AC bus, where its arrestors
protect the AC side of the converter transformer and the AC filter buses. The
prefault conditions on the DC side and the AC-side were nominal voltages and the
current and the AC network were strong on rectifier side and weak on the inverter
side. At t=1.5s the AC line breakers at the inverter side opens and remains open
the reaming time of the simulation.
Figure 5.16 shown the AC bus voltage between the inverter and the AC breakers.
When the breakers open at the inverter the AC voltage is oscillating between the
filter subbank and the converter transformers. This oscillating is reduced faster in
the detailed model compared to the simplified model. However it is not possible
to compare the two models because the prefault in alpha order is 134 in the
detailed model and 141 in the simplified model, as shown in figure 5.18, but the
result of this test is that the behavior of the simplified control system is not equal
to the detailed model during this kind of fault.
AC bus voltage AC bus voltage
800 800
Phase A Phase A
Phase B Phase B
600 600 Phase C
Phase C

400 400

200 200
Voltage [kV]
Voltage [kV]

0 0

-200 -200

-400 -400

-600 -600

-800 -800
1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.59 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.59
Time [s] Time [s]

Figure 5.16 AC bus voltage.

a) Detailed model. b) Simplified model.

Direct voltage (V d) Direct voltage (V d)

800 800

600 600

400 400
Voltage [kV]
Voltage [kV]

200 200

0 0

-200 -200

-400 -400

-600 -600

1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.59 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.59
Time [s] Time [s]

Figure 5.17 Direct voltage at inverter.

a) Detailed model. b) Simplified model.

33
 Alpha order Alpha order
150 170

140 160

130 150

120 140
Degrees

130

Degrees
110

100 120

90 110

100
80

90
70

1.4 1.5 1.6 1.7 1.8 1.9 2 80

1.4 1.5 1.6 1.7 1.8 1.9 2
Time [s]
Time [s]

Figure 5.18 Alpha order at the inverter.

a) Detailed model. b) Simplified model.

34
5.4 Commutation failure
The system is disturbed at the AC bus on the inverter side with an inductance of
0.05 H at each phase. The AC network is strong on the rectifier side and weak on
the inverter side. The disturbance is applied at t=1.5s and the fault duration is
50ms.
This test is to investigate the stability of the HVDC system and to investigate how
the control system can take care of load disturbances. As shown in figure 5.19a
and 5.19b the inverter AC voltage is quite similar for both models. This is due to
the isolating converter transformer between the converter and the AC system.
The differences in alpha-order between the detailed and the simplified model are
caused by a function named Commutation Failure Prediction (CFPRED) included
in the detailed model but not in the simplified model. The function of CFPRED is
to detect one and three phase AC faults. The detection of AC faults will give an
angle reduction in the Alphamax controller. As shown in figure 5.21a, the alpha
order decreases when the fault is applied and is dependent on CFPRED.

AC bus voltage AC bus voltage

500 500
Phase A Phase A
400 Phase B 400 Phase B
Phase C Phase C
300 300

200 200

100 100
Voltage [kV]
Voltage [kV]

0 0

-100 -100

-200 -200

-300 -300

-400 -400

-500 -500
1.5 1.52 1.54 1.56 1.58 1.6 1.5 1.52 1.54 1.56 1.58 1.6
Time [s] Time [s]

Figure 5.19 AC bus voltage.

a) Detailed model. b) Simplified model.

Direct voltage (V d) Direct voltage (V d)

600 600

500
500
400

400 300

200
Voltage [kV]

Voltage [kV]

300
100

0
200
-100
100 -200

-300
0
-400

-100 -500
1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2
Time [s] Time [s]

Figure 5.20 Direct voltage at the inverter.

a) Detailed model. b) Simplified model.

35
 Alpha order Alpha order
152 160

150 155

148 150

146 145

Degrees
Degrees
144 140

142 135

140 130

138 125

136 120
1.4 1.5 1.6 1.7 1.8 1.9 2 1.4 1.5 1.6 1.7 1.8 1.9 2
Time [s] Time [s]

Figure 5.21 Alpha order at the inverter.

a) Detailed model. b) Simplified model.

36
6 Discussion
In this chapter there will be a discussion about problems that arose during the
work, possible reasons for their occurrences and suggestions on how to continue
with this work.

6.1 The project

During the project, there have been different kinds of problems comparing the
simplified model with the detailed model. The most serious problem was in 5.1
Ground fault between the valve bridge and the converter transformer. The
control in the simplified model and the detailed model did not form a bpp in the
same leg after the fault was applied, even though the delay time was the same
between the fault and the bpp. The reasons could be that the function forming a
bpp was not the same in the two models, or that the shape of the AC voltage is not
exactly the same after the fault was applied and as a result a commutation from
one thyristor to another did not occur at the same time in the two models. To solve
this problem the functions controlling the bpp was forced to get the same tyristor
pairs in the two models.
Another problem during the work was a displacement in the AC voltage between
the models where, the point of wave at the AC voltage when the fault was applied
was not exactly the same. A function that applied the fault at the same voltage
amplitude was designed although, the fault was applied with a time difference of a
few micro seconds. Since the time difference was short, it should not have
affected the results.

6.2 Future work

To make the simplified control function more like the specific control, a couple of
functions can be added and improved. An essential function is the one that decides
the reference voltage in the inverter and rectifier.
The VDCOL function is especially important at a AC faults. The VDCOL that is
used in the simplified control has been copied from the PSCAD master library and
modified. My opinion is that one should try to make a VDCOL that operate
exactly as the VDCOL in the detailed model.
The test described in 5.2 Energizing an open DC line, did not function correctly
since the Voltage controller was not modulated on the lower limitation in the
CCA. If this function is added the test will work more properly.
At an AC fault, the simplified control was not able to fulfill the task. The reason
could be that the simplified control lacks the function CFPRED, as mentioned in

37
5.4. Commutation failure. To make the simplified control work correctly, the
function CFPRED could be tried.

38
7 Conclusions
In this master thesis, I have developed a simplified control system to HVDC
Classic based on the control function from ABB Power Systems by using the
EMTDC simulation program with PSCAD v.4.2 user interface. The control is a
basic control that can easily be used for different projects. Further, the control
model will mainly be used to dimension surge arresters for different disturbances
that are applied in the systems.
Through simulation I have shown that during single-phase ground fault
disturbances between the converter transformers and the rectifier (surge arresters
is connected in parallel with each thyristor valve), the current and the voltage
curve shapes are practically the same independent of which model is used. In the
case of a bpp formation in leg 3 more energy will be generated compared to the
other four cases. The detailed model generates 2 % more energy than the
simplified model which is a highly acceptable result.
The current and voltage curve shapes in the surge arrestors connected to the
neutral line deviate in some cases. When a bpp is not followed by a fault is
applied the energy difference in the surge arrestors is 30 % more in the simplified
versus the detailed model. One reason to the large differences could be that the
converter is not the same in the two models. However, the shape of the DC
voltage when the system is disturbed is practically the same when the simplified
control model is used compared to the detailed model. This is probably the best
result one can expect with a simplified control. Unfortunately the simplified
model cannot control the DC voltage when there is a disturbance in the AC
network. Therefore future development is required before the simplified control
can be used in the design of the surge arresters.

39
8 References
[1]. M. Szechman, T. Wess, & C.V. Thio. First benchmark model for HVDC
control studies, CIGRE WG 1991:14(2); 5473.
[2]. M. O. Faruque, Y. Zhang, V. Dinavahi. Detailed Modeling of CIGRE
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30 th ASEE/IEEE Frontiers in Education Conference, Kansas City 2000

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Appendix A
CCA

41
VDCOL

42
Voltage controller

43
Alphamax controller

44
Gamma0 controller

45
Over voltage limiter

46
RAML

47