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Code: 9D57101 / 9D57101b

M. Tech I Semester Regular & Supplementary Examinations, April/May 2013

VLSI TECHNOLOGY
(Common to VLSIS, VLSISD, VLSI, VLSID & ES)
Time: 3 hours Max. Marks: 60
Answer any FIVE questions.
All questions carry equal marks.

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1 (a) Compare bipolar technologies with MOS technologies and hence explain about Bi-
CMOS technology.
(b) Explain why NMOS technology is preferred to PMOS.

L D
With the help of MOS transistor circuit model derive an expression for threshold voltage
and hence explain how it can be varied during fabrication process.

3 (a)

(b)

O R
Derive an expression for drain current of MOS transistor and explain how it varies with
(i) Drain voltage (ii) Gate voltage (iii) W/L ratio (iv) Mobility of carriers.
Discuss the effects of varying Zpu / Zpd ratio on the transfer characteristics of inverter
in NMOS technology.

4 (a)
(b) W
Explain the design and working of three transistor DRAM cell.

U
With the help of transistor schematic explain the design of a two input AND gate in

T
domino logic.

N
5 (a) Explain lambda based design rules that govern the layout of individual components,
interacting-spacing and electrical connections between the components in CMOS

6
(b)

(a)
(b)
J
technology.
Draw the layout diagram of three input NAND gate in CMOS.

With suitable examples explain about network delays combinational logic circuits.
Implement an n-bit shift register and explain its operation over one clock cycle.

7 (a) Discuss about two architectural methods for reducing power consumption.
(b) What is meant by latch-up in CMOS circuits?

8 Write about the following:

(a) Design validation and testing.
(b) Logic synthesis.

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