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Reconfigurable hardware components: FPGA

• Classification

• FPGA
• Basic logic cells
• Routing strategies
• Configuration methods

• PLA/PAL

• Design flow

• eFPGA

• Examples
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 1
Classification of digital integrated circuits (see Section 2.2.3 )

programmable programmable Application


standard logic specific logic
architectures

µP
Semi
custom Full
µC custom
DSP

(E)EPROM
gate standard
(P)ROM FPGA array cells
PAL/PLA CPLD
RAM

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 2


Features of FPGA implementation against ASICs

Advantages
• fast and cheap procedure for implementing hardware
• fast functional verification
• low cost of low-volume production
• improved time-to-market
• re-configurability in the field

Disadvantages
• non-optimal utilisation of silicon area
• signal delay and power consumption are high
• routing problems could limit flexibility
• potential clock-skew problems

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 3


Business/market models for FPGAs

OTP-architectures (one time programmable)


• derivatives of standard devices
• low cost of customisation for low quantities
• fast time-to-market for low volume designs

Re-programmable architectures
• prototyping and functional development on standard platforms
• in-field customisation and updating
• multiple-application hardware

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 4


Basic building blocks of FPGAs (see Section 2)

Logic blocks
(CLB)

Memory blocks
(configuration)

Wiring and
interconnect

Interface blocks

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 5


Basic architectures of FPGAs (see Section 2.1)
Routing
channel Routing
channel

Symmetric matrix (a)

Logic
module
Row of cells (b)

(a) Logic module (b)

Routing channels overlaid


Sea of cells (c) on logic modules
(no dedicated routing channels)
Logic
module
Routing
channel
Logic
Hierarchical architecture (d) module

(c) (d)
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 6
Basic elements of Configurable Logic Cells (CLC)

Logic elements
• Transistors
• Basic gates (NAND, XOR, ... )
• Flip-flops
• Multiplexers
• Look-up tables (LUTs)
• AND-OR arrays (sum-of-products)

The term granularity refers to a quantification of the complexity of the CLC and
can depend on the following:
• Number of logical functions which may be implemented by each CLC
• Number of equivalent NAND2 gates of each CLC
• Total number of transistors that physically constitute the CLC

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 7


Granularity of FPGAs (see Section 2.2)

High granularity FPGA Low granularity FPGA


low complexity CLC High complexity CLC
Large number of CLCs Smaller number of CLCs
Complex routing resources Simpler routing resources

Transistor/Gate LUT PAL/PLA µP/ALU

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 8


Multiplexer based CLB (configurable logic block) (see Section 2.2.1 )

Multiplexer based CLB

example from Actel 40MK

8-input, 1-output cell

implements basic logic


functions (and, or, nor, ..) with
2,3, or 4 inputs

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 9


Look-up table (LUT) based CLB (see Section 2.2.2 )

LUT based CLB

depending on the
combination of the input
words, a predefined
output value is assigned

Memory implementation:

input values =
address of memory

predefined values =
content of memory
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 10
Registered output based CLB

The output of the LUT may be registered or not, depending on the


functional description (selection is implemented via multiplexers)

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 11


CLB with registered output

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 12


CLB with registered output

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 13


LUT output based CLB

LUT with four inputs A B C D O/p

only three inputs are used 0 0 0 x 0


0 1 0 x 0
input D is a dont’care
1 0 0 x 1
1 1 0 x 1
0 0 1 x 0
Exercise:
extract the logic function!
0 1 1 x 1
1 0 1 x 0
1 1 1 x 1

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 14


LUT based CLB

Example from Actel


Varicore CLC:

LUT based

Multiplexer to decrease
LUT size

Registered output via


multiplexer selectable

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 15


LUT output based CLB

Example from Xilinx


XC3000:

Dual output complex


CLB

registers selectable

large combinational
function with two outputs

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 16


Complex programmable logic device (CPLD) (see Section 2.2.3 )

Simple
programmable logic
devices (SPLD) are
used to implement
the logic functions

PAL or PLA arrays

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 17


SPLD based on PAL implementation

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 18


PLA architecture (see Appendix A)

PLA consists of two ‘planes’:

the and-plane to build the min-terms

the or-plane to build the output values

the connections between input signals


and and-plane and between the planes
are flexible

PAL is a PLA with fixed OR-plane

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 19


FPGA design flow (see Section 3)
Design Entry
(VHDL, verilog, schematic)

Logic Synthesis
(VHDL, verilog, schematic)

Floorplanning
(VHDL, verilog, schematic)

Place and Route


(VHDL, verilog, schematic)

Layout Verification
(VHDL, verilog, schematic)

Macro Integration
(VHDL, verilog, schematic)
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 20
Routing strategies for FPGAs (see Section 2.3)

Four types of routing networks are needed in an FPGA device:

• Power feeding network


• Reset and multiple clock networks (local / global)
• Signal network interconnecting all cells
• Configuration lines

A strategy adopted by most manufacturers to different extent is the structuring


of the device into some sort of hierarchy, by segmenting the array into groups
of CLCs. Routing lines interconnecting the cells could then be broadly
classified into three different types:

• Local routing lines directly interconnecting neighbours


• Interconnects to route signals within a cluster of cells
• Global interconnects to transmit signals throughout the whole FPGA

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 21


Implementation of routing channels

Routing hierarchy:
• global lines
• double length lines
• local lines

switching nodes to
connect
neighbouring
modules

local switch for a


single bit with six
transistors

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 22


Electrical model of FPGA routing track

Complex routing model


crossing various
hierarchies of the FPGA
requires very accurate
electrical modelling for
place & route

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 23


Configuration of FPGAs (see Section 2.4)

FPGA devices allow the configuration of all CLCs, I/O cells and interconnect resources.
The gate of each configurable transistor is controlled by the contents of a 1-bit memory
cell, with a logic '0' or logic '1' determining whether the gate is off or on. To reduce the
wiring required for configuration, the memory cells can be connected in a chain and the
configuration is then loaded using a shift operation. Depending on the physical
configuration mechanism, it is possible to classify FPGAs into three classes:

• One-time configurable devices


• Non-volatile re-configurable devices
• Volatile re-configurable devices

One-time programmable devices store configuration using fuses or anti-fuses. The


former are normally closed structures, while the latter are normally open. A device based
on fuse technology is programmed by physically breaking the connections between
appropriate structures. On the other hand, a device based on anti-fuses is programmed
by melting interconnections between particular cells to generate contacts.

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 24


Implementation of FPGA configuration

Pass structure and tri-state buffer controlled by locally stored configuration


information (SRAM cells)

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 25


Configurable output cell of a FPGA (see Section 2.6)

Example from Xilinx


XC4000C Series IO-cell

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 26


ATMEL AT94K field programmable system level integrated
circuit (FPSLIC)

5-40 Kgates FPGA

8-bit microcontroller

various peripheral
units

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 27


ATMEL AT94K FPSLIC: technical data

IC Characteristics AT94K05AL AT94K10AL AT94K40AL

Process Parameter (2l) 0.35m 0.35m 0.35m


Metallisation Layers 5 5 5
Supply Voltage 3.0 - 3.6 V 3.0 - 3.6 V 3.0 - 3.6 V
System SRAM Block Size 24K x 8 36K x 8 36K x 8
CISC or RISC RISC RISC RISC
Embedded Register Size 8 bits 8 bits 8 bits
mPC Clock Freq. 20 / 40 MHz 20 / 40 MHz 20 / 40 MHz
MIPS 19 / 30 19 / 30 19 / 30

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 28


ATMEL AT94K FPSLIC: technical data
FPGA Macro Architecture AT94K05AL AT94K10AL AT94K40AL

CLCs 256 576 2304


Array of
Configurable CLC Type LUT LUT LUT
Logical Cells Registers / CLC 1 1 1
(CLCs)
LUTs / CLC Size 2 8x1 2 8x1 2 8x1
Matrix Structure Symmetric Symmetric Symmetric
Equivalent ASIC Gate Count 5000 10000 40000
Max. I/O Lines Available to User 96 144 288
Typ. Core Power Consumption 6 mW / MHz 6 mW / MHz 6 mW / MHz
Method of Configuration Storage SRAM SRAM SRAM
Re-configurability Volatile Volatile Volatile
Blocks 16 32 144
Distributed RAM Block Size 32x4 32x4 32x4
Total Size 2048 bits 4608 bits 18432 bits

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 29


ATMEL AT94K FPSLIC: array of CLCs

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 30


ATMEL AT94K FPSLIC: 16x16 array of CLCs

Hierarchical routing
scheme

CLC are connected to


the eight (!)
neighbours

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 31


ATMEL AT94K

One of five identical


bus planes
connecting
neighbouring CLBs

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 32


ATMEL AT94K FPSLIC: bus plane

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 33


ATMEL AT94K FPSLIC: LUT based CLC

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 34


ATMEL AT94K FPSLIC: design flow

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 35


Actel Varicore: embedded FPGA
Varicore Architecture V18L2x1 V18L2x2 V18L4x1 V18L4x2

CLCs 512 1024 1024 2048


Array of
Configurable CLC Type LUT LUT LUT LUT
Business model: Logical Cells
(CLCs)
Registers / CLC 1 1 1 1
LUTs / CLC Size 2 8x1 2 8x1 2 8x1 2 8x1
Sea of Sea of Sea of Sea of
Matrix Structure
Cells Cells Cells Cells
embedded FPGA for Equivalent ASIC Gate Count 5000 10000 10000 20000

various circuits and Max. I/O Lines Available to User 224 320 352 448
Process Parameter (2l) 0.18m 0.18m 0.18m 0.18m
applications
Metallisation Layers 5 5 5 5
Supply Voltage 1.8 V 1.8 V 1.8 V 1.8 V
eFPGA array can be Max. Clock Frequency 250 MHz 250 MHz 250 MHz 250 MHz
adapted in Typ. Core Power Consumption 2.4 mW / 2.4 mW/ 2.4 mW/ 2.4 mW/

performance and size! MHz MHz MHz MHz


Method of Configuration Storage SRAM SRAM SRAM SRAM
Re-configurability Volatile Volatile Volatile Volatile
System SRAM Block Size NA NA NA NA
Blocks NA NA NA NA
Distributed RAM Block Size NA NA NA NA
Max. Amount NA NA NA NA

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 36


Actel Varicore: embedded FPGA
FPGA Macro Characteristics V18L4x4 V18L2x2R V18L4x2R V18L4x4R

CLCs 4096 1024 2048 4096


Array of
Configurable CLC Type LUT LUT LUT LUT
Logical Cells Registers / CLC 1 1 1 1
(CLCs)
LUTs / CLC Size 2 8x1 2 8x1 2 8x1 2 8x1
Matrix Structure Sea of Cells Sea of Cells Sea of Cells Sea of Cells
Equivalent ASIC Gate Count 40000 10000 20000 40000
Max. I/O Lines Available to User 6140 320 448 6140
Process Parameter (2l) 0.18m 0.18m 0.18m 0.18m
Metallisation Layers 5 5 5 5
Supply Voltage 1.8 V 1.8 V 1.8 V 1.8 V
Max. Clock Freq. 250 MHz 250 MHz 250 MHz 250 MHz
2.4 mW / 2.4 mW / 2.4 mW / 2.4 mW /
Typ. Core Power Consumption
MHz MHz MHz MHz
Method of Configuration Storage SRAM SRAM SRAM SRAM
Re-configurability Volatile Volatile Volatile Volatile
System SRAM Block Size NA 36864 bits 73728 bits 73728 bits
Blocks NA NA NA NA
Distributed RAM Block Size NA NA NA NA
Max. Amount NA NA NA NA

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 37


Actel Varicore: embedded FPGA

Hierarchy of PEG (processor


element groups, processor groups
and functional groups)

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 38


Actel Varicore: embedded FPGA

Top level view on the 4x4


PEG array

local RAMs for user needs

• configuration RAM
• BIST interface (build in
self-test)
• JTAG interface for test
access and programming

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 39


Actel Varicore: embedded FPGA

Array of functional groups


inside PEG

Functional group consists for


four LUT including registers

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 40


Actel Varicore: embedded FPGA

Basic configuration of
CLB for DSP-like
applications

split LUT

selectable register

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 41


Actel Varicore: design flow

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 42


Actel Varicore: embedded FPGA conclusion

Embedded FPGA will bring


• higher flexibility to ASIC systems
• better cost efficiency to processor systems

The size of the embedded FPGA can be adapted to the problem/application

The design flow is compatible with a standard ASIC design flow

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 43


FPGA conclusion

The market for re-programmable solutions is steadily increasing

FPGA are taking market shares from the ASIC business for low volume
products

Embedded FPGAs allow to build systems with the best from all worlds:
• general purpose processor cores
• optimised and adapted µP/µC cores for special applications
• flexible hardware modules (eFPGA) for time critical tasks
• area and speed optimised ASIC parts for certain time critical tasks

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 44