Dalavai Devarajulu

Mobile: +91-9916605070, E-mail: dalavaideva@gmail.com

Career Objective:
To become a key technical resource for an organization, where I am able to explore my
full potential, add to my learning curve, as well as contribute effectively and efficiently to
achieve organizational goals.
Experience:
Overall experience of over 3 years of industry experience.
2nd Jan 2017 to till date working at Tessolve Semiconductors Pvt. Ltd. as a Design
Engineer.
27th Jun 2016 to 23nd Dec 2016 working as a Component Engineer in HVT
Technologies Pvt Ltd, Bangalore.
04th Sep 2013 to 23nd Jul 2015 working as a Component Engineer in LG CNS Pvt
Ltd , Bangalore.
Expertise in FPGA based RTL implementation using VHDL/Verilog, functional
verification, hardware board bring-up and debugging.
Proficient in RTL design, simulation and synthesis using Xilinx ISE, Vivado tools.
Educational Qualification:
Bachelor of Technology in Electronics and Communication Engineering at JNTU
Anantapur in 2013 with 74.81%.
Board of Intermediate (M.P.C) in 2009 with 80.1%.
Board of Secondary Education (SSC) in 2007 with 87.66%.
Certification/Course:
VLSI Design and Verification Certified Engineer from Sandeepani School of
Embedded Design.
Technical Skills:
Languages : C
HDLs : Verilog, System Verilog
EDK Tools:
Xilinx ISE / VIVADO, Questa sim, Chipscope
Hardware used:
Spartan 3E and Spartan 6
Operating Systems
Windows, Linux
Area of interest:
RTL Design.
FPGA Design.
ASIC Design
Roles at Tessolve Semiconductors Pvt. Ltd.
Role: Design Engineer
Working on ASIC designs.
Low power design techniques.
Clock gating for low power.

Project(s) :
Current Project : Design of low Speed Protocol I2C in ASIC Level:
Description: Development of I2C IP interfaced with APB Slave. It is designed in ASIC level
verilog coding
Role: RTL Design Engineer
Understanding the specifications and features of the protocol.
Writing Verilog code for development of I2C IP.
RTL coding in Verilog, FSMs.
Simulation and Debugging of test cases using Xilinx ISim simulator.
System Generator Schematics, Synthesis.
Creating design documents.
Academic Projects:
1. Design and Implementation of VGA Controller
Description: The aim of the project is to design and implement VGA Controller which
can generate the Control Signals according to standard VGA timings to print Horizontal,
Vertical colour spectrum of 640x480 pixels. The design is compatible and has a high
potential to be used in Xilinx FPGA-based systems.
Software Tools: Xilinxs ISE Design Suite 14.2
Hardware: Xilinxs Spartan-3E Starter Kit, Monitor, VGA and JTag Cable

2. Design, Implementation and Development of Verification Environment For

Round Robin Arbiter Using System Verilog
Description: The aim of this project is to design, implementation and develop a
constraint random coverage driven verification test bench architecture using system
verilog for round robin arbiter (RRA). The RRA is based on a priority logic and ring
counter. The test bench architecture consist of one stimulus generator, 2 Drivers, 2
DUT(reference, model), 2 Monitors and 1 Scoreboard and we used code coverage
and function coverage metrics to prove design is working effectively under Frequency
of 620MHz.
Software Tools: QuestaSim 6.6, Xilinx ISE Design Suite 14.2

ACCOMPLISHMENTS
Received award on Accomplishment and Outstanding Performance at LG
CNS India Pvt Ltd in Mar 2014.

Hobbies: Reading books, playing cricket, net surfing, making new friends.
Personal Details:
Date of Birth : 30rd, Aug 1992
Father : Dalavai Venkatesulu Reddy
Sex : Male
Address : #2, 1st floor, 1st Main road, Munihanumaiah colony, RMV 2nd Stage
Extn, Lottegolla Halli, Bangalore-560094
Languages known : English, Kannada, Telugu, Tamil.

I hereby declare that the above mentioned details are true to the best of my knowledge and
belief.
Date: Declaration
Place: Bangalore Dalavai Devarajulu