I

CERTIFICATE BY STUDENT

\This is to certify that PRATUL NIJHAWAN has undergone the training on "VLSI DESIGN
and Illustrated a project on Implementation of Image Edge Detection Techniques using
Verilog HDL and displayed it on Screen using FPGA", under my guidance and supervision.
He is the sole author of this report and the work carried out by him in the field of Digital Image
Processing using Verilog HDL presents an idea of how one field of Electronics may work with
the other producing efficient and accurate results. He has given best of his efforts in carrying out
his work with the available resources.
This is also to certify that the matter embodied in this dissertation has not been submitted earlier
in any institute/university for the award of degree/diploma to the best of my knowledge and
belief.
I wish him all the best for his future career.

Supervisor Head Of Department

Er. Devender Saini Prof. Bijender M'dia
(Assistant Professor)
Department of Electronics and Comm. Department of Electronics and Comm.
Gurgaon Institute of Tech. & Mgmt.

II
 ORGANIZATION PROFILE

DKOP Labs Pvt. Ltd. ( Earlier Design KOP Labs ) is a Research and Training company in VLSI
Design, Software & Embedded Systems. It is founded by a team of highly experienced and
qualified Semiconductor & EDA Industry Professionals. The Training Division of DKOP Labs
Pvt Ltd conducts various industrial training programs in VLSI Design, Software Development &
Embedded Technology. They conduct Summer Training in VLSI Design, Six Months Industrial
Training in VLSI Design, Summer Training in Software Development, Six Months Industrial
Training in Software Development, and Six Months Industrial Training in Embedded
Technology. They had observed for quite some time that the interview-to-selection ratio was
drastically going down. Companies screen 100s of candidates to fill one single position. Lot of
human resource is wasted in the process and it is primarily because the candidates are not
industry-ready although they may have scored good marks in the academics. They had observed
for quite some time that the interview-to-selection ratio was drastically going down. Companies
screen 100s of candidates to fill one single position. Lot of human resource is wasted in the
process and it is primarily because the candidates are not industry-ready although they may have
scored good marks in the academics.

III
 ACKNOWLEDGEMENT

It is my pleasure to acknowledge the help that I received from different individuals during the
completion of my project.

My first sincere appreciation and gratitude goes to respected Dr.Kamal Thakur,

(Director,Gurgaon Institute of Technology And Management,Gurgaon) for encouragement
and unstinted support given by him.

I would like to acknowledge the continuous guidance and incessant support rendered by Prof.
Bijender MDia, Head of the Department, Electronics and Communication Engineering not
only for this project but also in my overall career development.

Also, it gives me immense pleasure to express my sincere and wholehearted sense of gratitude to
my esteemed training supervisor Er. Devender Saini (Assistant Professor, ECE
Department,GITM) for his invaluable and untiring guidance and supervision throughout this
session. To derive benefits of the enormous experience of above listed people, it is a matter of
great privilege for me.

I am grateful to Mr. NITIN KUMAR TIWARI (Project Manager, DKOP Labs Pvt Ltd.) for his
guidance and suggestions that helped me in the preparation of this project. Also, I would also like
to extend my thanks to Mr. Manu Lauria (Chairman & Director, Strategic Partnerships, DKOP
Labs Pvt. Ltd.) , Mr.Devender Khari(CEO & Director, Business Development , DKOP Labs
Pvt. Ltd.) for providing me with the an atmosphere of healthy learning through their well
equipped labs with latest tools available.

Morale boosting and support from the family , all the faculty members and friends is also
acknowledged.
-Pratul Nijhawan
(12-ECE-135)

IV
 ABSTRACT

The advancement in the VLSI technology has led to innovations in almost every other field in the
Electronics and Communication. Digital Image Processing lays a prominent example where the
algorithms which were earlier limited to the software implementations only were slow due to the
limited processor speed which has been significantly enhanced by the advancements in VLSI
Technology. The project presents three fundamental edge detection algorithms : (i)XOR operator
, (ii) Sobel operator and (iii) Prewitt Operator for the detection of edges of a given input image,
which is coded using Verilog HDL and synthesized using XILINX ISE Design Suite and finally
implemented on FPGA (Digilent Nexys 2 - XC3S500e using the XILINX Spartan 3e Board with
gate count of 500K). Here, due to limitations of the pins of FPGA and for simplicity of
calculations I have converted the input image to 90*90 using MATLAB.

V
 DECLARATION
I hereby certify the work which is being presented in the TRAINING REPORT on VLSI
DESIGN(Illustrating a project on Implementation of Image Edge Detection Techniques using
Verilog HDL and displaying it on Screen using FPGA) by Pratul Nijhawan in partial fulfillment
of requirements for the award of degree B.Tech (Electronics and Communication
Engineering) has been submitted in the Department of ELECTRONICS &
COMMUNICATION ENGINEERING, Gurgaon Institute of Technology and Management,
Gurgaon (affiliated to Maharashi Dayanand University, Rohtak) is carried out during a period
from Feb 8 2016 to June 2016 under the supervision of Er Devender Saini(Assistant Professor,
Department of Electronics And Communication Engineering, GITM, Gurgaon). The matter
presented in this project has not been submitted by anyone in any University/ Institute for the
award of any Degree/ diploma.

-Pratul Nijhawan

(12-ECE-135)

VI
 TABLE OF CONTENTS

CERTIFICATE ......................................................................................................................... I
CERTIFICATE BY STUDENT ............................................................................................... II
ORGANIZATION PROFILE ................................................................................................... III
ACKNOWLEDGEMENT ......................................................................................................... IV
ABSTRACT ................................................................................................................................ V
DECLARATION ........................................................................................................................ VI
TABLE OF CONTENTS ................................................................................... VII
LIST OF FIGURES .......................................................................................... XIII
LIST OF EXAMPLES .................................................................................
LIST OF TABLES AND FORMULAE .............................................................

CHAPTER 1 INTRODUCTION................................................................................................. 1
1.1 VLSI ..................................................................................................................................... 1
1.2 EDA ...................................................................................................................................... 2
1.3 VERILOG HDL ................................................................................................................... 1
1.4 IMAGE PROCESSING ....................................................................................................... 2
1.5 EDGE DETECTION ............................................................................................................ 2
1.6 MOTIVATION ..................................................................................................................... 2
1.7 FIELD PROGRAMMABLE GATE ARRAY (FPGA) ........................................................ 3

CHAPTER 2 VERY LARGE SCALE INTEGRATION(VLSI) AND ELECTRONIC

DESIGN AUTOMATION(EDA) ....................................................................................... 1
2.1 VLSI .........................................................................................................................................
2.1.1 HISTORY OF VLSI....................................................................................................
2.1.2 DEVELOPMENTS ...........................................................................................................
2.1.3 STRUCTURED DESIGN..................................................................................................
2.1.4 VLSI DESIGN FLOW.......................................................................................................
2.1.4.1 DESIGN STEPS IN VLSI FRONTEND .....................................................................
2.1.4.2 DESIGN STEPS IN VLSI BACKEND .......................................................................
2.1.4.3 FLOWCHART FOR VLSI DESIGN ..........................................................................
2.1.5 CHALLENGES TO VLSI .................................................................................................
2.2 EDA..........................................................................................................................................
2.2.1 History of EDA ...................................................................................................................
2.2.1.1 Early Days ....................................................................................................................

VII
 2.2.1.2 Birth of Commercial EDA ..........................................................................................
2.2.2 Current Status of EDA ........................................................................................................
2.2.3 Software Focuses of EDA Industry ...................................................................................
2.2.3.1 Design ........................................................................................................................
2.2.3.2 Simulation ..............................................................................................
2.2.3.3 Analysis and verification ...........................................................................
2.2.3.4 Manufacturing preparation ..........................................................................

CHAPTER 3 DESCRIPTION OF THE TOOLS USED ........................................................

3.1 XILINX ISE DESIGN SUITE ............................................................................................

3.1.1 User Interface ..................................................................................................................
3.1.2 Simulation ............................................................................................
3.1.3 Synthesis ............................................................................................
3.1.4 Editions ............................................................................................
3.1.5 XST Detailed Design Flow ............................................................................................
3.1.6 Steps while running a design on XILINX ISE(For Synthesis) .......................................
3.1.6.1 XST Synthesis Overview in Xilinx ISE ....................................................................
3.1.6.1.1 XST Input and Output Files ...........................................................................
3.1.6.2 Implementation Overview ..........................................................................................
3.1.6.2 .1 Translate ............................................................................................................
3.1.5.2 .2 Map ................................................................................................................
3.1.6.2 .3 Place and Route .............................................................................................
3.1.6.2 .4 Generate Programming File Process ...................................................................
3.1.6.3 Configuring or Programming a Target Device ........................................................
3.2 MATLAB .....................................................................................................................
3.2.1 Features of MATLAB ..........................................................................
3.2.2 Uses of MATLAB ...............................................................................
3.2.3 Image processing toolbox in MATLAB .......................................................................
3.2.3.1 Key Features ............................................................................................
3.2.3.2 Functions used during coding................................................................................

CHAPTER 4 VERILOG HDL .........................................................................................

4.1 HISTORY OF VERILOG HDL .......................................................................................
4.2 Verilog-95 .......................................................................................
4.3 Verilog 2001 .......................................................................................
4.4 WHY VERILOG ? .......................................................................................
4.5 IMPORTANCE OF HDLs .......................................................................................
4.6 DIFFERENT LEVELS OF ABSTRACTION(MODELING) IN VERILOG ................

VIII
 4.6.1 GATE LEVEL MODELING
4.6.1.1 GATE PRIMITIVES
4.6.1.1.1 BASIC LOGIC GATE PRIMITIVES
4.6.1.1.2 TRANSMISSION GATE PRIMITIVES
4.6.2 DATAFLOW MODELING
4.6.2.1 USAGE OF ASSIGN STATEMENT
4.6.2.2 OPERATORS IN DATAFLOW MODELLING
4.6.3 BEHAVIORAL MODELING
4.6.3.1 INITIAL AND ALWAYS BLOCKS IN VERILOG
4.6.3.1.1 Initial Blocks
4.6.3.1.2 Always Blocks
4.6.3.1.2.1 Asynchronous always block
4.6.3.1.2.2 Synchronous always block
4.6.3.1.2.3 Implementations of an always block
4.6.3.1.2.4 Edge-Triggers
4.6.3.1.2.5 Restrictions on always blocks
4.6.3.2 Begin-end
4.6.3.3 If, If-Else and Case statements in Verilog
4.6.3.3.1 If-Else
4.6.3.3.2 Case Statement
4.6.3.4 Loop Statements in Verilog

CHAPTER 5 FIELD PROGRAMMABLE GATE ARRAY(FPGA) .........................................

5.1 Technical design of FPGA
5.2 History of FPGA
5.3 Modern developments in FPGA
5.4 FPGA comparisons
5.5 FPGA General Architecture
5.6 Security considerations
5.7 Applications of FPGA
5.8 FPGA design and programming
5.9 Major manufacturers of FPGA
5.10 FPGA Boards Used during coding
5.10.1 Digilent Basys 2
5.10.1.1 Overview
5.10.1.2 Features
5.10.1.3 Board Power
5.10.1.4 Configuration
5.10.1.5 Oscillators

IX
 5.10.1.6 User I/O
5.10.1.7 Basys 2 Interfaces used by me during coding
5.10.1.7.1 Seven Segment Display
5.10.1.7.2 Keyboard
5.10.1.8 Basys 2 Extenal Connection Ports
5.10.1.8.1 FPGA Pin Definitions
5.10.2 Digilent Nexys 2
5.10.2.1 Overview
5.10.2.2 Features
5.10.2.3 Power Supplies
5.10.2.4 Clocks
5.10.2.5 The peripheral used during coding (VGA Port)
5.10.2.5.1 VGA System Timing

CHAPTER 7 DIGITAL IMAGE PROCESSING AND IMAGE EDGE

DETECTION ...............................................................................................................................
7.1 INTRODUCTION TO IMAGE PROCESSING
7.1.1 Applications of Digital Image Processing
7.2 IMAGE EDGE DETECTION
7.2.1 Edge properties
7.2.2 Thresholding and linking
7.2.3 Prewitt Operator
7.2.3.1 Formulation of Prewitt Operator
7.2.4 Sobel Operator
7.2.4.1 Difference with Prewitt Operator
7.2.4.2 Formulation of Sobel Operator
7.2.5 XOR OPERATION TO DETECT EDGES

CHAPTER 8 IMAGE EDGE DETECTION USING PREWITT,SOBEL AND XOR

OPERATORS
8.1 MATLAB CODING TILL INPUT AVAILABLE FOR VERILOG CODING
8.1.1 INPUT IMAGE
8.1.2 MATLAB STEPS FOR FURTHER PROCESS
8.2 VERILOG HDL STEPS FOR EDGE DETECTION AND OBTAINING MATLAB
OUTPUT AS WELL AS FPGA IMPLEMENTATION OF SAME AND OBTAINING
OUTPUT ON ON VGA SCREEN
8.2.1 Prewitt Operator
8.2.1.1 Prewitt Gradient
8.2.1.1.1 Verilog code for prewitt gradient and obtaining output text file

X
 8.2.1.1.2 MATLAB Code to get the output image file from the text file obtained as output of
verilog code(Prewitt Gradient)
8.2.1.1.3 Verilog Code to display the text file as output on VGA screen through FPGA for
Prewitt Gradient
8.2.1.2 Approximate Prewitt Gradient
8.2.1.2.1 Verilog coding for approximate prewitt gradient and obtaining output text file and
displaying output
8.2.1.2.2 MATLAB Code to get the output image file from the text file obtained as output of
verilog code (Approximate Prewitt Gradient)
8.2.1.2.3 Verilog Code to display the text file as output on VGA screen through FPGA for
Approximate Prewitt Gradient
8.2.2 Sobel Operator
8.2.2.1 Sobel Gradient
8.2.2.1.1 Verilog code for sobel gradient and obtaining output text file
8.2.2.1.2 MATLAB Code to get the output image file from the text file obtained as output of
verilog code (Sobel Gradient)
8.2.2.1.3 Verilog Code to display the text file as output on VGA screen through FPGA for
Sobel Gradient
8.2.2.2 Approximate Sobel Gradient
8.2.2.2.1 Verilog coding for approximate sobel gradient and obtaining output text file and
displaying output
8.2.2.2.2 MATLAB Code to get the output image file from the text file obtained as output of
verilog code (Approximate Sobel Gradient)
8.2.2.2.3 Verilog Code to display the text file as output on VGA screen through FPGA(For
Approximate Sobel Gradient)
8.2.3 XOR Operator
8.2.3.1 Verilog code for XOR Operator and obtaining output text file
8.2.3.2 MATLAB Code to get the output image file from the text file obtained as output of
verilog code (XOR Operator)
8.2.3.3 Verilog Code to display the text file as output on VGA screen through FPGA for XOR
Operator
8.3 Results and Conclusion
8.4 Future Scope

XI
 LIST OF FIGURES

Figure 2.1. An Integrated Circuit ............................................................................................... 4

Figure 2.2 VLSI Design Flow ....................................................................................................
Figure 2.3 A 3D PCB Layout ....................................................................................................
Figure 2.4 Layout of a Ripple Carry Adder ....................................................................................................
Figure 3.1 XST Design Flow ....................................................................................................
Figure 4.1 Simulation Results for 4:1 MULTIPLEXER using gate level modeling ....................
Figure 4.2 Simulation Results for 4:1 MULTIPLEXER using dataflow modeling .......................
Figure 4.3 Simulation Results for 4:1 MULTIPLEXER using behavioral modeling .....................
Figure 5.1 An FPGA board ....................................................................................................
Figure 5.2 A Xilinx Zynq-7000 All Programmable System on a Chip ........................................
Figure 5.3 A general FPGA architecture ....................................................................................................
Figure 5.4 Simplified example illustration of a logic cell .....................................................................
Figure 5.5 Various Basys 2 Ports connected to Xilinx Spartan 3E-100 CP132 Family FPGA ..................
Figure 5.6 A Basys 2 FPGA Board ...................................................................................................
Figure 5.7 A Basys 2 FPGA board connected to my laptop ...................................................................
Figure 5.8 A Xilinx XC3S100E FPGA Chip(Used in Basys 2 Board) ....................................................
Figure 5.9 Basys 2 Power Options ...................................................................................................
Figure 5.10 Basys2 Programming Circuits ..................................................................................................
Figure 5.11 Basys2 oscillator circuit configurations ..................................................................................
Figure 5.12 Basys 2 I/O Circuits ...................................................................................................
Figure 5.13 Seven Segment Display and illumination patterns of digits 1-9 using
Seven Segment Display..........................................................................................................................
Figure 5.14 Multiplexed 7 segment display timing ..............................................................................
Figure 5.15 PS/2 connector and Basys2 PS/2 circuit ....................................................................................
Figure 5.16 PS/2 signal timing ....................................................................................................
Figure 5.17 Keyboard Scan Codes ....................................................................................................
Figure 5.18 Basys 2 external connection ports .......................................................................................
Figure 5.19 Various Nexys 2 Ports connected to Xilinx Spartan 3E-500 FG320 Family FPGA............
Figure 5.20 A Nexys 2 FPGA Board ...................................................................................................
Figure 5.21 A Nexys 2 FPGA board connected to my laptop ............................................................
Figure 5.22 A Xilinx XC3S500E Chip(Used in Nexys 2 Board) ..........................................................
Figure 5.23 Nexys2 power supply block diagram ................................................................................
Figure 5.24 Nexys 2 Power Options ................................................................................................
Figure 5.25 Nexys 2 Power Jumpers...............................................................................................
Figure 5.26 Nexys 2 Clocks ...................................................................................................
Figure 5.27 VGA PIN Definitions .................................................................................................
Figure 5.28 Nexys 2 pins corresponding to VGA pin definitions ................................................
Figure 5.29 CRT deflection system ............................................................................................

XII
Figure 5.30 VGA System Signals ..................................................................................................
Figure 5.31 VGA system timing diagram ........................................................................................
Figure 5.32 Schematic for a VGA controller circuit ..........................................................................
Figure 7.1 The Electromagnetic Spectrum .........................................................................................
Figure 7.2 The Prewitt kernels ....................................................................................................
Figure 7.3 The Sobel kernels ....................................................................................................
Figure 8.1 Image edge detection steps
Figure 8.2 Input Image File
Figure 8.3 90 * 90 grayscale image for given input image
Figure 8.4 Image after applying im2bw function
Figure 8.5 Output after applying threshold 0.50
Figure 8.6 Output after applying threshold 0.49
Figure 8.7 Output after applying threshold 0.48
Figure 8.8 Output after applying threshold 0.47
Figure 8.9 Output after applying threshold 0.39
Figure 8.10 Output after applying threshold 0.38
Figure 8.11 Output after applying threshold 0.379
Figure 8.12 Output after applying threshold 0.378
Figure 8.13 Output after applying threshold 0.377
Figure 8.14 Output after applying threshold 0.376
Figure 8.15 Text file of image with optimum threshold(0.376)
Figure 8.16 MATLAB Command Window for Section 8.1.2
Figure 8.17 Simulation results for Prewitt Gradient
Figure 8.18 Initial values of output text file after performing prewitt gradient
Figure 8.19 Matlab Command window for conversion of text file to image(Prewitt Gradient)
Figure 8.20 Prewitt gradient output(As from MATLAB)
Figure 8.21 Design summary for implementing prewitt gradient operation on FPGA
Figure 8.22 VGA output of Prewitt Gradient implemented through Digilent Nexys 2 FPGA
Figure 8.22 MATLAB Command window for conversion of text file to image(Approximate Prewitt
Gradient)
Figure 8.23 Simulation results for approximate prewitt gradient
Figure 8.24 Initial values of output text file after performing approximate prewitt gradient
Figure 8.25 Prewitt approximate gradient output(As from MATLAB)
Figure 8.26 Design summary for implementing approximate prewitt gradient operation on FPGA
Figure 8.27 VGA output of Approximate Prewitt Gradient implemented through Digilent Nexys 2 FPGA
Figure 8.28 Simulation results for sobel gradient
Figure 8.29 Initial values of output text file after performing sobel gradient
Figure 8.30 MATLAB Command window for conversion of text file to image(Sobel Gradient)
Figure 8.31 Sobel gradient output(As from MATLAB)
Figure 8.32 Design summary for implementing sobel gradient operation on FPGA
Figure 8.33 VGA output of Sobel Gradient implemented through Digilent Nexys 2 FPGA
Figure 8.34 Simulation results for approximate sobel gradient

XIII
Figure 8.35 Initial values of output text file after performing approximate sobel gradient
Figure 8.36 MATLAB Command window for conversion of text file to image(Sobel Approximate
Gradient)
Figure 8.37 Sobel approximate gradient output(As from MATLAB)
Figure 8.38 Design summary for implementing approximate sobel gradient operation on FPGA
Figure 8.39 VGA output of Approximate Sobel Gradient implemented through Digilent Nexys 2 FPGA
Figure 8.40 Simulation results for XOR Operator
Figure 8.41 Initial values of output text file after performing XOR Operator
Figure 8.42 MATLAB Command window for conversion of text file to image(XOR Operator)
Figure 8.43 XOR Operator output(As from MATLAB)
Figure 8.44 Design summary for implementing XOR operator on FPGA
Figure 8.45 VGA output of XOR Operator implemented through Digilent Nexys 2 FPGA

XIV
 LIST OF EXAMPLES

Example 4.1 :- A 4:1 MULTIPLEXER using gate level modeling ....................................................

Example 4.2 :- Testbench for 4:1 MULTIPLEXER using gate level modeling ...............................
Example 4.3 A 4:1 MULTIPLEXER using dataflow modeling .............................................................
Example 4.4 Testbench of a 4:1 MULTIPLEXER using dataflow modeling ........................................
Example 4.5 A 4:1 MULTIPLEXER using behavioral modeling ...........................................................
Example 4.6 Testbench of a 4:1 MULTIPLEXER using behavioral modeling .....................................
Example 8.1 Verilog code for applying Prewitt Gradient on input text file and displaying output
Example 8.2 Verilog code for displaying the output image of Prewitt Gradient on VGA Screen via
Digilent Nexys 2 FPGA Board
Example 8.3 Verilog code for applying Approximate Prewitt Gradient on input text file
Example 8.4 Verilog code for displaying the output image of Approximate Prewitt Gradirnt on VGA
Screen
Example 8.5 Verilog code for applying Sobel Gradient on input text file and displaying output
Example 8.6 Verilog code for displaying the output image of Sobel Gradient on VGA Screen via
Digilent Nexys 2 FPGA Board
Example 8.7 Verilog code for applying Approximate Sobel Gradient on input text file and displaying
output
Example 8.8 Verilog code for displaying the output image of Approximate Sobel Gradient on VGA
Screen via Digilent Nexys 2 FPGA Board
Example 8.9 Verilog code for applying XOR Operator on input text file and displaying output
Example 8.10 Verilog code for displaying the output image of Sobel Gradient on VGA Screen via
Digilent Nexys 2 FPGA Board

XV
 LIST OF TABLES AND FORMULAE

TABLES

Table 4.1 Operators in Verilog HDL ............................................................................................................

Table 5.1 PS/2 signal timing .......................................................................................................................
Table 5.2 FPGA pin definition table color key ...........................................................................................
Table 5.3 Basys2 Spartan-3E pin definitions ....................................................................................
Table 5.4 VGA System Timing ......................................................................................................

FORMULAE

Formula 7.1 Prewitt Gradient ................................................................................................

Formula 7.2 Approximate Prewitt Gradient ..........................................................................
Formula 7.3 Sobel Gradient ...................................................................
Formula 7.4 Approximate Sobel Gradient ...................................................................
Formula 7.5 XOR Operator .....................................................................................................

XVI