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Digital Clock Design Using Verilog Dhl

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Table of Contents
1.0 INTRODUCTION ........................................................................................................................... 4
1.1 OBJECTIVES .............................................................................................................................. 4
1.1.1 General Objective: ............................................................................................................ 4
1.1.2 Specific Objectives ............................................................................................................ 4
1.2 OVERVIEW ............................................................................................................................... 4
1.3 Verilog HDL .............................................................................................................................. 4
1.4 Counter .................................................................................................................................... 5
1.5 LED .......................................................................................................................................... 5
1.6 KEY /PUSH BUTTONS ................................................................................................................ 5
2.0 METHODOLOGY ........................................................................................................................... 6
2.1 Compilation ............................................................................................................................. 7
2.2 Pins assignment ....................................................................................................................... 8
2.3 Block diagram .......................................................................................................................... 9
3.0 IMPLEMENTATION ..................................................................................................................... 10
3.1 Verilog HDL codes .................................................................................................................. 11
3.2 Loading verilog HDL codes into Cyclone II FPGA Experiment board. ........................................ 14
4.0 RESULTS ..................................................................................................................................... 15
5.0 CONCLUSION ............................................................................................................................. 16
6.0 References ................................................................................................................................. 17

3Table of figures
Figure 1: Full compilation............................................................................................................. ........... 7
Figure 2: Pins assignment. ....................................................................................................................... 8
Figure 3: Schematic diagram for digital clock. .......................................................................................... 9
Figure 4 : Cyclone II FPGA Experiment Board ......................................................................................... 10
Figure 5 : USB-Blaster
.......................................................................................................................... 14
Figure 6 : Cyclone II FPGA board display the results.
............................................................................ 15

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1.0 INTRODUCTION
Digital clock means clock is using ciphers to display time digitally which is completely differentfrom Analog
Clock, where the time is displayed by mechanical hands. Digital clocks are oftenmade up by electronic drives;
the word "digital" refer only to the display and not the drivemechanism. All type of Clock that is analog and digital clocks
both can be driven eithermechanically or electronically.

1.1 OBJECTIVES1.1.1

General Objective:
The main objective of this project was to design and implementation of digital clock usingVerilog HDL.

1.1.2 Specific Objectives


The following were specific objectives1. The designed program must count hours from 00:00:00 to 23:59:59
using eight sevensegment displays.2.

The digital clock design using Magic SOPC experiment box. That means the pins assignmentmust be finished.

1.2 OVERVIEW
A digital clock has been designed and implemented as presented in this report. It displays thetime on seven
segment led displays and time from 00:00:00 to 23:59:59 .Which means it displayhours, minutes, and seconds
.It made up by 7 segment LED patterns with two bits key enablesignal, 25 bits Counters, Registers.
1.3 Verilog HDL

To make this digital clock to work properly we used Verilog language to program each andevery device. All
enable signal are active low (enabled when a signal is 0) and if enable signal isfast enough the human eyes
cannot distinguish the between ON/OFF interval of the LEDs andperceives that all displays are lit
simultaneously. To supply a 1Hz signal to the concurrentalways blocks, one can make use of a counter that
receives a 50MHz clock from the onboardclock source.

1.4 Counter

Apart from the clock there is counter which plays a major role in this project. It was used tocount and increment
the output before next state to occur during display of seven segmentdisplay and normally works on positive
edge clock. Counters in the tens place resent onachieving a value of 5, 5 and 2 (with the units counter on 3) for seconds, minutes
and hoursrespectively. This is because the LED accepts only one character at a time, and converting abinary
number into a two decimal digit number. The three counters are updated using the samemethod of concurrent
always blocks and a counter generating a 1Hz signal.

1.5 LED
To display data on the LED, one needs to first initialize the LED on power-on. The LED connectsto the FPGA
through a 4-bit data bus and three control bits. Since the data bus is also sharedwith the onboard Magic SOPC, it
is necessary to write a logical high bit at all times while usingthe LED. A schematic diagram is given in the user
manual, which has been reproduced here forconvenience.

The three most significant bits are decoded to generate the enable signal and areused as the selection signal for
multiplexing .As it shown on program codes in section 2.0 weuse timing of 0.5second for 50Hz to count up by
increment of 1 bit and when it reachesmaximum bit value {25 bits} it clear the counter to zero and start again to
count. The threemost significant bits are decoded to generate the enable signal and are used as the
selectionsignal for multiplexing.

1.6 KEY /PUSH BUTTONS

Using the push button switches SET or KEY, we set the desired time and the set time could beseen on the
seven-segment LED displays. Every time a push button is pressed, thecorresponding display advances by one.
By pressing the button continuously for more than 2 s,the displays advance fast. The figure 1 below show the
six seven segment display and threepush button named SET. In this system, hours, minutes, and seconds can be
set by pushbuttons. We need three independent push button switches to set them.

Six seven segment display and three push button (SET)

2.0 METHODOLOGY
This section presents the methods used to implement the design of a digital clock. HardwareDescriptive
Language used in the design of digital clock and implemented using the Magic SOPCexperiment box. Typical
digital clocks applied were of the 50 or 60hertzoscillation of AC poweror a 32,768 hertzcrystal oscillatoras in
aquartz clockto keep time, a frequency of 1 Hertz was used in this particular experiment. Mostdigitalclocks
display the hour of the dayin24 hour format.A more commonly used hour sequence option is12 hour format(with
some indication of AM or PM). Emulations of analog-style faces often use anLCDscreen, and theseare also
sometimes described as digital.

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2.1 Compilation
Here is where .v file named as clock (clock.v) is simulated to see whether the written Verilogcodes had some
errors or not. The figure below presents the full compilation of the Verilogcodes for the digital clock which was
successful compiled as it shown below.

Figure 1: Full compilation.

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2.2 Pins assignment
The diagram below shows how pins where assigned ready for download into SOPC board forimplementation.
Figure 2: Pins assignment

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2.3 Block diagram
The below diagram represents schematic diagram for the digital clock after pins assignment wassuccessful.
Figure 3: Schematic diagramfor digitalclock.

Figure 3: Schematic diagramfor digitalclock


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3.0 IMPLEMENTATION
The implementation of the digital clock design was done using Cyclone II Altera FPGAexperiment board as
shown below. This part involves Verilog HDL codes used to design digitalclock

3.1 Verilog HDL codes


Below are Verilog codes designed for the implementation of the digital clock.

module clock(clk,key,dig,seg);
input clk;
input[1:0] key;
output[7:0] dig;
output[7:0] seg;
reg[7:0] seg_r;
reg[7:0] dig_r;
reg[3:0] disp_dat;
reg[24:0]count;
reg[23:0]hour;
reg sec,keyen;
reg[1:0]dout1,dout2,dout3;
wire[1:0]key_done;
assign dig = dig_r;
assign seg = seg_r;
// signal generation section
always @(posedge clk)

begin
count = count + 1'b1;
if(count == 25'd25000000)

begin
count = 25'd0;
sec = ~sec;
end
end

// Button debounce processing section


assign key_done = (dout1 | dout2 | dout3);
always @(posedge count[17])
begin
dout1 <= key;
dout2 <= dout1;
dout3 <= dout2;
end
always @(negedge key_done[0])
begin
keyen = ~keyen;
end

//Dynamic scanning of the digital tube display section


always @(posedge clk)
begin
case(count[17:15])
3'd0:disp_dat = hour[3:0];
3'd1:disp_dat = hour[7:4];
3'd2:disp_dat = 4'ha;
3'd3:disp_dat = hour[11:8];
3'd4:disp_dat = hour[15:12];
3'd5:disp_dat = 4'ha;
3'd6:disp_dat = hour[19:16];
3'd7:disp_dat = hour[23:20];
Endcase
case(count[17:15])
3'd0:dig_r = 8'b11111110;
3'd1:dig_r = 8'b11111101;
3'd2:dig_r = 8'b11111011;
3'd3:dig_r = 8'b11110111;
3'd4:dig_r = 8'b11101111;
3'd5:dig_r = 8'b11011111;
3'd6:dig_r = 8'b10111111;
3'd7:dig_r = 8'b01111111;
endcase
end
always @(posedge clk)
begincase(disp_dat)
4'h0:seg_r = 8'hc0;
4'h1:seg_r = 8'hf9;
4'h2:seg_r = 8'ha4;
4'h3:seg_r = 8'hb0;
4'h4:seg_r = 8'h99;
4'h5:seg_r = 8'h92;
4'h6:seg_r = 8'h82;
4'h7:seg_r = 8'hf8;
4'h8:seg_r = 8'h80;
4'h9:seg_r = 8'h90;
4'ha:seg_r = 8'hbf;
default:
seg_r = 8'hff;
endcase
if((count[17:15]== 3'd2)&sec)
seg_r = 8'hff;
end
//Timing processing section
always @(negedge sec or negedge key_done[1])
Begin
if(!key_done[1])
begin
hour = 24'h0;
end
else if(!keyen)

begin
hour[3:0] = hour[3:0] + 1'b1;
if(hour[3:0] == 4'ha)
begin
hour[3:0] = 4'h0;
hour[7:4] = hour[7:4] + 1'b1;
if(hour[7:4] == 4'h6)
begin
hour[7:4] = 4'h0;
hour[11:8] = hour[11:8] + 1'b1;
if(hour[11:8] == 4'ha)
begin
hour[11:8] = 4'h0;
hour[15:12] = hour[15:12] + 1'b1;
if(hour[15:12] == 4'h6)
begin
hour[15:12] = 4'h0;
hour[19:16] = hour[19:16] + 1'b1;
if(hour[19:16] == 4'ha)
begin
hour[19:16] = 4'h0;
hour[23:20] = hour[23:20] + 1'b1;
end
if(hour[23:16] == 8'h24)hour[23:16] = 8'h0;
end
end
end
end
end
end

end module

3.2

Loading verilog HDL codes into Cyclone II FPGA Experiment board.


The processing of loading was done using USB-Blaster via JTAG and AS pins. Figure below shows theUSB-
Blaster.

4.0 RESULTS
The below photo shows the results after loading Verilog HDL codes into experiment board. It was able
todisplay hours, minutes and seconds then counts from 00:00:00 to 23:59:59.

5.0 CONCLUSION
The objectives of this project were met and a digital clock has been designed and implementedas presented in this
report. The Verilog HDL codes for program counts hours from 00:00:00 to23:59:59 was successful implemented and also pins
assignment was done successful .It displaysthe time on seven segment led displays and time from 00:00:00 to
23:59:59 which means itdisplay hours, minutes, and seconds