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Course Information
Labs&Lessons&Report:
System Design&Methodologies Fö 1&2- 4
A/D
RF & LAN
D/A High-Speed Control
• Dedicated (not general purpose) DSP Blocks Logic
Gateway
• Safety
• Time to market
☞ Safety critical:
☞ Short time to market:
☞ A schedule:
Time 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
Task WCET task
T1 4 ---- T1 T2 T4 T3 T5 T6 T7 T8
----
T2 6 ----
T3 4
T4 7 Using this architecture we got a solution with:
Estimator µprocessor
T5 8 arch. model
T6 12 • Execution time: 58 > 42
T7 7
WCET
T8 10 • Cost: 4 < 8
☞ We look after a µprocessor which is fast enough: µp2 ☞ Now we have to look to a multiprocessor solution.
In order to meet cost constraints we try two cheap (and slow) µps:
☞ For each task the WCET, when executed on µp2, is estimated. µp3: cost 3
µp4: cost 2
WCET
interconnection bus: cost 1 Task
Task WCET µp3 µp4
Using this architecture we got a solution with: T1 2 T1 5 6
☞ For each task the WCET, when executed
T2 3 on µp3 and µp4, is estimated. T2 7 9
• Execution time: 28 < 42 T3 2 T3 5 6
T4 3 T4 8 10
• Cost: 15 > 8 T5 4 T5 10 11
µp3 µp4
T6 6 T6 17 21
T7 3 T7 10 14
☞ We have to try with another architecture! T8 5
Bus
T8 15 19
µp4 T2 T4
☞ If communicating tasks are mapped to different processors, they
have to communicate over the bus. bus
Communication time has to be estimated; it depends on the amount C1-2 C4-8
of bits transferred between the tasks and on the speed of the bus.
☞ Try a new mapping; move T5 to µp4, in order to increase parallelism. ☞ There exists a better schedule!
Two new communications are introduced, with estimated times: 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
Time
C3-5: 2
µp3 T1 T3 T6 T7 T8
C5-7: 1
µp4 T2 T5 T4
☞ A schedule:
bus
Time 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 C1-2 C3-5 C5-7 C4-8
µp3 T1 T3 T6 T7 T8
Using this architecture we got a solution with:
µp4 T2 T4 T5
Informal Specification,
Constraints
Testing Prototype
not OK
OK
Fabrication
What is the essential difference compared to the flow on slide 20? ☞ Some additional remarks:
• It is the inner loop which is performed before the effective • Formal verification
hardware/software implementation. It is impossible to do an exhaustive verification by simulation!
This loop is performed several times as part of the design space Especially for safety critical systems (but not only) formal
exploration. Different architectures, mappings and schedules are verification is needed.
explored, before the actual implementation and prototyping.
• Simulation
Simulation is used not only for functional validation.
• We get highly optimised good quality solutions in short time. It is used also after mapping and scheduling in order to test, for
We have a good chance that the outer loop, including prototyping, example, timing aspects.
is not repeated. It is used also during the implementation steps; especially
interesting: hardware/software cosimulation.
Informal Specification,
Constraints
Modeling Functional
Simulation
System Design&Methodologies Fö 1&2- 37
System Level
The Design Flow (cont’d)
System
architecture Mapping
• Hardware/software codesign
codesign
Hardware/Software
(software) and what is going into partitioning Mapped and
hardware (ASIC, FPGA). scheduled model Simulation
During the implementation phase,
OK Formal
hardware and software Verification
components have to be developed
in a coordinated way, keeping their
consistency (hardware/software
cosimulation is important here) Softw. model Simulation Hardw. model
Lower Levels
Softw. blocks Simulation Hardw. blocks
not OK
Testing Prototype
OK
Fabrication
• Software generation:
- Encoding in an implementation language (C, C++, assembler). • Hardware/software integration:
- Compiling (this can include particular optimizations for - The software is “run” together with the hardware model (cosim-
application specific processors, DSPs, etc.). ulation)
- Generation of a real-time kernel or adapting to an existing
operating system.
- Testing and debugging (in the development environment).
• Prototyping:
- A prototype of the hardware is constructed and the software is
• Hardware synthesis: executed on the target architecture.
- Encoding in a hardware description language (VHDL, Verilog)
- Successive synthesis steps: high-level, register-transfer level,
logic-level synthesis.
- Testing and debugging (by simulation)
☞ There are available tools on the market which automatically perform • This is a hot research area.
many of the low level tasks: • Very few commercial tools are offered.
• Mostly experimental and academic tools available.
• Code generators (software model → C, hardware model → VHDL)
• Compilers ☞ Huge efforts and investments are currently made in order to
• Test generators and debuggers develop tools and methodologies for system level design.
• Simulation and cosimulation tools Ad-hoc solutions are less and less acceptable.
• Hardware synthesis tools
- High level synthesis
- RT-level synthesis It is the system level we are interested in, in this course!
- Logic synthesis
- Layout and physical implementation