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CSE460 (LAB)/ EEE412:VLSI DESIGN

LABORATORY LAB PROJECT

FALL 2017

Design of ALU (Arithmetic Logic Unit) with Shifter

Submitted By:

Name: Nehal Hasnain Refath

Student Id: 13221012

Section: 01(Theory section)

G0 G1 G2 G3 G4 G5 G6 G7 G8 G9

Slot:

Tuesday (12.30pm02.00pm) Thursday (11.00am12.30pm)

Thursday (12.30pm02.00pm) Thursday (03.30pm04.50pm)


ReOrganized table according to your group number:

S2S1S0 Op F Description Bin Cin Cpass Result Cout


No.

000 5 A-1 Decrement 1 0 carry sum Cout


A
001 6 A-B B 1 carry sum Cout
Subtract B
from A

010 1 A+1 Increment A 0 1 carry sum Cout

011 8 A AND B Bitwise B 0 0 carry 0


AND
100 4 A XOR B Bitwise B 0 0 sum 0
XOR
101 2 A OR B Bitwise OR B 1 1 carry 0

110 3 A+B Add A to B B 0 carry sum Cout

111 7 A Complement 1 0 0 sum 0


of A

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