UNIT 3

COMBINATIONAL DESIGN
TOPICS
Dataflow Style Behavioral Style

Logical and relational
Process statement

operators
Case statement

Signal assignments
If statement

Don’t care conditions
Loop statement

Lookup tables
Variables
DATAFLOW STYLE

Logical and relational operators

Signal assignments

Encoders and decoders

Lookup tables
OPERATORS
VHDL operators listed from higher to lower
precedence
Miscellaneous ** abs not
Multiplying * / mod rem
Sign + -
Adding + - &
Shift sll srl sla sra rol ror
Relational = /= < <= > >=
Logical and or nand nor xor xnor
LOGICAL OPERATORS
A B not A A and B A nand B A or B A nor B A xor B A xnor B
0 0 1 0 1 0 1 0 1
0 1 1 0 1 1 0 1 0
1 0 0 0 1 1 0 1 0
1 1 0 1 0 1 0 0 1

All operators have the same level of precedence

except for not

Associative operators: and, or, xor, xnor

A and B and C -- valid

A nand B nand C -- invalid
SIGNAL ASSIGNMENTS

A signal assignment placed in the statement part
of an architecture is a concurrent statement.

2 forms of concurrent signal assignment:

Selected signal assignment

Conditional signal assignment

Using Boolean expression (3rd form)

Synthesizable signal assignment form:
target <= value_expression;
EXAMPLE: 4-TO-1 MULTIPLEXER
Logic Symbol Entity Declaration

entity mux4to1 is
Port ( I : in STD_LOGIC_VECTOR
(3 downto 0);
S : in STD_LOGIC_VECTOR
(1 downto 0);
nE : in STD_LOGIC;
Y : out STD_LOGIC);
end mux4to1;
EXAMPLE: 4-TO-1 MULTIPLEXER

Concurrent signal assignment using Boolean
expression:

architecture Dataflow of mux4to1 is

begin
Y <= (not nE) and (
(not S(1) and not S(0) and I(0))
or (not S(1) and S(0) and I(1))
or (S(1) and not S(0) and I(2))
or (S(1) and S(0) and I(3)));
end Dataflow;
SELECTED SIGNAL ASSIGNMENT

Also called a with-select-when statement

It allows one of several possible values to be
assigned to a signal based on a select
expression.

Form:

with expression select

target <= value_expression1 when choices1,
value_expression2 when choices2,
…
value_expressionn when others;
EXAMPLE: 4-TO-1 MULTIPLEXER

Selected signal assignment:

architecture Dataflow of mux4to1 is

begin
with (nE & S) select
Y <= I(0) when "000",
I(1) when "001",
I(2) when "010",
I(3) when "011",
'Z' when others;
end Dataflow;
RELATIONAL OPERATORS
Operator Operation Left Right Result
Operand Operand
= Equality Any except Same as Boolean
file left
/= Inequality -do- -do- -do-
< Less than Scalar or -do- -do-
composite
discrete type
<= Less than or -do- -do- -do-
equal
> Greater than -do- -do- -do-
>= Greater than -do- -do- -do-
or equal
CONDITIONAL SIGNAL ASSIGNMENT

Also called when-else statement

It allows a signal to be assigned a value based on
a set of conditions (expressions involving
relational operators).

Form:

target <= value_expression1 when condition1 else

value_expression2 when condition2 else
…
value_expressionn-1 when condition-1 else
value_expressionn;
EXAMPLE: 4-TO-1 MULTIPLEXER

Conditional signal assignment:

architecture Dataflow of mux4to1 is

signal tmp : std_logic_vector(2 downto 0);
begin
tmp <= nE & S;
Y <= I(0) when tmp = "000" else
I(1) when tmp = "001" else
I(2) when tmp = "010" else
I(3) when tmp = "011" else
'Z';
end Dataflow;
UNDESIRED IMPLIED LATCH
EXAMPLE: MAGNITUDE COMPARATOR
entity Comparator is
Port ( A, B : in STD_LOGIC_VECTOR (7 downto
0);
G, E, L : out STD_LOGIC);
end Comparator;

architecture Behavioral of Comparator is

begin
G <= '1' when A > B else '0';
E <= '1' when A = B else '0';
L <= '1' when A < B else '0';
end Behavioral;
EXAMPLE: PRIORITY ENCODER

I3 I2 I1 I0 A1 A0
X X X 1 0 0
X X 1 0 0 1
X 1 0 0 1 0
1 0 0 0 1 1
EXAMPLE: PRIORITY ENCODER
entity PEncoder is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
A : out STD_LOGIC_VECTOR (1 downto 0));
end PEncoder;

architecture Conditional of PEncoder is

begin
A <= "00" when I(0) = '1' else
"01" when I(1) = '1' else
"10" when I(2) = '1' else
"11" when I(3) = '1' else
"ZZ";
end Conditional;
DON’T CARE INPUTS AND OUTPUTS

Traditional logic design

Could be 1 or 0

Represented as ‘-’ in VHDL

Simulator

treated as a literal value

For output, it indicates that a choice for that output’s
state has not been made

Synthesizer

treated as a literal value

For output, it is treated as a true don’t care condition
used for logic minimization
EXAMPLE: PRIORITY ENCODER
RTL Schematic w/ don’t care conditions
EXAMPLE: PRIORITY ENCODER W/ DON’T
CARE CONDITIONS

A <= "00" when temp = "---1" else

"01" when temp = "--10" else
"10" when temp = "-100" else
"11" when temp = "1000" else
"ZZ";
EXAMPLE: PRIORITY ENCODER W/ DON’T
CARE CONDITIONS & STD_MATCH

A <= "00" when std_match(temp, "---1") else

"01" when std_match(temp, "--10") else
"10" when std_match(temp, "-100") else
"11" when std_match(temp, "1000") else
"ZZ";
SEATWORK 3-1
1. Given the entity diagram, create a dataflow
VHDL description of a 3-to-8 line decoder. Use
selective signal assignment. (Note: Follow the
truth table of the 74LS138 for the behavior of the
system).

decoder3to8
A(3)
G1 D(8)
nG2A
nG2B
SEATWORK 3-1
2. Given the entity diagram, create a dataflow
VHDL description of a 8-input priority encoder.
Use conditional signal assignment with don’t care
conditions and std_match function. (Note: Follow
the truth table of the 74LS148 for the behavior of
the system).
PEncoder
nI(8) nGS
nE A(3)
nEO
LOOKUP TABLE

A simple way to describe a combinational system

For single output systems, use a constant vector

For multiple outputs systems, use an array of

constant vectors

Usually uses the to_integer function found in
the package numeric_std

Hardware implementation is similar to a ROM

When target of synthesis is a PLD, the synthesizer
does not synthesize the circuit as a ROM but as an
inferred logic in its reduced form.
LUT EXAMPLE 1
A B C Y library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
0 0 0 0 use IEEE.NUMERIC_STD.ALL;
0 0 1 1 entity LUT_1 is
Port ( A, B, C : in STD_LOGIC;
0 1 0 - Y : out STD_LOGIC);
0 1 1 0 end LUT_1;
architecture Behavioral of LUT_1 is
1 0 0 1
constant output : std_logic_vector (0 to 7) :=
1 0 1 - "01-01-10";
begin
1 1 0 1 y <= output(to_integer(unsigned'(A, B, C)));
1 1 1 0 end Behavioral;
SIMULATION WAVEFORM
LUT EXAMPLE 2
input output library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
00 11 use IEEE.NUMERIC_STD.ALL;
01 10 entity LUT_2 is
Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
10 01 output : out STD_LOGIC_VECTOR (1 downto 0));
11 00 end LUT_2;
architecture Behavioral of LUT_2 is
type bin2ref is array (0 to 3) of std_logic_vector(1 downto 0);
constant reflected_lut : bin2ref := ("11", "10", "01", "00");
begin
output <= reflected_lut(to_integer(unsigned(input)));
end Behavioral;
SIMULATION WAVEFORM
SEATWORK 3-2
1. Given the ff. truth table, write a complete VHDL
description for a design entity named two_out_lut
that implements the function described by the
truth table above. The architecture body must
use only a lookup table to implement this
function.
decoder3to8
A(3)
G1 D(8)
nG2A
nG2B
SEATWORK 3-2
2. Given the ff. truth table, A B C X Y
write a complete VHDL 0 0 0 1 0
description for a design 0 0 1 0 -
entity named two_out_lut 0 1 0 1 0
that implements the 0 1 1 0 -
function described by the 1 0 0 0 0
truth table above. The 1 0 1 - 1
architecture body must use 1 1 0 - 0
only a lookup table to
1 1 1 1 1
implement this function.
BEHAVIORAL STYLE

Process statement

Case statement

If statement

Loop statement

Variables
COMPARISON: HALF ADDER
Dataflow Behavioral

Sum <= A xor B; p1: process(A, B)

Cout <= A and B; begin
Sum <= A xor B;
end process;
p2: process(A, B)
begin
Carry <= A and B;
end process;
COMPARISON: FULL ADDER
Structural Behavioral

component Half_Adder is ha1: process(A, B)

Port ( A : in STD_LOGIC; begin
B : in STD_LOGIC;
if a = '1' then
Sum : out STD_LOGIC;
Cout : out STD_LOGIC); sig1 <= not b;
end component; sig2 <= b;
else
signal sumsig, coutsig1, sig1 <= b;
coutsig2 : STD_LOGIC;
sig2 <= '0';
end if;
end process;
COMPARISON: FULL ADDER (CONT…)
Structural Behavioral

begin ha2: process(sig1, Cin)

HA1: Half_Adder port map begin
( A, B, sumsig, coutsig1 );
if sig1 = '1' then
HA2: Half_Adder port map
( A => sumsig, Sum <= not Cin;
B => Cin, sig3 <= Cin;
Sum => Sum, else
Cout => coutsig2); Sum <= Cin;
Cout <= coutsig1 or
sig3 <= '0';
coutsig2;
end if;
end process;
COMPARISON: FULL ADDER (CONT…)
Behavioral

or1: process(sig2, sig3)

begin
if (sig3 = '1') or (sig2 = '1')
then
Cout <= '1';
else
Cout <= '0';
end if;
end process;
PROCESS STATEMENT

A concurrent statement that is comprised of
sequential statements

It can represent the behavior of all or some
portion of a design

Syntax:

[ process_label: ]
process [(sensitivity_list)] is
{ process_declarative_item }
begin
{ sequential_statement }
end process [ process_label ];
PROCESS STATEMENT

Can be used to define combinational and
sequential systems

No signals can be declared in a process.

Sensitivity list is optional

A process with a sensitivity list must not contain
wait statements.

A process without a sensitivity list must contain at
least one wait statement, or its simulation will never
end
PROCESS STATEMENT

2 requirements for a process to synthesize to a
combinational system are:
1. The process’s sensitivity list must contain all
signals read in the process.
2. A signal or variable assigned a value in a process
must be assigned a value in all possible executions
of the process.
SENSITIVITY LIST

It is a list of signals to which a process is
sensitive

These signals can be signals declared in the
enclosing architecture and/or ports of the
associated declaration

Order of signals is not important
VHDL’S SEQUENTIAL STATEMENTS

signal assignment
case

variable assignment
null

wait
If

assertion
loop

report
next

procedure call
exit

return
CASE STATEMENT

It is appropriate to use this statement when the
selection can be based on the value of a single
expression

Equivalent to a concurrent selected signal
assignment statement

Syntax:

case expression is
when choices => sequence_of_statements
{ when choices => sequence_of_statements }
end case [ case_level ];
EXAMPLE: XOR_CASE
entity XOR_case is
Port ( A, B : in STD_LOGIC;
C : out STD_LOGIC);
end XOR_case;
architecture Behavioral of XOR_case is
begin
process(A, B)
begin
case std_logic_vector'(A,B) is
when "01" | "10" => C <= '1';
when others => C <= '0';
end case;
end process;
end Behavioral;
EXAMPLE: DECODE
architecture Behavioral of decode is
begin
casey: process(g_bar, a, b)
begin
y0 <= '1'; y1 <= '1'; y2 <= '1'; y3 <= '1';
case std_logic_vector'(g_bar, a, b) is
g_bar y0 when "000" => y0 <= '0';
a y1 when "001" => y1 <= '0';
b y2 when "010" => y2 <= '0';
decode when "011" => y3 <= '0';
y3
(Behavioral) when others =>null;
end case;
end process;
end Behavioral;
SIMULATION OUTPUT (W/ INITIALIZATION)
SIMULATION OUTPUT
(W/O INITIALIZATION)
SEATWORK 3-3
Problem statement Truth table

Using a case statement, a b c W Y

write a behavioral
description that 0 0 0 1 0
implements the function
described by the 0 0 1 0 1
following truth table. In 0 1 0 1 1
addition, the
specification for the 0 1 1 1 0
system states that input
combinations 110 and 1 0 0 1 1
111 will never occur in
the application. 1 0 1 0 0
IF STATEMENT

It selects one or none of its alternative sequences
of statements, depending on the value of each
branch’s condition.

It establishes a priority in the determination of
which sequence of statements is executed.

Syntax:

if condition then
sequence_of_statements
{elsif condition then
sequence_of_statements
end if [if_label];
EXAMPLE: XOR_IF
entity XOR_if is
Port ( A, B : in STD_LOGIC;
C : out STD_LOGIC);
end XOR_if;
architecture Behavioral of XOR_if is
begin
process(A, B)
begin
if A /= B then -- C <= ‘0’;
C <= '1';
else -- if A /= B then
C <= '0'; -- C <= ‘1’;
end if;
end process;
end Behavioral;
EXAMPLE: DECODE
architecture Behavioral2 of decode is
begin
iffy: process(g_bar, a, b)
begin
y0 <= '1'; y1 <= '1'; y2 <= '1'; y3 <= '1';
if (g_bar = '0') then
if ((a = '0') and (b = '0')) then y0 <= '0';
g_bar y0 end if;
if ((a = '0') and (b = '1')) then y1 <= '0';
a y1
end if;
b y2
decode if ((a = '1') and (b = '0')) then y2 <= '0';
y3 end if;
(Behavioral)
if ((a = '1') and (b = '1')) then y3 <= '0';
end if;
end if;
end process;
end Behavioral2;
EXAMPLE: MAG_COMP
architecture Behavioral of mag_comp is
begin
pgtq: process(p, q)
begin
if p > q then p_gt_q <= '1';
else p_gt_q <= '0';
end if;
p p_gt_q end process pgtq;
q p_eq_q peqq: process(p, q)
mag_comp p_lt_q begin
(Behavioral) if p = q then p_eq_q <= '1';
else p_eq_q <= '0';
end if;
end process peqq;
pltq: process(p, q)
begin
if p < q then p_lt_q <= '1';
else p_lt_q <= '0';
end if;
end process pltq;
end Behavioral;
CASE STATEMENT VS IF STATEMENT
CASE statement IF statement

Evaluates a single
Evaluates one or more

case expression conditions in
succession

Provides inherent
priority

More flexible
SEATWORK 3-4
Problem statement Truth table

Given the following a b c X

truth table, write an 0 0 0 1
implementation that
0 0 1 0
uses a process that
contains an if 0 1 0 1
statement. 0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
LOOP STATEMENT

It contains a sequence of sequential statements
that can be repeatedly executed, zero or more
times.

Execution continues until loop is terminated as a
result of any of the following:

Completion of its iteration scheme

Execution of an exit statement

Execution of a next statement that specifies a label
outside of the loop

Execution of a return statement

A return statement can appear inside a loop only if the loop
is in a subprogram.
LOOP STATEMENT

Syntax:
[ loop_label: ]
[ iteration_scheme ] loop
sequence_of_statements
end loop [loop_label ];

iteration_scheme:
for identifier in discrete_range
while condition

discrete_range:
discrete_subtype_indication
range
FOR LOOP STATEMENT

It is synthesizable

The identifier serves as an implicit declaration of
a loop parameter.

The loop parameter’s type is the base type of the
discrete range.

The loop parameter only exists while the loop is
being executed, and is not visible outside of the
loop.

The loop parameter is treated as a constant,
thus, can be read but cannot be written
FOR LOOP STATEMENT

Syntax:
[ loop_label: ]
for identifier in range loop
sequence_of_statements
end loop [loop_label ];
WHILE LOOP STATEMENT

It is not synthesizable

It is useful in testbenches

The condition is evaluated before each iteration

If condition is true, the sequence of statements in the
loop is executed.

If condition is false, the iteration scheme is complete
and the loop is terminated.

The condition is not tested during the execution
of the sequence of statements in the loop.
WHILE LOOP STATEMENT

Syntax:
[ loop_label: ]
while condition loop
sequence_of_statements
end loop [loop_label ];
NEXT STATEMENT

It is used to terminate the current iteration of an
enclosing loop statement and go to the next
iteration.

If the next statement includes a condition,
completion of the current loop iteration is
conditional.

A next statement that has a loop label is only
allowed within the loop that has that label, and
applies to only that loop.
NEXT STATEMENT

A next statement without a loop label is only
allowed within a loop, and applies only to the
innermost enclosing loop.

Execution of a next statement can cause a loop to
be terminated, if the loop is nested inside an
outer loop and the next statement has a label
that denotes the outer loop.

Syntax:

[ label: ] next [ loop_label ] [ when condition];

EXIT STATEMENT

It is used to terminate the execution of an
enclosing loop statement.

If it includes a condition, termination of the loop
is conditional.

An exit statement with a loop label is only
allowed within the loop that has that label, and
applies to only to the innermost enclosing loop
(whether labeled or not).
EXIT STATEMENT

For the execution, the condition, if present, is
first evaluated. The loop is terminated if the
value of the condition is true or if there is no
condition.

Syntax:

[ label: ] exit [ loop_label ] [ when condition];

Example:

exit when x = 25;

EXAMPLE: MAG_COMP4BIT
architecture Behavioral of mag_comp4bit is
begin
comp: process(p, q)
begin
p_gt_q <= '0'; p_eq_q <= '0'; p_lt_q <= '0';
for i in 3 downto 0 loop
if ((p(i) = '1') and (q(i) = '0')) then
p_gt_q <= '1‘; exit;
p(3:0) p_gt_q
elsif ((p(i) = '0') and (q(i) = '1')) then
q(3:0) p_eq_q
p_lt_q <= '1‘; exit;
p_lt_q
mag_comp4bit elsif i = 0 then
(Behavioral) p_eq_q <= '1';
end if;
end loop;
end process;
end Behavioral;
SIMULATION WAVEFORM
VARIABLE

Used to store intermediate values in a process or
subprogram

2 kinds

Normal variables can only be accessed from a single
process or subprogram and are synthesizable

Shared variables can be accessed from multiple
processes and are not synthesizable

Must be declared in the declarative part of the
process or subprogram in which they are used

Local to the process or subprogram in which it is
declared
VARIABLE

Syntax:
variable identifier_list : subtype_indication [ :=
expression ];

Initialization“:

variable count : std_logic_vector (3 downto 0) :=

“0000”;
VARIABLES VS SIGNALS
Variables Signals

Must be declared
Must be declared

inside the process outside of the process

Visible in the process
Visible to all the
in which it is declared processes in the
architecture in which
it is declared
EXAMPLE: MAG_COMP4BIT
architecture Behavioral of mag_comp4bit is
begin
comp: process(p, q)
variable p_gt_q_v, p_lt_q_v, p_eq_q_v: std_logic;
begin
p_gt_q_v <= '0'; p_eq_q_v <= '0'; p_lt_q_v <= '0';
for i in 3 downto 0 loop
if ((p(i) = '1') and (q(i) = '0')) then
p(3:0) p_gt_q p_gt_q_v := '1‘; exit;
q(3:0) p_eq_q elsif ((p(i) = '0') and (q(i) = '1')) then
p_lt_q p_lt_q_v := '1‘; exit;
mag_comp4bit end if;
(Behavioral) end loop;
if ((p_gt_q_v =‘0’) and (p_lt_q_v =‘0’)) then
p_eq_q_v := ‘1’;
p_gt_q <= p_gt_q_v; p_lt_q <= p_lt_q_v;
p_eq_q <= p_eq_q_v;
end process;
end Behavioral;
SEATWORK 3-5
1. Write a complete behavioral style description
that uses a loop instruction to implement an 8-
input NAND gate. The input to the gate is an 8-
bit vector name inputs and the output is named
nandout. Name the entity nand8 and the
architecture bhvloop.
SEATWORK 3-5
Problem statement Truth table

2. Given the truth table, a b c X Y

write a complete 0 0 0 0 1
behavioral VHDL
0 0 1 1 0
design description of a
design entity that 0 1 0 0 1
accomplishes defined 0 1 1 0 0
truth table using 2 1 0 0 1 0
processes, each one to
1 0 1 0 0
assign a value for X
and Y. 1 1 0 0 0
1 1 1 0 1
SOURCE

VHDL for Engineers, Kenneth Short, Pearson
Education, Inc., 2009

VHDL Modular Design and Synthesis of Cores

and Systems, Zainalabedin Navabi, Mc-Graw-
Hill Companies, 2007