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Preface
Tutorial Contents
This guide covers the following topics.
Chapter 1, Overview of ISE, introduces you to the ISE primary user interface,
Project Navigator, and the synthesis tools available for your design.
Chapter 2, HDL-Based Design, guides you through a typical HDL-based design
procedure using a design of a runners stopwatch. This chapter also shows how to use
ISE accessories such as CORE Generator, and ISE Text Editor.
Chapter 3, Schematic-Based Design, explains many different facets of a schematic-
based ISE design flow using a design of a runners stopwatch. This chapter also
shows how to use ISE accessories such as CORE Generator, and ISE Text Editor.
Chapter 4, Behavioral Simulation, explains how to simulate a design before design
implementation to verify that the logic that you have created is correct.
Chapter 5, Design Implementation, describes how to Translate, Map, Place, Route,
and generate a Bit file for designs.
Chapter 6, Timing Simulation, explains how to perform a timing simulation using
the block and routing delay information from the routed design to give an accurate
assessment of the behavior of the circuit under worst-case conditions.
Chapter 7, iMPACT Tutorial explains how to program a device with a newly
created design using the IMPACT configuration tool.
Tutorial Flows
This document contains three tutorial flows. In this section, the three tutorial flows are
outlined and briefly described, in order to help you determine which sequence of chapters
applies to your needs. The tutorial flows include:
HDL Design Flow
Schematic Design Flow
Implementation-only Flow
Implementation-only Flow
The Implementation-only flow is as follows:
Chapter 5, Design Implementation
Chapter 6, Timing Simulation
Note that although timing simulation is optional, it is strongly recommended in this
tutorial flow.
Chapter 7, iMPACT Tutorial
Additional Resources
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Adding Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Checking the Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Correcting HDL Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Creating an HDL-Based Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Using the New Source Wizard and ISE Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Using the Language Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Adding a Language Template to Your File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Creating a CORE Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Instantiating the CORE Generator Module in the HDL Code. . . . . . . . . . . . . . . . . . . . . 34
Creating a DCM Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Using the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Instantiating the dcm1 Macro - VHDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Instantiating the dcm1 Macro - Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Synthesizing the Design using XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Entering Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
The RTL / Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Synthesizing the Design using Synplify/Synplify Pro . . . . . . . . . . . . . . . . . . . . . . . . . 43
Examining Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Synthesizing the Design Using Precision Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Entering Synthesis Options through ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
The RTL/Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 1
Overview of ISE
This chapter includes the following sections:
Overview of ISE
Using Project Revision Management Features
Overview of ISE
ISE controls all aspects of the design flow. Through the Project Navigator interface, you can
access all of the design entry and design implementation tools. You can also access the files
and documents associated with your project.
Preface:
Design Panel
Sources View
The Sources view displays the project name, the target device, and user documents and
design source files associated with the selected Design View. The Design View (Sources
for) drop-down list at the top of the Sources tab allows you to view only those source files
associated with the selected Design View, such as Synthesis/Implementation or
Simulation.
Each file in a Design View has an associated icon. The icon indicates the file type (HDL file,
schematic, core, or text file, for example). For a complete list of possible source types and
Overview of ISE
their associated icons, see the ISE Help. Select Help > ISE Help Contents, select the
Index tab and search for Source file types.
If a file contains lower levels of hierarchy, the icon has a + to the left of the name. You can
expand the hierarchy by clicking the +. You can open a file for editing by double-clicking
on the filename.
Processes View
The Processes view is context sensitive and it changes based upon the source type selected
in the Sources tab and the Top-Level Source in your project. From the Processes tab, you
can run the functions necessary to define, run and analyze your design. The Processes tab
provides access to the following functions:
Design Summary/Reports
Provides access to design reports, messages, and summary of results data. Message
filtering can also be performed.
Design Utilities
Provides access to symbol generation, instantiation templates, viewing command line
history, and simulation library compilation.
User Constraints
Provides access to editing location and timing constraints.
Synthesis
Provides access to Check Syntax, Synthesis, View RTL or Technology Schematic, and
synthesis reports. Available processes vary depending on the synthesis tools you use.
Implement Design
Provides access to implementation tools, and post-implementation analysis tools.
Generate Programming File
Provides access to bitstream generation.
Configure Target Device
Provides access to configuration tools for creating programming files and
programming the device.
The Processes tab incorporates dependency management technology. The tools keep track
of which processes have been run and which processes need to be run. Graphical status
indicators display the state of the flow at any given time. When you select a process in the
flow, the software automatically runs the processes necessary to get to the desired step. For
example, when you run the Implement Design process, Project Navigator also runs the
Synthesis process because implementation is dependent on up-to-date synthesis results.
To view a running log of command line arguments used on the current project, expand
Design Utilities and select View Command Line Log File. See the Command Line
Implementation section of Chapter 5, Design Implementation for further details.
Files Panel
The Files panel provides a flat sortable list of all the source files in the project. Files can be
sorted by any of the columns in the view. Properties for each file can be viewed and
modified by right-clicking on the file and selecting Source Properties.
Preface:
Libraries Panel
The Libraries tab allows you to manage HDL libraries and their associated HDL source
files. You can create, view, and edit libraries and their associated sources.
Console Panel
The Console provides all standard output from processes run from Project Navigator. It
displays errors, warnings, and information messages. Errors are signified by a red (X) next
to the message, while warnings have a yellow exclamation mark (!).
Errors Panel
Displays only error messages. Other console messages are filtered out.
Warnings Panel
Displays only warning messages. Other console messages are filtered out.
Workspace
The Workspace is where design editors, viewers, and analysis tools will open. These
include ISE Text Editor, Schematic Editor, Timing Constraint Editor, Design Summary &
Report Viewer, RTL and Technology Viewers, and Timing Analyzer.
Other tools such as PlanAhead for I/O planning and floorplanning, ISE Simulator (ISim),
3rd party Text Editors, XPower Analyzer, and iMPACT open in separate windows outside
the main Project Navigator environment when invoked.
individual reports. Messaging features such as message filtering, tagging, and incremental
messaging are also available from this view.
The ISE project file includes the following characteristics, which are compatible with
source control environments:
Contains all of the necessary source settings and input data for the project.
Can be opened in Project Navigator in a read-only state.
Only updated or modified if a source-level change is made to the project.
Can be kept in a directory separate from the generated output directory (working
directory).
Note: A sourcelevel change is a change to a property or the addition or removal of a source file.
Changes to the contents of a source file or changes to the state of an implementation run are not
considered source-level changes and do not result in an update to the project file.
Preface:
Creating an Archive
To create an archive:
1. Select Project > Archive.
2. In the Create Zip Archive dialog box, enter the archive name and location.
Note: The archive contains all of the files in the project directory along with project settings. Remote
sources are included in the archive under a folder named remote_sources. For more information, see
the ISE Help.
Restoring an Archive
You cannot restore an archived file directly into Project Navigator. The compressed file can
be extracted with any ZIP utility and you can then open the extracted file in Project
Navigator.
Chapter 2
HDL-Based Design
This chapter includes the following sections:
Overview of HDL-Based Design
Getting Started
Design Description
Design Entry
Synthesizing the Design
Getting Started
The following sections describe the basic requirements for running the tutorial.
Required Software
To perform this tutorial, you must have the following software and software components
installed:
Xilinx Series ISE 11.x
Spartan-3A libraries and device files
Note: For detailed software installation instructions, refer to the ISE Design Suite: Installation,
Licensing and Release Notes.
This tutorial assumes that the software is installed in the default location
c:\xilinx\11.1\ISE. If you have installed the software in a different location, substitute your
installation path for c:\xilinx\11.1\ISE in the procedures that follow.
VHDL or Verilog?
This tutorial supports both VHDL and Verilog designs, and applies to both designs
simultaneously, noting differences where applicable. You will need to decide which HDL
language you would like to work through for the tutorial, and download the appropriate
files for that language. XST can synthesize a mixed-language design. However, this tutorial
does not go over the mixed language feature.
Getting Started
5. Select the following values in the New Project Wizard - Device Properties window:
Product Category: All
Family: Spartan3A and Spartan3AN
Device: XC3S700A
Package: FG484
Speed: -4
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISim (VHDL/Verilog)
Preferred Language: VHDL or Verilog depending on preference. This will
determine the default language for all processes that generate HDL files.
Other properties can be left at their default values.
6. Click Next, then Next, and then click Add Source in the New Project Wizard - Add
Existing Sources window.
7. Browse to c:\xilinx\11.1\ISE\ISEexamples\wtut_vhd or
c:\xilinx\11.1\ISE\ISEexamples\wtut_ver.
8. Select the following files (.vhd files for VHDL design entry or .v files for Verilog
design entry) and click Open.
clk_div_262k
lcd_control
statmach
stopwatch
Design Description
Design Description
The design used in this tutorial is a hierarchical, HDL-based design, which means that the
top-level design file is an HDL file that references several other lower-level macros. The
lower-level macros are either HDL modules or IP modules.
The design begins as an unfinished design. Throughout the tutorial, you will complete the
design by generating some of the modules from scratch and by completing others from
existing files. When the design is complete, you will simulate it to verify the designs
functionality.
In the runners stopwatch design, there are five external inputs and four external output
buses. The system clock is an externally generated signal. The following list summarizes
the input and output signals of the design.
Inputs
The following are input signals for the tutorial stopwatch design.
strtstop
Starts and stops the stopwatch. This is an active low signal which acts like the
start/stop button on a runners stopwatch.
reset
Puts the stopwatch in clocking mode and resets the time to 0:00:00.
clk
Externally generated system clock.
mode
Toggles between clocking and timer modes. This input is only functional while the
clock or timer is not counting.
lap_load
This is a dual function signal. In clocking mode it displays the current clock value in
the Lap display area. In timer mode it loads the pre assigned values from the ROM to
the timer display when the timer is not counting.
Outputs
The following are outputs signals for the design.
lcd_e, lcd_rs, lcd_rw
These outputs are the control signals for the LCD display of the Spartan-3A demo
board used to display the stopwatch times.
sf_d[7:0]
Provides the data values for the LCD display.
Functional Blocks
The completed design consists of the following functional blocks.
clk_div_262k
Macro which divides a clock frequency by 262,144. Converts 26.2144 MHz clock into
100 Hz 50% duty cycle clock.
dcm1
Clocking Wizard macro with internal feedback, frequency controlled output, and
duty-cycle correction. The CLKFX_OUT output converts the 50 MHz clock of the
Spartan-3A demo board to 26.2144 MHz.
debounce
Schematic module implementing a simplistic debounce circuit for the strtstop, mode,
and lap_load input signals.
Design Entry
lcd_control
Module controlling the initialization of and output to the LCD display.
statmach
State machine HDL module which controls the state of the stopwatch.
timer_preset
CORE Generator 64x20 ROM. This macro contains 64 preset times from 0:00:00 to
9:59:99 which can be loaded into the timer.
time_cnt
Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. This
macro has five 4-bit outputs, which represent the digits of the stopwatch time.
Design Entry
For this hierarchical design, you will examine HDL files, correct syntax errors, create an
HDL macro, and add a CORE Generator and a Clocking module. You will create and use
each type of design macro. All procedures used in the tutorial can be used later for your
own designs.
With the wtut_vhd.ise or wtut_ver.ise project open in Project Navigator, the
Hierarchy view in the Design tab displays all of the source files currently added to the
project, with the associated entity or module names (see Figure 2-6).
Instantiated components with no entity or module declaration are displayed with a red
question mark.
The red question-mark (?) for time_cnt should change to show the VHD file icon.
Each source Design unit is represented under the sources tab using the following syntax:
<instance name> - <entity name> - <architecture name>* - (<file name>).
*VHDL only
Design Entry
5. Enter two input ports named sig_in and clk and an output port named sig_out for the
debounce component in this way:
a. In the first three Port Name fields type sig_in, clk and sig_out.
b. Set the Direction field to in for sig_in and clk and to out for sig_out.
c. Leave the Bus designation boxes unchecked.
Design Entry
Design Entry
4. Open the debounce.v or debounce.vhd source file to verify that the Language
Template was properly inserted.
5. (Verilog only) Complete the Verilog module by doing the following:
a. Remove the reset logic (not used in this design) by deleting the three lines
beginning with if and ending with else.
b. Change <reg_name> to q in all six locations.
Note: You can select Edit -> Find & Replace to facilitate this. The Find fields appear at the bottom
of the Text Editor.
c. Change <clock> to clk; <input> to sig_in; and <output> to sig_out.
6. (VHDL only) Complete the VHDL module by doing the following:
a. Move the line beginning with the word signal so that it is between the
architecture and begin keywords.
b. Remove the reset logic (not used in this design) by deleting the five lines beginning
with if (<reset>... and ending with else, and delete one of the end if;
lines.
c. Use Edit > Find & Replace to change <clock> to clk; D_IN to sig_in; and
Q_OUT to sig_out.
You now have complete and functional HDL code.
7. Save the file by selecting File > Save.
8. Select one of the debounce instances in the Sources tab.
9. In the Processes tab, double-click Check Syntax. Verify that the syntax check passes
successfully. Correct any errors as necessary.
10. Close the ISE Text Editor.
7. Fill in the Distributed Memory Generator customization GUI with the following
settings:
Component Name: timer_preset - Defines the name of the module.
Depth: 64 - Defines the number of values to be stored
Data Width: 20 - Defines the width of the output bus.
Memory Type: ROM
8. Click Next.
Design Entry
10. Specify the Coefficients File: Click the Browse button and select
definition1_times.coe located in the project directory.
11. Check that only the following pins are used (used pins are highlighted on the symbol
on the left side of the customization GUI):
a[5:0]
spo[19:0]
12. Click Generate.
This file is the netlist that is used during the Translate phase of implementation.
timer_preset.xco
This file stores the configuration information for the timer_preset module and is
used as the project source in the ISE project.
timer_preset.mif
This file provides the initialization values of the ROM for simulation.
VHDL Flow
To instantiate the CORE Generator module using a VHDL flow:
1. In Project Navigator, double-click stopwatch.vhd to open the file in ISE Text Editor.
2. Place your cursor after the line that states:
-- Insert CORE Generator ROM component declaration here
3. Select Edit > Insert File, then select ipcore_dir/timer_preset.vho and click
Open.
The VHDL template file for the CORE Generator instantiation is inserted.
Design Entry
9. Edit this instantiated code to connect the signals in the Stopwatch design to the ports
of the CORE Generator module as shown below.
10. The inserted code of timer_preset.vho contains several lines of commented text
for instruction and legal documentation. Delete these commented lines if desired.
11. Save the design using File > Save, and close the ISE Text Editor.
Verilog Flow
To instantiate the CORE Generator module using a Verilog flow:
1. In Project Navigator, double-click stopwatch.v to open the file in the ISE Text Editor.
2. Place your cursor after the line that states:
//Place the Coregen module instantiation for timer_preset here
3. Select Edit > Insert File, and select ipcore_dir/timer_preset.veo.
4. The inserted code of timer_preset.veo contains several lines of commented text
for instruction and legal documentation. Delete these commented lines if desired.
5. Change the instance name from YourInstanceName to t_preset.
6. Edit this code to connect the signals in the Stopwatch design to the ports of the CORE
Generator module as shown below.
Design Entry
14. Select Use output frequency and type 26.2144 in the box and select MHz.
18
( 26.2144Mhz ) 2 = 100Hz
9. Highlight the instantiation template in the newly opened HDL Instantiation Template,
shown below.
3. From the newly opened HDL Instantiation Template (dcm1.tfi), copy the
instantiation template, shown below.
The synthesis tool can be changed at any time during the design flow. To change the
synthesis tool:
1. Select the targeted part in the Sources tab.
2. Right-click and select Design Properties.
3. In the Design Properties dialog box, click on the Synthesis Tool value and use the pull-
down arrow to select the desired synthesis tool from the list.
Note: If you do not see your synthesis tool among the options in the list, you may not have the
software installed or may not have it configured in ISE. The Synthesis tools are configured in the
Preferences dialog box (Edit > Preferences, expand ISE General, then click Integrated Tools).
Note: Changing the design flow results in the deletion of implementation data. You have not yet
created any implementation data in this tutorial. For projects that contain implementation data, Xilinx
recommends that you make a copy of the project using File > Copy Project if you would like to make
a backup of the project before continuing.
The RTL Viewer allows you to select the portions of the design to display as schematic.
When the schematic is displayed, double-click on the symbol to push into the schematic
and view the various design elements and connectivity. Right-click the schematic to view
the various operations that can be performed in the schematic viewer.
You have completed XST synthesis. An NGC file now exists for the Stopwatch design.
To continue with the HDL flow:
Go to Chapter 4, Behavioral Simulation, to perform a pre-synthesis simulation of
this design.
OR
Proceed to Chapter 5, Design Implementation, to place and route the design.
Note: For more information about XST constraints, options, reports, or running XST from the
command line, see the XST User Guide. This guide is available in the collection of software manuals
and is accessible from ISE by selecting Help > Software Manuals, or from the web at
http://www.xilinx.com/support/software_manuals.htm.
Lists the synthesis optimizations that were performed on the design and gives a brief
timing and mapping report.
View RTL Schematic
Accessible from the Launch Tools hierarchy, this process displays Synplify or Synplify
Pro with a schematic view of your HDL code
View Technology Schematic
Accessible from the Launch Tools hierarchy, this process displays Synplify or Synplify
Pro with a schematic view of your HDL code mapped to the primitives associated with
the target technology.
Compiler Report
The compiler report lists each HDL file that was compiled, names which file is the top
level, and displays the syntax checking result for each file that was compiled. The report
also lists FSM extractions, inferred memory, warnings on latches, unused ports, and
removal of redundant logic.
Note: Black boxes (modules not read into a design environment) are always noted as unbound in
the Synplify reports. As long as the underlying netlist (.ngo, .ngc or .edn) for a black box exists in the
project directory, the implementation tools merge the netlist into the design during the Translate
phase.
Mapper Report
The mapper report lists the constraint files used, the target technology, and attributes set in
the design. The report lists the mapping results of flattened instances, extracted counters,
optimized flip-flops, clock and buffered nets that were created, and how FSMs were coded.
Timing Report
The timing report section provides detailed information on the constraints that you
entered and on delays on parts of the design that had no constraints. The delay values are
based on wireload models and are considered preliminary. Consult the post-place and
route timing reports discussed in Chapter 5, Design Implementation, for the most
accurate delay information.
Resource Utilization
This section of the report lists all of the resources that Synplify uses for the given target
technology.
You have now completed Synplify synthesis. At this point, a netlist EDN file exists for the
Stopwatch design.
To continue with the HDL flow:
Go to Chapter 4, Behavioral Simulation, to perform a pre-synthesis simulation of
this design.
OR
Proceed to Chapter 5, Design Implementation, to place and route the design.
Accessible from the Launch Tools hierarchy, this process displays Precision with a
schematic-like view of your HDL code mapped to the primitives associated with the
target technology.
View Critical Path Schematic
Accessible from the Launch Tools hierarchy, this process displays Precision with a
schematic-like view of the critical path of your HDL code mapped to the primitives
associated with the target technology.
You have now completed the design synthesis. At this point, an EDN netlist file exists for
the Stopwatch design.
To continue with the HDL flow:
Go to Chapter 4, Behavioral Simulation, to perform a pre-synthesis simulation of
this design.
OR
Proceed to Chapter 5, Design Implementation, to place and route the design.
Chapter 3
Schematic-Based Design
This chapter includes the following sections:
Overview of Schematic-Based Design
Getting Started
Design Description
Design Entry
Getting Started
The following sections describe the basic requirements for running the tutorial.
Required Software
You must have Xilinx ISE11 installed to follow this tutorial. For this design you must install
the Spartan-3A libraries and device files.
A schematic design flow is supported on both Windows and Linux platforms.
This tutorial assumes that the software is installed in the default location, at
c:\xilinx\11.1\ISE. If you have installed the software in a different location,
substitute that for your installation path.
Note: For detailed instructions about installing the software, refer to the ISE 11.1 Installation Guide
and Release Notes.
Getting Started
5. Select the following values in the New Project Wizard - Device Properties window:
Product Category: All
Family: Spartan3A and Spartan3AN
Device: XC3S700A
Package: FG484
Speed: -4
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISim(VHDL/Verilog)
Preferred Language: VHDL or Verilog depending on preference. This will
determine the default language for all processes that generate HDL files.
Other properties can be left at their default values.
6. Click Next twice, and then click Add Source in the New Project Wizard - Add Existing
Sources window.
7. Browse to c:\xilinx\11.1\ISE\ISEexamples\wtut_sc.
8. Select the following files and click Open.
cd4rled.sch
ch4rled.sch
clk_div_262k.vhd
lcd_control.vhd
stopwatch.sch
statmach.vhd
9. Click Next, then Finish to complete the New Project Wizard.
10. Verify that all added source files are set to Design View Association of All, and Library
is work.
Design Description
The design used in this tutorial is a hierarchical, schematic-based design, which means that
the top-level design file is a schematic sheet that refers to several other lower-level macros.
The lower-level macros are a variety of different types of modules, including schematic-
based modules, a CORE Generator module, an Architecture Wizard module, and HDL
modules.
The runners stopwatch design begins as an unfinished design. Throughout the tutorial,
you will complete the design by creating some of the modules and by completing others
from existing files. A schematic of the completed stopwatch design is shown in the
following figure. Through the course of this chapter, you will create these modules,
instantiate them, and then connect them.
Design Description
After the design is complete, you will simulate the design to verify its functionality. For
more information about simulating your design, see Chapter 4, Behavioral Simulation.
There are five external inputs and four external outputs in the completed design. The
following sections summarize the inputs and outputs, and their respective functions.
Inputs
The following are input signals for the tutorial stopwatch design.
strtstop
Starts and stops the stopwatch. This is an active low signal which acts like the
start/stop button on a runners stopwatch.
reset
Puts the stopwatch in clocking mode and resets the time to 0:00:00.
clk
Externally generated system clock.
mode
Toggles between clocking and timer modes. This input is only functional while the
clock or timer is not counting.
lap_load
This is a dual function signal. In clocking mode it displays the current clock value in
the Lap display area. In timer mode it will load the pre-assigned values from the
ROM to the timer display when the timer is not counting.
Outputs
The following are outputs signals for the design.
lcd_e, lcd_rs, lcd_rw
These outputs are the control signals for the LCD display of the Spartan-3A demo
board used to display the stopwatch times.
sf_d[7:0]
Provides the data values for the LCD display.
Functional Blocks
The completed design consists of the following functional blocks. Most of these blocks do
not appear on the schematic sheet in the project until after you create and add them to the
schematic during this tutorial.
The completed design consists of the following functional blocks.
clk_div_262k
Macro which divides a clock frequency by 262,144. Converts 26.2144 MHz clock into
100 Hz 50% duty cycle clock.
dcm1
Clocking Wizard macro with internal feedback, frequency controlled output, and
duty-cycle correction. The CLKFX_OUT output converts the 50 MHz clock of the
Spartan-3A demo board to 26.2144 MHz.
debounce
Module implementing a simplistic debounce circuit for the strtstop, mode, and
lap_load input signals.
lcd_control
Module controlling the initialization of and output to the LCD display.
statmach
State machine module which controls the state of the stopwatch.
timer_preset
CORE Generator 64X20 ROM. This macro contains 64 preset times from 0:00:00 to
9:59:99 which can be loaded into the timer.
Design Entry
time_cnt
Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. This
macro has five 4-bit outputs, which represent the digits of the stopwatch time.
Design Entry
In this hierarchical design, you will create various types of macros, including schematic-
based macros, HDL-based macros, and CORE Generator macros. You will learn the
process for creating each of these types of macros, and you will connect the macros
together to create the completed stopwatch design. All procedures used in the tutorial can
be used later for your own designs.
The stopwatch schematic diagram opens in the Project Navigator Workspace. You will see
the unfinished design with elements in the lower right corner as shown in the figure below.
Design Entry
In the following steps, you will create a schematic-based macro by using the New Source
Wizard in Project Navigator. An empty schematic file is then created, and you can define
the appropriate logic. The created macro is then automatically added to the projects
library.
The macro you will create is called time_cnt. This macro is a binary counter with five, 4-
bit outputs, representing the digits of the stopwatch.
To create a schematic-based macro:
1. In Project Navigator, select Project > New Source. The New Source dialog box opens:
The New Source dialog displays a list of all of the available source types.
2. Select Schematic as the source type.
3. Enter time_cnt as the file name.
4. Click Next and click Finish.
A new schematic called time_cnt.sch is created, added to the project, and opened for
editing.
5. Change the size of the schematic sheet by doing the following.
Right-click on the schematic page and select Object Properties.
Click on the down arrow next to the sheet size value and select D = 34 x 22.
Click OK and then click Yes to acknowledge that changing the sheet size cannot
be undone with the Edit > Undo option.
4. Click OK. The eleven I/O markers are added to the schematic sheet.
Note: The Create I/O Marker function is available only for an empty schematic sheet. However, I/O
markers may be added to nets at any time by selecting Add > I/O Marker and selecting the desired
net.
Design Entry
This opens the Symbol Browser to the left of the schematic editor, displaying the
libraries and their corresponding components.
The first component you will place is a cd4rled, a 4-bit, loadable, bi-directional, BCD
counter with clock enable and synchronous clear.
2. Select the cd4rled component, using one of two ways:
Highlight the project directory category from the Symbol Browser dialog box and
select the component cd4rled from the symbols list.
or
Select All Symbols and type cd4rled in the Symbol Name Filter at the bottom of
the Symbol Browser window.
3. Move the mouse back into the schematic window.
You will notice that the cursor has changed to represent the cd4rled symbol.
4. Move the symbol outline near the top and center of the sheet and click the left mouse
button to place the object.
Note: You can rotate new components being added to a schematic by selecting Ctrl+R. You
can rotate existing components by selecting the component, and then selecting Ctrl+R.
5. Place three more cd4rled symbols on the schematic by moving the cursor with
attached symbol outline to the desired location, and clicking the left mouse button. See
Figure 3-10
6. Follow the procedure outlined in steps 1 through 4 above to place the following
components on the schematic sheet:
AND2b1
ch4rled
AND5
Refer to Figure 3-10 for placement locations.
To exit the Symbols Mode, press the Esc key on the keyboard.
Design Entry
Correcting Mistakes
If you make a mistake when placing a component, you can easily move or delete the
component.
To move the component, click the component and drag the mouse around the window.
Delete a placed component in one of two ways:
Click the component and press the Delete key on your keyboard.
or
Right-click the component and select Delete.
Drawing Wires
Use the Add Wire icon in the Tools toolbar to draw wires (also called nets) to connect the
components placed in the schematic.
Perform the following steps to draw a net between the AND2b1 and top cd4rled
components on the time_cnt schematic.
1. Select Add > Wire or click the Add Wire icon in the Tools toolbar.
2. Click the output pin of the AND2b1 and then click the destination pin CE on the
cd4rled component. The Schematic Editor draws a net between the two pins.
3. Draw a net to connect the output of the AND5 component to the inverted input of the
AND2b1 component. Connect the other input of the AND2b1 to the ce input IO
marker.
4. Connect the load, up, clk, and clr input IO markers respectively to the L, UP, C, and R
pins of each of the five counter blocks and connect the CEO pin of the first four
counters to the CE pin of the next counter as shown in Figure 3-10.
To specify the shape of the net:
1. Move the mouse in the direction you want to draw the net.
2. Click the mouse to create a 90-degree bend in the wire.
To draw a net between an already existing net and a pin, click once on the component pin
and once on the existing net. A junction point is drawn on the existing net.
Adding Buses
In the Schematic Editor, a bus is simply a wire that has been given a multi-bit name. To add
a bus, use the methodology for adding wires and then add a multi-bit name. Once a bus
has been created, you have the option of tapping this bus off to use each signal
individually.
The next step is to create three buses for each of the five outputs of the time_cnt
schematic. The results can be found in the completed schematic.
To add the buses hundredths(3:0), tenths(3:0), sec_lsb(3:0), sec_msb(3:0) and minutes(3:0)
to the schematic, perform the following steps:
1. Select all of the output IO markers by drawing a box around them and then drag the
group so that minutes(3:0) is below the Q3 output of the bottom counter block.
2. Select Add > Wire or click the Add Wire icon in the Tools toolbar.
3. Click in the open space just above and to the right of the top cd4rled and then click
again on the pin of the hundredths(3:0) I/O marker. The thick line should
automatically be drawn to represent a bus with the name matching that of the I/O
marker.
The cursor changes, indicating that you are now in Draw Bus Tap mode.
2. From the Options tab to the left of the schematic, choose the --< Right orientation for
the bus tap.
Design Entry
3. Click on the hundreths(3:0) bus with the center bar of the cursor.
The Selected Bus Name and the Net Name values of the options window are now
populated.
Note: The indexes of the Net Name may be incremented or decremented by clicking the arrow
buttons next to the Net Name box.
4. With hundredths(3) as the Net Name value, move the cursor so the tip of the attached
tap touches the Q3 pin of the top cd4rled component.
Note: Four selection squares appear around the pin when the cursor is in the correct position.
5. Click once when the cursor is in the correct position.
A tap is connected to the hundredths(3:0) bus and a wire named hundreths(3) is drawn
between the tap and the Q3 pin.
Click successively on pins Q2, Q1, and Q0 to create taps for the remaining bits of the
hundredths(3:0) bus.
6. Repeat Steps 3 to 6 to tap off four bits from each of the five buses.
Note: It is the name of the wire that makes the electrical connection between the bus and the wire
(e.g sec_msb(2) connects to the third bit of sec(3:0)). The bus tap figure is for visual purposes only.
The following section shows additional electrical connections by name association.
7. Press Esc to exit the Add Net Name mode.
8. Compare your time_cnt schematic with Figure 3-15 to ensure that all connections are
made properly.
2. Type tc_out0 in the Name box and select Increase the Name in the Add Net Names
Options dialog box.
The net name tc_out0 is now attached to the cursor.
3. Click the net attached to the first input of the AND5 component.
The name is then attached to the net. The net name appears above the net if the name
is placed on any point of the net other than an end point.
4. Click on the remaining input nets of the AND5 to add tc_out1, tc_out2, tc_out3 and
tc_out4.
The Schematic Editor increments the net Name as each name is placed on a net.
Alternatively, name the first net tc_out4 and select Decrease the name in the Add Net
Names Options dialog box, and nets are named from the bottom up.
5. Repeat step 2 and then click successively on the nets connected to the TC output to add
tc_out0, tc_out1, tc_out2, tc_out3, and tc_out4 to these nets.
Note: Each of the wires with identical names are now electrically connected. In this case, the nets
do not need to be physically connected on the schematic to make the logical connection.
Finally, connect the input pins of the counters through net name association.
1. Select Add > Wire or click the Add Wire icon and add a hanging net to the four data
pins of each of the five counters.
2. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar.
3. Type q(0) in the Name box of the Add Net Name options dialog box.
4. Select Increase the name in the Add Net Name options dialog box.
The net name q(0) is now attached to the cursor.
5. Click successively on each of the nets connected to data inputs, starting from the top so
that the net named q(0) is attached to the D0 pin of the top counter and the net named
q(19) is attached to the D3 pin of the bottom counter. Refer to Figure 3-15.
Note: If the nets appear disconnected, select View > Refresh to refresh the screen.
Design Entry
7. Fill in the Distributed Memory Generator customization GUI with the following
settings:
Component Name: timer_preset - Defines the name of the module.
Design Entry
10. Specify the Coefficients File: Click the Browse button and select
definition1_times.coe.
11. Check that only the following pins are used (used pins are highlighted on the symbol
on the left side of the customization GUI):
a[5:0]
spo[19:0]
12. Click Generate.
The module is created and automatically added to the project library.
Note: A number of files are added to the project directory. Some of these files are:
timer_preset.sym
This file is a schematic symbol file.
timer_preset.vhd or timer_preset.v
These are HDL wrapper files for the core and are used only for simulation.
timer_preset.ngc
This file is the netlist that is used during the Translate phase of implementation.
timer_preset.xco
This file stores the configuration information for the timer_preset module and is
used as a project source.
timer_preset.mif
This file provides the initialization values of the ROM for simulation.
Design Entry
Feedback Value: 1X
Use Duty Cycle Correction: Selected
Design Entry
In the ISE Text Editor, the ports are already declared in the HDL file, and some of the basic
file structure is already in place. Keywords are displayed in blue, comments in green, and
values are black. The file is color-coded to enhance readability and help you recognize
typographical errors.
Design Entry
This opens the Symbol Browser to the left of the Schematic Editor, which displays the
libraries and their corresponding components.
2. View the list of available library components in the Symbol Browser.
3. Locate the project-specific macros by selecting the project directory name in the
Categories window.
4. Select the appropriate symbol, and add it to the stopwatch schematic in the
approximate location, as shown in Figure 3-28.
Note: Do not worry about drawing the wires to connect the symbols. You will connect components
in the schematic later in the tutorial.
Design Entry
Hierarchy Push/Pop
First, perform a hierarchy push down, which enables you to focus in on a lower-level of
the schematic hierarchy to view the underlying file. Push down into the time_cnt macro,
which is a schematic-based macro created earlier in this tutorial, and examine its
components.
To push down into time_cnt from the top-level, stopwatch, schematic:
1. Click time_cnt symbol in the schematic, and select the Hierarchy Push icon. You can
also right-click the macro and select Symbol > Push into Symbol.
In the time_cnt schematic, you see five counter blocks. Push into any of the counter
blocks by selecting the block and clicking on the Hierarchy Push icon. This process
may be repeated until the schematic page contains only Xilinx primitive components.
If a user pushes into a symbol that has an underlying HDL or IP core file, the
appropriate text editor or customization GUI will open and be ready to edit the file.
2. After examining the macro, return to the top-level schematic by selecting View > Pop
to Calling Schematic, or select the Hierarchy Pop icon when nothing in the
schematic is selected. You can also right-click in an open space of the schematic and
select Pop to Calling Schematic.
Design Entry
5. To make the LOC attribute visible, select the Add button adjacent to the LOC attribute
in the Attribute window.
6. In the Net Attribute Visibility window, click on a location near the center of the
displayed net and then select OK.
This will display the LOC attribute on the schematic above the clk net.
Click OK to close the Object properties window.
The above procedure constrains clk to pin E12. Notice that the LOC property has
already been added to the sf_d(7:0) bus. The remaining pin location constraints will be
added in Using the Constraints Editor and Assigning I/O Locations Using PlanAhead of
Chapter 5, Design Implementation.
Note: To turn off the Location constraint without deleting it, select the loc attribute, and click Edit
Traits. Select VHDL or Verilog and select Ignore this attribute.
Design Entry
to in this section has been discussed in detail in earlier sections of the tutorial. Please see
the earlier sections for detailed instructions.
Chapter 4
Behavioral Simulation
This chapter contains the following sections.
Overview of Behavioral Simulation Flow
ModelSim Setup
ISim Setup
Getting Started
Adding an HDL Test Bench
Behavioral Simulation Using ModelSim
Behavioral Simulation Using ISim
ModelSim Setup
In order to use this tutorial, you must install ModelSim on your computer. The following
sections discuss requirements and setup for ModelSim PE, ModelSim SE, and
ModelSim XE.
ModelSim PE and SE
ModelSim PE and ModelSim SE are full versions of ModelSim available for purchase
directly from Mentor Graphics. In order to simulate with the ISE 11 libraries, use ModelSim
6.4b or newer. Older versions may work but are not supported. For more information
about ModelSim PE or SE, please contact Mentor Graphics.
ISim Setup
ISim is automatically installed and set up with the ISE 11.1 installer on supported
operating systems. Please see list of operating systems supported by ISim on the web at
http://www.xilinx.com/ise/ossupport/index.htm#simulator
Getting Started
The following sections outline the requirements for performing behavioral simulation in
this tutorial.
Required Files
The behavioral simulation flow requires design files, a test bench file, and Xilinx
simulation libraries.
Getting Started
For a detailed description of each library, see Chapter 5 of the Synthesis and Simulation
Design Guide. This Guide is accessible from within ISE by selecting Help > Software
Manuals, and from the web at
http://www.xilinx.com/support/documentation/dt_ise11-1.htm.
ModelSim PE or SE
If you are using ModelSim PE or SE, you must compile the simulation libraries with the
updated models. See Chapter 6 of the Synthesis and Simulation Design Guide. This Guide is
accessible from within ISE by selecting Help > Software Manuals, or from the web at
http://www.xilinx.com/support/documentation/dt_ise11-1.htm.
Xilinx ISim
Updated simulation libraries for the ISim are precompiled and installed with ISE
installations and software updates.
If the MODELSIM environment variable is not set, and the modelsim.ini file has not
been copied to the working directory, the modelsim.ini file in the ModelSim installation
directory is used.
ModelSim PE or SE
If you are using ModelSim PE or SE, refer to the Development System Reference Guide and use
COMPXLIB to compile the libraries. While compiling the libraries, COMPXLIB also
updates the modelsim.ini file with the correct library mapping. Open the
modelsim.ini file and make sure that the library mappings are correct.
For future projects, you can copy the modelsim.ini file to the working directory and
make changes that are specific to that project, or you can use the MODELSIM environment
variable to point to the desired modelsim.ini file.
ISE Simulator
The modelsim.ini file is not applicable to the ISE Simulator.
VHDL Simulation
To add the tutorial VHDL test bench to the project:
1. Select Project > Add Source.
2. Select the test bench file stopwatch_tb.vhd.
3. Click Open.
4. Check that Simulation is selected for the file Association type.
5. Click OK.
ISE recognizes the top-level design file associated with the test bench, and adds the test
bench in the correct order.
Verilog Simulation
To add the tutorial Verilog test fixture to the project:
1. Select Project > Add Source.
2. Select the file stopwatch_tb.v.
3. Click Open.
4. Check that Simulation is selected for the file association type.
5. Click OK.
ISE recognizes the top-level design file associated with the test fixture, and adds the test
fixture in the correct order.
If ModelSim is installed but the processes are not available, the Project Navigator
preferences may not be set correctly.
To set the ModelSim location:
1. Select Edit > Preferences.
2. Click the + next to ISE General to expand the ISE preferences
3. Click Integrated Tools in the left pane.
4. In the right pane, under Model Tech Simulator, browse to the location of the
modelsim executable. For example,
C:\modeltech_xe\win32xoem\modelsim.exe
The following simulation processes are available:
Simulate Behavioral Model
This process starts the design simulation.
7. Click OK.
For a detailed description of each property available in the Process Properties dialog box,
click Help.
Performing Simulation
Once the process properties have been set, you are ready to run ModelSim. To start the
behavioral simulation, double-click Simulate Behavioral Model. ModelSim creates the
work directory, compiles the source files, loads the design, and performs simulation for the
time specified.
The majority of this design runs at 100 Hz and would take a significant amount of time to
simulate. The first outputs to transition after RESET is released are the SF_D and LCD_E
control signals at around 33 mS. This is why the counter may seem like it is not working in
a short simulation. For the purpose of this tutorial, only the DCM signals are monitored to
verify that they work correctly.
Adding Signals
To view internal signals during the simulation, you must add them to the Wave window.
ISE automatically adds all the top-level ports to the Wave window. Additional signals are
displayed in the Signal window based on the selected structure in the Structure window.
There are two basic methods for adding signals to the Simulator Wave window.
Drag and drop from the Signal/Object window.
Highlight signals in the Signal/Object window, and select Add > Wave > Selected
Signals.
The following procedure explains how to add additional signals in the design hierarchy. In
this tutorial, you will be adding the DCM signals to the waveform.
If you are using ModelSim version 6.0 or higher, all the windows are docked by default. To
undock the windows, click the Undock icon.
Adding Dividers
In ModelSim, you can add dividers in the Wave window to make it easier to differentiate
the signals. To add a divider called DCM Signals:
1. Right click anywhere in the signal section of the Wave window. If necessary, undock
the window and maximize the window for a larger view of the waveform.
2. Select Insert Divider.
3. Enter DCM Signals in the Divider Name box.
4. Click OK.
5. Click and drag the newly created divider to above the CLKIN_IN signal.
After adding the DCM Signals divider, the waveform will look like Figure 4-6.
The waveforms have not been drawn for any of the newly added signals. This is because
ModelSim did not record the data for these signals. By default, ModelSim records data
only for the signals that have been added to the Wave window while the simulation is
running. After new signals are added to the Wave window, you must rerun the simulation
for the desired amount of time.
Rerunning Simulation
To rerun simulation in ModelSim:
1. Click the Restart Simulation icon.
The simulation runs for 2000 ns. The waveforms for the DCM are now visible in the Wave
window.
5. Look at the bottom of the waveform for the distance between the two cursors.
The measurement should read 20000 ps. This converts to 50 MHz, which is the input
frequency from the test bench, which in turn should be the DCM CLK0 output.
6. Measure CLKFX_OUT using the same steps as above. The measurement should read
38462 ps. This comes out to approximately 26 MHz.
Performing Simulation
Once the process properties have been set, you are ready to run ISim to simulate the
design. To start the behavioral simulation, double-click Simulate Behavioral Model. ISim
creates the work directory, compiles the source files, loads the design, and performs
simulation for the time specified.
The majority of this design runs at 100 Hz and would take a significant amount of time to
simulate. The first outputs to transition after RESET is released are SF_D and LCD_E at
around 33 mS. This is why the counter may seem like it is not working in a short
simulation. For the purpose of this tutorial, only the DCM signals are monitored to verify
that they work correctly.
Adding Signals
To view signals during the simulation, you must add them to the Waveform window. ISE
automatically adds all the top-level ports to the Waveform window. Additional signals are
displayed in the Instances and Processes panel. The following procedure explains how to
add additional signals in the design hierarchy. For the purpose of this tutorial, add the
DCM signals to the waveform.
To add additional signals in the design hierarchy:
1. In the Instances and Processes panel, click the > next to stopwatch_tb to expand the
hierarchy.
2. Click the > next to UUT to expand the hierarchy.
The figure below shows the contents of the Instances and Processes panel for the VHDL
flow. The graphics and the layout of the window for a schematic or Verilog flow may be
different.
Notice that the waveforms have not been drawn for the newly added signals. This is
because ISim did not record the data for these signals. By default, ISim records data only
for the signals that have been added to the waveform window while the simulation is
running. Therefore, when new signals are added to the waveform window, you must rerun
the simulation for the desired amount of time.
Rerunning Simulation
To rerun the simulation in ISim:
1. Click the Restart Simulation icon.
2. At the ISE Simulator command prompt in the Console, enter run 2000 ns and press
Enter.
The simulation runs for 2000 ns. The waveforms for the DCM are now visible in the
Waveform window.
outputs are valid only after the LOCKED_OUT signal is high; therefore, the DCM signals
are analyzed only after the LOCKED_OUT signal has gone high.
ISim can add markers to measure the distance between signals. To measure the
CLK0_OUT:
1. If necessary, zoom in on the waveform using the zoom local toolbar icons.
2. Click on the Snap to Transition toolbar button in the waveform viewer local toolbar.
3. Click on the first rising edge transition on the CLK0_OUT signal after the
LOCKED_OUT signal has gone high, then drag the cursor to the right to the next rising
edge transition of the CLK0_OUT signal.
4. At the bottom of the waveform window, the start point time, end point time, and delta
times are shown. The delta should read 20,000 ps (or 20 ns). This converts to 50
MHz which is the input frequency from the test bench, which in turn is the DCM CLK0
output. .
5. Measure CLKFX_OUT using the same steps as above. The measurement should read
38,500 ps (or 38.5 ns). This equals approximately 26 MHz.
Your behavioral simulation is complete. To implement the design, follow the steps in
Chapter 5, Design Implementation.
Chapter 5
Design Implementation
This chapter contains the following sections.
Overview of Design Implementation
Getting Started
Specifying Options
Creating Timing Constraints
Translating the Design
Using the Constraints Editor
Assigning I/O Locations Using PlanAhead
Mapping the Design
Using Timing Analysis to Evaluate Block Delays After Mapping
Placing and Routing the Design
Using FPGA Editor to Verify the Place and Route
Evaluating Post-Layout Timing
Creating Configuration Data
Command Line Implementation
Getting Started
The tutorial design emulates a runners stopwatch with actual and lap times. There are five
inputs to the system: CLK, RESET, LAP_LOAD, MODE, and SRTSTP. This system
generates a traditional stopwatch with lap times and a traditional timer on a LCD display.
Specifying Options
3. Open ISE.
a. On a workstation, enter ise.
b. On a PC, select Start > Programs > Xilinx ISE 11 > Project Navigator.
4. Create a new project and add the EDIF netlist as follows:
a. Select File > New Project.
b. Type EDIF_Flow for the Project Name.
c. Select EDIF for the top_level SourceType.
d. Click Next.
e. Select stopwatch.edf for the Input Design file.
f. Select stopwatch.ucf for the Constraints file.
g. Click Next.
h. Select the following:
- Spartan3a for the Device Family
- xc3s700a for the Device
- -4 for the Speed Grade, fg484 for the Package
i. Keep the rest of the properties at their default values.
j. Click Next.
k. Click Finish.
l. Copy the timer_preset.ngc file into the EDIF_Flow directory.
In the Sources tab, select the top-level module, stopwatch.edf or stopwatch.edn.
This enables the design to be implemented.
Specifying Options
This section describes how to set some properties for design implementation. The
implementation properties control how the software maps, places, routes, and optimizes a
design.
To set the implementation property options for this tutorial:
1. In the Sources view in the Design tab, select the stopwatch top-level file.
Note: Be sure the Implementation view is active by selecting it from the Sources for: dropdown
menu in the Sources view.
2. In the Processes view in the Design tab, right-click the Implement Design process.
3. Select Process Properties from the right-click menu.
The Process Properties dialog box provides access to the Translate, Map, Place and
Route, and Timing Report properties. You will notice a series of categories, each
contains properties for one of these phases of design implementation.
4. Ensure that you have set the Property display level to Advanced. This global setting
enables you to see all available properties.
5. Click the Place & Route Properties category.
6. Change the Place & Route Effort Level (Overall) to High.
This option increases the overall effort level of Place and Route during
implementation.
This automatically runs the Translate step, which is discussed in the following section.
Then the Constraints Editor opens.
1. Double-click the row containing the clk signal in the Unconstrained Clocks table. The
Clock Period dialog box opens.
2. For the Clock Signal Definition, verify that Specify Time is selected.
This enables you to define an explicit period for the clock.
3. Enter a value of 7.0 in the Time field.
4. Verify that ns is selected from the Units drop-down list.
5. For the Input Jitter section, enter a value of 60 in the Time field.
6. Verify that ps is selected from the Units drop-down list.
7. Click OK.
The period constraint is displayed in the constraint table at the top of the window. The
period cell is updated with the global clock period constraint that you just defined
(with a default 50% duty cycle).
8. Select the Inputs branch under Timing Constraints in the Constraint Type tree view.
9. Double-click on the clk signal in the Global OFFSET IN Constraint table to bring up
the Create Setup Time (OFFSET IN) wizard.
10. Keep the default values on the first page of the screen and click Next.
11. In the External setup time (offset in) field, enter 6 ns.
12. In the Data valid duration field, enter 6 ns.
This creates a Global OFFSET IN constraint for the CLK signal.
13. Click Finish.
14. Select the Outputs branch under Timing Constraints in the Constraint Type tree view
15. Double-click the clk signal in the Global OFFSET OUT Constraint table.
16. In the External clock to pad (offset out) field, enter a value of 38 ns.
This creates a Global OFFSET OUT constraint for the CLK signal
17. Click OK.
18. In the Unconstrained Output Ports table, select the sf_d<0> through sf_d<7> signals
using Shift-Click to select multiple rows.
19. Right-click and select Create Time Group.
20. In the Create Time Group dialog, type display_grp for the Time group name, then
click OK. .
21. When asked if you would like to create an offest constraint, click OK.
22. In the External clock to pad (offset out) field, enter 32 ns.
I/O Pin Planning can be performed either Pre- or Post- Synthesis. Whenever possible
it is recommended that the process be run Post-Synthesis since the design then
contains information needed for I/O and clock related design rule checks that can be
performed by PlanAhead.
This process launches PlanAhead. If the design has not yet completed synthesis, Project
Navigator will first automatically run synthesis before launching PlanAhead for I/O
Planning.
The Welcome to PlanAhead screen provides links to detailed documentation, tutorials, and
other training material to help you learn more about PlanAhead. This tutorial provides a
simple overview of the use and capabilities of PlanAhead; for more information and to
learn about the full capabilities, please visit the other resources available.
7. Repeat the previous step to place the following additional output pins.
LCD_RS: Y14
LCD_RW: W13
Alternatively, you can type the location in the Site field in the I/O Port Properties tab
when the I/O signal is selected.
8. Using either the drag and drop or Port Properties method, place the following input
signals onto the appropriate I/O pin locations:
LAP_LOAD: T16
RESET: U15
MODE: T14
STRTSTOP: T15
9. Once the pins are locked down, select File > Save Project. The changes are saved in
the projects stopwatch.ucf file.
10. Close PlanAhead by selecting File > Exit.
Each step generates its own report as shown in the following table. .
To view a report:
1. Open the Design Summary/Reports window. If it is not already open in the
Workspace you can open it by running the Design Summary/Reports process.
2. Select a report such as the Translation Report or Map Report in the Detailed Reports
section of the Design Summary.
3. Review the report.
4. The Design Summary also provides a Summary of the design results, and a list of all of
the messages (Errors, Warnings, INFO) generated by the implementation run.
This analysis can help to determine if your timing constraints are going to be met. This
report is produced after Map and prior to Place and Route (PAR).
The work space shows the report for the selected constraint. At the top of this report, you
will find the selected period constraint and the minimum period obtained by the tools after
mapping. By default, only three paths per timing constraint will be shown. Selecting one of
the three paths allows you to see a breakdown of the path which contains the component
and routing delays.
Notice that the report displays the percentage of logic versus the percentage of routing at
the end of each path (e.g. 88.0% logic, 12.0% route). The unplaced floors listed are estimates
(indicated by the letter e next to the net delay) based on optimal placement of blocks.
5. After viewing the report, close the Timing Analyzer by selecting File > Close.
Note: Even if you do not generate a timing report, PAR still processes a design based on the
relationship between the block delays, floors, and timing specifications for the design. For example, if
a PERIOD constraint of 8 ns is specified for a path, and there are block delays of 7 ns and unplaced
floor net delays of 3 ns, PAR stops and generates an error message. In this example, PAR fails
because it determines that the total delay (10 ns) is greater than the constraint placed on the design
(8 ns). The Post-Map Static Timing Report will list any pre-PAR timing violations.
View and change the nets connected to the capture units of an Integrated Logic
Analyzer (ILA) core in your design.
To view the actual design layout of the FPGA:
1. Click the + next to Place & Route to expand the process hierarchy, and double-click
View/Edit Routed Design (FPGA Editor).
2. In FPGA Editor, change the List Window from All Components to All Nets. This
enables you to view all of the possible nets in the design.
3. Select the clk_262144K (Clock) net to see the fanout of the clock net.
The following is a summary of the Post-Place & Route Static Timing Report for the
stopwatch design:
The minimum period value increased due to the actual routing delays.
The Post-Map timing report showed logic delays contributed to 80% to 90% of the
minimum period attained. The post-layout report indicates that the logical delay
value now equals between 30% and 40% of the period. The total unplaced floors
estimate changed as well.
The post-layout result does not necessarily follow the 50/50 rule previously
described because the worst case path primarily includes component delays.
For some hard to meet timing constraints, the worst case path is mainly made up
of logic delay. Since total routing delay makes up only a small percentage of the
total path delay spread out across two or three nets, expecting the timing of these
paths to be reduced any further is unrealistic. In general, you can reduce excessive
block delays and improve design performance by decreasing the number of logic
levels in the design.
2. When PlanAhead opens, select one of the timing paths in the Timing Results tab. You
will be able to view the path graphically in the Device view, and also view details of
the path and the associated delays in the Properties tab.
3. Zoom in on the path in the Device view by clicking and dragging a box around the area
of interest.
For a detailed tutorial on the full set of capabilities in PlanAhead related to timing analysis
and design closure, see the Design Analysis and Floorplanning tutorial available in
PlanAhead by selecting Help > Tutorial > Design Analysis and Floorplanning.
4. Close PlanAhead by selecting File > Exit.
3. In the PROM File Formatter window, select Xilinx Flash/PROM in the Select Storage
Target section.
4. Click the green arrow to activate the next section.
5. In the Add Storage Device(s) section, click the Auto Select PROM checkbox.
6. Click the green arrow to activate the next section.
7. In the Enter Data section, enter an Output File Name of stopwatch1.
8. Verify that the Checksum Fill Value is set to FF and the File Format is MCS. .
information on programming a device, see the iMPACT Help, available from the iMPACT
application by selecting Help > Help Topics.
This completes the Design Implementation chapter of the tutorial. For more information
on this design flow and implementation methodologies, see the ISE Help, available from
the ISE application by selecting Help > Help Topics.
Chapter 6
Timing Simulation
This chapter includes the following sections.
Overview of Timing Simulation Flow
Getting Started
Timing Simulation Using ModelSim
Timing Simulation Using Xilinx ISim
Getting Started
The following sections outline the requirements to perform this part of the tutorial flow.
Required Software
To simulate with ModelSim, you must have Xilinx ISE 11 and ModelSim simulator
installed. Refer to Chapter 4, Behavioral Simulation for information on installing and
setting up ModelSim. Simulating with the Xilinx ISE simulator requires that the ISE 11
software is installed
Required Files
The timing simulation flow requires the following files:
Design Files (VHDL or Verilog)
This chapter assumes that you have completed Chapter 5, Design Implementation,
and thus, have a placed and routed design. The Netgen tool will be used in this chapter
to create a simulation netlist from the placed and routed design which will be used to
represent the design during the Timing Simulation.
Test Bench File (VHDL or Verilog)
In order to simulate the design, a test bench is needed to provide stimulus to the
design. You should use the same test bench that was used to perform the behavioral
simulation. Please refer to the Adding an HDL Test Bench in Chapter 4 if you do not
already have a test bench in your project.
Xilinx Simulation Libraries
For timing simulation, the SIMPRIM library is needed to simulate the design.
To perform timing simulation of Xilinx designs in any HDL simulator, the SIMPRIM
library must be set up correctly. The timing simulation netlist created by Xilinx is
composed entirely of instantiated primitives, which are modeled in the SIMPRIM library.
If you completed Chapter 4, Behavioral Simulation, the SIMPRIM library should already
be compiled. For more information on compiling and setting up Xilinx simulation
libraries, see to Xilinx Simulation Libraries in Chapter 4.
Specifying a Simulator
To select either the desired simulator to simulate the stopwatch design, complete the
following:
1. In the Sources tab, right-click the device line (xc3s700A-4fg484) and select Properties.
2. In the Project Properties dialog box click the down arrow in the Simulator value field
to display a list of simulators.
Note: ModelSim and Xilinx ISim are the only simulators that are integrated with Project
Navigator. Selecting a different simulator (e.g. NC-Sim or VCS) will set the correct options for
Netgen to create a simulation netlist for that simulator but Project Navigator will not directly open
the simulator. For additional information about simulation, and for a list of other supported
simulators, see Chapter 5 of the Synthesis and Verification Guide. This Guide is accessible from
within ISE by selecting Help > Software Manuals, and from the web at
http://www.xilinx.com/support/software_manuals.htm
3. Select ISim (VHDL/Verilog) or Modelsim with the appropriate version and language
in the Simulator value field.
For this tutorial, the default Simulation Model Properties are used.
10. In the Simulation Properties tab, set the Simulation Run Time property to 2000 ns.
Performing Simulation
To start the timing simulation, double-click Simulate Post-Place and Route Model in the
Processes tab.
ISE will run Netgen to create the timing simulation model. ISE will then call ModelSim and
create the working directory, compile the source files, load the design, and run the
simulation for the time specified.
Note: The majority of this design runs at 100 Hz and would take a significant amount of time to
simulate. This is why the counter will seem like it is not working in a short simulation. For the purpose
of this tutorial, only the DCM signals will be monitored to verify that they work correctly.
Adding Signals
To view signals during the simulation, you must add them to the Wave window. ISE
automatically adds all the top-level ports to the Wave window. Additional signals are
displayed in the Signal window based on the selected structure in the Structure window.
There are two basic methods for adding signals to the Simulator Wave window.
Drag and drop from the Signal/Object window.
Highlight signals in the Signal/Object window and then select Add > Wave >
Selected Signals.
The following procedure explains how to add additional signals in the design hierarchy. In
this tutorial, you will be adding the DCM signals to the waveform.
Note: If you are using ModelSim version 6.0 or higher, all the windows are docked by default. All
windows can be undocked by clicking the Undock icon.
1. In the Structure/Instance window, click the + next to uut to expand the hierarchy.
Figure 6-4 shows the Structure/Instance window for the Schematic flow. The graphics and
the layout of the Structure/Instance window for a Verilog or VHDL flow may appear
different.
8. Click and drag the following signals from the Signal/Object window to the Wave
window:
RST
CLKFX
CLK0
LOCKED
Note: Multiple signals can be selected by holding down the Ctrl key. In place of using the drag and
drop method select Add to Wave > Selected Signals.
Adding Dividers
Modelsim has the capability to add dividers in the Wave window to make it easier to
differentiate the signals. To add a divider called DCM Signals:
1. Click anywhere in the Wave window.
2. If necessary, undock the window and then maximize the window for a larger view of
the waveform.
3. Right-click the Wave window and click Insert > Divider.
4. Enter DCM Signals in the Divider Name box.
5. Click and drag the newly created divider to above the CLKIN signal.
Note: Stretch the first column in the waveform to see the signals clearly. The hierarchy in the signal
name can also be turned off by selecting Tools > Options > Wave Preferences. In the Display
Signal Path box, enter 2 and click OK.
The waveform should look as shown in Figure 6-5.
Notice that the waveforms have not been drawn for the newly added signals. This is
because ModelSim did not record the data for these signals. By default, ModelSim will
only record data for the signals that have been added to the Wave window while the
simulation is running. Therefore, after new signals are added to the Wave window, you
need to rerun the simulation for the desired amount of time.
Rerunning Simulation
To restart and re-run the simulation:
1. Click the Restart Simulation icon.
2. Click Restart.
3. At the ModelSim command prompt, enter run 2000 ns and hit the Enter key.
The simulation will run for 2000 ns. The waveforms for the DCM should now be visible in
the Wave window.
1. Select Add > Cursor twice to place two cursors on the wave view.
2. Click and drag the first cursor to the rising edge transition on the CLK0 signal after the
LOCKED signal has gone high.
3. Click and drag the second cursor to a position just right of the first cursor on the CLK0
signal.
4. Click the Find Next Transition icon twice to move the cursor to the next rising edge on
the CLK0 signal.
Look at the bottom of the waveform to view the distance between the two cursors. The
measurement should read 20000 ps. This converts to 50 Mhz, which is the input frequency
from the test bench, which in turn should be the DCM CLK0 output.
Measure CLKFX using the same steps as above. The measurement should read 38462 ps.
This equals approximately 26 Mhz.
3. Click Save.
After restarting the simulation, you can select File > Load in the Wave window to reload
this file.
Your timing simulation is complete and you are ready to program your device by
following Chapter 7, iMPACT Tutorial.
Performing Simulation
To start the timing simulation, double-click Simulate Post-Place and Route Model in the
Processes tab.
When a simulation process is run, Project Navigator automatically runs Netgen to generate
a timing simulation model from the placed and routed design. The ISE Simulator will then
compile the source files, load the design, and run the simulation for the time specified.
Note: The majority of this design runs at 100 Hz and would take a significant amount of time to
simulate. This is why the counter will seem like it is not working in a short simulation. For the purpose
of this tutorial, only the DCM signals will be monitored to verify that they work correctly.
Adding Signals
To view signals during the simulation, you must add them to the waveform window. ISE
automatically adds all the top-level ports to the waveform window. All available external
(top-level ports) and internal signals are displayed in the Sim Hierarchy window.
The following procedure explains how to add additional signals in the design hierarchy. In
this tutorial, you will be adding the DCM signals to the waveform.
1. In the Instances and Processes panel, click the > next to stopwatch_tb to expand the
hierarchy.
2. Click the > next to UUT to expand the hierarchy.
3. Locate and select Inst_dcm1_DCM_SP_INST
4. In the Objects window, select the locked signal and click on Add to Wave Window.
Figure 6-12 shows the Sim Instances and Sim Objects window for the VHDL flow. The
signal names and layout in the Sim Instances window for a schematic or VHDL flow may
appear different.
Figure 6-12: Sim Instances and Sim Objects Windows- VHDL Flow
5. Click and drag the following X_DCM_SP signals from the SIM Hierarchy window to
the waveform window:
RST
CLKFX
CLK0
CLKIN
Note: Multiple signals can be selected by holding down the Ctrl key.
Notice that the waveforms have not been drawn for the newly added signals. This is
because the ISE Simulator did not record the data for these signals. The ISE Simulator will
only record data for the signals that have been added to the waveform window while the
simulation is running. Therefore, after new signals are added to the waveform window,
you need to rerun the simulation for the desired amount of time.
Rerunning Simulation
To restart and re-run the simulation:
2. At the Sim Console command prompt, enter run 2000 ns and hit the Enter key.
The simulation will run for 2000 ns. The waveforms for the DCM should now be visible in
the Simulation window.
Your timing simulation is complete and you are ready to program your device by
following Chapter 7, iMPACT Tutorial..
Chapter 7
iMPACT Tutorial
This chapter takes you on a tour of iMPACT, a file generation and device programming
tool. iMPACT enables you to program through several parallel cables, including the
Platform Cable USB. iMPACT can create bit files, System ACE files, PROM files, and
SVF/XSVF files. The SVF/XSVF files can be played backed without having to recreate the
chain.
This tutorial contains the following sections:
Device Support
Download Cable Support
Configuration Mode Support
Getting Started
Creating a iMPACT New Project File
Using Boundary Scan Configuration Mode
Troubleshooting Boundary Scan Configuration
Creating an SVF File
Other Configuration Modes
Device Support
The following devices are supported.
Virtex/-E/-II/-II PRO/4/5/6
Spartan/-II/-IIE/XL/3/3E/3A/6
XC4000/E/L/EX/XL/XLA/XV
CoolRunnerXPLA3/-II
XC9500/XL/XV
XC18V00P
XCF00S
XCF00P
Parallel Cable IV
The Parallel Cable connects to the parallel port and can be used to facilitate Slave Serial and
Boundary-Scan functionality. For more information, go to
http://www.xilinx.com/support, select Documentation > Devices > Configuration
Solutions > Configuration Hardware > Xilinx Parallel Cable IV.
MultiPRO Cable
The MultiPRO cable connects to the parallel port and can be used to facilitate Desktop
Configuration Mode functionality. For more information, go to
http://www.xilinx.com/support, select Documentation > Devices > Configuration
Solutions > Configuration Hardware > MultiPRO Desktop Tool.
Getting Started
2. In the iMPACT Project dialog box, select create a new project (.ipf).
3. Click the Browse button.
4. Browse to the project directory and then enter stopwatch in the File Name field.
5. Click Save.
6. Click OK.
This creates a new project file in iMPACT. You are prompted to define the project, as
described in the next section.
2. Click OK.
iMPACT will pass data through the devices and automatically identify the size and
composition of the boundary scan chain. Any supported Xilinx device will be recognized
and labeled in iMPACT. Any other device will be labeled as unknown. The software will
then highlight each device in the chain and prompt you to assign a configuration file or
BSDL file.
Note: If you were not prompted to select a configuration mode or automatic boundary scan mode,
right-click in the iMPACT window and select Initialize Chain. The software will identify the chain if the
connections to the board are working. Go to Troubleshooting Boundary Scan Configuration if you
are having problems.
4. When the software prompts you to select a configuration file for the second device
(XCF04S), select the MCS file from your project working directory.
5. Click Open.
Note: If a configuration file is not available, a Boundary Scan Description File (BSDL or BSD) file
can be applied instead. The BSDL file provides the software with the necessary Boundary Scan
information that allows a subset of the Boundary Scan Operations to be available for that device. To
have ISE automatically select a BSDL file (for both Xilinx and non-Xilinx devices), select Bypass in
the Assign New Configuration File dialog box.
6. When the Device Programming Properties Dialog Box appears (see Figure 7-5). Select
the Verify option.
The Verify option enables the device to be readback and compared to the BIT file using
the MSK file that was created earlier.
7. Click OK to begin programming.
The options available in the Device Programming Properties dialog box vary based on the device you
have selected.
Editing Preferences
To edit the preferences for the Boundary Scan Configuration, select Edit > Preferences.
This selection opens the window shown in Figure 7-6. Click Help for a description of the
Preferences.
The software accesses the IDCODE for this Spartan-3 device. The result is displayed in the
log window (see Figure 7-8).
When the Program operation completes, a large blue message appears showing that
programming was successful (see Figure 7-9). This message disappears after a couple of
seconds.
Your design has been programmed and has been verified. The board should now be
working and should allow you to start, stop and reset the runners stopwatch.
When a connection is found, the bottom of the iMPACT window will display the type of
cable connected, the port attached to the cable, and the cable speed (see Figure 7-10).
If a cable is connected to the system and the cable autodetection fails, refer to Xilinx
Answer Record #15742. Go to http://www.xilinx.com/support and search for 15742.
For help using iMPACT Boundary-Scan Debug, use the iMPACT Help (accessible from
Help > Help Topics), or file a Web case at http://www.xilinx.com/support.
The instructions that are necessary to perform a Get Device ID operation are then
written to the file.
3. To see the results, select View > View SVF-STAPL File. Figure 7-13 shows what the
SVF file looks like after the Get Device ID operation is performed.
Figure 7-13: SVF File that Gets a Device ID from the First Device in the Chain