Time-frequency Quasi-matched Intelligence Receiver to
LPI Radar Signal
Deguo Zeng*, Hao Cheng, Keyu Long, Xiaodong Zeng, Haiyan Gu, Xiaodong He, Bin Tang
*School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
Email: zedg@sina.com
Abstract
An intelligence receiver quasi-matched to the received
LPI radar signals in time and frequency domain is presented.
The architecture and prototype using FPGA and DSP are
shown. The presented receiver works especially well when
the received signals are complex and time-varying.
Keywords: intelligence receiver, time frequency, quasi-
matched, electronic warfare, radar signal.
1. Introduction
In modern electronic warfare, the radar takes over almost
the entire electromagnetic spectrum from high frequency to
microwave, millimetre wave, infrared, even laser, etc. Further,
the density of the radar signals is increasing over time and it
is generally believed that the full-band stream of pulses per
second is from 300000 to 2000000. Its not an easy task for
the intelligence receiver to intercept signals within the whole
frequency range under such a high signal density. Whats
more, the use of low probability of intercept (LPI) radar, such
as the pulse compression radar, makes the modern electronic
warfare environment more complex for the intelligence
receiver to deal with.
The currently available LPI technologies are mainly
based on the operation or design of a radar. The operations of
LPI radar limit the transmission time as much as possible, and
prefer to use indirect identification information by detecting
the specified target region with external radiation source
searching. Lots of design methods are also adopted to achieve
lower peak power, including the increase of accumulation
time and the instantaneous bandwidth, the use of high gain,
low sidelobe, high load factor, high sensitivity receiver and
the control of transmitter power, etc.
In addition, the technologies can be extended using pulse
compression to widen the instantaneous bandwidth,
transmitting multiple beams with different frequencies
simultaneously to reduce the total scan time which limits the
accumulation time, changing the parameters of waveform
randomly to confuse the recognition and sorting of the
intelligence receiver, or copying the enemys waveform
properties to avoid to be recognized [1].
As one of the most important LPI technologies, the LPI
radar adopts a variety of complex radar waveforms, including
broadband frequency agility, waveform agility, pulse
repetition interval (PRI) and pulse transition, beam hopping,
and complex or hybrid modulation. The primary task of the
intelligence receiver is the detection because the signal
analysis is on the premise of it. However, the detection is
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978-1-4244-8443-0/11/$26.00 2011 IEEE

beyond the abilities of the classical interception architecture.
Moreover, the developments of the phased array radar,
synthetic aperture radar and other new LPI radar systems
undermine the advantages of the intelligence receiver. The
mismatch between traditional signal processing model and
new radar systems leads to a upgrading of the existed
intelligence receiver system.
2. The model of the received radar signal and the
interception architectures
2.1 Signal Model
The classical models for radar signals are mainly based
on the linear frequency modulation (LFM) and phase shift
keying (PSK), and they are too simple to describe the
received signals in new radar systems. Known to all, one of
the best ways to describe a signal is to choose the most
similar signal model to fit the unknown one. The complex
radar waveforms mentioned above could be modelled as the
hybrid of the polynomial phase signal, frequency agility and
PRI transition, so we combine the polynomial phase signal
and encoding signal model as the new LPI radar model which
could be uniformly expressed as
M 1 N 1
Q 1
r (t ) exp j M (m, n)  2S f (m, n)t  a (m, n)t
q
q
(1)
m 0 n 0 q 0
P (t  nTr1  mTr 2 )
1, 0 d t  TP
where P (t ) , TP is the sub pulse width, Tr1 the PRI
0, otherwise
of subpulse, Tr 2 the PRI, N the number of subpulse, Q the
order of polynomial phase and M the number of pulse.
M (m, n) , f (m, n) and aq (m, n) are the phase code, frequency
code and polynomial coefficient of the (m, n)th subpulse,
respectively. Tr 2 ! NTr1 , if Tr1 ! TP the signal is pulse-hybrid,
else the signal is continuous-hybrid. The parameter relations
of the signal model are shown in Fig. 1.

Fig.1 the parameter relations of the signal model.
The model includes broadband frequency agility,
waveform agility, parameter agility, frequency shift keying
(FSK), FSK/PSK, FM/PSK and FSK/FM modulation, etc.
The model fully reflects the mechanism of the LPI radar, and
theoretically predicts possible new LPI radars.
2.2 Interception Architecture
The good interception architectures for the discussed
kinds of signals should be based on the properties of LPI
signals. The properties of LPI could be summarized as wide
in frequency, continuous wave in time with weak energy,
burst in time with strong energy or beam mutation resulting in
a larger dynamic range, and all of these lead to the signal
interception difficult. The intelligence receiver could also be
summarized as three kinds of architectures, namely the fixed
architecture, predictive one and adaptive one.
The fixed architecture selects the focus area and
frequency range for interception according to a prior of the
theatre, and the signal could be targeted for interception when
the hostile signal come into the band range of interception.
The interception architecture is a strong way targeted and has
very high sensitivity, large dynamic range and specific signal
processing capability in the selected area and frequency band.
The architecture is often with narrow bandwidth.
The predictive architecture intercepts signals in the
battlefield by real-time spectrum sensing and predict the
possible next parameters of the agile signal and then
configure the receiver in real-time or near real-time to receive
the signal matched or quasi-matched. This architecture is
particularly suitable for interception of the wideband
frequency agility signal. However, the prediction strategy is
relatively complex which should have a strong intelligence.
This architecture is one of the directions of the intelligence
receiver.
The adaptive architecture selects the most of the regions
and some bands for interception according to a prior. The
signal could be intercepted when the hostile signal come into
the band range of interception. This architecture has no
special target in general, and then the requirement for the
amount of the receivers, the required signal number to
simultaneously deal with and the flexibility for signal
processing are higher than the ones with fixed architecture.
Since the adaptive architecture has wider bandwidth, it has
lower sensitivity and dynamic range.
The researches of the architectures mainly focused on
the fixed and adaptive ones because the predictive one is hard
for implementation. For the fixed and adaptive ones, the
solution technologies include: Nyquist-Shannon sampling
using high speed A/D, channelized sampling using hybrid
filter banks [2], high speed interleaving/multiplexing data-
acquisition system [3], ultra-wideband A/D via signal
expansion [4] and non-linear spectrum compression
technology [5], etc. These architectures have different
advantages in performance.
A LPI radar often uses continuous wave, interrupted
continuous wave or the spread spectrum technology to
transmit signals with low peak power. The radar receiver can
get high processing gain by pulse compression of large time
bandwidth product signal or long accumulation time. As the
peak power of these radar signals is very low, the output
signal to noise ratio (SNR) will become very low even for a
high sensitivity detection receiver, making the conventional
radar interception of such signals very difficult or the
detection be impossible. Further, some typical burst LPI
radars transmit relatively short signals in the time domain,
resulting in signal interception and processing difficult using
the classical interception receive. The channelized digital

receiver has a large data stream after A/D. To reduce the
burden of follow-up processors, there will be no difference
between short and long time signal decimation, leading to the
lack of information for burst signal processing, hence we
cannot effectively extract the desired signal parameters.
3. Architecture of the time-frequency quasi-matched
intelligence receiver (TFQMR)
In the radar receiver, the radar echo signal is matched
with the transmitted signal to obtain a high gain. In the
intelligence receiver, the signal cannot be predicted in
advance about the information such as frequency and symbol,
therefore we have no local signal to match the echo one. To
this end, we propose the time-frequency quasi-matched
intelligence receiver (TFQMR) as shown in Fig.2. The
TFQMR uses the most suitable spectrum for the signal
detection and the most suitable time width determined by
precision of the signal processing to realize the quasi-matched
interception. The TFQMR uses multiple time-bandwidth
analysis units to analyse the time width and bandwidth of the
received signal and the units will cover the whole monitoring
signal frequency. For signals with different time width and
bandwidth, the TFQMR could use adaptive signal processing
algorithms, which is suitable for interception of signals with
agile time width or bandwidth. When the requirements for the
interesting signals of the intelligence receiver increase, we
just need to add the units to complete the high probability of
interception. The TFQMR could be realized in time,
frequency, time-frequency or other domains. The TFQMR
has different dilution algorithms for different pulse width
signals and could lower the decimation factor of the burst
signal to assure the precision of parameter estimation and
recognition. The architecture could deal with the discussed
signals above.
ADC
PW Spectral
analysis analysis
Filter
Time frequency analysis
unit 1 Digital
signal
processing
(FPGA+
DSP)
PW Spectral
Filter
analysis analysis
Time frequency analysis
unit N
Fig.2 Architecture of TFQMR.
4. Implementation
With the development of the large scale integrated
circuit, high-speed analog-to-digital converter (A/D), ultra-
large-scale field programmable gate array (FPGA) and high-
speed digital signal processor (DSP) have made great
progress, and the intelligence receiver has entered a new
digital field.
Although the ADC and DSP have rapid development,
the work rate gap between the two still exists, and there
would be no significant improvement in a short term. To
alleviate this contradiction, the intelligence receiver needs an
additional data rate conversion system which will turn high-
speed data streams into low-speed ones, ensuring that the
signal information will not lose and easing pressure on the
follow-up DSP.
Since the electromagnetic environment of the electronic
warfare are more and more complex, a simple data-rate
conversion system is not enough to meet the actual needs,
then the enhanced digital signal processing capability has
become another way. This promotes the restructuring of the
FPGA, and the mainstream FPGA vendors have enhanced
signal processing capabilities. For example, the XC5VSX95T
of XLINX integrates a 640 DSP48E and 8784Kb RAM,
providing hard-core support for the multiply-accumulate
operations for FFT and FIR filtering. At the same time, a
series of complex calculation cores have been developed,
such as the coordinate rotation digital computer (CORDIC)
and direct digital synthesizer (DDS). To enhance the external
memory expansion capability, the interface cores based on
DDRI, DDRII and DDRIII have also been developed, making
the FPGA be a powerful data cache.
The FPGA has become responsible for some
sophisticated signal processing algorithms, such as FFT
operations, FIR filter operation, and arctangent operation. The
DSP is responsible for the most complex calculations. In
calculation, the array of the FPGA and DSP becomes a
popular hardware structure for digital signal processing.
From a design perspective, we hope that the application
of the DSP array will lead to increased processing power, but
the actual situation is not so simple. The use of the DSP array
will introduce computing resource allocation, data cache,
status updates and a series of complex logic problems, and
these problems are directly related to the processing power of
the DSP array. In order to realize the logic management of the
DSP array, we added a control system to the intelligence
receiver. The control system not only needs a rational
allocation of computing resources within the processor, but
also is responsible for data communications with peripheral
equipment.
Fig.3 The top view of the PCB of TFQMR.
We have implemented the TFQMR using high speed
A/D, FPGA and DSP. The top view of the printed circuit
board (PCB) is shown in Fig.3. The PCB of the TFQMR
includes the sample, data rate conversion, time frequency
quasi-match, central control and the follow-up signal
processing sectors.

4.1 Sample
High-speed A/D is the first important sector of the
intelligence receiver, and its performance is directly related to
the performance of the entire receiver. The important
parameters related to the performance of the intelligence
receiver are the resolution, effective number of bits (ENOB),
maximum conversion rate and bandwidth. The dynamic range
is closely related to the ENOB. In the design of circuits of
A/D, we try to reduce the mutual interference between the
digital part and the analog one. In order to reduce data latency,
we try to keep the data lines to the equal length, and retain
isolation around the data lines to further reduce interference.
To reduce the requirement for the maximum conversion
rate and the difficulty to design the anti-aliasing filter, the
analog front end uses the combination of superheterodyne and
channelized structures to mix the different channel signals
into the same intermediate frequency (IF). The IF is between
hundreds of MHz to several GHz, and the bandwidth of IF is
the bandwidth of analog channel and the receivers
instantaneous processing bandwidth, which is about 1GHz.
The basic structure of high-speed A/D is based on high speed
interleaving/multiplexing sampling, such as NS Companys
ADC083000, which is actually realized by the two low-speed
A/D.
In this system, the IF is 1.5GHz-2.5GHz, and we use the
ADC083000 by 2.7GHz undersampling which has simple
architecture and the ability to receive multiple signals.
4.2 Data buffer and data rate conversion
When the input signal is digitized, the data rate is very
high. For this system, the sampling rate is 2.7GHz with 8-bits,
and the bus data rate and single line data rate are up to
21.6Gb/s and 2.7Gb/s, respectively. In order to reduce the
difficulty of receiving data, high-speed A/D would generally
have a deserializer. The deserializer works as 1:4, and the
single line data rate is 675Mb/s, which is acceptable for the
major of devices. If the follow-up of the FPGA can widen the
data bus to 16bit and the speed of the processing clock should
be 337.5MHz, the additional data storage is unnecessary.
However, even if some modules of the FPGA can operate on
this clock, it is just based on the cost of consumption of
FPGA resources which is very important in signal processing.
From the application view, the intelligence receiver would
prefer to lose little pulses, especially when the pulse is in a
high intensity, to extract more information from pulses. In
conclusion, the data storage is very necessary.
The most important high-speed data storages are the first
in first out (FIFO) and synchronous dynamic random access
memory (SDRAM).
The FIFO is a data buffer, and the difference between
normal memories is that there is no external line for reading
and writing. The FIFO is easy to use with constrains that the
data first in must be read first. As the rapid development of
microelectronic technology, the capacity of a new generation
of the FIFO chip increases with smaller and smaller size.
As a new large scale integrated circuit with flexible,
convenient and efficient characteristics, the FIFO is gradually
and widely used in high speed data acquisition, processing,
transmission and multi-core processing system. The
72T36135M of Integrated Device Technology (IDT) works at
the clock of 225MHz, 36bit, and 18-Mbits cache.
The synchronization of the SDRAM is that the SDRAM
needs to synchronize the clock to data transmission and send
control commands. The dynamic is to constantly refresh the
storage array to ensure data is not lost. The random means
that the data is not linear sequence storage, but could be
freedom to read and write in the specified address.
In this system, if we use the FIFO as a buffer, there are
at least four parallel FIFOs whose clock is 168.75MHz, bit
width is 128-bits and the cache capacity is 72-Mbits; while if
we use the DDR as a buffer, there are at least four parallel
DDR SDRAMs whose clock is also 168.75MHz, bit width is
64bits because the SDRAM transfers data both edges, cache
capacity is 2048Mbits. In electronic warfare, the pulse width
of a LPI radar signal may be as long as a few hundred
microseconds. We set the pulse width to be 100s and the
data size of a single pulse to be 2Mbits. If we adopt the FIFO
as a buffer, we can store up to 36 pulses, which is difficult to
meet the actual requirements. 1024 pulses can be stored if we
use the DDR, which is enough for the intelligence receiver. In
addition, as the DDR is a single port RAM, the data could be
implemented using a ping pong buffer to achieve independent
reading and writing, and the buffer capacity will be increased
twice. Thus, the DDR is suitable for high-speed data buffer.
4.3 Time-frequency quasi-matched
The time-frequency quasi-matched architecture uses
several time-bandwidth analysis units to analyse the received
signals, and we used three units in this system. Here, we
adopt the efficient implementation architecture which is based
on the poly-phase filter bank and IDFT structure. We have
realized the channelized frequency by two FPGAs.
The time-frequency quasi-matched architecture consists
of two parts. The first part is the pulse width analysis which is
detailed as the detection and buffer of the radar signal with
noise, and the second part is to read the slow signal data
stream from the buffer and finish the frequency analysis. In
this way, we could get the time-frequency information of the
received signals. The detection algorithms include energy
accumulation and the autocorrelation of the received signals.
The buffers use the ping pong of several DDRs and SDRAMs.
The first, second and third channelized units are to process
the real, complex and complex data of the received signal,
respectively. There are 8 channels in the first unit with
channel bandwidth 337.5MHz, the decimation factor is 4 and
the sampling frequency 675MHz. The second unit has 32
channels and the channel bandwidth is just 21.09375MHz.
4.4 Central Control
The primary task of the central control is to finish the
buffer for many kinds of data and update their flags based on

the detection results of time-frequency quasi-matched units.
The central control will evaluate the processing priority based
on the time of arrival (TOA) of pulses and flags of the buffer.
Moreover, the modifications of TOA and pulse width are also
finished in the central control. The central control receives the
data from the buffer with slow data rate, the data from the
first unit and the second unit. We can improve the ability of
short time signal processing. In addition, the central control is
also responsible for the communication between DSPs and
other devices.
4.5 Follow-up signal processing
The follow-up signal processing technologies include the
intra-pulse analysis and signal deinterleaving. The first part
consists of automatic modulation classification and parameter
estimation of radar signals to give the pulse description word
(PDW) including TOA, direction of arrival (DOA), carrier
frequency (CF), pulse width (PW), pulse amplitude (PA) and
intra-pulse modulation (PM). The signal deinterleaving will
provide the antenna scan period (ASP) and pulse repetition
interval (PRI). The final result is the emitter description word
(EDW). These are implemented by the FPGA and DSP.
5. Conclusions
In this paper, we have presented an architecture denoted
as time-frequency quasi-matched for the intelligence receiver.
This structure is suitable for interception of most LPI radar
signals, especially for the agile signals widely used in
electronic warfare. We also showed the implementation of the
architecture and its key technologies. This architecture will be
useful for the modern electronic warfare.
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