DOC/LP/01/28.02.

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LESSON PLAN LP EC6302

LP Rev. No: 00
Sub Code & Name: EC6302 DIGITAL ELECTRONICS Date: 23/06/14
Page 01 of 06
Unit : I Branch : EC Semester: III

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 9

Syllabus:
Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of
Duality - Boolean expression - Minimization of Boolean expressions Minterm Maxterm - Sum of
Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditions -
Quine-McCluskey method of minimization.
Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR- Implementations of
Logic Functions using gates, NANDNOR implementations Multi level gate implementations- Multi
output gate implementations. TTL and CMOS Logic and their characteristics Tristate gates.

Objective: To introduce basic postulates of Boolean algebra and show the correlation between Boolean
expressions. To introduce the methods for simplifying Boolean expressions.

Session Topics to be covered Time Ref Teaching

No. (minutes) Method
1. Introduction to Digital Electronics, Boolean 50 1,6,7 BB
postulates and laws, De-Morgans Theorem.
2. Principle of duality, Minimization of 50 1,6,7 BB
expressions using Boolean laws.
3. Minterm, Maxterm, Sum of Products (SOP), 50 1,3 BB
Product of Sums (POS).
4. Minimization of expressions using Karnaugh 50 1 BB
map-3&4 variable K-map. 5
5. 5-variable K-map, K-map with dont care 50 1 BB
conditions. 5
6. Quine-McCluskey method of minimization. 50 2 BB
5
7. Truth table, symbol and expressions of AND, 50 2,3 BB
OR, NOT, NAND, NOR, ExOR and ExNOR.
8. Implementation of logic function using 50 1 BB
Universal gates, Multi level-output gate 2
implementations. 5
9. Tutorial 50 1,2 BB
10. Characteristics of TTL and CMOS Logic, 50 1 BB/PPT
Tristate gates.
 DOC/LP/01/28.02.02

LESSON PLAN LP EC6302

LP Rev. No: 00
Sub Code & Name: EC6302 DIGITAL ELECTRONICS Date: 23/06/14
Page 02 of 06
Unit : II Branch : EC Semester: III

UNIT II COMBINATIONAL CIRCUITS 9

Syllabus:
Design procedure Half adder Full Adder Half subtractor Full subtractor - Parallel binary adder,
parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/Subtractor - BCD
adder Binary Multiplier Binary Divider - Multiplexer/ Demultiplexer decoder - encoder parity
checker parity generators - code converters - Magnitude Comparator.

Objective: To outline the procedures for the analysis and design of combinational circuits.

Session Topics to be covered Time Ref Teaching

No. (minutes) Method
11. Design of half adder and full adder. 50 1,4,5 BB

12. Design of half subtractor, full subtractor and 50 1,4,5 BB

parallel binary adder/subtractor.
13. Disadvantages of parallel adder carry look ahead 50 1,4,5 BB
adder.
14. Design of serial adder/subtractor and BCD adder. 50 1,4,5 BB

15. Binary multiplier and binary divider. 50 1,4,5 BB

CAT-I 90 - -

16. Design and implementation of Multiplexer and 50 1,4,5 BB

Demultiplexer.
17. Encoder and decoder.Odd, Even: Parity generators 50 1,4,5 BB
and checker.
18. Code converters. 50 1,4,5 PPT

19. 2-bit, 4-bit Magnitude comparator. 50 1,4,5 PPT

20. Tutorial 50 1,4,5 BB

 DOC/LP/01/28.02.02

LESSON PLAN LP EC6302

LP Rev. No: 00
Sub Code & Name: EC6302 DIGITAL ELECTRONICS Date: 23/06/14
Page 03 of 06
Unit : III Branch : EC Semester: III

UNIT III SEQUENTIAL CIRCUITS 9

Syllabus:
Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application
table Edge triggering Level Triggering Realization of one flip flop using other flip flops serial
adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down counter -
Synchronous counters Synchronous Up/Down counters Programmable counters Design of
Synchronous counters: state diagram- State table State minimization State assignment - Excitation
table and maps-Circuit implementation - Modulon counter, Registers shift registers - Universal shift
registers Shift register counters Ring counter Shift counters - Sequence generators.

Objective: To outline the formal procedures for the analysis and design of sequential circuits.
.

Session Topics to be covered Time Ref Teaching

No. (minutes) Method
21. Latches, Characteristic table and equation of SR, 50 1 BB
JK, D and T flip flop.
22. Level triggering and edge triggering of flip flop. 50 1 BB
Conversion of one flip flop to other flip flops
23. Realizations of one flip flop using other flip flops, 50 1 BB
Master-Slave flip flop.
24. Asynchronous: ripple counter, Up/Down counter. 50 1,6,7 BB/PPT

25. Synchronous: Up/Down counters, Programmable 50 1,6,7 BB/PPT

counters.
26. State diagram, minimization and State assignment. 50 1,6,7 BB/PPT
Excitation table and maps.
27. Design of Modulo-n counter. 50 1 BB

28. Tutorial 50 1 BB
29. Shift registers, SISO, SIPO, PISO, PIPO 50 1,9 BB/ICT
,Universal shift registers

30. Shift register counters ,ring counter and shift 50 1,9 BB/ICT
counter.
31. Design of sequence generators. 50 1 BB
 DOC/LP/01/28.02.02

LESSON PLAN LP EC6302

LP Rev. No: 00
Sub Code & Name: EC6302 DIGITAL ELECTRONICS Date: 23/06/14
Page 04 of 06
Unit : IV Branch : EC Semester: III

UNIT IV MEMORY DEVICES 9

Syllabus:
Classification of memories ROM - ROM organization - PROM EPROM EEPROM EAPROM,
RAM RAM organization Write operation Read operation Memory cycle - Timing wave forms
Memory decoding memory expansion Static RAM Cell-Bipolar RAM cell MOSFET RAM cell
Dynamic RAM cell Programmable Logic Devices Programmable Logic Array (PLA) -
Programmable Array Logic (PAL) - Field Programmable Gate Arrays (FPGA) - Implementation of
combinational logic circuits using ROM, PLA, PAL.

Objective: To introduce the concept of memories and programmable logic devices.

Session Topics to be covered Time Ref Teaching

No. (minutes) Method
32. Classification of memories- ROM, RAM 50 1,5 BB/PPT

33. ROM Organisation - PROM, EPROM, 50 1,5 BB/PPT

EEPROM,EAPROM
34. RAM organization, - Write and Read operation, 50 1,5 BB/PPT
Memory cycle and Timing wave forms.
35. Memory decoding and memory expansion. 50 1,5 BB/PPT

CAT II 90 - -

36. Static RAM Cell, Bipolar RAM cell , 50 1,5 BB/PPT

Dynamic RAM Cell and MOSFET RAM cell.
37. Introduction to Programmable Logic Devices. 50 1 BB
Implementation of combinational logic circuits
using PLA.
38. Implementation of combinational logic circuits 50 1 BB
using ROM, PLA, PAL
39. Implementation of combinational logic circuits 50 1 BB,OHP
using PAL. Field Programmable Gate Arrays
(FPGA).
 DOC/LP/01/28.02.02
LP EC6302
LESSON PLAN LP Rev. No: 00
Date: 23/06/14
Sub Code & Name: EC6302 DIGITAL ELECTRONICS Page 05 of 06
Unit : V Branch : EC Semester: III

UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS 9

Syllabus:
Synchronous Sequential Circuits: General Model Classification Design Use of Algorithmic
State Machine Analysis of Synchronous Sequential Circuits
Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits
Incompletely specified State Machines Problems in Asynchronous Circuits Design of Hazard Free
Switching circuits. Design of Combinational and Sequential circuits using VERILOG.

Objective: To introduce the concept of synchronous and asynchronous sequential circuits and to design
Combinational and Sequential circuits using VERILOG.

Session Topics to be covered Time Ref Teaching

No. (minutes) Method
40. General sequential Model Classification and 50 1,4 BB/PPT
design of synchronous sequential circuit.
41. Analysis of Synchronous Sequential circuit. 50 1,4 BB/PPT

42. Algorithmic State Machine. 50 1,4 BB/PPT

43. Design of fundamental mode Incompletely 50 1,4 BB/PPT

specified State Machines
44. Design of Pulse mode - Incompletely specified 50 1,4 BB
State Machines
45. Problems in Asynchronous Circuits - Hazards and 50 1,4 BB
types of hazards.
46. Design of Hazard free Switching circuits. 50 1,4 BB/PPT

47. Design of Combinational and Sequential circuits 50 1,8 BB/ICT

using Verilog.
48. Design of Combinational and Sequential circuits 50 1,8 BB/ICT
using Verilog.
CAT - III. 90 - -
 DOC/LP/01/28.02.02
LP EC6302
LESSON PLAN LP Rev. No: 00
Date: 23/06/14
Sub Code & Name: EC6302 DIGITAL ELECTRONICS Page 06 of 06
Branch : EC Semester: III

Course Delivery Plan:

1 2 3 4 5 6 7 8 9 10 11 12
Week
I II I II I II I II I II I II I II I II I II I II I II I II

Units
1 2 3 4 5

TEXT BOOK: CAT 1 CAT 2 CAT 3

1. M. Morris Mano, Digital Design, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 /
Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCES:
2. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2008
3. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2006.
4. Charles H.Roth. Fundamentals of Logic Design, 6th Edition, Thomson Learning, 2013.
5. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th Edition, TMH, 2006
6. Thomas L. Floyd, Digital Fundamentals, 10th Edition, Pearson Education Inc, 2011
7. Donald D.Givone, Digital Principles and Design, TMH, 2003.
8. http://nptel.ac.in
9.http://distrct.bluegrass.kctcs.edu/kevin.dunn/files/shift_registers

Prepared by Approved by

Signature

Name Dr.G.A.Sathish Kumar Dr. S. Ganesh Vaidyanathan

Ms.D.Menaka
Ms.S.Kalyani
Designation Professor HOD/EC
Assistant Professor
Assistant Professor

Date 23/06/14 23/06/14

 SYLLABUS

EC 6302 DIGITAL ELECTRONICS LT PC

3 003
OBJECTIVES:
To introduce basic postulates of Boolean algebra and shows the correlation between Boolean
expressions
To introduce the methods for simplifying Boolean expressions
To outline the formal procedures for the analysis and design of combinational circuits
and sequential circuits
To introduce the concept of memories and programmable logic devices.
To illustrate the concept of synchronous and asynchronous sequential circuits

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 9

Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of
Duality - Boolean expression - Minimization of Boolean expressions Minterm Maxterm - Sum
of Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditions
Quine - Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR,
ExclusiveOR and ExclusiveNOR Implementations of Logic Functions using gates, NANDNOR
implementations Multi level gate implementations- Multi output gate implementations. TTL and
CMOS Logic and their characteristics Tristate gates
UNIT II COMBINATIONAL CIRCUITS 9
Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel binary
adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/Subtractor -
BCD adder Binary Multiplier Binary Divider - Multiplexer/Demultiplexer decoder -
encoder parity checker parity generators code converters - Magnitude Comparator.
UNIT III SEQUENTIAL CIRCUITS 9
Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application
table Edge triggering Level Triggering Realization of one flip flop using other flip flops s Serial
adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down counter -
Synchronous counters Synchronous Up/Down counters Programmable counters Design of
Synchronous counters: state diagram- State table State minimization State assignment - Excitation
table and maps-Circuit implementation - Modulon counter, Registers shift registers - Universal
shift registers Shift register counters Ring counter Shift counters - Sequence generators.
UNIT IV MEMORY DEVICES 9
Classification of memories ROM - ROM organization - PROM EPROM EEPROM
EAPROM, RAM RAM organization Write operation Read operation Memory cycle -
Timing wave forms Memory decoding memory expansion Static RAM Cell- Bipolar RAM cell
MOSFET RAM cell Dynamic RAM cell Programmable Logic Devices Programmable Logic Array
(PLA) - Programmable Array Logic (PAL) Field Programmable Gate Arrays (FPGA) -
Implementation of combinational logic circuits using ROM, PLA, PAL
UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS 9
Synchronous Sequential Circuits: General Model Classification Design Use of Algorithmic
State Machine Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits:
Design of fundamental mode and pulse mode circuits Incompletely specified State Machines
Problems in Asynchronous Circuits Design of Hazard Free Switching circuits. Design of
Combinational and Sequential circuits using VERILOG.

TOTAL: 45 PERIODS
OUTCOMES:
Students will be able to:
Analyze different methods used for simplification of Boolean expressions.
Design and implement Combinational circuits.
Design and implement synchronous and asynchronous sequential circuits.
Write simple HDL codes for the circuits.

TEXT BOOK:
1. M. Morris Mano, Digital Design, 4th
Edition, Prentice Hall of India Pvt. Ltd., 2008 / Pearson
Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCES:
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2008
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2006.
3. Charles H.Roth. Fundamentals of Logic Design, 6th
Edition, Thomson Learning, 2013.
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th
Edition, TMH, 2006
PROGRAMME EDUCATIONAL OBJECTIVES / PROGRAMME OUTCOMES / COURSE
OUTCOMES

Course Code & Name: EC 6302 DIGITAL ELECTRONICS

Student Branch: EC Semester: III

Programme Educational Objectives (PEOs):

PEO-2: To familiarize the student with the analysis and design of various electronic circuits along with
their applications in various electronic products

PEO-3: To learn the design concepts of digital systems, associated analysis and processing of digital
signals for various VLSI and DSP based applications

Course Outcomes (COs):

Group-III (Electronics and Communication Engineering Core courses): To gain in-depth
knowledge in the field of Electronics and Communication Engineering and to apply the concepts learnt
through theory and Laboratory in various applications to meet the empathetical needs of our society.
Also able to,
* Analyze different methods used for simplification of Boolean expressions.
* Design and implement Combinational circuits.
* Design and implement synchronous and asynchronous sequential circuits.
* Write simple HDL codes for the circuits.
Programme Outcomes (POs):
PO-4:To impart an ability to design and conduct experiments as well as to analyze and interpret data in
the areas of Computer hardware, Digital signal processing, VLSI and Communication systems.

PO-5:To teach the use of modern engineering tools, techniques, equipments, software and
programming language skills necessary for designing and testing Electronics and Communication
Engineering systems.

PO-12: To impart an ability to engage in life-long learning and to keep abreast with current
developments in the field of Electronics and Communication engineering.