Home

About
Electrical Engineer Jobs
Request Topic
Resources

Home VHDL Counter

Search this site...

VHDL Counter
Posted by Shannon Hilbert in Verilog / VHDL on 2-10-13

Counters are a principle part of nearly every FPGA design, facilitating time tracking in logic circuits by
counting clock cycles. Im going to discuss VHDL counter construction, and I also want to share a
very practical counter tip that I picked up from a colleague many years back: count backwards.

This article will cover the following concepts:

1. Counter Concepts
2. VHDL Implementation
3. Synthesis Considerations
4. Typical Uses

For a Verilog counter, see our corresponding counter article with example code.

Counter Concepts
The general idea behind the counter is pretty simple:
Start at some initial count value and store it in a register.
Increment the counter.
Save the new count value back into the register.

The counters that Im going to implement for you in this VHDL counter example count backwards
and forwards from/to 12. It may sound strange, but I have a very good reason for counting
backwards, and Ill get into that in the Synthesis Considerations section. After all, its just as easy to
compute x-1 as it is to compute x+1.

The code example implements a 5-bit counter that counts backwards, and two 4-bit counters that
count forwardone of which is allowed to free run.

VHDL Code
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4
5 entity counter is
6 port(
7 CLK : in std_logic;
8 RST : in std_logic;
9 F_COUNT_OUT : out unsigned(3 downto 0);
10 B_COUNT_OUT : out unsigned(3 downto 0);
11 FR_COUNT_OUT : out unsigned(3 downto 0)
12 );
13 end counter;
14
15
16 architecture bhv of counter is
17
18 ----------------------------------------------------------------
19 -- signal definitions
20 ----------------------------------------------------------------
21
22 --counter signals
23 constant count_stop : unsigned(3 downto 0) := X"C";
24 signal counter_b : unsigned(4 downto 0);
25 signal counter_f : unsigned(3 downto 0);
26 signal counter_fr : unsigned(3 downto 0);
27
28 begin
29
30 ----------------------------------------------------------------
31 -- counter
32 ----------------------------------------------------------------
33
34 --counter
35 process(RST,CLK,counter_f,counter_b)
36 begin
37 if(rising_edge(CLK)) then
38
39 --intitialize counters on reset
40 if(RST='1') then
41 counter_f <= (others=>'0');
42 counter_b <= '0' & count_stop;
43 counter_fr <= (others=>'0');
44 else
45
46 --free running counter
47 counter_fr <= counter_fr + 1;
48
49 --forward counter
50 if(counter_f /= count_stop) then
51 counter_f <= counter_f + 1;
52 end if;
53
54 --backward counter
55 if(counter_b(4)='0') then
56 counter_b <= counter_b - 1;
57 end if;
58
59 end if;
60 end if;
61 end process;
62
63 ----------------------------------------------------------------
64 -- outputs
65 ----------------------------------------------------------------
66
67 --module output registers
68 process(RST,CLK)
69 begin
70 if(rising_edge(CLK)) then
71 if(RST='1') then
72 F_COUNT_OUT <= (others=>'0');
73 B_COUNT_OUT <= (others=>'0');
74 FR_COUNT_OUT <= (others=>'0');
75 else
76 F_COUNT_OUT <= counter_f;
77 B_COUNT_OUT <= counter_b(3 downto 0);
78 FR_COUNT_OUT <= counter_fr;
79 end if;
80 end if;
81 end process;
82
83
84
85 end bhv;

Counters are Not Clocks!

Before I get into talking about counter synthesis, I want to stress how not to make a mistake that
Ive seen over and over from even experienced engineers. Dont generate clocks directly from
counters!
There are a few ways to generate other clock speeds within an FPGA. The best way to generate new
clocks for logic is by using dedicated clock resources, like a PLL, DLL, DCM or other clock
management tile resources. If you cant uses those resources for whatever reason, you can use a
counter to divide down the clock, but you should never drive logic directly from the counter!

FPGA manufacturers have sophisticated architectures for clock distribution within a chip to prevent
clock skew and ensure that your design runs synchronously and as fast as possible. If you drive logic
directly from a counter output, you will bypass all of that. Your design will compile with more
difficulty, be less optimized, and run at lower speeds.

To make an analogy, normal logic connects (like those in a counter) are like backroads or
neighborhood streets in a city; clock lines are like 10-lane freeways. Driving the clock pin on logic
with a counter is like going from San Francisco to Los Angeles using side roads. Youll get there, but
youre going to do a lot of zig-zagging. The clock lines in an FPGA are literally much wider than
normal logic connects and have drastically reduced parasitic impedances. The figure notionally
illustrates this with clock routes in green and logic routes in blue.

Try to use clock resources to derive clocks. If you use a counter to generate a clock, always run it
into a clock distribution point (like a global or regional clock buffer) before driving logic with that
clock.

Synthesis Considerations
The most lightweight clock is the free-running clock. It just continuously adds (or subtracts) from the
previously registered value. It does not need supporting logic to stop at a certain number, and the
counter register just rolls over (refered to as overflow condition) when the maximum value has been
reached.

We naturally count in increasing order, so our natural tendency in implementing a stop counter is to
increment the counter. If we want to stop the counter at 12, as in this example, we have to start at
0 and then check to see if the counter value is equal to 12 each clock cycle. Remember that the
counter register is 4 bits and that 12 in binary is 1100. Lets look at that comparison in logical form,
or in a boolean equation:
check if: [counter(3)=1] AND [counter(2)=1] AND [counter(1)=0] AND [counter(0)=0].

Thats 7 logic operations to check for the number 12. If we were counting using a 32 bit register,
that would be 63 logic operations!

The point is that you can use a forward counter that doesnt free run, but depending on the size of
your counter register, the compare operation to stop the counter may take a long time with multiple
levels of logic. You can get away doing this with small width registers (like this example) or slow
clock speeds, but youll take a major performance hit in high-speed designs.

The most lightweight counter to that is not free-running is a backward counter. In this example, we
started the counter at 12 and counted back to zero. Instead of comparing all four bits every clock
cycle, we used a 5th bit in the most significant bit (MSB) position to see if the count was complete.
When the counter reaches zero and decrements again, the register rolls over (overflows) and moves
to the value 31, or 11111 in binary. Examine the count sequence in binary, starting from 5:

00101 (5)
00100 (4)
00011 (3)
00010 (2)
00001 (1)
00000 (0)
11111 (31)

Using this method, we can just watch for the MSB to be equal to 1 to see if were done counting.
Thats a single logic operation no matter how wide the count register is!

T ypical Uses
Counters are used in almost every logic design. Fundamentally, theyre the only way to keep track of
time in an FPGA, and the uses are endless. A few examples are keeping track of packet sizes when
sending data in a protocol, response timeouts, physical button debouncing, etc.

Happy coding!

We want to hear from you! Do you have a comment, question, or suggestion? Feel free to drop us an
email or post a comment.

Related content:
1. Verilog Counter
2. VHDL Type Conversion
3. VHDL Shift Register

Did you enjoy this article? Get Free Updates

Share
 the 0
Tweet
Subscribe
Love 404
S ubm it a C om m ent

You must be logged in to post a comment.

S tay Updated with BitWeenie

First Name :
Email Address : Join now!

Bitweenie on Twitter

RT @NikolaT_bw: Part 3 of the @bitweenie #Altium #pcbdesign video tutorial is up: http://t.co
/SpVnf2srH8 Learn the basics of #pcblayout in about 4 months ago from TweetDeck
ReplyRetweetFavorite
@SHilbertBW posted part 2 of the #Xilinx system generator video series for doing #DSP #FPGA
designs. http://t.co/GSQKLuMbJu about 4 months ago from TweetDeck in reply to SHilbertBW
ReplyRetweetFavorite
@shilbertbw just posted a good graphic to keep around the office, showing how to convert
between #VHDL data types http://t.co/YRLQ7Nb5sC about 4 months ago from TweetDeck in
reply to SHilbertBW ReplyRetweetFavorite

@@bitweenie

Topics

Altium bit BRA M byte cast clock distribution cons conversion counter crosstalk dBm dBm/Hz dds direct digital
synthesizer dsp fft resolution fixed point floating point FPGA fpga program m ing function matlab m odel pcb

construction pcb design pcb fabrication pcb layers PCB Materials pcb stackup power

power spectrum pros psd quantization shift register simulation simulink system generator therm al
spectral density

noise two-dim ensional type type conversion verilog VHDL xilinx

Recent P osts

Converting dBm to Watts

Recent C om m ents
 BitWeenie, LLC

Privacy Policy

Site Map

Designed by Elegant Themes | Powered by WordPress